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2025-03-11cmd/internal/obj/loong64: add {V,XV}MUL{B/H/W/V} and {V,XV}MUH{B/H/W/V}[U] ↵Xiaolin Zhao
instructions support Go asm syntax: VMUL{B/H/W/V} VK, VJ, VD VMUH{B/H/W/V}[U] VK, VJ, VD XVMUL{B/H/W/V} XK, XJ, XD XVMUH{B/H/W/V}[U] XK, XJ, XD Equivalent platform assembler syntax: vmul.{b/h/w/d} vd, vj, vk vmuh.{b/h/w/d}[u] vd, vj, vk xvmul.{b/h/w/d} xd, xj, xk xvmuh.{b/h/w/d}[u] xd, xj, xk Change-Id: I2f15a5b4b6303a0f82cb85114477f58e1b5fd950 Reviewed-on: https://go-review.googlesource.com/c/go/+/636375 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Auto-Submit: abner chenc <chenguoqi@loongson.cn> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn>
2025-03-10cmd/internal/obj/loong64: add {V,XV}SEQI, {V,XV}.{AND,OR,XOR,NOR} ↵Guoqi Chen
instructions support Go asm syntax: VSEQB $1, V2, V3 XVSEQB $2, X2, X3 V{AND,OR,XOR,NOR}B $1, V2, V3 XV{AND,OR,XOR,NOR}B $1, V2, V3 V{AND,OR,XOR,NOR,ANDN,ORN}V V1, V2, V3 XV{AND,OR,XOR,NOR,ANDN,ORN}V V1, V2, V3 Equivalent platform assembler syntax: vseqi.b v3, v2, $1 xvseqi.b x3, x2 ,$2 v{and,or,xor,nor}.b v3, v2, $1 xv{and,or,xor,nor}.b x3, x2, $1 v{and,or,xor,nor,andn,orn}v v3, v2, v1 xv{and,or,xor,nor,andn,orn}v x3, x2, x1 Change-Id: I56ae0db72c7f473755cbdc7f7171c1058a9def97 Reviewed-on: https://go-review.googlesource.com/c/go/+/635515 Reviewed-by: Meidan Li <limeidan@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: David Chase <drchase@google.com>
2025-03-06cmd/internal/obj/loong64: add {V,XV}ILV{L/H}.{B/H/W/D} instructions supportXiaolin Zhao
Go asm syntax: VILV{L/H}{B/H/W/V} VK, VJ, VD XVILV{L/H}{B/H/W/V} XK, XJ, XD Equivalent platform assembler syntax: vilv{l/h}.{b/h/w/d} vd, vj, vk xvilv{l/h}.{b/h/w/d} xd, xj, xk Change-Id: I40e21737649d9fdbbc9a423e859f4c0a56d069fb Reviewed-on: https://go-review.googlesource.com/c/go/+/635936 Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Michael Pratt <mpratt@google.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Auto-Submit: Junyang Shao <shaojunyang@google.com>
2025-03-05cmd/internal/obj/loong64: add {V,XV}{ADD/SUB}.{B,H,W,D,Q} and ↵Xiaolin Zhao
{V,XV}{ADD/SUB}.{B,H,W,D}Uinstructions support Go asm syntax: V{ADD/SUB}{B,H,W,V,Q} VK, VJ, VD XV{ADD/SUB}{B,H,W,V,Q} XK, XJ, XD V{ADD/SUB}{B,H,W,V}U $1, VJ, VD XV{ADD/SUB}{B,H,W,V}U $1, XJ, XD Equivalent platform assembler syntax: v{add/sub}.{b,h,w,d,q} vd, vj, vk xv{add/sub}.{b,h,w,d,q} xd, xj, xk v{add/sub}i.{b,h,w,d}u vd, vj, $1 xv{add/sub}i.{b,h,w,d}u xd, xj, $1 Change-Id: Ia1ef0bc062f4403bb0b1514c2cf1c0264f5d22ee Reviewed-on: https://go-review.googlesource.com/c/go/+/637795 Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Michael Pratt <mpratt@google.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-03-03cmd/internal/obj/loong64: add F{MAXA/MINA}.{S/D} instructionsXiaolin Zhao
Go asm syntax: F{MAXA/MINA}{F/D} FK, FJ, FD Equivalent platform assembler syntax: f{maxa/mina}.{s/d} fd, fj, fk Ref: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html Change-Id: I6790657d2f36bdf5e6818b6c0aaa48117e782b8d Reviewed-on: https://go-review.googlesource.com/c/go/+/653915 Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Michael Pratt <mpratt@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Junyang Shao <shaojunyang@google.com>
2025-03-03cmd/internal/obj/loong64: add {V,XV}{SLL/SRL/SRA/ROTR}[I].{B/H/W/D} ↵Xiaolin Zhao
instructions support Go asm syntax: V{SLL/SRL/SRA/ROTR}{B/H/W/V} $1, V2, V3 XV{SLL/SRL/SRA/ROTR}{B/H/W/V} $1, X2, X3 V{SLL/SRL/SRA/ROTR}{B/H/W/V} VK, VJ, VD XV{SLL/SRL/SRA/ROTR}{B/H/W/V} XK, XJ, XD Equivalent platform assembler syntax: v{sll/srl/sra/rotr}i.{b/h/w/d} v3, v2, $1 xv{sll/srl/sra/rotr}i.{b/h/w/d} x3, x2, $1 v{sll/srl/sra/rotr}.{b/h/w/d} vd, vj, vk xv{sll/srl/sra/rotr}.{b/h/w/d} xd, xj, xk Change-Id: Ie4f04de1c77491a71688d226f7d91cd1a699ab47 Reviewed-on: https://go-review.googlesource.com/c/go/+/637775 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Michael Pratt <mpratt@google.com>
2025-02-28cmd/internal/obj, cmd/asm: reclassify 32-bit immediate value of loong64limeidan
Change-Id: If9fd257ca0837a8c8597889c4f5ed3d4edc602c1 Reviewed-on: https://go-review.googlesource.com/c/go/+/636995 Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Michael Pratt <mpratt@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-02-27cmd/internal/obj/riscv: implement vector load/store instructionsJoel Sing
Implement vector unit stride, vector strided, vector indexed and vector whole register load and store instructions. The vector unit stride instructions take an optional vector mask register, which if specified must be register V0. If only two operands are given, the instruction is encoded as unmasked. The vector strided and vector indexed instructions also take an optional vector mask register, which if specified must be register V0. If only three operands are given, the instruction is encoded as unmasked. Cq-Include-Trybots: luci.golang.try:gotip-linux-riscv64 Change-Id: I35e43bb8f1cf6ae8826fbeec384b95ac945da50f Reviewed-on: https://go-review.googlesource.com/c/go/+/631937 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Pengcheng Wang <wangpengcheng.pp@bytedance.com>
2025-02-20cmd/internal/obj/loong64: optimize immediate loadinglimeidan
| old | new | | sec/op | sec/op vs base | BinaryTree17 11.08 ± 2% 11.16 ± 1% ~ (p=0.529 n=10) Fannkuch11 2.716 ± 0% 2.737 ± 0% +0.79% (p=0.000 n=10) FmtFprintfEmpty 67.37n ± 0% 66.42n ± 0% -1.41% (p=0.000 n=10) FmtFprintfString 95.28n ± 0% 90.85n ± 0% -4.64% (p=0.000 n=10) FmtFprintfInt 97.69n ± 0% 98.06n ± 0% +0.38% (p=0.000 n=10) FmtFprintfIntInt 149.1n ± 0% 147.4n ± 0% -1.14% (p=0.000 n=10) FmtFprintfPrefixedInt 223.6n ± 0% 196.5n ± 0% -12.10% (p=0.000 n=10) FmtFprintfFloat 290.9n ± 0% 281.6n ± 1% -3.21% (p=0.000 n=10) FmtManyArgs 670.6n ± 0% 642.6n ± 0% -4.18% (p=0.000 n=10) GobDecode 10.26m ± 1% 10.23m ± 1% ~ (p=0.105 n=10) GobEncode 12.09m ± 1% 11.94m ± 1% -1.24% (p=0.000 n=10) Gzip 316.9m ± 0% 315.9m ± 0% -0.32% (p=0.001 n=10) Gunzip 65.48m ± 0% 59.77m ± 0% -8.72% (p=0.000 n=10) HTTPClientServer 70.36µ ± 0% 68.72µ ± 0% -2.34% (p=0.000 n=10) JSONEncode 13.61m ± 1% 13.19m ± 1% -3.13% (p=0.000 n=10) JSONDecode 57.52m ± 1% 54.15m ± 1% -5.86% (p=0.000 n=10) Mandelbrot200 4.577m ± 0% 4.572m ± 0% -0.10% (p=0.002 n=10) GoParse 6.466m ± 0% 6.363m ± 0% -1.58% (p=0.000 n=10) RegexpMatchEasy0_32 89.20n ± 0% 87.72n ± 0% -1.65% (p=0.000 n=10) RegexpMatchEasy0_1K 748.6n ± 0% 907.6n ± 0% +21.22% (p=0.000 n=10) RegexpMatchEasy1_32 94.14n ± 0% 93.81n ± 0% -0.35% (p=0.000 n=10) RegexpMatchEasy1_1K 832.1n ± 0% 953.6n ± 0% +14.59% (p=0.000 n=10) RegexpMatchMedium_32 982.7n ± 0% 1018.0n ± 0% +3.59% (p=0.000 n=10) RegexpMatchMedium_1K 30.51µ ± 0% 30.00µ ± 0% -1.65% (p=0.000 n=10) RegexpMatchHard_32 1.721µ ± 0% 1.664µ ± 0% -3.34% (p=0.000 n=10) RegexpMatchHard_1K 50.76µ ± 0% 50.92µ ± 0% +0.32% (p=0.000 n=10) Revcomp 870.5m ± 0% 710.5m ± 0% -18.38% (p=0.000 n=10) Template 93.18m ± 1% 93.67m ± 1% ~ (p=0.123 n=10) TimeParse 309.2n ± 0% 307.8n ± 0% -0.45% (p=0.000 n=10) TimeFormat 401.5n ± 0% 394.2n ± 0% -1.82% (p=0.000 n=10) geomean 72.73µ 71.70µ -1.41% Change-Id: Id8d342ef3bb82a420434b2b841674683efef67be Reviewed-on: https://go-review.googlesource.com/c/go/+/620737 Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn>
2025-02-20cmd/internal/obj/x86: add support for the endbr64 instruction on amd64Joel Sing
Add support for endbr64, which terminates an indirect branch in 64-bit mode. This is effectively used to mark locations where an indirect branch is permitted to land, when Indirect Branch Tracking (IBT) is enforced on Intel CPUs. Updates #66054 Change-Id: Ib898031711cfaaa6e05c197bfe727ded0bce6f52 Reviewed-on: https://go-review.googlesource.com/c/go/+/649215 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Keith Randall <khr@golang.org> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2025-02-14cmd/internal/obj/riscv: support MOVD with floating point constantsJoel Sing
Currently, we only support loading of values from memory (or other registers). Add floating point constant support to MOVD. This is implemented by storing the floating point constant to a symbol, which is then loaded into the floating point register. Change-Id: I6db242d27f606f0d5d084a3ab93538698d3a4f8c Reviewed-on: https://go-review.googlesource.com/c/go/+/631876 Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-02-14cmd/asm,cmd/internal/obj/riscv: implement vector configuration setting ↵Joel Sing
instructions Implement vector configuration setting instructions (VSETVLI, VSETIVLI, VSETL). These allow the vector length (vl) and vector type (vtype) CSRs to be configured via a single instruction. Unfortunately each instruction has its own dedicated encoding. In the case of VSETVLI/VSETIVLI, the vector type is specified via a series of special operands, which specify the selected element width (E8, E16, E32, E64), the vector register group multiplier (M1, M2, M4, M8, MF2, MF4, MF8), the vector tail policy (TU, TA) and vector mask policy (MU, MA). Note that the order of these special operands matches non-Go assemblers. Partially based on work by Pengcheng Wang <wangpengcheng.pp@bytedance.com>. Cq-Include-Trybots: luci.golang.try:gotip-linux-riscv64 Change-Id: I431f59c1e048a3e84754f0643a963da473a741fe Reviewed-on: https://go-review.googlesource.com/c/go/+/631936 Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2025-02-07cmd/internal/obj/riscv: update references to RISC-V specificationJoel Sing
Update references to version 20240411 of the RISC-V specifications. Reorder and regroup instructions to maintain ordering. Also be consistent with formatting. The instruction encodings table was seemingly missed in CL 616115. Change-Id: I47b7c8538383ff3b0503ba59db570c3d4f0d5653 Reviewed-on: https://go-review.googlesource.com/c/go/+/631935 Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Ian Lance Taylor <iant@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Pengcheng Wang <wangpengcheng.pp@bytedance.com>
2024-11-21cmd/internal/obj/ppc64: support for decimal floating point instructionsJayanth Krishnamurthy jayanth.krishnamurthy@ibm.com
1. Support for decimal arithmetic quad instructions of powerpc: DADDQ, DSUBQ, DMULQ and DDIVQ. 2. Support for decimal compare ordered, unordered, quad instructions of powerpc: DCMPU, DCMPO, DCMPUQ, and DCMPOQ. Change-Id: I32a15a7f0a127b022b1f43d376e0ab0f7e9dd108 Cq-Include-Trybots: luci.golang.try:gotip-linux-ppc64_power10,gotip-linux-ppc64_power8,gotip-linux-ppc64le_power8,gotip-linux-ppc64le_power9,gotip-linux-ppc64le_power10 Reviewed-on: https://go-review.googlesource.com/c/go/+/623036 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Auto-Submit: Paul Murphy <murp@ibm.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Paul Murphy <murp@ibm.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2024-11-13cmd/asm: fix format string so vet doesn't complainKeith Randall
Fixes #70309 Change-Id: I4a3e27e89bdfda66d64f2efbb4c08a5ddde34a52 Reviewed-on: https://go-review.googlesource.com/c/go/+/626040 Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Auto-Submit: Keith Randall <khr@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Russ Cox <rsc@golang.org> Reviewed-by: Keith Randall <khr@golang.org> Reviewed-by: Keith Randall <khr@google.com>
2024-11-13cmd/internal/obj/loong64: add support of VMOVQ and XVMOVQGuoqi Chen
This CL refers to the implementation of ARM64 and adds support for the following types of SIMD instructions: 1. Move general-purpose register to a vector element, e.g.: VMOVQ Rj, <Vd>.<T>[index] <T> can have the following values: B, H, W, V 2. Move vector element to general-purpose register, e.g.: VMOVQ <Vj>.<T>[index], Rd <T> can have the following values: B, BU, H, HU, W, WU, VU 3. Duplicate general-purpose register to vector, e.g.: VMOVQ Rj, <Vd>.<T> <T> can have the following values: B16, H8, W4, V2, B32, H16, W8, V4 4. Move vector, e.g.: XVMOVQ Xj, <Xd>.<T> <T> can have the following values: B16, H8, W4, V2, Q1 5. Move vector element to scalar, e.g.: XVMOVQ Xj, <Xd>.<T>[index] XVMOVQ Xj.<T>[index], Xd <T> can have the following values: W, V 6. Move vector element to vector register, e.g.: VMOVQ <Vn>.<T>[index], Vn.<T> <T> can have the following values: B, H, W, V This CL only adds syntax and doesn't break any assembly that already exists. Change-Id: I7656efac6def54da6c5ae182f39c2a21bfdf92bb Reviewed-on: https://go-review.googlesource.com/c/go/+/616258 Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2024-11-08cmd/asm: use single-instruction forms for all loong64 sign and zero extensionsXiaolin Zhao
8-bit and 16-bit sign extensions and 32-bit zero extensions were realized with left and right shifts before this change. We now support assembling EXTWB, EXTWH and BSTRPICKV, so all three can be done with a single insn respectively. This patch is a copy of CL 479496. Co-authored-by: WANG Xuerui <git@xen0n.name> Change-Id: Iee5741dd9ebb25746f51008f3f6c86704339d615 Reviewed-on: https://go-review.googlesource.com/c/go/+/626195 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: David Chase <drchase@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2024-11-08cmd/internal/obj/loong64: add {V,XV}PCNT.{B,H,W,D} instructions supportGuoqi Chen
Go asm syntax: VPCNT{B,H,W,V} VJ, VD XVPCNT{B,H,W,V} XJ, XD Equivalent platform assembler syntax: vpcnt.{b,w,h,d} vd, vj xvpcnt.{b,w,h,d} xd, xj Change-Id: Icec4446b1925745bc3a0bc3f6397d862953b9098 Reviewed-on: https://go-review.googlesource.com/c/go/+/620736 Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn>
2024-11-07cmd/internal/obj/loong64: add {V,XV}SEQ.{B,H,W,D} instructions supportGuoqi Chen
Go asm syntax: VSEQ{B,H,W,V} VJ, VK, VD XVSEQ{B,H,W,V} XJ, XK, XD Equivalent platform assembler syntax: vseq.{b,w,h,d} vd, vj, vk xvseq.{b,w,h,d} xd, xj, xk Change-Id: Ia87277b12c817ebc41a46f4c3d09f4b76995ff2f Reviewed-on: https://go-review.googlesource.com/c/go/+/616076 Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Qiqi Huang <huangqiqi@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Cherry Mui <cherryyz@google.com>
2024-11-07cmd/internal/obj/loong64: add {V,XV}LD/{V,XV}LDX/{V,XV}ST/{V,XV}STX ↵Guoqi Chen
instructions support This CL adding primitive asm support of Loong64 LSX [1] and LASX [2], by introducing new sets of register V0-V31 (C_VREG), X0-X31 (C_XREG) and 8 new instructions. On Loong64, VLD,XVLD,VST,XVST implement vector memory access operations using immediate values offset. VLDX, XVLDX, VSTX, XVSTX implement vector memory access operations using register offset. Go asm syntax: VMOVQ n(RJ), RV (128bit vector load) XVMOVQ n(RJ), RX (256bit vector load) VMOVQ RV, n(RJ) (128bit vector store) XVMOVQ RX, n(RJ) (256bit vector store) VMOVQ (RJ)(RK), RV (128bit vector load) XVMOVQ (RJ)(RK), RX (256bit vector load) VMOVQ RV, (RJ)(RK) (128bit vector store) XVMOVQ RX, (RJ)(RK) (256bit vector store) Equivalent platform assembler syntax: vld vd, rj, si12 xvld xd, rj, si12 vst vd, rj, si12 xvst xd, rj, si12 vldx vd, rj, rk xvldx xd, rj, rk vstx vd, rj, rk xvstx xd, rj, rk [1]: LSX: Loongson SIMD Extension, 128bit [2]: LASX: Loongson Advanced SIMD Extension, 256bit Change-Id: Ibaf5ddfd29b77670c3c44cc32bead36b2c8b8003 Reviewed-on: https://go-review.googlesource.com/c/go/+/616075 Reviewed-by: Qiqi Huang <huangqiqi@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2024-11-02cmd/asm: add support for loong64 FMA instructionsXiaolin Zhao
Add support for assembling the FMA instructions present in the LoongArch base ISA v1.00. This requires adding a new instruction format and making use of a third source operand, which is put in RestArgs[0]. The single-precision instructions have the `.s` prefix in their official mnemonics, and similar Go asm instructions all have `S` prefix for the other architectures having FMA support, but in this change they instead have `F` prefix in Go asm because loong64 currently follows the mips backends in the naming convention. This could be changed later because FMA is fully expressible in pure Go, making it unlikely to have to hand- write such assembly in the wild. Example mapping between actual encoding and Go asm syntax: fmadd.s fd, fj, fk, fa -> FMADDF fa, fk, fj, fd (prog.From = fa, prog.Reg = fk, prog.RestArgs[0] = fj and prog.To = fd) fmadd.s fd, fd, fk, fa -> FMADDF fa, fk, fd (prog.From = fa, prog.Reg = fk and prog.To = fd) This patch is a copy of CL 477716. Co-authored-by: WANG Xuerui <git@xen0n.name> Change-Id: I9b4e4c601d6c5a854ee238f085849666e4faf090 Reviewed-on: https://go-review.googlesource.com/c/go/+/623877 Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Carlos Amedee <carlos@golang.org>
2024-11-01cmd/asm: add support for loong64 CRC32 instructionsXiaolin Zhao
This patch is a copy of CL 478595. Co-authored-by: WANG Xuerui <git@xen0n.name> Change-Id: Ifb6e8183c83a5dfe5dec84e173a74d5de62692a0 Reviewed-on: https://go-review.googlesource.com/c/go/+/623875 Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Michael Pratt <mpratt@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2024-11-01cmd/asm: add support for the rest of loong64 unary bitopsXiaolin Zhao
All remaining unary bitop instructions in the LoongArch v1.00 base ISA are added with this change. While at it, add the missing W suffix to the current CLO/CLZ names. They are not used anywhere as far as we know, so no breakage is expected. Also, stop reusing SLL's instruction format for simplicity, in favor of a new but trivial instruction format case. This patch is a copy of CL 477717. Co-authored-by: WANG Xuerui <git@xen0n.name> Change-Id: Idbcaca25dda1ed313674ef8b26da722e8d7151c0 Reviewed-on: https://go-review.googlesource.com/c/go/+/623876 Reviewed-by: abner chenc <chenguoqi@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Cherry Mui <cherryyz@google.com>
2024-10-29cmd/internal/obj/ppc64: support for extended mnemonics of BCJayanth Krishnamurthy
BGT, BLT, BLE, BGE, BNE, BVS, BVC, and BEQ support by assembler. This will simplify the usage of BC constructs like BC 12, 30, LR <=> BEQ CR7, LR BC 12, 2, LR <=> BEQ CR0, LR BC 12, 0, target <=> BLT CR0, target BC 12, 2, target <=> BEQ CR0, target BC 12, 5, target <=> BGT CR1, target BC 12, 30, target <=> BEQ CR7, target BC 4, 6, target <=> BNE CR1, target BC 4, 5, target <=> BLE CR1, target code cleanup based on the above additions. Change-Id: I02fdb212b6fe3f85ce447e05f4d42118c9ce63b5 Cq-Include-Trybots: luci.golang.try:gotip-linux-ppc64_power10,gotip-linux-ppc64_power8,gotip-linux-ppc64le_power8,gotip-linux-ppc64le_power9,gotip-linux-ppc64le_power10 Reviewed-on: https://go-review.googlesource.com/c/go/+/612395 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Paul Murphy <murp@ibm.com> Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Michael Pratt <mpratt@google.com>
2024-10-29cmd/internal/obj/ppc64: add double-decimal arithmetic instructionsJayanth Krishnamurthy
Assembler support provided for the instructions DADD, DSUB, DMUL, and DDIV. Change-Id: Ic12ba02ce453cb1ca275334ca1924fb2009da767 Reviewed-on: https://go-review.googlesource.com/c/go/+/620856 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Paul Murphy <murp@ibm.com> Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2024-10-25cmd/internal/obj/riscv: update references to RISC-V specificationJoel Sing
Update references to version 20240411 of the RISC-V specifications. Reorder and regroup instructions to maintain ordering. Change-Id: Iea2a5d22ad677e04948e9a9325986ad301c03f35 Reviewed-on: https://go-review.googlesource.com/c/go/+/616115 Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: David Chase <drchase@google.com>
2024-10-24cmd/internal/obj,cmd/asm: add vector registers to riscv64 assemblerJoel Sing
This adds V0 through V31 as vector registers, which are available on CPUs that support the V extension. Change-Id: Ibffee3f9a2cf1d062638715b3744431d72d451ce Reviewed-on: https://go-review.googlesource.com/c/go/+/595404 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Michael Pratt <mpratt@google.com> Reviewed-by: 鹏程汪 <wangpengcheng.pp@bytedance.com>
2024-10-23cmd/asm: add support for LDREXB/STREXBMauri de Souza Meneguzzo
These are 8-bit ARM Load/Store atomics and are available starting from armv6k. See https://developer.arm.com/documentation/dui0379/e/arm-and-thumb-instructions/strex For #69735 Change-Id: I12623433c89070495c178208ee4758b3cdefd368 GitHub-Last-Rev: d6a797836af1dccdcc6e6554725546b386d01615 GitHub-Pull-Request: golang/go#69959 Cq-Include-Trybots: luci.golang.try:gotip-linux-arm Reviewed-on: https://go-review.googlesource.com/c/go/+/621395 Reviewed-by: Keith Randall <khr@google.com> Reviewed-by: Keith Randall <khr@golang.org> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2024-10-21cmd/asm: add position to PCALIGN directivesPaul E. Murphy
This allows PCALIGN to be used in the end-to-end assembly tests without causing an error due to missing file position. Change-Id: Iadea2875854ffd544a963acd21293dc9840da2d0 Reviewed-on: https://go-review.googlesource.com/c/go/+/620635 Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2024-09-18cmd/internal/obj/s390x: fix m6 field encoding for VSTRC instruction on s390xSrinivas Pokala
M6 field for all extended mnemonics of VSTRC set to zero This fixes VSTRC codegen to emit correctly and added testcases for all the extended mnemonics. Fixes #69216 Change-Id: I2a1b7fb61d6bd6444286eab56a506225c90b75e7 Reviewed-on: https://go-review.googlesource.com/c/go/+/612315 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Vishwanatha HD <vishwanatha.hd@ibm.com> Reviewed-by: Carlos Amedee <carlos@golang.org>
2024-09-13cmd/internal/obj/loong64: add support for instructions FSCALEB{F/D} and ↵Xiaolin Zhao
FLOGB{F/D} Go asm syntax: FSCALEB{F/D} FK, FJ, FD FLOGB{F/D} FJ, FD Equivalent platform assembler syntax: fscaleb.{s/d} fd, fj, fk flogb.{s/d} fd, fj Ref: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html Change-Id: I6cd75c7605adbb572dae86d6470ec7cf20ce0f6c Reviewed-on: https://go-review.googlesource.com/c/go/+/612975 Auto-Submit: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Tim King <taking@google.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: abner chenc <chenguoqi@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2024-09-12cmd/compile,cmd/internal/obj/riscv: always provide ANDN, ORN and XNOR for ↵Joel Sing
riscv64 The ANDN, ORN and XNOR RISC-V Zbb extension instructions are easily synthesised. Make them always available by adding support to the riscv64 assembler so that we either emit two instruction sequences, or a single instruction, when permitted by the GORISCV64 profile. This means that these instructions can be used unconditionally, simplifying compiler rewrite rules, codegen tests and manually written assembly. Around 180 instructions are removed from the Go binary on riscv64 when built with rva22u64. Change-Id: Ib2d90f2593a306530dc0ed08a981acde4d01be20 Reviewed-on: https://go-review.googlesource.com/c/go/+/611895 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Tim King <taking@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2024-09-06cmd/asm/internal: use slices.ContainsTobias Klauser
Now that Go 1.22.6 is the minimum bootstrap toolchain (cf. CL 606156), the slices package (introduced in Go 1.21) can be used in packages built using the bootstrap toolchain. For #64751 Change-Id: I0115213da4b1f0a1fa0ef7ad34456fbf52e00fae Reviewed-on: https://go-review.googlesource.com/c/go/+/611095 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Auto-Submit: Tobias Klauser <tobias.klauser@gmail.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2024-09-05cmd/internal/obj/loong64: add support for instructions ANDN and ORNXiaolin Zhao
Go asm syntax: ANDN/ORN RK, RJ, RD or ANDN/ORN RK, RD Equivalent platform assembler syntax: andn/orn rd, rj, rk or andn/orn rd, rd, rk Ref: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html Change-Id: I6d240ecae8f9443811ca450aed3574f13f0f4a81 Reviewed-on: https://go-review.googlesource.com/c/go/+/610475 Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Commit-Queue: abner chenc <chenguoqi@loongson.cn> Reviewed-by: abner chenc <chenguoqi@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Auto-Submit: abner chenc <chenguoqi@loongson.cn>
2024-09-04all: fix printf(var) mistakes detected by latest printf checkerAlan Donovan
These will cause build failures once we vendor x/tools. In once case I renamed a function err to errf to indicate that it is printf-like. Updates golang/go#68796 Change-Id: I04d57b34ee5362f530554b7e8b817f70a9088d12 Reviewed-on: https://go-review.googlesource.com/c/go/+/610739 Commit-Queue: Alan Donovan <adonovan@google.com> Reviewed-by: Robert Findley <rfindley@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Tim King <taking@google.com> Auto-Submit: Alan Donovan <adonovan@google.com>
2024-08-23cmd/internal/obj/loong64: add support for instructions BSTRPICK.{W/D} and ↵Xiaolin Zhao
BSTRINS.{W/D} Go asm syntax: BSTRPICK{W/V} $msb, RJ, $lsb, RD BSTRINS{W/V} $msb, RJ, $lsb, RD Equivalent platform assembler syntax: bstrpick.{w/d} rd, rj, $msb, $lsb bstrins.{w/d} rd, rj, $msb, $lsb Ref: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html Change-Id: I8b89b766ed22a96da7d8d5b2b2873382a49208de Reviewed-on: https://go-review.googlesource.com/c/go/+/604735 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2024-08-03cmd/internal/obj/loong64: add FLDX,FSTX,LDX.STX instructions supportGuoqi Chen
The LDX.{B,BU,H,HU,W,WU,D},STX.{B,H,W,D}, FLDX.{S,D}, FSTX.{S,D} instruction on Loong64 implements memory access operations using register offset Go asm syntax: MOV{B,BU,H,HU,W,WU,V} (RJ)(RK), RD MOV{B,H,W,V} RD, (RJ)(RK) MOV{F,D} (RJ)(RK), FD MOV{F,D} FD, (RJ)(RK) Equivalent platform assembler syntax: ldx.{b,bu,h,hu,w,wu,d} rd, rj, rk stx.{b,h,w,d} rd, rj, rk fldx.{s,d} fd, rj, rk fstx.{s,d} fd, rj, rk Ref: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html Change-Id: Ic7d13bf45dab8342f034b6469465e6337a087144 Reviewed-on: https://go-review.googlesource.com/c/go/+/588215 Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Qiqi Huang <huangqiqi@loongson.cn> Reviewed-by: Meidan Li <limeidan@loongson.cn> Auto-Submit: abner chenc <chenguoqi@loongson.cn>
2024-08-03cmd/internal/obj/loong64: add support for instructions ↵Xiaolin Zhao
FTINT{RM/RP/RZ/RNE}.{W/L}.{S/D} These instructions convert floating-point numbers to fixed-point numbers with the specified rounding pattern. Go asm syntax: FTINT{RM/RP/RZ/RNE}{W/V}{F/D} FJ, FD Equivalent platform assembler syntax: ftint{rm/rp/rz/rne}.{w/l}.{s/d} fd, fj Ref: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html Change-Id: I6d650d1b48b10296d01a98fadf9d806206f9b96e Reviewed-on: https://go-review.googlesource.com/c/go/+/590995 Auto-Submit: abner chenc <chenguoqi@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Qiqi Huang <huangqiqi@loongson.cn>
2024-08-03cmd/internal/obj/loong64: add support for instructions FFINT.{S/D}.{W/L} and ↵Xiaolin Zhao
FTINT.{W/L}.{S/D} Go asm syntax: FFINT{F/D}{W/V} FJ, FD FTINT{W/V}{F/D} FJ, FD Equivalent platform assembler syntax: ffint.{s/d}.{w/l} fd, fj ftint.{w/l}.{s/d} fd, fj Ref: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html Change-Id: Ie7646c5d49645c63b274b34b66539f10370f4930 Reviewed-on: https://go-review.googlesource.com/c/go/+/590996 Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Auto-Submit: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Qiqi Huang <huangqiqi@loongson.cn> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2024-08-03cmd/internal/obj/loong64: add support for instructions FCOPYSIGN.{S/D} and ↵Xiaolin Zhao
FCLASS.{S/D} Go asm syntax: FCOPYSG{F/D} FK, FJ, FD FCLASSF{F/D} FJ, FD Equivalent platform assembler syntax: fcopysign.{s/d} fd, fj, fk fclass.{s/d} fd, fj Ref: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html Change-Id: Ied34b71c9d0b34456ac5782a59d29d2d0229e326 Reviewed-on: https://go-review.googlesource.com/c/go/+/590675 Reviewed-by: Cherry Mui <cherryyz@google.com> Auto-Submit: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2024-08-02cmd/internal/obj/loong64: add support for instructions F{MAX/NIN}.{S/D}Xiaolin Zhao
Go asm syntax: F{MAX/MIN}{F/D} FK, FJ, FD Equivalent platform assembler syntax: f{max/min}.{s/d} fd, fj, fk Ref: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html Change-Id: Ib11fed1fe3700be5ebba33b5818661c4071b7b7c Reviewed-on: https://go-review.googlesource.com/c/go/+/590676 Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Auto-Submit: abner chenc <chenguoqi@loongson.cn>
2024-08-02cmd/internal/obj/loong64: add support for MOV{GR2FCSR/FCSR2GR/FR2CF/CF2FR} ↵Xiaolin Zhao
instructions Go asm syntax example: MOVV R4, FCSR0 MOVV FCSR1, R5 MOVV F4, FCC0 MOVV FCC1, F5 Equivalent platform assembler syntax: movgr2fcsr fcsr0, r4 movfcsr2gr r5, fcsr1 movfr2cf fcc0, f4 movcf2fr f5, fcc1 Ref: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html This change also merges the case of floating point move instructions and add checks for the range of special registers. Change-Id: Ib08fbce83e7a31dc0ab4857bf9ba959855241d1c Reviewed-on: https://go-review.googlesource.com/c/go/+/580279 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2024-07-30cmd/internal/obj/loong64, cmd/asm: remove useless instructionslimeidan
Change-Id: I180c40898672a757d72cd0ef38e6e8cc20dc4c3d Reviewed-on: https://go-review.googlesource.com/c/go/+/565618 Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Qiqi Huang <huangqiqi@loongson.cn> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Cherry Mui <cherryyz@google.com>
2024-07-29cmd/internal/obj/loong64, cmd/asm: remove invalid optab itemslimeidan
Cases 27 and 28 are used to handle floating point operations, MOVW is usually used for integer processing, and, in two cases there is code like this: a :=AMOVF if p.As == AMOVD { a=AMOVD } This means that MOVW was eventually replaced by MOVF, so removed MOVW from cases 27 and 28. Change-Id: Ib438febab88058e98b569e0dfe70b8610668ee31 Reviewed-on: https://go-review.googlesource.com/c/go/+/565622 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Qiqi Huang <huangqiqi@loongson.cn> Auto-Submit: abner chenc <chenguoqi@loongson.cn> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2024-07-29cmd/asm: change register type for loong64 floating-pointXiaolin Zhao
On Loong64, the two input operands and one output operand of the ADDF instruction are both floating-point registers; and the floating-point comparison instruction CMPEQ{F,D}, CMPGE{F,D}, CMPGT{F,D} both input operands are floating-point registers, and the output operation is a floating-point condition register, currently, only FCC0 is used as the floating-point condition register. Example: ADDF F0, F1, F0 CMPEQF F0, F1, FCC0 Change-Id: I4c1c453e522d43f294a8dcab7b6b5247f41c9c68 Reviewed-on: https://go-review.googlesource.com/c/go/+/580281 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Auto-Submit: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Michael Knyszek <mknyszek@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2024-07-27cmd/internal/obj/loong64: add CPUCFG instructions supportGuoqi Chen
The CPUCFG instruction is used to dynamically obtain the features supported by the current CPU during the running of the program. Go asm syntax: CPUCFG RJ, RD Equivalent platform assembler syntax: cpucfg rd, rj Reference: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html Change-Id: I545110ff837ae9c5ccd7c448a1daf2d1277f9aa1 Reviewed-on: https://go-review.googlesource.com/c/go/+/493436 Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Qiqi Huang <huangqiqi@loongson.cn> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2024-07-24cmd/internal/obj/arm64: support MSR DITRoland Shoemaker
Set the right instruction bits in asmout in order to allow using MSR with DIT and an immediate value. This allows us to avoid using an intermediary register when we want to set DIT (unsetting DIT already worked with the zero register). Ref: https://developer.arm.com/documentation/ddi0602/2024-06/Base-Instructions/MSR--immediate---Move-immediate-value-to-special-register-?lang=en Change-Id: Id049a0b4e0feb534cea992553228f9b5e12ddcea Reviewed-on: https://go-review.googlesource.com/c/go/+/597595 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2024-06-25cmd/internal/obj/arm64: fix return with registerJoel Sing
ARM64 allows for a register to be specified with a return instruction. While the assembler parsing and encoding currently supports this, the preprocess function uses LR unconditionally. Correct this such that if a register is specified, the register is used. Change-Id: I708f6c7e910d141559b60d2d5ee76ae2e1dc3a0e Reviewed-on: https://go-review.googlesource.com/c/go/+/592796 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: David Chase <drchase@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2024-06-21cmd/internal: separate counter package from telemetry packageMichael Matloob
Move the code that opens and increments counters out of the cmd/internal/telemetry package into cmd/internal/telemetry/counter. The telemetry package has dependencies on the upload code, which we do not want to pull into the rest of the go toolchain. For #68109 Change-Id: I463c106819b169177a783de4a7d93377e81f4e3e Reviewed-on: https://go-review.googlesource.com/c/go/+/593976 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Robert Findley <rfindley@google.com>
2024-06-13cmd/go: call telemetry.MaybeChild at start of go commandMichael Matloob
Call the new telemetry.MaybeChild function at the start of the go command so that the child process logic can be run immediately without running toolchain selection if this is the child process. The Start function in the telemetry shim package has been renamed to OpenCounters to make it clear that that's its only function. The StartWithUpload function in the telemetry shim package has been renamed to MaybeParent because that's its actual effective behavior in cmd/go, the only place it's called: it won't run as the child because MaybeChild has already been called and would have run as the child if the program was the telemetry child, and it won't open counters because telemetry.Start has been called. Checks are added that those functions are always called before so that the function name and comment are accurate. It might make sense to add a true telemetry.MaybeParent function that doesn't try to start the child or open counters to make things a little simpler. Change-Id: Ie81e2418af85cef18ec41f75db66365f6597b8b1 Reviewed-on: https://go-review.googlesource.com/c/go/+/592535 Reviewed-by: Robert Findley <rfindley@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
generated by cgit v1.3-5-g9baa (git 2.53.0) at 2026-04-17 09:13:29 +0000