cmd/internal/obj/riscv: implement vector load/store instructions

Implement vector unit stride, vector strided, vector indexed and
vector whole register load and store instructions.

The vector unit stride instructions take an optional vector mask
register, which if specified must be register V0. If only two
operands are given, the instruction is encoded as unmasked.

The vector strided and vector indexed instructions also take an
optional vector mask register, which if specified must be register
V0. If only three operands are given, the instruction is encoded as
unmasked.

Cq-Include-Trybots: luci.golang.try:gotip-linux-riscv64
Change-Id: I35e43bb8f1cf6ae8826fbeec384b95ac945da50f
Reviewed-on: https://go-review.googlesource.com/c/go/+/631937
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
Reviewed-by: Michael Knyszek <mknyszek@google.com>
Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
Reviewed-by: Pengcheng Wang <wangpengcheng.pp@bytedance.com>

2 files changed, 137 insertions, 0 deletions

diff --git a/src/cmd/asm/internal/asm/testdata/riscv64.s b/src/cmd/asm/internal/asm/testdata/riscv64.s
index fc44f561f2..5aa2563b6f 100644
--- a/src/cmd/asm/internal/asm/testdata/riscv64.s
+++ b/src/cmd/asm/internal/asm/testdata/riscv64.s
@@ -448,6 +448,104 @@ start:
 	VSETIVLI $31, E32, M1, TA, MA, X12		// 57f60fcd
 	VSETVL	X10, X11, X12				// 57f6a580
 
+	// 31.7.4: Vector Unit-Stride Instructions
+	VLE8V		(X10), V3			// 87010502
+	VLE8V		(X10), V0, V3			// 87010500
+	VLE16V		(X10), V3			// 87510502
+	VLE16V		(X10), V0, V3			// 87510500
+	VLE32V		(X10), V3			// 87610502
+	VLE32V		(X10), V0, V3			// 87610500
+	VLE64V		(X10), V3			// 87710502
+	VLE64V		(X10), V0, V3			// 87710500
+	VSE8V		V3, (X10)			// a7010502
+	VSE8V		V3, V0, (X10)			// a7010500
+	VSE16V		V3, (X10)			// a7510502
+	VSE16V		V3, V0, (X10)			// a7510500
+	VSE32V		V3, (X10)			// a7610502
+	VSE32V		V3, V0, (X10)			// a7610500
+	VSE64V		V3, (X10)			// a7710502
+	VSE64V		V3, V0, (X10)			// a7710500
+	VLMV		(X10), V3			// 8701b502
+	VSMV		V3, (X10)			// a701b502
+
+	// 31.7.5: Vector Strided Instructions
+	VLSE8V		(X10), X11, V3			// 8701b50a
+	VLSE8V		(X10), X11, V0, V3		// 8701b508
+	VLSE16V		(X10), X11, V3			// 8751b50a
+	VLSE16V		(X10), X11, V0, V3		// 8751b508
+	VLSE32V		(X10), X11, V3			// 8761b50a
+	VLSE32V		(X10), X11, V0, V3		// 8761b508
+	VLSE64V		(X10), X11, V3			// 8771b50a
+	VLSE64V		(X10), X11, V0, V3		// 8771b508
+	VSSE8V		V3, X11, (X10)			// a701b50a
+	VSSE8V		V3, X11, V0, (X10)		// a701b508
+	VSSE16V		V3, X11, (X10)			// a751b50a
+	VSSE16V		V3, X11, V0, (X10)		// a751b508
+	VSSE32V		V3, X11, (X10)			// a761b50a
+	VSSE32V		V3, X11, V0, (X10)		// a761b508
+	VSSE64V		V3, X11, (X10)			// a771b50a
+	VSSE64V		V3, X11, V0, (X10)		// a771b508
+
+	// 31.7.6: Vector Indexed Instructions
+	VLUXEI8V	(X10), V2, V3			// 87012506
+	VLUXEI8V	(X10), V2, V0, V3		// 87012504
+	VLUXEI16V	(X10), V2, V3			// 87512506
+	VLUXEI16V	(X10), V2, V0, V3		// 87512504
+	VLUXEI32V	(X10), V2, V3			// 87612506
+	VLUXEI32V	(X10), V2, V0, V3		// 87612504
+	VLUXEI64V	(X10), V2, V3			// 87712506
+	VLUXEI64V	(X10), V2, V0, V3		// 87712504
+	VLOXEI8V	(X10), V2, V3			// 8701250e
+	VLOXEI8V	(X10), V2, V0, V3		// 8701250c
+	VLOXEI16V	(X10), V2, V3			// 8751250e
+	VLOXEI16V	(X10), V2, V0, V3		// 8751250c
+	VLOXEI32V	(X10), V2, V3			// 8761250e
+	VLOXEI32V	(X10), V2, V0, V3		// 8761250c
+	VLOXEI64V	(X10), V2, V3			// 8771250e
+	VLOXEI64V	(X10), V2, V0, V3		// 8771250c
+	VSUXEI8V	V3, V2, (X10)			// a7012506
+	VSUXEI8V	V3, V2, V0, (X10)		// a7012504
+	VSUXEI16V	V3, V2, (X10)			// a7512506
+	VSUXEI16V	V3, V2, V0, (X10)		// a7512504
+	VSUXEI32V	V3, V2, (X10)			// a7612506
+	VSUXEI32V	V3, V2, V0, (X10)		// a7612504
+	VSUXEI64V	V3, V2, (X10)			// a7712506
+	VSUXEI64V	V3, V2, V0, (X10)		// a7712504
+	VSOXEI8V	V3, V2, (X10)			// a701250e
+	VSOXEI8V	V3, V2, V0, (X10)		// a701250c
+	VSOXEI16V	V3, V2, (X10)			// a751250e
+	VSOXEI16V	V3, V2, V0, (X10)		// a751250c
+	VSOXEI32V	V3, V2, (X10)			// a761250e
+	VSOXEI32V	V3, V2, V0, (X10)		// a761250c
+	VSOXEI64V	V3, V2, (X10)			// a771250e
+	VSOXEI64V	V3, V2, V0, (X10)		// a771250c
+
+	// 31.7.9: Vector Load/Store Whole Register Instructions
+	VL1RV		(X10), V3			// 87018502
+	VL1RE8V		(X10), V3			// 87018502
+	VL1RE16V	(X10), V3			// 87518502
+	VL1RE32V	(X10), V3			// 87618502
+	VL1RE64V	(X10), V3			// 87718502
+	VL2RV		(X10), V2			// 07018522
+	VL2RE8V		(X10), V2			// 07018522
+	VL2RE16V	(X10), V2			// 07518522
+	VL2RE32V	(X10), V2			// 07618522
+	VL2RE64V	(X10), V2			// 07718522
+	VL4RV		(X10), V4			// 07028562
+	VL4RE8V		(X10), V4			// 07028562
+	VL4RE16V	(X10), V4			// 07528562
+	VL4RE32V	(X10), V4			// 07628562
+	VL4RE64V	(X10), V4			// 07728562
+	VL8RV		(X10), V8			// 070485e2
+	VL8RE8V		(X10), V8			// 070485e2
+	VL8RE16V	(X10), V8			// 075485e2
+	VL8RE32V	(X10), V8			// 076485e2
+	VL8RE64V	(X10), V8			// 077485e2
+	VS1RV		V3, (X11)			// a7818502
+	VS2RV		V2, (X11)			// 27818522
+	VS4RV		V4, (X11)			// 27828562
+	VS8RV		V8, (X11)			// 278485e2
+
 	//
 	// Privileged ISA
 	//
diff --git a/src/cmd/asm/internal/asm/testdata/riscv64error.s b/src/cmd/asm/internal/asm/testdata/riscv64error.s
index a90f22af9f..82a2348894 100644
--- a/src/cmd/asm/internal/asm/testdata/riscv64error.s
+++ b/src/cmd/asm/internal/asm/testdata/riscv64error.s
@@ -50,4 +50,43 @@ TEXT errors(SB),$0
 	VSETVLI	$-1, E32, M2, TA, MA, X12	// ERROR "must be in range [0, 31] (5 bits)"
 	VSETIVLI X10, E32, M2, TA, MA, X12	// ERROR "expected immediate value"
 	VSETVL	X10, X11			// ERROR "expected integer register in rs1 position"
+	VLE8V	(X10), X10			// ERROR "expected vector register in rd position"
+	VLE8V	(V1), V3			// ERROR "expected integer register in rs1 position"
+	VLE8V	(X10), V1, V3			// ERROR "invalid vector mask register"
+	VSE8V	X10, (X10)			// ERROR "expected vector register in rs1 position"
+	VSE8V	V3, (V1)			// ERROR "expected integer register in rd position"
+	VSE8V	V3, V1, (X10)			// ERROR "invalid vector mask register"
+	VLSE8V	(X10), V3			// ERROR "expected integer register in rs2 position"
+	VLSE8V	(X10), X10, X11			// ERROR "expected vector register in rd position"
+	VLSE8V	(V1), X10, V3			// ERROR "expected integer register in rs1 position"
+	VLSE8V	(X10), V1, V0, V3		// ERROR "expected integer register in rs2 position"
+	VLSE8V	(X10), X10, V1, V3		// ERROR "invalid vector mask register"
+	VSSE8V	V3, (X10)			// ERROR "expected integer register in rs2 position"
+	VSSE8V	X10, X11, (X10)			// ERROR "expected vector register in rd position"
+	VSSE8V	V3, X11, (V1)			// ERROR "expected integer register in rs1 position"
+	VSSE8V	V3, V1, V0, (X10)		// ERROR "expected integer register in rs2 position"
+	VSSE8V	V3, X11, V1, (X10)		// ERROR "invalid vector mask register"
+	VLUXEI8V (X10), V2, X11			// ERROR "expected vector register in rd position"
+	VLUXEI8V (X10), V2, X11			// ERROR "expected vector register in rd position"
+	VLUXEI8V (V1), V2, V3			// ERROR "expected integer register in rs1 position"
+	VLUXEI8V (X10), X11, V0, V3		// ERROR "expected vector register in rs2 position"
+	VLUXEI8V (X10), V2, V1, V3		// ERROR "invalid vector mask register"
+	VSUXEI8V X10, V2, (X10)			// ERROR "expected vector register in rd position"
+	VSUXEI8V V3, V2, (V1)			// ERROR "expected integer register in rs1 position"
+	VSUXEI8V V3, X11, V0, (X10)		// ERROR "expected vector register in rs2 position"
+	VSUXEI8V V3, V2, V1, (X10)		// ERROR "invalid vector mask register"
+	VLOXEI8V (X10), V2, X11			// ERROR "expected vector register in rd position"
+	VLOXEI8V (V1), V2, V3			// ERROR "expected integer register in rs1 position"
+	VLOXEI8V (X10), X11, V0, V3		// ERROR "expected vector register in rs2 position"
+	VLOXEI8V (X10), V2, V1, V3		// ERROR "invalid vector mask register"
+	VSOXEI8V X10, V2, (X10)			// ERROR "expected vector register in rd position"
+	VSOXEI8V V3, V2, (V1)			// ERROR "expected integer register in rs1 position"
+	VSOXEI8V V3, X11, V0, (X10)		// ERROR "expected vector register in rs2 position"
+	VSOXEI8V V3, V2, V1, (X10)		// ERROR "invalid vector mask register"
+	VL1RV	(X10), V0, V3			// ERROR "too many operands for instruction"
+	VL1RV	(X10), X10			// ERROR "expected vector register in rd position"
+	VL1RV	(V1), V3			// ERROR "expected integer register in rs1 position"
+	VS1RV	V3, V0, (X11)			// ERROR "too many operands for instruction"
+	VS1RV	X11, (X11)			// ERROR "expected vector register in rs1 position"
+	VS1RV	V3, (V1)			// ERROR "expected integer register in rd position"
 	RET