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| author | Xiaolin Zhao <zhaoxiaolin@loongson.cn> | 2024-04-03 15:13:04 +0800 |
|---|---|---|
| committer | Gopher Robot <gobot@golang.org> | 2024-07-29 02:47:00 +0000 |
| commit | f95ae3d68989505fcac9ec23cacc03d602ec6739 (patch) | |
| tree | 47486a96eafcdcf29411b1a6dc66df726dc0efcc /src/cmd/asm | |
| parent | aec5cc52add9d8da0b5ac4e51758d10ee35589db (diff) | |
| download | go-f95ae3d68989505fcac9ec23cacc03d602ec6739.tar.xz | |
cmd/asm: change register type for loong64 floating-point
On Loong64, the two input operands and one output operand of the ADDF
instruction are both floating-point registers; and the floating-point
comparison instruction CMPEQ{F,D}, CMPGE{F,D}, CMPGT{F,D} both input
operands are floating-point registers, and the output operation is a
floating-point condition register, currently, only FCC0 is used as the
floating-point condition register.
Example:
ADDF F0, F1, F0
CMPEQF F0, F1, FCC0
Change-Id: I4c1c453e522d43f294a8dcab7b6b5247f41c9c68
Reviewed-on: https://go-review.googlesource.com/c/go/+/580281
Reviewed-by: Cherry Mui <cherryyz@google.com>
Reviewed-by: abner chenc <chenguoqi@loongson.cn>
Auto-Submit: abner chenc <chenguoqi@loongson.cn>
Reviewed-by: Michael Knyszek <mknyszek@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Diffstat (limited to 'src/cmd/asm')
| -rw-r--r-- | src/cmd/asm/internal/arch/loong64.go | 11 | ||||
| -rw-r--r-- | src/cmd/asm/internal/asm/asm.go | 6 | ||||
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/loong64enc1.s | 14 |
3 files changed, 7 insertions, 24 deletions
diff --git a/src/cmd/asm/internal/arch/loong64.go b/src/cmd/asm/internal/arch/loong64.go index bf34a94f07..48a62c4952 100644 --- a/src/cmd/asm/internal/arch/loong64.go +++ b/src/cmd/asm/internal/arch/loong64.go @@ -21,17 +21,6 @@ func jumpLoong64(word string) bool { return false } -// IsLoong64CMP reports whether the op (as defined by an loong64.A* constant) is -// one of the CMP instructions that require special handling. -func IsLoong64CMP(op obj.As) bool { - switch op { - case loong64.ACMPEQF, loong64.ACMPEQD, loong64.ACMPGEF, loong64.ACMPGED, - loong64.ACMPGTF, loong64.ACMPGTD: - return true - } - return false -} - // IsLoong64MUL reports whether the op (as defined by an loong64.A* constant) is // one of the MUL/DIV/REM instructions that require special handling. func IsLoong64MUL(op obj.As) bool { diff --git a/src/cmd/asm/internal/asm/asm.go b/src/cmd/asm/internal/asm/asm.go index b2eaa0a28d..bdbb3e17e0 100644 --- a/src/cmd/asm/internal/asm/asm.go +++ b/src/cmd/asm/internal/asm/asm.go @@ -642,12 +642,6 @@ func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) { break } } else if p.arch.Family == sys.Loong64 { - if arch.IsLoong64CMP(op) { - prog.From = a[0] - prog.Reg = p.getRegister(prog, op, &a[1]) - break - } - if arch.IsLoong64RDTIME(op) { // The Loong64 RDTIME family of instructions is a bit special, // in that both its register operands are outputs diff --git a/src/cmd/asm/internal/asm/testdata/loong64enc1.s b/src/cmd/asm/internal/asm/testdata/loong64enc1.s index a98fca08aa..a45ef88150 100644 --- a/src/cmd/asm/internal/asm/testdata/loong64enc1.s +++ b/src/cmd/asm/internal/asm/testdata/loong64enc1.s @@ -53,8 +53,7 @@ lable2: CLZ R4, R5 // 85140000 CPUCFG R4, R5 // 856c0000 ADDF F4, F5 // a5900001 - ADDF F4, R5, F6 // a6900001 - CMPEQF F4, R5 // a010120c + ADDF F4, F5, F6 // a6900001 ABSF F4, F5 // 85041401 MOVVF F4, F5 // 85181d01 MOVF F4, F5 // 85941401 @@ -220,11 +219,12 @@ lable2: MOVWR y+8(FP), R4 // 6440402e MOVWR 1(R5), R4 // a404402e - CMPGTF F4, R5 // a090110c - CMPGTD F4, R5 // a090210c - CMPGEF F4, R5 // a090130c - CMPGED F4, R5 // a090230c - CMPEQD F4, R5 // a010220c + CMPEQF F4, F5, FCC0 // a010120c + CMPGTF F4, F5, FCC1 // a190110c + CMPGTD F4, F5, FCC2 // a290210c + CMPGEF F4, F5, FCC3 // a390130c + CMPGED F4, F5, FCC4 // a490230c + CMPEQD F4, F5, FCC5 // a510220c RDTIMELW R4, R0 // 80600000 RDTIMEHW R4, R0 // 80640000 |