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| author | Guoqi Chen <chenguoqi@loongson.cn> | 2025-03-06 11:06:35 +0800 |
|---|---|---|
| committer | abner chenc <chenguoqi@loongson.cn> | 2025-03-10 17:55:19 -0700 |
| commit | e3ea8e68fb91bdc510cb7702981609ce5a9da12e (patch) | |
| tree | e9f00e5118ea11d9f1f3fe11360a9741849d339a /src/cmd/asm | |
| parent | 2a772a2fe7db5602a2932c63a0278ed45e8762cc (diff) | |
| download | go-e3ea8e68fb91bdc510cb7702981609ce5a9da12e.tar.xz | |
cmd/internal/obj/loong64: add {V,XV}SEQI, {V,XV}.{AND,OR,XOR,NOR} instructions support
Go asm syntax:
VSEQB $1, V2, V3
XVSEQB $2, X2, X3
V{AND,OR,XOR,NOR}B $1, V2, V3
XV{AND,OR,XOR,NOR}B $1, V2, V3
V{AND,OR,XOR,NOR,ANDN,ORN}V V1, V2, V3
XV{AND,OR,XOR,NOR,ANDN,ORN}V V1, V2, V3
Equivalent platform assembler syntax:
vseqi.b v3, v2, $1
xvseqi.b x3, x2 ,$2
v{and,or,xor,nor}.b v3, v2, $1
xv{and,or,xor,nor}.b x3, x2, $1
v{and,or,xor,nor,andn,orn}v v3, v2, v1
xv{and,or,xor,nor,andn,orn}v x3, x2, x1
Change-Id: I56ae0db72c7f473755cbdc7f7171c1058a9def97
Reviewed-on: https://go-review.googlesource.com/c/go/+/635515
Reviewed-by: Meidan Li <limeidan@loongson.cn>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Junyang Shao <shaojunyang@google.com>
Reviewed-by: David Chase <drchase@google.com>
Diffstat (limited to 'src/cmd/asm')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/loong64enc1.s | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/loong64enc1.s b/src/cmd/asm/internal/asm/testdata/loong64enc1.s index bb16f874f6..10f295d61c 100644 --- a/src/cmd/asm/internal/asm/testdata/loong64enc1.s +++ b/src/cmd/asm/internal/asm/testdata/loong64enc1.s @@ -515,6 +515,16 @@ lable2: XVSEQH X3, X2, X4 // 448c0074 XVSEQW X3, X2, X4 // 440c0174 XVSEQV X3, X2, X4 // 448c0174 + VSEQB $0, V2, V3 // 43008072 + VSEQH $1, V2, V3 // 43848072 + VSEQW $8, V2, V3 // 43208172 + VSEQV $15, V2, V3 // 43bc8172 + VSEQV $-15, V2, V3 // 43c48172 + XVSEQB $0, X2, X4 // 44008076 + XVSEQH $3, X2, X4 // 448c8076 + XVSEQW $12, X2, X4 // 44308176 + XVSEQV $15, X2, X4 // 44bc8176 + XVSEQV $-15, X2, X4 // 44c48176 // VPCNT{B,H,W,V}, XVPCNT{B,H,W,V} instruction VPCNTB V1, V2 // 22209c72 @@ -526,6 +536,34 @@ lable2: XVPCNTW X3, X2 // 62289c76 XVPCNTV X3, X2 // 622c9c76 + // VANDV,VORV,VXORV,VNORV,VANDNV,VORNV + VANDV V1, V2, V3 // 43042671 + VORV V1, V2, V3 // 43842671 + VXORV V1, V2, V3 // 43042771 + VNORV V1, V2, V3 // 43842771 + VANDNV V1, V2, V3 // 43042871 + VORNV V1, V2, V3 // 43842871 + + // VANDB,VORB,VXORB,VNORB + VANDB $0, V2, V3 // 4300d073 + VORB $64, V2, V3 // 4300d573 + VXORB $128, V2, V3 // 4300da73 + VNORB $255, V2, V3 // 43fcdf73 + + // XVANDV,XVORV,XVXORV,XVNORV,XVANDNV,XVORNV + XVANDV X1, X2, X3 // 43042675 + XVORV X1, X2, X3 // 43842675 + XVXORV X1, X2, X3 // 43042775 + XVNORV X1, X2, X3 // 43842775 + XVANDNV X1, X2, X3 // 43042875 + XVORNV X1, X2, X3 // 43842875 + + // XVANDB,XVORB,XVXORB,XVNORB + XVANDB $0, X2, X3 // 4300d077 + XVORB $1, X2, X3 // 4304d477 + XVXORB $127, X2, X3 // 43fcd977 + XVNORB $255, X2, X3 // 43fcdf77 + // MOVV C_DCON12_0, r MOVV $0x7a90000000000000, R4 // MOVV $8831558869273542656, R4 // 04a41e03 MOVV $0xea90000000000000, R4 // MOVV $-1544734672188080128, R4 // 04a43a03 |