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19 hoursall: prealloc slice with possible minimum capabilitiesShulhan
37 hourscmd/asm, cmd/internal/obj/arm64: support memory with MUL VL imm offsetJunyang Shao
This CL is generated by CL 765440. This CL supports this addressing pattern: (VL*imm)(Reg) (-VL*imm)(Reg) Change-Id: I4d1bab2ef6c4141699a47b28aa14b28cdee6cb3f Reviewed-on: https://go-review.googlesource.com/c/go/+/765420 LUCI-TryBot-Result: golang-scoped@luci-project-accounts.iam.gserviceaccount.com <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: David Chase <drchase@google.com> Commit-Queue: Junyang Shao <shaojunyang@google.com>
37 hourscmd/asm, cmd/internal/obj/arm64: support memory with imm offset in SVEJunyang Shao
This CL is generated by CL 765100 This CL supports this addressing pattern: imm(reg.T) Change-Id: I16789e8e6cf03c4fa225c0fe1bd31dc23c9feb21 Reviewed-on: https://go-review.googlesource.com/c/go/+/765080 Reviewed-by: David Chase <drchase@google.com> LUCI-TryBot-Result: golang-scoped@luci-project-accounts.iam.gserviceaccount.com <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
37 hourscmd/asm, cmd/internal/obj/arm64: support special operands in SVEJunyang Shao
This CL is generated by CL 764980. This CL supports these new special constants: <prfop>, which Go already support (prefetch modifier) <vl>, which include VLx2 and VLx4, which is the vector length specifier. Change-Id: I831f306a816493c08f3c22786e5360f2a37acf6c Reviewed-on: https://go-review.googlesource.com/c/go/+/765000 LUCI-TryBot-Result: golang-scoped@luci-project-accounts.iam.gserviceaccount.com <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: David Chase <drchase@google.com>
37 hourscmd/asm, cmd/internal/obj/arm64: support memory with extensions in SVEJunyang Shao
This CL is generated by CL 764800. Supported addressing patterns: (Z7.D.SXTW<<2)(Z6.D), where Z6.D is the base, Z7.D is the indices. SXTW/UXTW represents signed/unsigned extension, << represents LSL. Change-Id: Ifc6c47833d5113be7cfe96943d369ab977b3a6ee Reviewed-on: https://go-review.googlesource.com/c/go/+/764780 Reviewed-by: David Chase <drchase@google.com> LUCI-TryBot-Result: golang-scoped@luci-project-accounts.iam.gserviceaccount.com <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Commit-Queue: Junyang Shao <shaojunyang@google.com>
37 hourscmd/asm, cmd/internal/obj/arm64: support SVE register listsJunyang Shao
This CL adds the register list support for SVE: [Z1.B, Z2.B] [P1.B, P2.B] [Z1.D] [Z1.D, Z2.D, Z3.D] [Z1.D, Z2.D, Z3.D, Z4.D] This CL is generated by CL 763780. Change-Id: I92210097a8a7525a5a53a2dce0b7652397275dd6 Reviewed-on: https://go-review.googlesource.com/c/go/+/763820 Reviewed-by: David Chase <drchase@google.com> LUCI-TryBot-Result: golang-scoped@luci-project-accounts.iam.gserviceaccount.com <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
37 hourscmd/asm, cmd/internal/obj/arm64: add support for immediatesJunyang Shao
This CL supports various immediate operand patterns. ARM designs the immediate to carry significant semantics, this CL tries to address them as what GNU assembler do, and what the ARM ASL specifies. This CL is generated by CL 763781. Change-Id: I40e2b573f196a947c4f3e55c2be7b8d551471c84 Reviewed-on: https://go-review.googlesource.com/c/go/+/763769 LUCI-TryBot-Result: golang-scoped@luci-project-accounts.iam.gserviceaccount.com <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: David Chase <drchase@google.com> Commit-Queue: Junyang Shao <shaojunyang@google.com>
5 dayscmd/asm, cmd/internal/obj/arm64: support register with index in SVEJunyang Shao
This CL is generated by CL 759800. The new register patterns are (examples): Z1.B[5] Z2[6] P1[7] PN1[8] Change-Id: I5bccc4f1c0474dbd4cd4878bd488f36a7026c7ca Reviewed-on: https://go-review.googlesource.com/c/go/+/759780 Reviewed-by: David Chase <drchase@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
5 dayscmd/asm, cmd/internal/obj/arm64: add GP and SIMD reg support for SVEJunyang Shao
The GP registers and SIMD registers are comforming to the existing Go syntax: they are V or R registers, their widths are specified in the Opcode, the rules to specify them is: - if that instruction only contains one GP or SIMD register: If it's 32-bit GP, then append W to the end of the opcode. If it's 64-bit GP, no changes. If it's SIMD register with BHWD width specification, BHSDQ will just be appended to the end of the opcode. - if it contains multiple GP or SIMD registers, then manual observation found that they are either specified the same width, or they are fixed width. We distinguish them by their first Go ASM operand width. The rule to append suffixes are the same to the single-reg case above. This CL is generated by CL 759280. Change-Id: Icc819cc30dd8fd1609de31ba7bcb4e3ac83c465e Reviewed-on: https://go-review.googlesource.com/c/go/+/759261 Reviewed-by: David Chase <drchase@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
5 dayscmd/internal/obj/loong64: correct instruction encodinglimeidan
Change-Id: I4a9b5d8f7a452cbc6082783723450d8713a04fd9 Reviewed-on: https://go-review.googlesource.com/c/go/+/763940 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn>
7 dayscmd/internal/obj/arm64: add ASIMD cross-lane reduction instructionsAlexander Musman
Add support for ASIMD instructions that reduce a vector to a scalar by operating across all lanes. These use the ASIMDALL encoding class from the ARM architecture specification. Integer cross-lane reductions (.B8, .B16, .H4, .H8, .S4): Signed max/min across lanes: VSMAXV, VSMINV Unsigned max/min across lanes: VUMAXV, VUMINV Floating-point cross-lane reductions (.S4 arrangement): FP max/min across lanes: VFMAXV, VFMINV FP max/min across lanes (NM): VFMAXNMV, VFMINNMV Change-Id: I6af4462d26803dfc7c78db2ad9df4284083e31e8 Reviewed-on: https://go-review.googlesource.com/c/go/+/762202 Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Keith Randall <khr@google.com> Reviewed-by: Keith Randall <khr@golang.org> Auto-Submit: Keith Randall <khr@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
7 dayscmd/internal/obj/arm64: add ASIMD miscellaneous unary instructionsAlexander Musman
Add support for ASIMD unary miscellaneous instructions that operate on a single source register. These use the ASIMDMISC encoding class from the ARM architecture specification. These instruction need some validation for arrangement constraints: - VNOT only allows .B8/.B16 arrangements - VCLS/VCLZ do not support D arrangements - Floating-point variants (VFABS, VFNEG, VFSQRT, VFRINT*) only allow floating-point arrangements (S and D) New instructions by group: Integer absolute/negate: VABS, VNEG Floating-point abs/negate: VFABS, VFNEG Floating-point sqrt: VFSQRT Floating-point round: VFRINTN, VFRINTP, VFRINTM, VFRINTZ Saturating abs/negate: VSQABS, VSQNEG Bit/count operations: VCLS, VCLZ, VNOT Change-Id: I62242eda31f82cd34119c7d4f97316a030e7663b Reviewed-on: https://go-review.googlesource.com/c/go/+/762201 Reviewed-by: Keith Randall <khr@google.com> Reviewed-by: Keith Randall <khr@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: David Chase <drchase@google.com> Auto-Submit: Keith Randall <khr@golang.org>
7 dayscmd/internal/obj/arm64: add ASIMD arithmetic instructionsAlexander Musman
Add encoding support for ASIMD three-register instructions covering floating-point, saturating, halving, integer multiply/accumulate, min/max (including pairwise variants), and bitwise operations. These belong to the "Advanced SIMD Three-register (same)" instruction class defined by the ARM architecture, meaning the two source registers use the same element arrangement (e.g., both .S4 or both .D2). In the assembler they share a common encoding path using the ASIMDSAME() macro. New instructions by group: Floating-point arithmetic: VFADD, VFSUB, VFMUL, VFDIV Floating-point min/max: VFMAX, VFMAXNM, VFMIN, VFMINNM Pairwise floating-point: VFADDP, VFMAXP, VFMINP, VFMAXNMP, VFMINNMP Saturating arithmetic: VSQADD, VUQADD, VSQSUB, VUQSUB Average (halving add): VSHADD, VSRHADD, VUHADD, VURHADD Integer multiply/accum: VMUL, VMLA, VMLS Integer min/max: VSMAX, VSMIN Pairwise integer min/max: VSMAXP, VSMINP, VUMAXP, VUMINP Bitwise: VBIC, VORN Change-Id: I732c84123ad1f302260514fdfe0d020787da017b Reviewed-on: https://go-review.googlesource.com/c/go/+/762200 Auto-Submit: Keith Randall <khr@golang.org> Reviewed-by: Keith Randall <khr@golang.org> Reviewed-by: Keith Randall <khr@google.com> Reviewed-by: David Chase <drchase@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
7 dayscmd/internal/obj/arm64: add ASIMD shift instructionsAlexander Musman
Add support for ASIMD shift instructions. These use the ASIMDSHF encoding class from the ARM architecture specification, where the shift amount is encoded as an immediate derived from the element size. Also add ASIMD shifts-by-vector (3-register form) where the shift amount comes from a second vector register. These use the ASIMDSAME encoding class. New instructions by group: Shift by immediate (signed): VSSHR, VSRSHR Shift by immediate (saturating): VSQSHL, VUQSHL Narrowing shift by immediate: VSHRN, VSHRN2 Shift by vector (3-reg): VSSHL, VUSHL, VSQSHL, VUQSHL Change-Id: I039cc16bc01980b04e6940cc1d4670faf5fa7e3c Reviewed-on: https://go-review.googlesource.com/c/go/+/762180 Reviewed-by: Keith Randall <khr@google.com> Reviewed-by: Keith Randall <khr@golang.org> Auto-Submit: Keith Randall <khr@golang.org> Reviewed-by: David Chase <drchase@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
7 dayscmd/internal/obj/arm64: add remaining ASIMD compare instructionsAlexander Musman
Add remaining arm64 ASIMD vector compare instructions. All these instructions produce either all zeroes (false) or all ones (true) bits in each corresponding lane as the result. Added integer comparison instructions: - VCMEQ (compare to zero) - VCMGE, VCMGT (singed, both two-register and compare to zero) - VCMHI, VCMHS (unsigned two-register compare) - VCMLE, VCMLT (signed compare to zero) Added floating-point comparison instructions: - VFCMEQ, VFCMGE, VFCMGT (both two-register and zero variants) - VFCMLE, VFCMLT (compare to zero) Change-Id: I913165d3934f2556c9bdf38c5103ef56d86383ef Reviewed-on: https://go-review.googlesource.com/c/go/+/721640 Auto-Submit: Keith Randall <khr@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Keith Randall <khr@golang.org> Reviewed-by: Keith Randall <khr@google.com>
7 dayscmd/internal/obj: refactor arm64 ASIMD instruction encodingAlexander Musman
Refactor arm64 ASIMD opcodes to use common helper routines named after their instruction classes from the arm64 XML specification. Add helper routines like ASIMDSAME for instructions with encoding class "asimdsame" in arm64 encodingindex.xml. Helper arguments follow the bitfield order in the speficication tables. For example, the CMEQ instruction entry: <tr class="instructiontable" encname="CMEQ_asimdsame_only"...> <td bitwidth="1" class="bitfield">1</td> <td bitwidth="2" class="bitfield"></td> <td bitwidth="5" class="bitfield">10001</td> <td class="iformname" iformid="CMEQ_advsimd_reg">CMEQ (register)</td> <td class="enctags">Vector</td> </tr> Now corresponds to ASIMDSAME(1, 0, 0x11), where each argument matches the correspoding bitfield value in the table. Change-Id: I024f3eba552906a865841bc1a296f14e3fca73f5 Reviewed-on: https://go-review.googlesource.com/c/go/+/719280 Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
11 dayscmd/internal/obj/riscv: add assembly support for Zihintpause extensionsQiu Weihong
Add support for the PAUSE instruction provided by the Zihintpause extension. Change-Id: If06cce4ca57137275f567b5fe29ef85517f381ef Reviewed-on: https://go-review.googlesource.com/c/go/+/710495 Reviewed-by: Joel Sing <joel@sing.id.au> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
13 dayscmd/asm, cmd/go: pass -std to assembler for standard library packagesCherry Mui
For the compiler, we already pass -std when compiling the standard library. Do the same for the assembler. So the assembler and the linker can tell which objects are in the standard library. Change-Id: I35d28a4c72d32c344eda37a3ff407ea525ee5cea Reviewed-on: https://go-review.googlesource.com/c/go/+/761200 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Michael Matloob <matloob@golang.org> Reviewed-by: Michael Matloob <matloob@google.com>
2026-03-31cmd/internal/obj/riscv: add support for FENCE operands and FENCE.TSOwangboyao
Add support for fine-grained memory ordering flags in the RISC-V FENCE instruction to the assembler. This implements instruction validation and encoding for predecessor and successor flags (I, O, R, W) rather than always falling back to a full memory barrier. This allows more precise memory barriers like FENCE R, RW or FENCE W, W. Additionally, this adds assembly support for the FENCE.TSO, which is encoded as FENCE RW, RW with the fm field set to 1000. Change-Id: Ie9c6c8cd24b38b08013032972bd54515eaedd637 Reviewed-on: https://go-review.googlesource.com/c/go/+/758000 Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2026-03-26cmd/internal/obj/riscv: add assembly support of Zbc extensionXueqi Luo
The Zbc extension adds carry-less multiplication instructions for polynomial arithmetic over GF(2), which is used in cryptographic algorithms and error-correcting codes. The instructions included are: clmul, clmulh, and clmulr. Change-Id: I77a40add1a795c7b90b478dc65835c689e82167a GitHub-Last-Rev: 53790f0aafa46af2ed24183f58292df7f9fb224a GitHub-Pull-Request: golang/go#76301 Reviewed-on: https://go-review.googlesource.com/c/go/+/720520 Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Joel Sing <joel@sing.id.au> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2026-03-20cmd/internal/obj/arm64: new arm64 assembling path for SVEJunyang Shao
This CL integrates a new assembling path specifically designed for SVE and other modern ARM64 instructions, utilizing generated instruction tables. It contains the foundational files and modifications to direct the assembling pipeline to use this new data-driven path. In a.out.go, it registers new constants for registers and operand types used by SVE. A new file inst.go is added, which defines the instruction table data types and utility functions for the new path. The entry point from the upstream pipeline is `tryEncode`. `tryEncode` returns false upon an encoding failure, which allows the upstream matching logic to handle multiple potential matches. The exact match is not finalized until an instruction is actually encoded, as detailed in the comments for `elemEncoders`. This CL also introduces the core generated tables (`anames_gen.go`, `encoding_gen.go`, `goops_gen.go`, and `inst_gen.go`) which handle a wide variety of SVE instructions. A comprehensive end-to-end assembly test file (`arm64sveenc.s`) is added, containing hundreds of test cases for these SVE instructions to verify the new encoding path. To facilitate these encodings, this CL implements handling for operand types such as AC_ARNG, AC_PREG, AC_PREGZM, and AC_ZREG. Others are left as TODOs. The generated files in this CL are produced by the `instgen` tool in CL 755180. Original author Eric Fang (eric.fang@arm.com, CL 424137) Change-Id: I483f170c776fcd8edd8b8b04520f9d69ee0855dd Reviewed-on: https://go-review.googlesource.com/c/go/+/742620 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: David Chase <drchase@google.com>
2026-03-10cmd/internal/obj/riscv: materialise 32 bit unsigned constantsJoel Sing
Currently, we only materialise 32 bit signed constants - a 32 unsigned value that exceeds the 32 bit signed maximum value is loaded from rodata. A 32 bit unsigned value can be materialized by loading and zero extending, which requires four instructions on rva20u64 - on rva22u64 and above only three instructions are required. Change-Id: I874a457f329ac75c2a0fb59b453cf8ef17df2972 Reviewed-on: https://go-review.googlesource.com/c/go/+/748962 Reviewed-by: Mark Ryan <markdryan@meta.com> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2026-02-27cmd/internal/obj: arm64 assembler support unshifted hi for large offsetsAlexander Musman
Extend splitImm24uScaled to support an unshifted hi value (hi <= 0xfff) in addition to the shifted hi value (hi & ^0xfff000 == 0). This allows load/store instructions to handle more offsets using ADD + load/store sequences instead of falling back to the literal pool. This will be used by a subsequent change to add FMOVQ support in SSA form. Change-Id: I78490f5b1a60d49c1d42ad4daefb5d4e6021c965 Reviewed-on: https://go-review.googlesource.com/c/go/+/737320 Reviewed-by: Keith Randall <khr@golang.org> Reviewed-by: Keith Randall <khr@google.com> Auto-Submit: Keith Randall <khr@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: David Chase <drchase@google.com>
2026-02-24cmd/asm/internal/asm/testdata: add SB testsRoland Shoemaker
Add tests for the SB instruction which were omitted in CL 729501. Change-Id: Ia71940b813563a418011914660ee0f1aeaa78444 Reviewed-on: https://go-review.googlesource.com/c/go/+/748580 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Auto-Submit: Roland Shoemaker <roland@golang.org>
2026-02-22cmd/internal/obj: support arm64 FMOVQ from/to global addressAlexander Musman
Support arm64 FMOVQ from/to global address. Currently there are no global addresses known to be aligned by 16 bytes, and with this CL we will always use R_ADDRARM64 relocation with ADRP+ADD+FMOVQ instructions. Change-Id: I283009eda151d1875cf4457734e79b68a941a6df Reviewed-on: https://go-review.googlesource.com/c/go/+/718001 Auto-Submit: Keith Randall <khr@golang.org> Reviewed-by: Keith Randall <khr@google.com> Reviewed-by: Keith Randall <khr@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2026-02-17cmd/internal/obj: remove ARM64 prefix from encoding helpersAlexander Musman
Remove the ARM64 prefix from encoding helper functions that were moved to cmd/internal/obj to be used by both cmd/asm and cmd/compile. These functions now use the package prefix and look like: arm64.EncodeRegisterExtension and arm64.RegisterListOffset. Change-Id: I3548a4fce1072083eb2f55310c9f7ca6a8e12253 Reviewed-on: https://go-review.googlesource.com/c/go/+/714320 Reviewed-by: David Chase <drchase@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2026-02-17cmd/internal/obj: move ARM64RegisterListOffset from cmd/asm/internal/archAlexander Musman
Change-Id: Ieaacd8c40495e7dad61a068125b1d0e0cee832c4 Reviewed-on: https://go-review.googlesource.com/c/go/+/713500 Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2026-02-14cmd/internal/obj/loong64: improve ARNG type register name conversionGuoqi Chen
When resolving ARNG type names, the base value was not subtracted when calculating the variable simd_type, causing its actual value to not match the expected meaning after the base value adjustment. Fixes #77414 Change-Id: I713bab849ecdb5610d2593ba9bd9e1169842f00e Reviewed-on: https://go-review.googlesource.com/c/go/+/742980 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Michael Pratt <mpratt@google.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Meidan Li <limeidan@loongson.cn>
2025-12-23cmd/asm/internal/asm: run riscv64 end-to-end tests for each profileJoel Sing
Currently, the end-to-end tests are only run for the profile set via GORISCV64. Run each of the end-to-end tests for each profile, increasing test coverage. Also rename tests to be RISCV64 specific, rather than RISCV. Change-Id: I15a70939064122c79ec5f2edcda1fa2a47c8cc95 Reviewed-on: https://go-review.googlesource.com/c/go/+/731921 Auto-Submit: Joel Sing <joel@sing.id.au> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
2025-12-23cmd/asm/internal/asm: abort end to end test if assembly failedJoel Sing
If errors are encountered during assembly, do not attempt to perform verification. In this case the output is unlikely to be correct and all verification fails, which means the real issue gets lost in the noise. Change-Id: I62c1bf09fa025b0df4c06f0bfa424fb5d328184b Reviewed-on: https://go-review.googlesource.com/c/go/+/731920 Reviewed-by: Cherry Mui <cherryyz@google.com> Auto-Submit: Joel Sing <joel@sing.id.au> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Michael Knyszek <mknyszek@google.com>
2025-11-26cmd/internal/obj/loong64: remove the incorrect unsigned instructionsXiaolin Zhao
The loong64 ISA does not support the 32-bit unsigned arithmetic instructions ADDU, SUBU and MULU. Change-Id: Ifa67de9c59aa12d08844189ed23e6daad0cc11ea Reviewed-on: https://go-review.googlesource.com/c/go/+/722760 Reviewed-by: abner chenc <chenguoqi@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-11-26cmd/internal/obj/loong64: add {,x}vmadd series instructions supportGuoqi Chen
Go asm syntax: VMADD{B, H, W, V} V1, V2, V3 VMSUB{B, H, W, V} V1, V2, V3 XVMADD{B, H, W, V} X1, X2, X3 XVMSUB{B, H, W, V} X1, X2, X3 VMADDWEV{HB, WH, VW,QV}{,U} V1, V2, V3 VMADDWOD{HB, WH, VW,QV}{,U} V1, V2, V3 XVMADDWEV{HB, WH, VW,QV}{,U} X1, X2, X3 XVMADDWOD{HB, WH, VW,QV}{,U} X1, X2, X3 VMADDWEV{HBUB, WHUH, VWUW, QVUV} V1, V2, V3 VMADDWOD{HBUB, WHUH, VWUW, QVUV} V1, V2, V3 XVMADDWEV{HBUB, WHUH, VWUW, QVUV} X1, X2, X3 XVMADDWOD{HBUB, WHUH, VWUW, QVUV} X1, X2, X3 Equivalent platform assembler syntax: vmadd.{b,h,w,d} v3, v2, v1 vmsub.{b,h,w,d} v3, v2, v1 xvmadd.{b,h,w,d} x3, x2, x1 xvmsub.{b,h,w,d} x3, x2, x1 vmaddwev.{h.b, w.h, d.w, q.d}{,u} v3, v2, v1 vmaddwod.{h.b, w.h, d.w, q.d}{,u} v3, v2, v1 xvmaddwev.{h.b, w.h, d.w, q.d}{,u} x3, x2, x1 xvmaddwod.{h.b, w.h, d.w, q.d}{,u} x3, x2, x1 vmaddwev.{h.bu.b, d.wu.w, d.wu.w, q.du.d} v3, v2, v1 vmaddwod.{h.bu.b, d.wu.w, d.wu.w, q.du.d} v3, v2, v1 xvmaddwev.{h.bu.b, d.wu.w, d.wu.w, q.du.d} x3, x2, x1 xvmaddwod.{h.bu.b, d.wu.w, d.wu.w, q.du.d} x3, x2, x1 Change-Id: I2f4aae51045e1596d4744e525a1589586065cf8e Reviewed-on: https://go-review.googlesource.com/c/go/+/724200 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Auto-Submit: abner chenc <chenguoqi@loongson.cn>
2025-11-26cmd/internal/obj/loong64: add aliases to 32-bit arithmetic instructionsXiaolin Zhao
Both the MULW and MUL instructions point to the mul.w instruction in the loong64 ISA. Previously, MULW was not encoded; now it is encoded and used as an alias for MUL. The same applies to the following instructions: ADD, SUB, DIV. For consistency, we have added additional aliases for DIVU, REM and REMU. Change-Id: Iba201a3c4c2893ff7d301ef877fad9c81e54291b Reviewed-on: https://go-review.googlesource.com/c/go/+/721523 Reviewed-by: Cherry Mui <cherryyz@google.com> Auto-Submit: abner chenc <chenguoqi@loongson.cn> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-11-25cmd/internal/obj/loong64: add {,X}V{ADD,SUB}W{EV,OD}.{H.B,W.H,D.W,Q.D}{,U} ↵Guoqi Chen
instructions support Go asm syntax: VADDWEV{HB, WH, VW, QV}{,U} V1, V2, V3 VSUBWEV{HB, WH, VW, QV}{,U} V1, V2, V3 VADDWOD{HB, WH, VW, QV}{,U} V1, V2, V3 VSUBWOD{HB, WH, VW, QV}{,U} V1, V2, V3 XVADDWEV{HB, WH, VW, QV}{,U} X1, X2, X3 XVSUBWEV{HB, WH, VW, QV}{,U} X1, X2, X3 XVADDWOD{HB, WH, VW, QV}{,U} X1, X2, X3 XVSUBWOD{HB, WH, VW, QV}{,U} X1, X2, X3 Equivalent platform assembler syntax: vaddwev.{h.b, w.h, d.w, q.d}{,u} V3, V2, V1 vsubwev.{h.b, w.h, d.w, q.d}{,u} V3, V2, V1 vaddwod.{h.b, w.h, d.w, q.d}{,u} V3, V2, V1 vsubwod.{h.b, w.h, d.w, q.d}{,u} V3, V2, V1 xvaddwev.{h.b, w.h, d.w, q.d}{,u} X3, X2, X1 xvsubwev.{h.b, w.h, d.w, q.d}{,u} X3, X2, X1 xvaddwod.{h.b, w.h, d.w, q.d}{,u} X3, X2, X1 xvsubwod.{h.b, w.h, d.w, q.d}{,u} X3, X2, X1 Change-Id: I407dc65b32b89844fd303e265a99d8aafdf922ec Reviewed-on: https://go-review.googlesource.com/c/go/+/723620 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Freeman <markfreeman@google.com>
2025-11-20cmd/internal/obj/loong64: add {,X}VSLT.{B/H/W/V}{,U} instructions supportGuoqi Chen
Go asm syntax: VSLT{B,H,W,V} V1, V2, V3 VSLT{B,H,W,V}U V1, V2, V3 VSLT{B,H,W,V} $-2, V2, V3 VSLT{B,H,W,V}U $8, V2, V3 XVSLT{B,H,W,V} X1, X2, X3 XVSLT{B,H,W,V}U X1, X2, X3 XVSLT{B,H,W,V} $-16, X2, X3 XVSLT{B,H,W,V}U $31, X2, X3 Equivalent platform assembler syntax: vslt.{b,h,w,d} v3, v2, v1 vslt.{b,h,w,d}u v3, v2, v1 vslti.{b,h,w,d} v3, v2, $-2 vslti.{b,h,w,d}u v3, v2, $8 xvslt.{b,h,w,d} x3, x2, x1 xvslt.{b,h,w,d}u x3, x2, x1 xvslti.{b,h,w,d} x3, x2, $-16 xvslti.{b,h,w,d}u x3, x2, $31 Change-Id: Iccfb65c0c19b62d2c5ec279a077393c68e1bf7d4 Reviewed-on: https://go-review.googlesource.com/c/go/+/721620 Reviewed-by: Mark Freeman <markfreeman@google.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-11-20cmd/internal/obj/x86: handle global reference in From3 in dynlink modeCherry Mui
In dynlink mode, we rewrite reference to a global variable to a load from the GOT. Currently this code does not handle the case that the global reference is in From3 of a Prog. Most instructions don't expect a memory operand in From3, but some do, like VGF2P8AFFINEQB. Handle this case. Change-Id: Ibb6773606e6967bcc629d9ef5dac6e050f4008ef Reviewed-on: https://go-review.googlesource.com/c/go/+/722181 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Junyang Shao <shaojunyang@google.com>
2025-11-19cmd/internal/obj/loong64: add MULW.D.W[U] instructionsXiaolin Zhao
Go asm syntax: MULWVW RK, RJ, RD MULWVWU RK, RJ, RD Equivalent platform assembler syntax: mulw.d.w rd, rj, rk mulw.d.wu rd, rj, rk Change-Id: Ie46a21904a4c25d04200b0663f83072c38a76c6f Reviewed-on: https://go-review.googlesource.com/c/go/+/721521 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: Mark Freeman <markfreeman@google.com> Reviewed-by: Keith Randall <khr@google.com>
2025-11-18cmd/asm,cmd/compile,cmd/internal/obj/riscv: use compressed instructions on ↵Joel Sing
riscv64 Make use of compressed instructions on riscv64 - add a compress pass to the end of the assembler, which replaces non-compressed instructions with compressed alternatives if possible. Provide a `compressinstructions` compiler and assembler debug flag, such that the compression pass can be disabled via `-asmflags=all=-d=compressinstructions=0` and `-gcflags=all=-d=compressinstructions=0`. Note that this does not prevent the explicit use of compressed instructions via assembly. Note that this does not make use of compressed control transfer instructions - this will be implemented in later changes. Reduces the text size of a hello world binary by ~121KB and reduces the text size of the go binary on riscv64 by ~1.21MB (between 8-10% in both cases). Updates #71105 Cq-Include-Trybots: luci.golang.try:gotip-linux-riscv64 Change-Id: I24258353688554042c2a836deed4830cc673e985 Reviewed-on: https://go-review.googlesource.com/c/go/+/523478 Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Mark Freeman <markfreeman@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-11-13cmd/asm,cmd/internal/obj/riscv: add support for riscv compressed instructionsJoel Sing
Add support for compressed instructions in the RISC-V assembler. This implements instruction validation and encoding for all instructions in the "C" extension. It is worth noting that the validation and encoding of these instructions is far more convoluted then the typical instruction validation and encoding. While the current model has been followed for now, it would be worth revisiting this in the future and potentially switching to a table based or even per-instruction implementation. Additionally, the current instruction encoding is lacking some of the bits needed for compressed instructions - this is solved by compressedEncoding, which provides the missing information. This will also be addressed in the future, likely by changing the instruction encoding format. Updates #71105 Change-Id: I0f9359d63f93ebbdc6e708e79429b2d61eae220d Reviewed-on: https://go-review.googlesource.com/c/go/+/713020 Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
2025-11-12cmd/internal/obj/loong64: add {,X}VS{ADD,SUB}.{B/H/W/V}{,U} instructions supportGuoqi Chen
Go asm syntax: VSADD{B,H,W,V} V1, V2, V3 VSADD{B,H,W,V}U V1, V2, V3 VSSUB{B,H,W,V} V1, V2, V3 VSSUB{B,H,W,V}U V1, V2, V3 XVSADD{B,H,W,V} X1, X2, X3 XVSADD{B,H,W,V}U X1, X2, X3 XVSSUB{B,H,W,V} X1, X2, X3 XVSSUB{B,H,W,V}U X1, X2, X3 Equivalent platform assembler syntax: vsadd.{b,h,w,d} v3, v2, v1 vsadd.{b,h,w,d}u v3, v2, v1 vssub.{b,h,w,d} v3, v2, v1 vssub.{b,h,w,d}u v3, v2, v1 xvsadd.{b,h,w,d} x3, x2, x1 xvsadd.{b,h,w,d}u x3, x2, x1 xvssub.{b,h,w,d} x3, x2, x1 xvssub.{b,h,w,d}u x3, x2, x1 Change-Id: Iab8c1a9bdc4940598936f3beac846466e913ffa2 Reviewed-on: https://go-review.googlesource.com/c/go/+/719200 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Michael Pratt <mpratt@google.com>
2025-11-11std,cmd: go fix -any std cmdAlan Donovan
This change mechanically replaces all occurrences of interface{} by 'any' (where deemed safe by the 'any' modernizer) throughout std and cmd, minus their vendor trees. Since this fix is relatively numerous, it gets its own CL. Also, 'go generate go/types'. Change-Id: I14a6b52856c3291c1d27935409bca8d5fd4242a2 Reviewed-on: https://go-review.googlesource.com/c/go/+/719702 Commit-Queue: Alan Donovan <adonovan@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Dmitri Shuralyov <dmitshur@golang.org> Auto-Submit: Alan Donovan <adonovan@google.com>
2025-11-10cmd/internal/obj/arm64: shorten constant integer loadsKeith Randall
Large integer constants can take up to 4 instructions to encode. We can encode some large constants with a single instruction, namely those which are bit patterns (repetitions of certain runs of 0s and 1s). Often the constants we want to encode are *close* to those bit patterns, but don't exactly match. For those, we can use 2 instructions, one to load the close-by bit pattern and one to fix up any mismatches. The constants we use to strength reduce divides often fit this pattern. For unsigned divides by 1 through 15, this CL applies to the constant for N=3,5,6,10,12,15. Triggers 17 times in hello world. Change-Id: I623abf32961fb3e74d0a163f6822f0647cd94499 Reviewed-on: https://go-review.googlesource.com/c/go/+/717900 Auto-Submit: Keith Randall <khr@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Keith Randall <khr@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-11-05cmd/internal/obj/loong64: add {,X}VSHUF.{B/H/W/V} instructions supportGuoqi Chen
Go asm syntax: VSHUFB V1, V2, V3, V4 XVSHUFB X1, X2, X3, X4 VSHUF{H/W/V} V1, V2, V3 XVSHUF{H/W/V} X1, X2, X3 Equivalent platform assembler syntax: vshuf.b v4, v3, v2, v1 xvshuf.b x4, x3, x2, x1 vshuf.{h/w/d} v3, v2, v1 xvshuf.{h/w/d} x3, x2, x1 Change-Id: I8983467495f587cf46083fd81cb024400c7dc2a7 Reviewed-on: https://go-review.googlesource.com/c/go/+/716804 Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Michael Pratt <mpratt@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn>
2025-11-05cmd/internal/obj/loong64: add {,X}VEXTRINS.{B,H,W,V} instruction supportGuoqi Chen
Go asm syntax: VEXTRINS{B,H,W,V} $0x1b, vj,vd XVEXTRINS{B,H,W,V} $0x1b, vj,vd Equivalent platform assembler syntax: vextrins.{b,h,w,d} vd, vj, $0x1b xvextrins.{b,h,w,d} xd, xj, $0x1b Change-Id: Ibc0bf926befaa2f810cfedd9a40f7ad9a6a9d7fc Reviewed-on: https://go-review.googlesource.com/c/go/+/716803 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Michael Pratt <mpratt@google.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: Michael Knyszek <mknyszek@google.com>
2025-11-03cmd/internal/obj/loong64: using {xv,v}slli.d to perform copying between ↵Guoqi Chen
vector registers Go asm syntax: VMOVQ Vj, Vd XVMOVQ Xj, Xd Equivalent platform assembler syntax: vslli.d vd, vj, 0x0 xvslli.d xd, xj, 0x0 Change-Id: Ifddc3d4d3fbaa6fee2e079bf2ebfe96a2febaa1c Reviewed-on: https://go-review.googlesource.com/c/go/+/716801 Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Michael Pratt <mpratt@google.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-11-03cmd/internal/obj/loong64: add VPERMI.W, XVPERMI.{W,V,Q} instruction supportGuoqi Chen
Go asm syntax: VPERMIW $0x1b, vj, vd XVPERMI{W,V,Q} $0x1b, xj, xd Equivalent platform assembler syntax: vpermi.w vd, vj, $0x1b xvpermi.{w,d,q} xd, xj, $0x1b Change-Id: Ie23b2fdd09b4c93801dc804913206f1c5a496268 Reviewed-on: https://go-review.googlesource.com/c/go/+/716800 Reviewed-by: Michael Pratt <mpratt@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Michael Knyszek <mknyszek@google.com>
2025-11-03cmd/internal/obj: support arm64 FMOVQ large offset encodingAlexander Musman
Support arm64 FMOVQ with large offset in immediate which is encoded using register offset instruction in opldrr or opstrr. This will help allowing folding immediate into new ssa ops FMOVQload and FMOVQstore. For example: FMOVQ F0, -20000(R0) is encoded as following: MOVD 3(PC), R27 FMOVQ F0, (R0)(R27) RET ffff b1e0 # constant value Change-Id: Ib71f92f6ff4b310bda004a440b1df41ffe164523 Reviewed-on: https://go-review.googlesource.com/c/go/+/716960 Reviewed-by: Cherry Mui <cherryyz@google.com> Auto-Submit: Michael Pratt <mpratt@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Michael Pratt <mpratt@google.com>
2025-10-27cmd/internal/obj, cmd/asm: reclassify the offset of memory access operations ↵Xiaolin Zhao
on loong64 This CL also fixes the encoding error of LL/SC[V] instruction and adds the handling of offset greater than 16 bits in MOV{W/V}P instructions. Change-Id: I7a8fab4b68a6839da81c5e59af1f42289d00ef61 Reviewed-on: https://go-review.googlesource.com/c/go/+/706435 Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Michael Knyszek <mknyszek@google.com>
2025-10-23cmd/internal/obj/riscv: simplify validation and encoding of raw instructionsJoel Sing
Use wantImmU/immU rather than handrolling the same code. This also corrects the validation output - add tests to ensure this is the case. Change-Id: Id48f459c7c0de09ddde7a10506f66a3a269f325f Reviewed-on: https://go-review.googlesource.com/c/go/+/702396 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-10-21all: eliminate unnecessary type conversionsJes Cok
Found by github.com/mdempsky/unconvert Change-Id: I88ce10390a49ba768a4deaa0df9057c93c1164de GitHub-Last-Rev: 3b0f7e8f74f58340637f33287c238765856b2483 GitHub-Pull-Request: golang/go#75974 Reviewed-on: https://go-review.googlesource.com/c/go/+/712940 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Keith Randall <khr@golang.org> Auto-Submit: Keith Randall <khr@golang.org> Reviewed-by: Keith Randall <khr@google.com> Reviewed-by: David Chase <drchase@google.com>
generated by cgit v1.3 (git 2.53.0) at 2026-04-15 09:23:09 +0000