diff options
| author | wangboyao <wangboyao@bytedance.com> | 2026-03-23 17:21:18 +0800 |
|---|---|---|
| committer | Meng Zhuo <mengzhuo1203@gmail.com> | 2026-03-31 21:17:57 -0700 |
| commit | b5b9e3cdfee825829c95205dcae3e1d528990cd9 (patch) | |
| tree | 734968ea708ab5be987de618a059efb9b059e099 /src/cmd/asm | |
| parent | 87013ffec0a3cdd3ae8e21b688fdc5a6735058e9 (diff) | |
| download | go-b5b9e3cdfee825829c95205dcae3e1d528990cd9.tar.xz | |
cmd/internal/obj/riscv: add support for FENCE operands and FENCE.TSO
Add support for fine-grained memory ordering flags in the RISC-V FENCE
instruction to the assembler. This implements instruction validation and
encoding for predecessor and successor flags (I, O, R, W) rather than
always falling back to a full memory barrier. This allows more precise
memory barriers like FENCE R, RW or FENCE W, W.
Additionally, this adds assembly support for the FENCE.TSO, which is
encoded as FENCE RW, RW with the fm field set to 1000.
Change-Id: Ie9c6c8cd24b38b08013032972bd54515eaedd637
Reviewed-on: https://go-review.googlesource.com/c/go/+/758000
Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
Reviewed-by: Junyang Shao <shaojunyang@google.com>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
Reviewed-by: Joel Sing <joel@sing.id.au>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Diffstat (limited to 'src/cmd/asm')
| -rw-r--r-- | src/cmd/asm/internal/arch/riscv64.go | 4 | ||||
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/riscv64.s | 4 | ||||
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/riscv64error.s | 7 |
3 files changed, 15 insertions, 0 deletions
diff --git a/src/cmd/asm/internal/arch/riscv64.go b/src/cmd/asm/internal/arch/riscv64.go index 891d2be0e5..c7bb5cb55c 100644 --- a/src/cmd/asm/internal/arch/riscv64.go +++ b/src/cmd/asm/internal/arch/riscv64.go @@ -69,6 +69,10 @@ func RISCV64SpecialOperand(name string) riscv.SpecialOperand { } riscv64SpecialOperand[csrName] = riscv.SpecialOperand(int(csrCode) + int(riscv.SPOP_CSR_BEGIN)) } + // Add the FENCE operands + for opd := riscv.SPOP_FENCE_BEGIN + 1; opd < riscv.SPOP_FENCE_END; opd++ { + riscv64SpecialOperand[opd.String()] = opd + } } if opd, ok := riscv64SpecialOperand[name]; ok { return opd diff --git a/src/cmd/asm/internal/asm/testdata/riscv64.s b/src/cmd/asm/internal/asm/testdata/riscv64.s index 94d1476a6d..65ccf09066 100644 --- a/src/cmd/asm/internal/asm/testdata/riscv64.s +++ b/src/cmd/asm/internal/asm/testdata/riscv64.s @@ -140,6 +140,10 @@ start: // 2.7: Memory Ordering Instructions FENCE // 0f00f00f + FENCE W, W // 0f001001 + FENCE I, O // 0f004008 + FENCE IORW, IORW // 0f00f00f + FENCE.TSO // 0f003083 // 4.2: Integer Computational Instructions (RV64I) ADDIW $1, X5, X6 // 1b831200 diff --git a/src/cmd/asm/internal/asm/testdata/riscv64error.s b/src/cmd/asm/internal/asm/testdata/riscv64error.s index 3c09770d2a..e765fd66ca 100644 --- a/src/cmd/asm/internal/asm/testdata/riscv64error.s +++ b/src/cmd/asm/internal/asm/testdata/riscv64error.s @@ -68,6 +68,13 @@ TEXT errors(SB),$0 SD X5, 4294967296(X6) // ERROR "constant 4294967296 too large" FNES F1, (X5) // ERROR "needs an integer register output" + // Memory Ordering Instructions + FENCE X1, R // ERROR "invalid FENCE predecessor operand" + FENCE R, X2 // ERROR "invalid FENCE successor operand" + FENCE $1, R // ERROR "invalid FENCE predecessor operand" + FENCE R, $2 // ERROR "invalid FENCE successor operand" + FENCE.TSO R, R // ERROR "FENCE.TSO must not have operands" + // // "V" Standard Extension for Vector Operations, Version 1.0 // |