From b5b9e3cdfee825829c95205dcae3e1d528990cd9 Mon Sep 17 00:00:00 2001 From: wangboyao Date: Mon, 23 Mar 2026 17:21:18 +0800 Subject: cmd/internal/obj/riscv: add support for FENCE operands and FENCE.TSO Add support for fine-grained memory ordering flags in the RISC-V FENCE instruction to the assembler. This implements instruction validation and encoding for predecessor and successor flags (I, O, R, W) rather than always falling back to a full memory barrier. This allows more precise memory barriers like FENCE R, RW or FENCE W, W. Additionally, this adds assembly support for the FENCE.TSO, which is encoded as FENCE RW, RW with the fm field set to 1000. Change-Id: Ie9c6c8cd24b38b08013032972bd54515eaedd637 Reviewed-on: https://go-review.googlesource.com/c/go/+/758000 Reviewed-by: Meng Zhuo Reviewed-by: Junyang Shao Reviewed-by: Dmitri Shuralyov Reviewed-by: Joel Sing LUCI-TryBot-Result: Go LUCI --- src/cmd/asm/internal/arch/riscv64.go | 4 ++++ src/cmd/asm/internal/asm/testdata/riscv64.s | 4 ++++ src/cmd/asm/internal/asm/testdata/riscv64error.s | 7 +++++++ 3 files changed, 15 insertions(+) (limited to 'src/cmd/asm') diff --git a/src/cmd/asm/internal/arch/riscv64.go b/src/cmd/asm/internal/arch/riscv64.go index 891d2be0e5..c7bb5cb55c 100644 --- a/src/cmd/asm/internal/arch/riscv64.go +++ b/src/cmd/asm/internal/arch/riscv64.go @@ -69,6 +69,10 @@ func RISCV64SpecialOperand(name string) riscv.SpecialOperand { } riscv64SpecialOperand[csrName] = riscv.SpecialOperand(int(csrCode) + int(riscv.SPOP_CSR_BEGIN)) } + // Add the FENCE operands + for opd := riscv.SPOP_FENCE_BEGIN + 1; opd < riscv.SPOP_FENCE_END; opd++ { + riscv64SpecialOperand[opd.String()] = opd + } } if opd, ok := riscv64SpecialOperand[name]; ok { return opd diff --git a/src/cmd/asm/internal/asm/testdata/riscv64.s b/src/cmd/asm/internal/asm/testdata/riscv64.s index 94d1476a6d..65ccf09066 100644 --- a/src/cmd/asm/internal/asm/testdata/riscv64.s +++ b/src/cmd/asm/internal/asm/testdata/riscv64.s @@ -140,6 +140,10 @@ start: // 2.7: Memory Ordering Instructions FENCE // 0f00f00f + FENCE W, W // 0f001001 + FENCE I, O // 0f004008 + FENCE IORW, IORW // 0f00f00f + FENCE.TSO // 0f003083 // 4.2: Integer Computational Instructions (RV64I) ADDIW $1, X5, X6 // 1b831200 diff --git a/src/cmd/asm/internal/asm/testdata/riscv64error.s b/src/cmd/asm/internal/asm/testdata/riscv64error.s index 3c09770d2a..e765fd66ca 100644 --- a/src/cmd/asm/internal/asm/testdata/riscv64error.s +++ b/src/cmd/asm/internal/asm/testdata/riscv64error.s @@ -68,6 +68,13 @@ TEXT errors(SB),$0 SD X5, 4294967296(X6) // ERROR "constant 4294967296 too large" FNES F1, (X5) // ERROR "needs an integer register output" + // Memory Ordering Instructions + FENCE X1, R // ERROR "invalid FENCE predecessor operand" + FENCE R, X2 // ERROR "invalid FENCE successor operand" + FENCE $1, R // ERROR "invalid FENCE predecessor operand" + FENCE R, $2 // ERROR "invalid FENCE successor operand" + FENCE.TSO R, R // ERROR "FENCE.TSO must not have operands" + // // "V" Standard Extension for Vector Operations, Version 1.0 // -- cgit v1.3-6-g1900