cmd/asm,cmd/internal/obj/riscv: add support for riscv compressed instructions

Add support for compressed instructions in the RISC-V assembler. This
implements instruction validation and encoding for all instructions in
the "C" extension.

It is worth noting that the validation and encoding of these instructions
is far more convoluted then the typical instruction validation and
encoding. While the current model has been followed for now, it would be
worth revisiting this in the future and potentially switching to a table
based or even per-instruction implementation.

Additionally, the current instruction encoding is lacking some of the bits
needed for compressed instructions - this is solved by compressedEncoding,
which provides the missing information. This will also be addressed in the
future, likely by changing the instruction encoding format.

Updates #71105

Change-Id: I0f9359d63f93ebbdc6e708e79429b2d61eae220d
Reviewed-on: https://go-review.googlesource.com/c/go/+/713020
Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
Reviewed-by: Junyang Shao <shaojunyang@google.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>

3 files changed, 210 insertions, 1 deletions

diff --git a/src/cmd/asm/internal/arch/arch.go b/src/cmd/asm/internal/arch/arch.go
index 8481a8f378..fb9e785111 100644
--- a/src/cmd/asm/internal/arch/arch.go
+++ b/src/cmd/asm/internal/arch/arch.go
@@ -92,7 +92,8 @@ func jumpX86(word string) bool {
 func jumpRISCV(word string) bool {
 	switch word {
 	case "BEQ", "BEQZ", "BGE", "BGEU", "BGEZ", "BGT", "BGTU", "BGTZ", "BLE", "BLEU", "BLEZ",
-		"BLT", "BLTU", "BLTZ", "BNE", "BNEZ", "CALL", "JAL", "JALR", "JMP":
+		"BLT", "BLTU", "BLTZ", "BNE", "BNEZ", "CALL", "CBEQZ", "CBNEZ", "CJ", "CJALR", "CJR",
+		"JAL", "JALR", "JMP":
 		return true
 	}
 	return false
diff --git a/src/cmd/asm/internal/asm/testdata/riscv64.s b/src/cmd/asm/internal/asm/testdata/riscv64.s
index 702b82223b..4615119af0 100644
--- a/src/cmd/asm/internal/asm/testdata/riscv64.s
+++ b/src/cmd/asm/internal/asm/testdata/riscv64.s
@@ -372,6 +372,76 @@ start:
 	// 21.7: Double-Precision Floating-Point Classify Instruction
 	FCLASSD	F0, X5					// d31200e2
 
+	//
+	// "C" Extension for Compressed Instructions, Version 2.0
+	//
+
+	// 26.3.1: Compressed Stack-Pointer-Based Loads and Stores
+	CLWSP	20(SP), X10				// 5245
+	CLDSP	24(SP), X10				// 6265
+	CFLDSP	32(SP), F10				// 0235
+	CSWSP	X10, 20(SP)				// 2aca
+	CSDSP	X10, 24(SP)				// 2aec
+	CFSDSP	F10, 32(SP)				// 2ab0
+
+	// 26.3.2: Compressed Register-Based Loads and Stores
+	CLW	20(X10), X11				// 4c49
+	CLD	24(X10), X11				// 0c6d
+	CFLD	32(X10), F11				// 0c31
+	CSW	X11, 20(X10)				// 4cc9
+	CSD	X11, 24(X10)				// 0ced
+	CFSD	F11, 32(X10)				// 0cb1
+
+	// 26.4: Compressed Control Transfer Instructions
+	CJ	1(PC)					// 09a0
+	CJR	X5					// 8282
+	CJALR	X5					// 8292
+	CBEQZ	X10, 1(PC)				// 09c1
+	CBNEZ	X10, 1(PC)				// 09e1
+
+	// 26.5.1: Compressed Integer Constant-Generation Instructions
+	CLI	$-32, X5				// 8152
+	CLI	$31, X5					// fd42
+	CLUI	$-32, X5				// 8172
+	CLUI	$31, X5					// fd62
+
+	// 26.5.2: Compressed Integer Register-Immediate Operations
+	CADD	$-32, X5				// 8112
+	CADD	$31, X5					// fd02
+	CADDI	$-32, X5				// 8112
+	CADDI	$31, X5					// fd02
+	CADDW	$-32, X5				// 8132
+	CADDW	$31, X5					// fd22
+	CADDIW	$-32, X5				// 8132
+	CADDIW	$31, X5					// fd22
+	CADDI16SP $-512, SP				// 0171
+	CADDI16SP $496, SP				// 7d61
+	CADDI4SPN $4, SP, X10				// 4800
+	CADDI4SPN $1020, SP, X10			// e81f
+	CSLLI	$63, X5					// fe12
+	CSRLI	$63, X10				// 7d91
+	CSRAI	$63, X10				// 7d95
+	CAND	$-32, X10				// 0199
+	CAND	$31, X10				// 7d89
+	CANDI	$-32, X10				// 0199
+	CANDI	$31, X10				// 7d89
+
+	// 26.5.3: Compressed Integer Register-Register Operations
+	CMV	X6, X5					// 9a82
+	CADD	X9, X8					// 2694
+	CAND	X9, X8					// 658c
+	COR	X9, X8					// 458c
+	CXOR	X9, X8					// 258c
+	CSUB	X9, X8					// 058c
+	CADDW	X9, X8					// 259c
+	CSUBW	X9, X8					// 059c
+
+	// 26.5.5: Compressed NOP Instruction
+	CNOP						// 0100
+
+	// 26.5.6: Compressed Breakpoint Instruction
+	CEBREAK						// 0290
+
 	// 28.4.1: Address Generation Instructions (Zba)
 	ADDUW		X10, X11, X12			// 3b86a508
 	ADDUW		X10, X11			// bb85a508
diff --git a/src/cmd/asm/internal/asm/testdata/riscv64validation.s b/src/cmd/asm/internal/asm/testdata/riscv64validation.s
index c8ae4c9211..6a2e5f92de 100644
--- a/src/cmd/asm/internal/asm/testdata/riscv64validation.s
+++ b/src/cmd/asm/internal/asm/testdata/riscv64validation.s
@@ -16,6 +16,144 @@ TEXT validation(SB),$0
 	WORD	$0x100000000			// ERROR "must be in range [0x0, 0xffffffff]"
 
 	//
+	// "C" Extension for Compressed Instructions, Version 2.0
+	//
+	CLWSP	20(X5), X10				// ERROR "rs2 must be SP/X2"
+	CLWSP	20(SP), X0				// ERROR "cannot use register X0"
+	CLWSP	20(SP), F10				// ERROR "expected integer register in rd position"
+	CLWSP	22(SP), X10				// ERROR "must be a multiple of 4"
+	CLDSP	24(X5), X10				// ERROR "rs2 must be SP/X2"
+	CLDSP	24(SP), X0				// ERROR "cannot use register X0"
+	CLDSP	24(SP), F10				// ERROR "expected integer register in rd position"
+	CLDSP	28(SP), X10				// ERROR "must be a multiple of 8"
+	CFLDSP	32(X5), F10				// ERROR "rs2 must be SP/X2"
+	CFLDSP	32(SP), X10				// ERROR "expected float register in rd position"
+	CFLDSP	36(SP), F10				// ERROR "must be a multiple of 8"
+	CSWSP	X10, 20(X5)				// ERROR "rd must be SP/X2"
+	CSWSP	F10, 20(SP)				// ERROR "expected integer register in rs2 position"
+	CSWSP	X10, 22(SP)				// ERROR "must be a multiple of 4"
+	CSDSP	X10, 24(X5)				// ERROR "rd must be SP/X2"
+	CSDSP	F10, 24(SP)				// ERROR "expected integer register in rs2 position"
+	CSDSP	X10, 28(SP)				// ERROR "must be a multiple of 8"
+	CFSDSP	F10, 32(X5)				// ERROR "rd must be SP/X2"
+	CFSDSP	X10, 32(SP)				// ERROR "expected float register in rs2 position"
+	CFSDSP	F10, 36(SP)				// ERROR "must be a multiple of 8"
+	CLW	20(X10), F11				// ERROR "expected integer prime register in rd position"
+	CLW	20(X5), X11				// ERROR "expected integer prime register in rs1 position"
+	CLW	20(X10), X5				// ERROR "expected integer prime register in rd position"
+	CLW	-1(X10), X11				// ERROR "must be in range [0, 127]"
+	CLW	22(X10), X11				// ERROR "must be a multiple of 4"
+	CLW	128(X10), X11				// ERROR "must be in range [0, 127]"
+	CLD	24(X10), F11				// ERROR "expected integer prime register in rd position"
+	CLD	24(X5), X11				// ERROR "expected integer prime register in rs1 position"
+	CLD	-1(X10), X11				// ERROR "must be in range [0, 255]"
+	CLD	30(X10), X11				// ERROR "must be a multiple of 8"
+	CLD	256(X10), X11				// ERROR "must be in range [0, 255]"
+	CFLD	32(X10), X11				// ERROR "expected float prime register in rd position"
+	CFLD	32(X5), F11				// ERROR "expected integer prime register in rs1 position"
+	CFLD	-1(X10), F11				// ERROR "must be in range [0, 255]"
+	CFLD	34(X10), F11				// ERROR "must be a multiple of 8"
+	CFLD	256(X10), F11				// ERROR "must be in range [0, 255]"
+	CSW	F11, 20(X10)				// ERROR "expected integer prime register in rs2 position"
+	CSW	X11, -1(X10)				// ERROR "must be in range [0, 127]"
+	CSW	X11, 22(X10)				// ERROR "must be a multiple of 4"
+	CSW	X11, 128(X10)				// ERROR "must be in range [0, 127]"
+	CSD	F11, 24(X10)				// ERROR "expected integer prime register in rs2 position"
+	CSD	X11, -1(X10)				// ERROR "must be in range [0, 255]"
+	CSD	X11, 28(X10)				// ERROR "must be a multiple of 8"
+	CSD	X11, 256(X10)				// ERROR "must be in range [0, 255]"
+	CFSD	X11, 32(X10)				// ERROR "expected float prime register in rs2 position"
+	CFSD	F11, -1(X10)				// ERROR "must be in range [0, 255]"
+	CFSD	F11, 36(X10)				// ERROR "must be a multiple of 8"
+	CFSD	F11, 256(X10)				// ERROR "must be in range [0, 255]"
+	CJR	X0					// ERROR "cannot use register X0 in rs1"
+	CJR	X10, X11				// ERROR "expected no register in rs2"
+	CJALR	X0					// ERROR "cannot use register X0 in rs1"
+	CJALR	X10, X11				// ERROR "expected no register in rd"
+	CBEQZ	X5, 1(PC)				// ERROR "expected integer prime register in rs1"
+	CBNEZ	X5, 1(PC)				// ERROR "expected integer prime register in rs1"
+	CLI	$3, X0					// ERROR "cannot use register X0 in rd"
+	CLI	$-33, X5				// ERROR "must be in range [-32, 31]"
+	CLI	$32, X5					// ERROR "must be in range [-32, 31]"
+	CLUI	$0, X5					// ERROR "immediate cannot be zero"
+	CLUI	$3, X0					// ERROR "cannot use register X0 in rd"
+	CLUI	$3, X2					// ERROR "cannot use register SP/X2 in rd"
+	CLUI	$-33, X5				// ERROR "must be in range [-32, 31]"
+	CLUI	$32, X5					// ERROR "must be in range [-32, 31]"
+	CADD	$31, X5, X6				// ERROR "rd must be the same as rs1"
+	CADD	$-33, X5				// ERROR "must be in range [-32, 31]"
+	CADD	$32, X5					// ERROR "must be in range [-32, 31]"
+	CADDI	$0, X5					// ERROR "immediate cannot be zero"
+	CADDI	$31, X5, X6				// ERROR "rd must be the same as rs1"
+	CADDI	$-33, X5				// ERROR "must be in range [-32, 31]"
+	CADDI	$32, X5					// ERROR "must be in range [-32, 31]"
+	CADDW	$-33, X5				// ERROR "must be in range [-32, 31]"
+	CADDW	$32, X5					// ERROR "must be in range [-32, 31]"
+	CADDIW	$-33, X5				// ERROR "must be in range [-32, 31]"
+	CADDIW	$32, X5					// ERROR "must be in range [-32, 31]"
+	CADDI16SP $0, SP				// ERROR "immediate cannot be zero"
+	CADDI16SP $16, X5				// ERROR "rd must be SP/X2"
+	CADDI16SP $-513, SP				// ERROR "must be in range [-512, 511]"
+	CADDI16SP $20, SP				// ERROR "must be a multiple of 16"
+	CADDI16SP $512, SP				// ERROR "must be in range [-512, 511]"
+	CADDI4SPN $4, SP, X5				// ERROR "expected integer prime register in rd"
+	CADDI4SPN $4, X5, X10				// ERROR "SP/X2 must be in rs1"
+	CADDI4SPN $-1, SP, X10				// ERROR "must be in range [0, 1023]"
+	CADDI4SPN $0, SP, X10				// ERROR "immediate cannot be zero"
+	CADDI4SPN $6, SP, X10				// ERROR "must be a multiple of 4"
+	CADDI4SPN $1024, SP, X10			// ERROR "must be in range [0, 1023]"
+	CSLLI	$63, X5, X6				// ERROR "rd must be the same as rs1"
+	CSLLI	$-1, X5					// ERROR "must be in range [0, 63]"
+	CSLLI	$0, X5					// ERROR "immediate cannot be zero"
+	CSLLI	$64, X5					// ERROR "must be in range [0, 63]"
+	CSRLI	$63, X10, X11				// ERROR "rd must be the same as rs1"
+	CSRLI	$63, X5					// ERROR "expected integer prime register in rd"
+	CSRLI	$-1, X10				// ERROR "must be in range [0, 63]"
+	CSRLI	$0, X10					// ERROR "immediate cannot be zero"
+	CSRLI	$64, X10				// ERROR "must be in range [0, 63]"
+	CSRAI	$63, X10, X11				// ERROR "rd must be the same as rs1"
+	CSRAI	$63, X5					// ERROR "expected integer prime register in rd"
+	CSRAI	$-1, X10				// ERROR "must be in range [0, 63]"
+	CSRAI	$0, X10					// ERROR "immediate cannot be zero"
+	CSRAI	$64, X10				// ERROR "must be in range [0, 63]"
+	CAND	$1, X10, X11				// ERROR "rd must be the same as rs1"
+	CAND	$1, X5					// ERROR "expected integer prime register in rd"
+	CAND	$-64, X10				// ERROR "must be in range [-32, 31]"
+	CAND	$63, X10				// ERROR "must be in range [-32, 31]"
+	CANDI	$1, X10, X11				// ERROR "rd must be the same as rs1"
+	CANDI	$1, X5					// ERROR "expected integer prime register in rd"
+	CANDI	$-64, X10				// ERROR "must be in range [-32, 31]"
+	CANDI	$63, X10				// ERROR "must be in range [-32, 31]"
+	CMV	X0, X5					// ERROR "cannot use register X0 in rs2"
+	CMV	X5, X6, X7				// ERROR "expected no register in rs1"
+	CMV	X5, X0					// ERROR "cannot use register X0 in rd"
+	CMV	F1, X5					// ERROR "expected integer register in rs2"
+	CMV	X5, F1					// ERROR "expected integer register in rd"
+	CADD	X5, X6, X7				// ERROR "rd must be the same as rs1"
+	CADD	X0, X8					// ERROR "cannot use register X0 in rs2"
+	CADD	X8, X0					// ERROR "cannot use register X0 in rd"
+	CAND	X10, X11, X12				// ERROR "rd must be the same as rs1"
+	CAND	X5, X11					// ERROR "expected integer prime register in rs2"
+	CAND	X10, X5					// ERROR "expected integer prime register in rd"
+	COR	X10, X11, X12				// ERROR "rd must be the same as rs1"
+	COR	X5, X11					// ERROR "expected integer prime register in rs2"
+	COR	X10, X5					// ERROR "expected integer prime register in rd"
+	CXOR	X10, X11, X12				// ERROR "rd must be the same as rs1"
+	CXOR	X5, X11					// ERROR "expected integer prime register in rs2"
+	CXOR	X10, X5					// ERROR "expected integer prime register in rd"
+	CSUB	X10, X11, X12				// ERROR "rd must be the same as rs1"
+	CSUB	X5, X11					// ERROR "expected integer prime register in rs2"
+	CSUB	X10, X5					// ERROR "expected integer prime register in rd"
+	CADDW	X10, X11, X12				// ERROR "rd must be the same as rs1"
+	CADDW	X5, X11					// ERROR "expected integer prime register in rs2"
+	CADDW	X10, X5					// ERROR "expected integer prime register in rd"
+	CSUBW	X10, X11, X12				// ERROR "rd must be the same as rs1"
+	CSUBW	X5, X11					// ERROR "expected integer prime register in rs2"
+	CSUBW	X10, X5					// ERROR "expected integer prime register in rd"
+	CNOP	X10					// ERROR "expected no register in rs2"
+	CEBREAK	X10					// ERROR "expected no register in rs2"
+
+	//
 	// "V" Standard Extension for Vector Operations, Version 1.0
 	//
 	VSETVLI		$32, E16, M1, TU, MU, X12	// ERROR "must be in range [0, 31] (5 bits)"