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path: root/src/cmd/internal/obj/riscv/cpu.go
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12 dayscmd/internal/obj/riscv: add assembly support for Zihintpause extensionsQiu Weihong
Add support for the PAUSE instruction provided by the Zihintpause extension. Change-Id: If06cce4ca57137275f567b5fe29ef85517f381ef Reviewed-on: https://go-review.googlesource.com/c/go/+/710495 Reviewed-by: Joel Sing <joel@sing.id.au> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2026-03-31cmd/internal/obj/riscv: add support for FENCE operands and FENCE.TSOwangboyao
Add support for fine-grained memory ordering flags in the RISC-V FENCE instruction to the assembler. This implements instruction validation and encoding for predecessor and successor flags (I, O, R, W) rather than always falling back to a full memory barrier. This allows more precise memory barriers like FENCE R, RW or FENCE W, W. Additionally, this adds assembly support for the FENCE.TSO, which is encoded as FENCE RW, RW with the fm field set to 1000. Change-Id: Ie9c6c8cd24b38b08013032972bd54515eaedd637 Reviewed-on: https://go-review.googlesource.com/c/go/+/758000 Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2026-03-26cmd/internal/obj/riscv: add assembly support of Zbc extensionXueqi Luo
The Zbc extension adds carry-less multiplication instructions for polynomial arithmetic over GF(2), which is used in cryptographic algorithms and error-correcting codes. The instructions included are: clmul, clmulh, and clmulr. Change-Id: I77a40add1a795c7b90b478dc65835c689e82167a GitHub-Last-Rev: 53790f0aafa46af2ed24183f58292df7f9fb224a GitHub-Pull-Request: golang/go#76301 Reviewed-on: https://go-review.googlesource.com/c/go/+/720520 Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Joel Sing <joel@sing.id.au> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-11-18cmd/asm,cmd/compile,cmd/internal/obj/riscv: use compressed instructions on ↵Joel Sing
riscv64 Make use of compressed instructions on riscv64 - add a compress pass to the end of the assembler, which replaces non-compressed instructions with compressed alternatives if possible. Provide a `compressinstructions` compiler and assembler debug flag, such that the compression pass can be disabled via `-asmflags=all=-d=compressinstructions=0` and `-gcflags=all=-d=compressinstructions=0`. Note that this does not prevent the explicit use of compressed instructions via assembly. Note that this does not make use of compressed control transfer instructions - this will be implemented in later changes. Reduces the text size of a hello world binary by ~121KB and reduces the text size of the go binary on riscv64 by ~1.21MB (between 8-10% in both cases). Updates #71105 Cq-Include-Trybots: luci.golang.try:gotip-linux-riscv64 Change-Id: I24258353688554042c2a836deed4830cc673e985 Reviewed-on: https://go-review.googlesource.com/c/go/+/523478 Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Mark Freeman <markfreeman@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-09-25cmd/internal/obj/riscv: remove ACFLWSP/ACFSWSP and ACFLW/ACFSWJoel Sing
These are RV32-only instructions that will not be implemented. Updates #71105 Change-Id: Ie386fe36e56f1151bb8756088dd79804584317c0 Reviewed-on: https://go-review.googlesource.com/c/go/+/702395 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Mark Freeman <markfreeman@google.com> Reviewed-by: Michael Pratt <mpratt@google.com>
2025-09-17cmd/internal/obj/riscv: add support for Zicond instructionslxq015
This patch implement assembler for the Zicond extension: CZEROEQZ and CZERONEZ. Follow-up to CL 631576 Updates #75350 Change-Id: Icf4be131fe61c3b7a3bde4811cf42dc807660907 GitHub-Last-Rev: 6539cc86cbf3c49c3247ed935bcbbb31bb886dea GitHub-Pull-Request: golang/go#75408 Reviewed-on: https://go-review.googlesource.com/c/go/+/702677 Reviewed-by: Mark Freeman <markfreeman@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> TryBot-Bypass: Joel Sing <joel@sing.id.au>
2025-09-15cmd/internal/obj/riscv: implement vector segment load/store instructionswangboyao
https://github.com/riscv/riscv-opcodes/pull/361. After this pr was merged, riscv-opcode can generate RVV segment load/store instructions for Go. Implement vector segment load/store instuctions. Change-Id: I154bb75be70c0a45e2279a75c67f68b5bb57c36e Reviewed-on: https://go-review.googlesource.com/c/go/+/691695 Reviewed-by: Mark Freeman <markfreeman@google.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-09-12cmd/asm, cmd/internal/obj: add riscv64 generic CSR opsMark Ryan
Support is added for the generic RISC-V CSR operations; CSRRC, CSRRCI, CSRRS, CSRRSI, CSRRW, CSRRWI. These instructions require special handling as their second operand is a symbolic CSR register name and not an immediate value or a register. CSR names are implemented as special operands. RISC-V CSRs are not currently saved and restored when a go routine is asynchronously pre-empted so it is only safe to use these instructions in hand written assembler. Note that CSRRS was already partially supported by the assembler so this restriction predates this commit. We mention it here as this commit makes CSRRS much easier to use. Change-Id: I9ff8d804328b418a879d463e7d9cc31f489c7a00 Reviewed-on: https://go-review.googlesource.com/c/go/+/630519 Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Michael Pratt <mpratt@google.com>
2025-08-14cmd/internal/obj/riscv: add encoding for compressed riscv64 instructionsJoel Sing
Regenerate instruction encodings for riscv64, including rv64_c, rv_c and rv_c_d. Updates #71105 Change-Id: I004cc00290bf018ebb848592d84d924481f03851 Reviewed-on: https://go-review.googlesource.com/c/go/+/523476 Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2025-05-08cmd/internal/obj/riscv: fix LMUL encoding for MF2 and MF8Mark Ryan
The encodings for the riscv64 special operands SPOP_MF2 and SPOP_MF8 are incorrect, i.e., their values are swapped. This leads to incorrect encodings for the VSETVLI and VSETIVLI instructions. The assembler currently encodes VSETVLI X10, E32, MF8, TA, MA, X12 as VSETVLI X10, E32, MF2, TA, MA, X12 We update the encodings for SPOP_MF2 and SPOP_MF8 so that they match the LMUL table in section "31.3.4. Vector type register, vtype" of the "RISC-V Instruction Set Manual Volume 1". Change-Id: Ic73355533d7c2a901ee060b35c2f7af6d58453e4 Reviewed-on: https://go-review.googlesource.com/c/go/+/670016 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Joel Sing <joel@sing.id.au>
2025-05-02cmd/internal/obj/riscv: add support for vector mask instructionsJoel Sing
Add support for vector mask instructions to the RISC-V assembler. These allow manipulation of vector masks and include mask register logical instructions, population count and find-first bit set instructions. Change-Id: I3ab3aa0f918338aee9b37ac5a2b2fdc407875072 Reviewed-on: https://go-review.googlesource.com/c/go/+/646779 Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Junyang Shao <shaojunyang@google.com>
2025-05-01cmd/internal/obj/riscv: add support for vector floating-point instructionsJoel Sing
Add support for vector floating-point instructions to the RISC-V assembler. This includes single-width and widening addition and subtraction, multiplication and division, fused multiply-addition, comparison, min/max, sign-injection, classification and type conversion instructions. Change-Id: I8bceb1c5d7eead0561ba5407ace00805a6144f51 Reviewed-on: https://go-review.googlesource.com/c/go/+/646777 Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Junyang Shao <shaojunyang@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
2025-03-29cmd/internal/obj/riscv: add support for vector integer arithmetic instructionsJoel Sing
Add support for vector integer arithmetic instructions to the RISC-V assembler. This includes vector addition, subtraction, integer extension, add-with-carry, subtract-with-borrow, bitwise logical operations, comparison, min/max, integer division and multiplication instructions. Change-Id: I8c191ef8e31291e13743732903e4f12356133a46 Reviewed-on: https://go-review.googlesource.com/c/go/+/646775 Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
2025-02-27cmd/internal/obj/riscv: implement vector load/store instructionsJoel Sing
Implement vector unit stride, vector strided, vector indexed and vector whole register load and store instructions. The vector unit stride instructions take an optional vector mask register, which if specified must be register V0. If only two operands are given, the instruction is encoded as unmasked. The vector strided and vector indexed instructions also take an optional vector mask register, which if specified must be register V0. If only three operands are given, the instruction is encoded as unmasked. Cq-Include-Trybots: luci.golang.try:gotip-linux-riscv64 Change-Id: I35e43bb8f1cf6ae8826fbeec384b95ac945da50f Reviewed-on: https://go-review.googlesource.com/c/go/+/631937 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Pengcheng Wang <wangpengcheng.pp@bytedance.com>
2025-02-14cmd/asm,cmd/internal/obj/riscv: implement vector configuration setting ↵Joel Sing
instructions Implement vector configuration setting instructions (VSETVLI, VSETIVLI, VSETL). These allow the vector length (vl) and vector type (vtype) CSRs to be configured via a single instruction. Unfortunately each instruction has its own dedicated encoding. In the case of VSETVLI/VSETIVLI, the vector type is specified via a series of special operands, which specify the selected element width (E8, E16, E32, E64), the vector register group multiplier (M1, M2, M4, M8, MF2, MF4, MF8), the vector tail policy (TU, TA) and vector mask policy (MU, MA). Note that the order of these special operands matches non-Go assemblers. Partially based on work by Pengcheng Wang <wangpengcheng.pp@bytedance.com>. Cq-Include-Trybots: luci.golang.try:gotip-linux-riscv64 Change-Id: I431f59c1e048a3e84754f0643a963da473a741fe Reviewed-on: https://go-review.googlesource.com/c/go/+/631936 Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2025-02-13cmd/link,cmd/internal: add R_GOT_PCREL_ITYPE_RELOC for riscv64Meng Zhuo
This CL adds new relocation type for riscv64: R_GOT_PCREL_ITYPE_RELOC which generate an AUIPC + I-type pair with relocation type of GOT_HI20 and PCREL_LO12_I. According to RISCV elf psabi doc, medium position independent code model, the GNU as example is: ``` # Calculate address of non-local symbol .Ltmp3: aupipc a0, %got_pcrel_hi(symbol) ld a0, %pcrel_lo(.Ltmp3)(a0) ``` Change-Id: I719dd05e009ca2d9291f0689b346c059f9c56918 Reviewed-on: https://go-review.googlesource.com/c/go/+/612635 Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-02-07cmd/internal/obj/riscv: update references to RISC-V specificationJoel Sing
Update references to version 20240411 of the RISC-V specifications. Reorder and regroup instructions to maintain ordering. Also be consistent with formatting. The instruction encodings table was seemingly missed in CL 616115. Change-Id: I47b7c8538383ff3b0503ba59db570c3d4f0d5653 Reviewed-on: https://go-review.googlesource.com/c/go/+/631935 Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Ian Lance Taylor <iant@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Pengcheng Wang <wangpengcheng.pp@bytedance.com>
2024-10-30cmd/internal/obj/riscv: update RISC-V instruction tableJoel Sing
Regenerate RISC-V instruction table from the riscv-opcodes repository, due to various changes and shuffling upstream. This has been changed to remove pseudo-instructions, since Go only needs the instruction encodings and including the pseudo-instructions is creating unnecessary complications (for example, the inclusion of ANOP and ARET, as well as strangely named aliases such as AJALPSEUDO/AJALRPSEUDO). Remove pseudo-instructions that are not currently supported by the assembler and add specific handling for RDCYCLE, RDTIME and RDINSTRET, which were previously implemented via the instruction encodings. Change-Id: I78be4506ba6b627eba1f321406081a63bab5b2e6 Cq-Include-Trybots: luci.golang.try:gotip-linux-riscv64 Reviewed-on: https://go-review.googlesource.com/c/go/+/616116 Reviewed-by: Michael Pratt <mpratt@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Cherry Mui <cherryyz@google.com>
2024-10-25cmd/internal/obj/riscv: update references to RISC-V specificationJoel Sing
Update references to version 20240411 of the RISC-V specifications. Reorder and regroup instructions to maintain ordering. Change-Id: Iea2a5d22ad677e04948e9a9325986ad301c03f35 Reviewed-on: https://go-review.googlesource.com/c/go/+/616115 Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: David Chase <drchase@google.com>
2024-10-24cmd/internal/obj,cmd/asm: add vector registers to riscv64 assemblerJoel Sing
This adds V0 through V31 as vector registers, which are available on CPUs that support the V extension. Change-Id: Ibffee3f9a2cf1d062638715b3744431d72d451ce Reviewed-on: https://go-review.googlesource.com/c/go/+/595404 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Michael Pratt <mpratt@google.com> Reviewed-by: 鹏程汪 <wangpengcheng.pp@bytedance.com>
2024-10-24cmd/internal/obj/riscv: add vector instruction encodingsJoel Sing
Regenerate the riscv instruction encoding table with the V extension enabled. Add constants and names for the resulting 375 instructions. Change-Id: Icce688493aeb1e9880fb76a0618643f57e481273 Reviewed-on: https://go-review.googlesource.com/c/go/+/595403 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: 鹏程汪 <wangpengcheng.pp@bytedance.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Michael Pratt <mpratt@google.com>
2024-03-20cmd/internal/obj: support Zba, Zbb, Zbs extensions in riscv64 assemblerWang Yaduo
Add assembler support for Zba, Zbb, Zbs extensions, which are mandatory in the rva22u64 profile. These can be used to accelerate address computation and bit manipulation. Change-Id: Ie90fe6b76b1382cf69984a0e71a72d3cba0e750a Reviewed-on: https://go-review.googlesource.com/c/go/+/559655 Reviewed-by: M Zhuo <mengzhuo1203@gmail.com> Run-TryBot: Joel Sing <joel@sing.id.au> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> Reviewed-by: Keith Randall <khr@google.com> TryBot-Result: Gopher Robot <gobot@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2024-03-07cmd/compile,cmd/internal/obj: provide rotation pseudo-instructions for riscv64Joel Sing
Provide and use rotation pseudo-instructions for riscv64. The RISC-V bitmanip extension adds support for hardware rotation instructions in the form of ROL, ROLW, ROR, RORI, RORIW and RORW. These are easily implemented in the assembler as pseudo-instructions for CPUs that do not support the bitmanip extension. This approach provides a number of advantages, including reducing the rewrite rules needed in the compiler, simplifying codegen tests and most importantly, allowing these instructions to be used in assembly (for example, riscv64 optimised versions of SHA-256 and SHA-512). When bitmanip support is added, these instruction sequences can simply be replaced with a single instruction if permitted by the GORISCV64 profile. Change-Id: Ia23402e1a82f211ac760690deb063386056ae1fa Reviewed-on: https://go-review.googlesource.com/c/go/+/565015 TryBot-Result: Gopher Robot <gobot@golang.org> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: M Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Carlos Amedee <carlos@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Run-TryBot: Joel Sing <joel@sing.id.au>
2024-02-21cmd/asm, cmd/internal/obj: enable rounding mode suffix for riscv64Meng Zhuo
This CL adds rounding modes for riscv64 floating point conversion instructions by suffix with 5 modes: RNE, RTZ, RDN, RUP and RMM. For example, for round to nearest (RNE), we can use `FCVTLD.RNE` According to RISCV manual 8.7 and 9.5, we changed these conversion instructions: FCVTWS FCVTLS FCVTWUS FCVTLUS FCVTWD FCVTLD FCVTWUD FCVTLUD Note: Round towards zero (RTZ) by default for all these instructions above. Change-Id: I491e522e14d721e24aa7f528ee0c4640c54c5808 Reviewed-on: https://go-review.googlesource.com/c/go/+/504736 Reviewed-by: Joel Sing <joel@sing.id.au> Run-TryBot: M Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> TryBot-Result: Gopher Robot <gobot@golang.org> Reviewed-by: Than McIntosh <thanm@google.com>
2023-09-19cmd/internal/obj/riscv,cmd/link: rework riscv64 call relocationsJoel Sing
The riscv64 assembler and linker generate three types of calls. Most calls are made via a single JAL instruction, however this is limited to +/-1MB of text. In the case where a call target is unreachable (or unknown), the JAL targets an AUIPC+JALR trampoline. All other cases use AUIPC+JALR pairs, including the case where a single function exceeds 1MB in text size, potentially making it impossible to reach trampolines. Currently, the single instruction JAL call is marked with R_RISCV_CALL and the two instruction AUIPC+JALR call is marked with R_RISCV_PCREL_ITYPE, which is also used for memory load instructions. This means that we have no way to identify that the latter is a call. Switch to using R_RISCV_CALL to mark the AUIPC+JALR pair (aligning somewhat with the elf.R_RISCV_CALL, which is deprecated in favour of elf.R_RISCV_CALL_PLT). Add R_RISCV_JAL and use this to mark the single instruction JAL direct calls. This is clearer and allows us to map elf.R_RISCV_CALL_PLT to Go's R_RISCV_CALL. Add all three types to IsDirectCall, so that direct calls are correctly identified when a function exceeds 1MB of text. Fixes #62465 Change-Id: Id3eea09688a2b7d6e481eae9ed0aa0d1f9a3a48f Reviewed-on: https://go-review.googlesource.com/c/go/+/520095 TryBot-Result: Gopher Robot <gobot@golang.org> Reviewed-by: Cherry Mui <cherryyz@google.com> Run-TryBot: Joel Sing <joel@sing.id.au> Reviewed-by: Than McIntosh <thanm@google.com>
2023-08-23cmd/internal/obj/riscv,cmd/link: add support for internal cgo linking on riscv64Joel Sing
Make it possible to internally link cgo on riscv64, which also adds support for SDYNIMPORT calls without external linking being required. This reduces the time of an ./all.bash run on a Sifive Hifive Unleashed by approximately 20% (~140 minutes down to ~110 minutes). Change-Id: I43f1348de31672718ae8676cc82f6fdc1dfee054 Reviewed-on: https://go-review.googlesource.com/c/go/+/431104 TryBot-Result: Gopher Robot <gobot@golang.org> Reviewed-by: Cherry Mui <cherryyz@google.com> Run-TryBot: Joel Sing <joel@sing.id.au> Reviewed-by: Than McIntosh <thanm@google.com>
2023-05-10cmd/internal/obj/riscv: regenerate instruction encoding tableMeng Zhuo
This CL updates riscv instructions by https://github.com/riscv/riscv-opcodes which adds instruction: APAUSE And removes the following unused instructions: AFENCEI AFMVQX AFMVXQ AHFENCEGVMA AHFENCEVVMA ASLLIRV32 ASRAIRV32 ASRLIRV32 AURET Change-Id: I314570c643af3e6bbc9d2cd471b6b39985bcbdff Reviewed-on: https://go-review.googlesource.com/c/go/+/409415 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Benny Siegert <bsiegert@gmail.com> Reviewed-by: Joel Sing <joel@sing.id.au> TryBot-Result: Gopher Robot <gobot@golang.org> Run-TryBot: M Zhuo <mzh@golangcn.org>
2022-04-01all: fix various doc comment formatting nitsRuss Cox
A run of lines that are indented with any number of spaces or tabs format as a <pre> block. This commit fixes various doc comments that format badly according to that (standard) rule. For example, consider: // - List item. // Second line. // - Another item. Because the - lines are unindented, this is actually two paragraphs separated by a one-line <pre> block. This CL rewrites it to: // - List item. // Second line. // - Another item. Today, that will format as a single <pre> block. In a future release, we hope to format it as a bulleted list. Various other minor fixes as well, all in preparation for reformatting. For #51082. Change-Id: I95cf06040d4186830e571cd50148be3bf8daf189 Reviewed-on: https://go-review.googlesource.com/c/go/+/384257 Trust: Russ Cox <rsc@golang.org> Run-TryBot: Russ Cox <rsc@golang.org> Reviewed-by: Ian Lance Taylor <iant@golang.org> TryBot-Result: Gopher Robot <gobot@golang.org>
2022-03-10cmd/compile,bytealg: change context register on riscv64Meng Zhuo
The register ABI will use X8-X23 (CL 356519), this CL changes context register from X20(S4) to X26(S10) to meet the prerequisite. Update #40724 Change-Id: I93d51d22fe7b3ea5ceffe96dff93e3af60fbe7f6 Reviewed-on: https://go-review.googlesource.com/c/go/+/357974 Trust: mzh <mzh@golangcn.org> Run-TryBot: mzh <mzh@golangcn.org> Reviewed-by: Joel Sing <joel@sing.id.au> Reviewed-by: Cherry Mui <cherryyz@google.com> TryBot-Result: Gopher Robot <gobot@golang.org>
2021-11-11obj/riscv: fix link to risc-v dwarf register numbershasheddan
The repository name and structure in the RISC-V GitHub org has been modified, rendering the existing link invalid. This updates to point at the new location of the RISC-V DWARF specification. Change occured in https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/208 Change-Id: I8ca4c390bee2d7ce20418cdd00e4945a426cf5f7 Reviewed-on: https://go-review.googlesource.com/c/go/+/363355 Reviewed-by: Brad Fitzpatrick <bradfitz@golang.org> Trust: Brad Fitzpatrick <bradfitz@golang.org> Trust: Than McIntosh <thanm@google.com>
2021-10-02cmd/internal/obj/riscv,cmd/link/internal/riscv64: add call trampolines for ↵Joel Sing
riscv64 CALL and JMP on riscv64 are currently implemented as an AUIPC+JALR pair. This means that every call requires two instructions and makes use of the REG_TMP register, even when the symbol would be directly reachable via a single JAL instruction. Add support for call trampolines - CALL and JMP are now implemented as a single JAL instruction, with the linker generating trampolines in the case where the symbol is not reachable (more than +/-1MiB from the JAL instruction), is an unknown symbol or does not yet have an address assigned. Each trampoline contains an AUIPC+JALR pair, which the relocation is applied to. Due to the limited reachability of the JAL instruction, combined with the way that the Go linker currently assigns symbol addresses, there are cases where a call is to a symbol that has no address currently assigned. In this situation we have to assume that a trampoline will be required, however we can patch this up during relocation, potentially calling directly instead. This means that we will end up with trampolines that are unused. In the case of the Go binary, there are around 3,500 trampolines of which approximately 2,300 are unused (around 9200 bytes of machine instructions). Overall, this removes over 72,000 AUIPC instructions from the Go binary. Change-Id: I2d9ecfb85dfc285c7729a3cd0b3a77b6f6c98be0 Reviewed-on: https://go-review.googlesource.com/c/go/+/345051 Trust: Joel Sing <joel@sing.id.au> Run-TryBot: Joel Sing <joel@sing.id.au> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Cherry Mui <cherryyz@google.com>
2021-09-10cmd/compile: add support for Abs and Copysign intrinsics on riscv64Michael Munday
Also, add the FABSS and FABSD pseudo instructions to the assembler. The compiler could use FSGNJX[SD] directly but there doesn't seem to be much advantage to doing so and the pseudo instructions are easier to understand. Change-Id: Ie8825b8aa8773c69cc4f07a32ef04abf4061d80d Reviewed-on: https://go-review.googlesource.com/c/go/+/348989 Trust: Michael Munday <mike.munday@lowrisc.org> Run-TryBot: Michael Munday <mike.munday@lowrisc.org> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Joel Sing <joel@sing.id.au>
2021-09-04cmd/internal/obj/riscv: avoid obj.Prog rewriting for load instructionsJoel Sing
Rather than rewriting the obj.Prog for a load instruction, generate the appropriate machine instruction sequence directly. Change-Id: Iba656dbf2dff2bce02aa221d9a5cad7b7c4630d8 Reviewed-on: https://go-review.googlesource.com/c/go/+/344451 Trust: Joel Sing <joel@sing.id.au> Reviewed-by: Cherry Mui <cherryyz@google.com> Run-TryBot: Cherry Mui <cherryyz@google.com> TryBot-Result: Go Bot <gobot@golang.org>
2020-10-21cmd/compile,cmd/internal/obj/riscv: move g register on riscv64Joel Sing
The original riscv64 port used the thread pointer (TP aka X4) register for the g pointer, however this register is also used when TLS support is required, resulting in a conflict (for example, when a signal is received we have no way of readily knowing if X4 contains a pointer to the TCB or a pointer to a g). In order to support cgo, free up the X4 register by moving g to X27. This unfortunately means that the X4 register is unused in non-cgo mode, however the alternative is to not support cgo on this platform. Update #36641 Change-Id: Idcaf3e8ccbe42972a1b8943aeefde7149d9c960a Reviewed-on: https://go-review.googlesource.com/c/go/+/263477 Trust: Joel Sing <joel@sing.id.au> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2020-03-31cmd/asm,cmd/internal/obj/riscv: provide branch pseudo-instructionsJoel Sing
Implement various branch pseudo-instructions for riscv64. These make it easier to read/write assembly and will also make it easier for the compiler to generate optimised code. Change-Id: Ic31a7748c0e1495522ebecf34b440842b8d12c04 Reviewed-on: https://go-review.googlesource.com/c/go/+/226397 Run-TryBot: Cherry Zhang <cherryyz@google.com> Reviewed-by: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org>
2020-03-17cmd/internal/obj/riscv: add comments for Go registersJoel Sing
Change-Id: Id9aa6ba268eee67f2dc74096d4ec3bc0a80aefe2 Reviewed-on: https://go-review.googlesource.com/c/go/+/223563 Reviewed-by: Cherry Zhang <cherryyz@google.com>
2020-03-15cmd/internal/obj/riscv: add NEG/NEGW pseudo-instructionsJoel Sing
Provide NEG/NEGW pseudo-instructions, which translate to SUB/SUBW with the zero register as a source. Change-Id: I2c1ec1e75611c234c5ee8e39390dd188f8e42bae Reviewed-on: https://go-review.googlesource.com/c/go/+/221689 Reviewed-by: Cherry Zhang <cherryyz@google.com>
2020-03-15cmd/internal/obj/riscv: add NOT pseudo-instructionJoel Sing
Add a NOT pseudo-instruction that translates to XORI $-1. Change-Id: I2be4cfe2939e988cd7f8d30260b704701d78475f Reviewed-on: https://go-review.googlesource.com/c/go/+/221688 Reviewed-by: Cherry Zhang <cherryyz@google.com>
2020-01-21cmd/internal/obj/riscv: populate DWARF register mapping for riscv64Joel Sing
Updates #27532 Change-Id: If147242c45d5c2d5cdc5b0428db32eeec13a958a Reviewed-on: https://go-review.googlesource.com/c/go/+/215377 Reviewed-by: Cherry Zhang <cherryyz@google.com> Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org>
2019-12-24cmd/internal/obj/riscv: handle call, jmp and branchJoel Sing
Also provide REG_LR to more clearly define the link register. Based on the riscv-go port. Updates #27532 Change-Id: I0805f373682f93b3918a01c21d4ef34eb3817c75 Reviewed-on: https://go-review.googlesource.com/c/go/+/204627 Reviewed-by: Cherry Zhang <cherryyz@google.com> Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org>
2019-09-25cmd/internal/obj/riscv: implement floating point instructionsJoel Sing
Add support for assembling various single-precision and double-precision floating point instructions. Based on the riscv-go port. Updates #27532 Change-Id: Iac1aec9b03bb6cbf116b229daeef944d4df550fa Reviewed-on: https://go-review.googlesource.com/c/go/+/196839 Reviewed-by: Cherry Zhang <cherryyz@google.com> Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org>
2019-09-12cmd/asm,cmd/internal/obj: initial support for riscv64 assemblerJoel Sing
Provide the initial framework for the riscv64 assembler. For now this only supports raw WORD instructions, but at least allows for basic testing. Additional functionality will be added in separate changes. Based on the riscv-go port. Updates #27532 Change-Id: I181ffb2d37a34764a3e91eded177d13a89c69f9a Reviewed-on: https://go-review.googlesource.com/c/go/+/194117 Reviewed-by: Cherry Zhang <cherryyz@google.com>
2019-09-11cmd/internal/obj/riscv: fix up instruction groupingsJoel Sing
Some of the instructions were incorrectly grouped - untangle this and separate the RV64I instructions, which are under separate sections of the RISC-V specification. Change-Id: I232962ab4054bf0b4745887506f51e74ea73f73d Reviewed-on: https://go-review.googlesource.com/c/go/+/194238 Reviewed-by: Cherry Zhang <cherryyz@google.com>
2019-09-07cmd/internal/obj: instructions and registers for RISC-VJoel Sing
Start implementing an assembler for RISC-V - this provides register definitions and instruction mnemonics as defined in the RISC-V Instruction Set Manual, along with instruction encoding. The instruction encoding is generated by the parse_opcodes script with the "opcodes" and "opcodes-pseudo" files from (`make inst.go`): https://github.com/riscv/riscv-opcodes This is based on the riscv-go port: https://github.com/riscv/riscv-go Contributors to the riscv-go port are: Amol Bhave <ammubhave@gmail.com> Benjamin Barenblat <bbaren@google.com> Josh Bleecher Snyder <josharian@gmail.com> Michael Pratt <michael@pratt.im> Michael Yenik <myenik@google.com> Ronald G. Minnich <rminnich@gmail.com> Stefan O'Rear <sorear2@gmail.com> This port has been updated to Go 1.13: https://github.com/4a6f656c/riscv-go Updates #27532 Change-Id: I257b6de87e9864df61a2b0ce9be15968c1227b49 Reviewed-on: https://go-review.googlesource.com/c/go/+/193677 Run-TryBot: Brad Fitzpatrick <bradfitz@golang.org> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Cherry Zhang <cherryyz@google.com>
generated by cgit v1.3 (git 2.53.0) at 2026-04-16 10:11:36 +0000