diff options
| author | Joel Sing <joel@sing.id.au> | 2025-02-02 23:09:12 +1100 |
|---|---|---|
| committer | Joel Sing <joel@sing.id.au> | 2025-05-02 04:24:40 -0700 |
| commit | 936ecc3e24c5b2e3ea4b0d2ca9eb32c39fdc097e (patch) | |
| tree | 9b2d43c09040e40fb0fea32845925aa6ef899acb /src/cmd/internal/obj/riscv/cpu.go | |
| parent | 2e60916f6e153db682fd4ea269c7d0a32e3d1768 (diff) | |
| download | go-936ecc3e24c5b2e3ea4b0d2ca9eb32c39fdc097e.tar.xz | |
cmd/internal/obj/riscv: add support for vector mask instructions
Add support for vector mask instructions to the RISC-V assembler.
These allow manipulation of vector masks and include mask register
logical instructions, population count and find-first bit set
instructions.
Change-Id: I3ab3aa0f918338aee9b37ac5a2b2fdc407875072
Reviewed-on: https://go-review.googlesource.com/c/go/+/646779
Reviewed-by: Carlos Amedee <carlos@golang.org>
Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
Reviewed-by: Junyang Shao <shaojunyang@google.com>
Diffstat (limited to 'src/cmd/internal/obj/riscv/cpu.go')
| -rw-r--r-- | src/cmd/internal/obj/riscv/cpu.go | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/cmd/internal/obj/riscv/cpu.go b/src/cmd/internal/obj/riscv/cpu.go index 3cad4f9d94..d87b6b1efb 100644 --- a/src/cmd/internal/obj/riscv/cpu.go +++ b/src/cmd/internal/obj/riscv/cpu.go @@ -1180,12 +1180,16 @@ const ( ASNEZ AVFABSV AVFNEGV - AVMFGEVV - AVMFGTVV AVL1RV AVL2RV AVL4RV AVL8RV + AVMCLRM + AVMFGEVV + AVMFGTVV + AVMMVM + AVMNOTM + AVMSETM AVMSGEUVI AVMSGEUVV AVMSGEVI |