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12 dayscmd/internal/obj/riscv: add assembly support for Zihintpause extensionsQiu Weihong
Add support for the PAUSE instruction provided by the Zihintpause extension. Change-Id: If06cce4ca57137275f567b5fe29ef85517f381ef Reviewed-on: https://go-review.googlesource.com/c/go/+/710495 Reviewed-by: Joel Sing <joel@sing.id.au> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2026-03-31cmd/internal/obj/riscv: add support for FENCE operands and FENCE.TSOwangboyao
Add support for fine-grained memory ordering flags in the RISC-V FENCE instruction to the assembler. This implements instruction validation and encoding for predecessor and successor flags (I, O, R, W) rather than always falling back to a full memory barrier. This allows more precise memory barriers like FENCE R, RW or FENCE W, W. Additionally, this adds assembly support for the FENCE.TSO, which is encoded as FENCE RW, RW with the fm field set to 1000. Change-Id: Ie9c6c8cd24b38b08013032972bd54515eaedd637 Reviewed-on: https://go-review.googlesource.com/c/go/+/758000 Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2026-03-26cmd/internal/obj/riscv: add assembly support of Zbc extensionXueqi Luo
The Zbc extension adds carry-less multiplication instructions for polynomial arithmetic over GF(2), which is used in cryptographic algorithms and error-correcting codes. The instructions included are: clmul, clmulh, and clmulr. Change-Id: I77a40add1a795c7b90b478dc65835c689e82167a GitHub-Last-Rev: 53790f0aafa46af2ed24183f58292df7f9fb224a GitHub-Pull-Request: golang/go#76301 Reviewed-on: https://go-review.googlesource.com/c/go/+/720520 Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Joel Sing <joel@sing.id.au> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2026-03-10cmd/internal/obj/riscv: materialise 32 bit unsigned constantsJoel Sing
Currently, we only materialise 32 bit signed constants - a 32 unsigned value that exceeds the 32 bit signed maximum value is loaded from rodata. A 32 bit unsigned value can be materialized by loading and zero extending, which requires four instructions on rva20u64 - on rva22u64 and above only three instructions are required. Change-Id: I874a457f329ac75c2a0fb59b453cf8ef17df2972 Reviewed-on: https://go-review.googlesource.com/c/go/+/748962 Reviewed-by: Mark Ryan <markdryan@meta.com> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2026-03-10cmd/internal/obj/riscv: factor out constant materialisation codeJoel Sing
Pull the constant materialisation code out into its own function, which reduces indentation and improves readability. Change-Id: Ia06baefa99c8f1a738c1b13d1a8b27111fa948b5 Reviewed-on: https://go-review.googlesource.com/c/go/+/748961 Reviewed-by: David Chase <drchase@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Ryan <markdryan@meta.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2026-03-10cmd/internal/obj/riscv: factor out constant materialisation identificationJoel Sing
Change-Id: Ia7fedd934ecc2b11cb0de445f299dc5c6004e7b0 Reviewed-on: https://go-review.googlesource.com/c/go/+/748960 Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Mark Ryan <markdryan@meta.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2026-03-07cmd/internal/obj: fix indirect tail call codeKeith Randall
The assembler isn't handling this correctly for most architectures. Of course, the two I tried first, arm64 and amd64, worked, so I assumed other archs could handle it also. Apparently not. Should fix dashboard failures introduced by CL 751465. Change-Id: I9fc4f123d11acf3d10cc9806abfb93ec077509a7 Reviewed-on: https://go-review.googlesource.com/c/go/+/752560 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Keith Randall <khr@google.com> Auto-Submit: Keith Randall <khr@golang.org> Reviewed-by: Cuong Manh Le <cuong.manhle.vn@gmail.com>
2026-02-10cmd/internal/obj: add Align field to LSymIan Lance Taylor
This will permit the compiler and assembler to specify the alignment of symbols that they create. Careful placement of the new field, plus rearranging an existing field, means that LSym does not change size (as tested by TestSizeof). The new alignment field is int16, permitting alignment up to 16384, more than we ever need in practice. If necessary we could change the field to uint8 and store the alignment as a power of two, as is done in the linker. This replaces the Align field in FuncInfo. For #6853 For #36313 Change-Id: I421e8238ab57958fea8e4eab0649ce5288e7f92f Reviewed-on: https://go-review.googlesource.com/c/go/+/727020 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Keith Randall <khr@golang.org> Auto-Submit: Ian Lance Taylor <iant@golang.org> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Keith Randall <khr@google.com>
2025-11-25cmd/internal/obj/riscv: document compressed instructionsMark Ryan
We update the RISC-V assembler documentation to describe how the RISC-V compressed instruction set is implemented by the assembler and how compressed instructions can be disabled. Change-Id: Ic7b1cb1586e6906af78adb8ff5fa10f5fbfde292 Reviewed-on: https://go-review.googlesource.com/c/go/+/719221 Reviewed-by: Mark Freeman <markfreeman@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Joel Sing <joel@sing.id.au> Auto-Submit: Joel Sing <joel@sing.id.au> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
2025-11-21cmd/internal/obj/riscv: improve large branch/call/jump testsJoel Sing
Rework these tests such that they are built on all architectures and actually executed when run on riscv64. This increases the likelihood of catching code generation issues, especially those that impact relocations. Also ensure that the generated assembly includes the instruction sequence that is expected for the large branch/call/jump. Change-Id: I15c40a439dd1d0d4ed189ab81697e93d82c4ef4d Reviewed-on: https://go-review.googlesource.com/c/go/+/721621 Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Mark Freeman <markfreeman@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Junyang Shao <shaojunyang@google.com>
2025-11-18cmd/asm,cmd/compile,cmd/internal/obj/riscv: use compressed instructions on ↵Joel Sing
riscv64 Make use of compressed instructions on riscv64 - add a compress pass to the end of the assembler, which replaces non-compressed instructions with compressed alternatives if possible. Provide a `compressinstructions` compiler and assembler debug flag, such that the compression pass can be disabled via `-asmflags=all=-d=compressinstructions=0` and `-gcflags=all=-d=compressinstructions=0`. Note that this does not prevent the explicit use of compressed instructions via assembly. Note that this does not make use of compressed control transfer instructions - this will be implemented in later changes. Reduces the text size of a hello world binary by ~121KB and reduces the text size of the go binary on riscv64 by ~1.21MB (between 8-10% in both cases). Updates #71105 Cq-Include-Trybots: luci.golang.try:gotip-linux-riscv64 Change-Id: I24258353688554042c2a836deed4830cc673e985 Reviewed-on: https://go-review.googlesource.com/c/go/+/523478 Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Mark Freeman <markfreeman@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-11-17cmd/internal/sys,internal/goarch,runtime: enable the use of compressed ↵Joel Sing
instructions on riscv64 Enable the use of compressed instructions on riscv64 by reducing the PC quantum to two bytes and reducing the minimum instruction length to two bytes. Change gostartcall on riscv64 to land at two times the PC quantum into goexit, so that we retain four byte alignment and revise the NOP instructions in goexit to ensure that they are never compressed. Additionally, adjust PCALIGN so that it correctly handles two byte offsets. Fixes #47560 Updates #71105 Cq-Include-Trybots: luci.golang.try:gotip-linux-riscv64 Change-Id: I4329a8fbfcb4de636aadaeadabb826bc22698640 Reviewed-on: https://go-review.googlesource.com/c/go/+/523477 Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Mark Freeman <markfreeman@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
2025-11-14doc, cmd/internal/obj/riscv: document the riscv64 assemblerMark Ryan
Add documentation for the riscv64 assembler with a link to the documentation from asm.html. Architecture specific assembler documentation is provided for the other architectures but has been missing for riscv64 until now. Change-Id: I62ed7e6a2a4b52e0720d869e964b29e2a980223a Reviewed-on: https://go-review.googlesource.com/c/go/+/652717 Reviewed-by: Joel Sing <joel@sing.id.au> Reviewed-by: Michael Pratt <mpratt@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Auto-Submit: Joel Sing <joel@sing.id.au> Reviewed-by: Junyang Shao <shaojunyang@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-11-13cmd/asm,cmd/internal/obj/riscv: add support for riscv compressed instructionsJoel Sing
Add support for compressed instructions in the RISC-V assembler. This implements instruction validation and encoding for all instructions in the "C" extension. It is worth noting that the validation and encoding of these instructions is far more convoluted then the typical instruction validation and encoding. While the current model has been followed for now, it would be worth revisiting this in the future and potentially switching to a table based or even per-instruction implementation. Additionally, the current instruction encoding is lacking some of the bits needed for compressed instructions - this is solved by compressedEncoding, which provides the missing information. This will also be addressed in the future, likely by changing the instruction encoding format. Updates #71105 Change-Id: I0f9359d63f93ebbdc6e708e79429b2d61eae220d Reviewed-on: https://go-review.googlesource.com/c/go/+/713020 Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
2025-11-13cmd/internal/obj/riscv: implement better bit pattern encodingJoel Sing
Replace the extractBitAndShift function with an encodeBitPattern function. This allows the caller to specify a slice of bits that are to be extracted and encoded, rather than making multiple function calls and combining the results. Change-Id: I3d51caa10ecf714f2ad2fb66d38376202c4e0628 Reviewed-on: https://go-review.googlesource.com/c/go/+/702397 Reviewed-by: Junyang Shao <shaojunyang@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-10-23cmd/internal/obj/riscv: simplify validation and encoding of raw instructionsJoel Sing
Use wantImmU/immU rather than handrolling the same code. This also corrects the validation output - add tests to ensure this is the case. Change-Id: Id48f459c7c0de09ddde7a10506f66a3a269f325f Reviewed-on: https://go-review.googlesource.com/c/go/+/702396 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-10-21all: eliminate unnecessary type conversionsJes Cok
Found by github.com/mdempsky/unconvert Change-Id: I88ce10390a49ba768a4deaa0df9057c93c1164de GitHub-Last-Rev: 3b0f7e8f74f58340637f33287c238765856b2483 GitHub-Pull-Request: golang/go#75974 Reviewed-on: https://go-review.googlesource.com/c/go/+/712940 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Keith Randall <khr@golang.org> Auto-Submit: Keith Randall <khr@golang.org> Reviewed-by: Keith Randall <khr@google.com> Reviewed-by: David Chase <drchase@google.com>
2025-10-15cmd: fix three printf problems reported by newest vetAlan Donovan
Change-Id: Id70985d217c940eb022dbc95bfaa20373672512c Reviewed-on: https://go-review.googlesource.com/c/go/+/712220 Auto-Submit: Alan Donovan <adonovan@google.com> TryBot-Bypass: Alan Donovan <adonovan@google.com> Commit-Queue: Alan Donovan <adonovan@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-10-08cmd/internal/obj: fix Link.Diag printf errorsAlan Donovan
go1.26's vet printf checker can associate the printf-wrapper property with local vars and struct fields if they are assigned from a printf-like func literal (CL 706635). This leads to better detection of mistakes. Change-Id: I604be1e200aa1aba75e09d4f36ab68c1dba3b8a3 Reviewed-on: https://go-review.googlesource.com/c/go/+/710195 Auto-Submit: Alan Donovan <adonovan@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-09-25cmd/internal/obj/riscv: remove ACFLWSP/ACFSWSP and ACFLW/ACFSWJoel Sing
These are RV32-only instructions that will not be implemented. Updates #71105 Change-Id: Ie386fe36e56f1151bb8756088dd79804584317c0 Reviewed-on: https://go-review.googlesource.com/c/go/+/702395 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Mark Freeman <markfreeman@google.com> Reviewed-by: Michael Pratt <mpratt@google.com>
2025-09-24cmd/internal/obj/riscv: add support for vector unit-stride fault-only-first ↵wangboyao
load instructions Add support for vector unit-stride fault-only-first load instructions to the RISC-V assembler. This includes vle8ff, vle16ff, vle32ff and vle64ff. Change-Id: I5575a1ea155663852f92194fb79f08b5d52203de Reviewed-on: https://go-review.googlesource.com/c/go/+/690115 Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-09-17cmd/internal/obj/riscv: add support for Zicond instructionslxq015
This patch implement assembler for the Zicond extension: CZEROEQZ and CZERONEZ. Follow-up to CL 631576 Updates #75350 Change-Id: Icf4be131fe61c3b7a3bde4811cf42dc807660907 GitHub-Last-Rev: 6539cc86cbf3c49c3247ed935bcbbb31bb886dea GitHub-Pull-Request: golang/go#75408 Reviewed-on: https://go-review.googlesource.com/c/go/+/702677 Reviewed-by: Mark Freeman <markfreeman@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> TryBot-Bypass: Joel Sing <joel@sing.id.au>
2025-09-16cmd/internal/obj/riscv: improve handling of float point movesJoel Sing
Translate moves from an integer register to a floating point register, or from a floating point register to an integer register, to the appropriate move instruction (i.e. FMVXW/FMVWX/FMVXD/FMVDX). Add support for MOVF with a constant - we previously added support for MOVD but not for MOVF. Add special handling for 0.0, which we can translate to a move from the zero register to a floating point register (leveraging the above mentioned change). Change-Id: If8df2f5610e69b4ec0af85efb884951024685f5b Reviewed-on: https://go-review.googlesource.com/c/go/+/703216 Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Mark Freeman <markfreeman@google.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
2025-09-15cmd/internal/obj/riscv: implement vector segment load/store instructionswangboyao
https://github.com/riscv/riscv-opcodes/pull/361. After this pr was merged, riscv-opcode can generate RVV segment load/store instructions for Go. Implement vector segment load/store instuctions. Change-Id: I154bb75be70c0a45e2279a75c67f68b5bb57c36e Reviewed-on: https://go-review.googlesource.com/c/go/+/691695 Reviewed-by: Mark Freeman <markfreeman@google.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-09-12cmd/asm, cmd/internal/obj: add riscv64 generic CSR opsMark Ryan
Support is added for the generic RISC-V CSR operations; CSRRC, CSRRCI, CSRRS, CSRRSI, CSRRW, CSRRWI. These instructions require special handling as their second operand is a symbolic CSR register name and not an immediate value or a register. CSR names are implemented as special operands. RISC-V CSRs are not currently saved and restored when a go routine is asynchronously pre-empted so it is only safe to use these instructions in hand written assembler. Note that CSRRS was already partially supported by the assembler so this restriction predates this commit. We mention it here as this commit makes CSRRS much easier to use. Change-Id: I9ff8d804328b418a879d463e7d9cc31f489c7a00 Reviewed-on: https://go-review.googlesource.com/c/go/+/630519 Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Michael Pratt <mpratt@google.com>
2025-09-09runtime: remove duff support for riscv64Meng Zhuo
Change-Id: I987d9f49fbd2650eef4224f72271bf752c54d39c Reviewed-on: https://go-review.googlesource.com/c/go/+/700538 Reviewed-by: Mark Freeman <markfreeman@google.com> Reviewed-by: Keith Randall <khr@golang.org> Reviewed-by: Keith Randall <khr@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
2025-08-14cmd/internal/obj/riscv: add encoding for compressed riscv64 instructionsJoel Sing
Regenerate instruction encodings for riscv64, including rv64_c, rv_c and rv_c_d. Updates #71105 Change-Id: I004cc00290bf018ebb848592d84d924481f03851 Reviewed-on: https://go-review.googlesource.com/c/go/+/523476 Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2025-08-05cmd: remove dead codeqiulaidongfeng
Fixes #74076 Change-Id: Icc67b3d4e342f329584433bd1250c56ae8f5a73d Reviewed-on: https://go-review.googlesource.com/c/go/+/690635 Reviewed-by: Alan Donovan <adonovan@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Commit-Queue: Alan Donovan <adonovan@google.com> Reviewed-by: Keith Randall <khr@golang.org> Reviewed-by: Keith Randall <khr@google.com> Auto-Submit: Alan Donovan <adonovan@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2025-07-24cmd/internal/obj: rip out argp adjustment for wrapper framesKeith Randall
The previous CL made this adjustment unnecessary. The argp field is no longer used by the runtime. Change-Id: I3491eeef4103c6653ec345d604c0acd290af9e8f Reviewed-on: https://go-review.googlesource.com/c/go/+/685356 Reviewed-by: Michael Knyszek <mknyszek@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Cuong Manh Le <cuong.manhle.vn@gmail.com>
2025-05-21cmd/internal/obj/riscv: fix vector integer multiply addMark Ryan
The RISC-V integer vector multiply add instructions are not encoded correctly; the first and second arguments are swapped. For example, the instruction VMACCVV V1, V2, V3 encodes to b620a1d7 or vmacc.vv v3,v1,v2 and not b61121d7 or vmacc.vv v3,v2,v1 as expected. This is inconsistent with the argument ordering we use for 3 argument vector instructions, in which the argument order, as given in the RISC-V specifications, is reversed, and also with the vector FMA instructions which have the same argument ordering as the vector integer multiply add instructions in the "The RISC-V Instruction Set Manual Volume I". For example, in the ISA manual we have the following instruction definitions ; Integer multiply-add, overwrite addend vmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] ; FP multiply-accumulate, overwrites addend vfmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] It's reasonable to expect that the Go assembler would use the same argument ordering for both of these instructions. It currently does not. We fix the issue by switching the argument ordering for the vector integer multiply add instructions to match those of the vector FMA instructions. Change-Id: Ib98e9999617f991969e5c831734b3bb3324439f6 Reviewed-on: https://go-review.googlesource.com/c/go/+/670335 Reviewed-by: Carlos Amedee <carlos@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-05-08cmd/internal/obj/riscv: reject invalid vadc/vsbc encodingsMark Ryan
The RISC-V Instruction Set Manual Volume states that "for vadc and vsbc, the instruction encoding is reserved if the destination vector register is v0". The assembler currently allows instructions like VADCVVM V1, V2, V0, V0 to be assembled. It's not clear what the behaviour of such instructions will be on target hardware so it's best to disallow them. For reference, binutils (2.44-3.fc42) allows the instruction vadc.vvm v0, v4, v8, v0 to be assembled and the instruction actually executes on a Banana PI F3 without crashing. However, clang (20.1.2) refuses to assemble the instruction, producing the following error. error: the destination vector register group cannot be V0 vadc.vvm v0, v4, v8, v0 ^ Change-Id: Ia913cbd864ae8dbcf9227f69b963c93a99481cff Reviewed-on: https://go-review.googlesource.com/c/go/+/669315 Reviewed-by: Carlos Amedee <carlos@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Joel Sing <joel@sing.id.au>
2025-05-08cmd/internal/obj/riscv: fix LMUL encoding for MF2 and MF8Mark Ryan
The encodings for the riscv64 special operands SPOP_MF2 and SPOP_MF8 are incorrect, i.e., their values are swapped. This leads to incorrect encodings for the VSETVLI and VSETIVLI instructions. The assembler currently encodes VSETVLI X10, E32, MF8, TA, MA, X12 as VSETVLI X10, E32, MF2, TA, MA, X12 We update the encodings for SPOP_MF2 and SPOP_MF8 so that they match the LMUL table in section "31.3.4. Vector type register, vtype" of the "RISC-V Instruction Set Manual Volume 1". Change-Id: Ic73355533d7c2a901ee060b35c2f7af6d58453e4 Reviewed-on: https://go-review.googlesource.com/c/go/+/670016 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Joel Sing <joel@sing.id.au>
2025-05-05Revert "cmd/compile: allow all of the preamble to be preemptible"Keith Randall
This reverts commits 3f3782feed6e0726ddb08afd32dad7d94fbb38c6 (CL 648518) b386b628521780c048af14a148f373c84e687b26 (CL 668475) Fixes #73542 Change-Id: I218851c5c0b62700281feb0b3f82b6b9b97b910d Reviewed-on: https://go-review.googlesource.com/c/go/+/670055 Reviewed-by: Keith Randall <khr@google.com> Auto-Submit: Keith Randall <khr@golang.org> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-05-02cmd/internal/obj/riscv: add support for vector permutation instructionsJoel Sing
Add support for vector permutation instructions to the RISC-V assembler. This includes integer scalar move, floating point scalar move, slide up and slide down, register gather, compression and whole vector register move instructions. Change-Id: I1da9f393091504fd81714006355725b8b9ecadea Reviewed-on: https://go-review.googlesource.com/c/go/+/646780 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
2025-05-02cmd/internal/obj/riscv: add support for vector mask instructionsJoel Sing
Add support for vector mask instructions to the RISC-V assembler. These allow manipulation of vector masks and include mask register logical instructions, population count and find-first bit set instructions. Change-Id: I3ab3aa0f918338aee9b37ac5a2b2fdc407875072 Reviewed-on: https://go-review.googlesource.com/c/go/+/646779 Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Junyang Shao <shaojunyang@google.com>
2025-05-02cmd/internal/obj/riscv: add support for vector reduction instructionsJoel Sing
Add support for vector reduction instructions to the RISC-V assembler, including single-width integer reduction, widening integer reduction, single-width floating-point reduction and widening floating-point reduction. Change-Id: I8f17bef11389f3a017e0430275023fc5d75936e3 Reviewed-on: https://go-review.googlesource.com/c/go/+/646778 Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2025-05-01cmd/internal/obj/riscv: add support for vector floating-point instructionsJoel Sing
Add support for vector floating-point instructions to the RISC-V assembler. This includes single-width and widening addition and subtraction, multiplication and division, fused multiply-addition, comparison, min/max, sign-injection, classification and type conversion instructions. Change-Id: I8bceb1c5d7eead0561ba5407ace00805a6144f51 Reviewed-on: https://go-review.googlesource.com/c/go/+/646777 Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Junyang Shao <shaojunyang@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
2025-04-25cmd/compile: allow all of the preamble to be preemptibleKeith Randall
We currently make some parts of the preamble unpreemptible because it confuses morestack. See comments in the code. Instead, have morestack handle those weird cases so we can remove unpreemptible marks from most places. This CL makes user functions preemptible everywhere if they have no write barriers (at least, on x86). In cmd/go the fraction of functions that need preemptible markings drops from 82% to 36%. Makes the cmd/go binary 0.3% smaller. Update #35470 Change-Id: Ic83d5eabfd0f6d239a92e65684bcce7e67ff30bb Reviewed-on: https://go-review.googlesource.com/c/go/+/648518 Auto-Submit: Keith Randall <khr@google.com> Reviewed-by: Keith Randall <khr@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-04-01cmd/internal/obj/riscv: add support for vector fixed-point arithmetic ↵Joel Sing
instructions Add support for vector fixed-point arithmetic instructions to the RISC-V assembler. This includes single width saturating addition and subtraction, averaging addition and subtraction and scaling shift instructions. Change-Id: I9aa27e9565ad016ba5bb2b479e1ba70db24e4ff5 Reviewed-on: https://go-review.googlesource.com/c/go/+/646776 Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-03-29cmd/internal/obj/riscv: add support for vector integer arithmetic instructionsJoel Sing
Add support for vector integer arithmetic instructions to the RISC-V assembler. This includes vector addition, subtraction, integer extension, add-with-carry, subtract-with-borrow, bitwise logical operations, comparison, min/max, integer division and multiplication instructions. Change-Id: I8c191ef8e31291e13743732903e4f12356133a46 Reviewed-on: https://go-review.googlesource.com/c/go/+/646775 Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
2025-03-27cmd/internal/obj/riscv,internal/bytealg: synthesize MIN/MAX/MINU/MAXU ↵Joel Sing
instructions Provide a synthesized version of the MIN/MAX/MINU/MAXU instructions if they're not natively available. This allows these instructions to be used in assembly unconditionally. Use MIN in internal/bytealg.compare. Cq-Include-Trybots: luci.golang.try:gotip-linux-riscv64 Change-Id: I8a5a3a59f0a9205e136fc3d673b23eaf3ca469f8 Reviewed-on: https://go-review.googlesource.com/c/go/+/653295 Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-03-27cmd/internal/obj/riscv: improve constant constructionJoel Sing
Attempt to construct large constants that have a consecutive sequence of ones from a small negative constant, with a logical right and/or left shift. This allows for a large range of mask like constants to be constructed with only two or three instructions, avoiding the need to load from memory. Change-Id: I35a77fecdd2df0ed3f33b772d518f85119d4ff66 Reviewed-on: https://go-review.googlesource.com/c/go/+/652778 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
2025-03-21cmd/internal/obj/riscv: factor out shift constant codeJoel Sing
Move the code that tests to see if a constant can be represented by a 32 bit signed integer and a logical left shift. This reduces duplication and increases readability. Also add test coverage now that this is an independent function. Change-Id: Id25395b1380b00cf5b69ca201b7715ef84f7ade6 Reviewed-on: https://go-review.googlesource.com/c/go/+/652777 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-03-20cmd/internal/obj/riscv: fix the encoding for REV8 and ORCBMark Ryan
The instructions are currently encoded and validated using an iIIEncoding which is incorrect as these instructions do not take an immediate operand. Encode them instead using an rIIEncoding as is done for the other two register argument bitmanip instructions. Change-Id: Ia4d9c6f6ebd2dfc381935ebc11afa8fc3664232b Reviewed-on: https://go-review.googlesource.com/c/go/+/637317 Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-03-19cmd/internal/obj/riscv: prevent panics on bad branchesMark Ryan
Syntactically incorrect branches, such as BEQ X5, X6, $1 BEQ X5, X6, 31(X10) cause the assembler to panic, which they shouldn't really do. It's better for the user to see a normal error, as reported for other syntax errors in riscv64 assembly. The panics also prevent us from writing negative tests for these sorts of errors. Here we fix the issue by ensuring we generate a normal error instead of panicking when the user provides an invalid branch target. We also add a couple of negative tests. Change-Id: I1da568999a75097484b61a01d418f5d4be3e04fa Reviewed-on: https://go-review.googlesource.com/c/go/+/637316 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
2025-03-18cmd/internal/obj/riscv: prevent duplicate error reportsMark Ryan
The riscv64 Go assembler can output certain errors, ones produced by instructionsForProg, multiple times. These errors are guaranteed to be output at least twice and can appear three or more times if a rescan is needed to recompute branch addresses. For example, the syntactically incorrect instruction MOV (X10), $1 will generate at least two identical errors asm: 86076 (asm.s:21524) MOV (X10), $1: unsupported MOV asm: 86076 (asm.s:21524) MOV (X10), $1: unsupported MOV asm: assembly failed In addition to confusing the user, these duplicate errors make it difficult to write negative tests for certain types of instructions, e.g., branches, whose duplicate errors are not always identical, and so not ignored by endtoend_test.go. We fix the issue by returning from preprocess if any errors have been generated by the time we reach the end of the rescan loop. One implication of this change is that validation errors will no longer be reported if an error is generated earlier in the preprocess stage. Negative test cases for validation errors are therefore moved to their own file as the existing riscv64error.s file contains errors generated by instructionsForProg that will now suppress the validation errors. Change-Id: Iffacdbefce28f44970dd5dda44990b822b8a23d4 Reviewed-on: https://go-review.googlesource.com/c/go/+/637315 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Joel Sing <joel@sing.id.au> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-03-01cmd/internal/obj/riscv: add riscv64 CSR mapMark Ryan
The map is automatically generated by running the latest version of parse.py from github.com/riscv/riscv-opcodes. Change-Id: I05e00ab27ec583750752c25e1835c2578b339fbf Reviewed-on: https://go-review.googlesource.com/c/go/+/630518 Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Pengcheng Wang <wangpengcheng.pp@bytedance.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Joel Sing <joel@sing.id.au> Reviewed-by: Michael Pratt <mpratt@google.com>
2025-02-27cmd/internal/obj/riscv: implement vector load/store instructionsJoel Sing
Implement vector unit stride, vector strided, vector indexed and vector whole register load and store instructions. The vector unit stride instructions take an optional vector mask register, which if specified must be register V0. If only two operands are given, the instruction is encoded as unmasked. The vector strided and vector indexed instructions also take an optional vector mask register, which if specified must be register V0. If only three operands are given, the instruction is encoded as unmasked. Cq-Include-Trybots: luci.golang.try:gotip-linux-riscv64 Change-Id: I35e43bb8f1cf6ae8826fbeec384b95ac945da50f Reviewed-on: https://go-review.googlesource.com/c/go/+/631937 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Pengcheng Wang <wangpengcheng.pp@bytedance.com>
2025-02-19all: implement plugin build mode for riscv64Meng Zhuo
Change-Id: I8d7bbeebbf4a46f2fd8d630b1edbaf79b8ffccc5 Reviewed-on: https://go-review.googlesource.com/c/go/+/420114 Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> TryBot-Bypass: Joel Sing <joel@sing.id.au>
2025-02-14cmd/internal/obj/riscv: support MOVD with floating point constantsJoel Sing
Currently, we only support loading of values from memory (or other registers). Add floating point constant support to MOVD. This is implemented by storing the floating point constant to a symbol, which is then loaded into the floating point register. Change-Id: I6db242d27f606f0d5d084a3ab93538698d3a4f8c Reviewed-on: https://go-review.googlesource.com/c/go/+/631876 Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
generated by cgit v1.3 (git 2.53.0) at 2026-04-15 19:23:18 +0000