diff options
| author | Joel Sing <joel@sing.id.au> | 2024-11-24 12:39:20 +1100 |
|---|---|---|
| committer | Joel Sing <joel@sing.id.au> | 2025-02-14 07:13:11 -0800 |
| commit | c8545439b596ffc88d09b9f6970fefdf69fcfc5d (patch) | |
| tree | a3ec5f07be452bfc110f9e577d908d47efd740b1 /src/cmd/internal/obj/riscv/cpu.go | |
| parent | b16c04f43993436f24b1e4155a4652193eb1b90c (diff) | |
| download | go-c8545439b596ffc88d09b9f6970fefdf69fcfc5d.tar.xz | |
cmd/asm,cmd/internal/obj/riscv: implement vector configuration setting instructions
Implement vector configuration setting instructions (VSETVLI,
VSETIVLI, VSETL). These allow the vector length (vl) and vector
type (vtype) CSRs to be configured via a single instruction.
Unfortunately each instruction has its own dedicated encoding.
In the case of VSETVLI/VSETIVLI, the vector type is specified via
a series of special operands, which specify the selected element
width (E8, E16, E32, E64), the vector register group multiplier
(M1, M2, M4, M8, MF2, MF4, MF8), the vector tail policy (TU, TA)
and vector mask policy (MU, MA). Note that the order of these
special operands matches non-Go assemblers.
Partially based on work by Pengcheng Wang <wangpengcheng.pp@bytedance.com>.
Cq-Include-Trybots: luci.golang.try:gotip-linux-riscv64
Change-Id: I431f59c1e048a3e84754f0643a963da473a741fe
Reviewed-on: https://go-review.googlesource.com/c/go/+/631936
Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
Diffstat (limited to 'src/cmd/internal/obj/riscv/cpu.go')
| -rw-r--r-- | src/cmd/internal/obj/riscv/cpu.go | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/src/cmd/internal/obj/riscv/cpu.go b/src/cmd/internal/obj/riscv/cpu.go index 2b75ed38a6..143164ac41 100644 --- a/src/cmd/internal/obj/riscv/cpu.go +++ b/src/cmd/internal/obj/riscv/cpu.go @@ -1227,6 +1227,77 @@ const ( RM_RMM // Round to Nearest, ties to Max Magnitude ) +type SpecialOperand int + +const ( + SPOP_BEGIN SpecialOperand = obj.SpecialOperandRISCVBase + + // Vector mask policy. + SPOP_MA SpecialOperand = obj.SpecialOperandRISCVBase + iota - 1 + SPOP_MU + + // Vector tail policy. + SPOP_TA + SPOP_TU + + // Vector register group multiplier (VLMUL). + SPOP_M1 + SPOP_M2 + SPOP_M4 + SPOP_M8 + SPOP_MF2 + SPOP_MF4 + SPOP_MF8 + + // Vector selected element width (VSEW). + SPOP_E8 + SPOP_E16 + SPOP_E32 + SPOP_E64 + + SPOP_END +) + +var specialOperands = map[SpecialOperand]struct { + encoding uint32 + name string +}{ + SPOP_MA: {encoding: 1, name: "MA"}, + SPOP_MU: {encoding: 0, name: "MU"}, + + SPOP_TA: {encoding: 1, name: "TA"}, + SPOP_TU: {encoding: 0, name: "TU"}, + + SPOP_M1: {encoding: 0, name: "M1"}, + SPOP_M2: {encoding: 1, name: "M2"}, + SPOP_M4: {encoding: 2, name: "M4"}, + SPOP_M8: {encoding: 3, name: "M8"}, + SPOP_MF2: {encoding: 5, name: "MF2"}, + SPOP_MF4: {encoding: 6, name: "MF4"}, + SPOP_MF8: {encoding: 7, name: "MF8"}, + + SPOP_E8: {encoding: 0, name: "E8"}, + SPOP_E16: {encoding: 1, name: "E16"}, + SPOP_E32: {encoding: 2, name: "E32"}, + SPOP_E64: {encoding: 3, name: "E64"}, +} + +func (so SpecialOperand) encode() uint32 { + op, ok := specialOperands[so] + if ok { + return op.encoding + } + return 0 +} + +func (so SpecialOperand) String() string { + op, ok := specialOperands[so] + if ok { + return op.name + } + return "" +} + // All unary instructions which write to their arguments (as opposed to reading // from them) go here. The assembly parser uses this information to populate // its AST in a semantically reasonable way. |
