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34 hourscmd/asm, cmd/internal/obj/arm64: support SVE register listsJunyang Shao
This CL adds the register list support for SVE: [Z1.B, Z2.B] [P1.B, P2.B] [Z1.D] [Z1.D, Z2.D, Z3.D] [Z1.D, Z2.D, Z3.D, Z4.D] This CL is generated by CL 763780. Change-Id: I92210097a8a7525a5a53a2dce0b7652397275dd6 Reviewed-on: https://go-review.googlesource.com/c/go/+/763820 Reviewed-by: David Chase <drchase@google.com> LUCI-TryBot-Result: golang-scoped@luci-project-accounts.iam.gserviceaccount.com <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2026-03-20cmd/internal/obj/arm64: new arm64 assembling path for SVEJunyang Shao
This CL integrates a new assembling path specifically designed for SVE and other modern ARM64 instructions, utilizing generated instruction tables. It contains the foundational files and modifications to direct the assembling pipeline to use this new data-driven path. In a.out.go, it registers new constants for registers and operand types used by SVE. A new file inst.go is added, which defines the instruction table data types and utility functions for the new path. The entry point from the upstream pipeline is `tryEncode`. `tryEncode` returns false upon an encoding failure, which allows the upstream matching logic to handle multiple potential matches. The exact match is not finalized until an instruction is actually encoded, as detailed in the comments for `elemEncoders`. This CL also introduces the core generated tables (`anames_gen.go`, `encoding_gen.go`, `goops_gen.go`, and `inst_gen.go`) which handle a wide variety of SVE instructions. A comprehensive end-to-end assembly test file (`arm64sveenc.s`) is added, containing hundreds of test cases for these SVE instructions to verify the new encoding path. To facilitate these encodings, this CL implements handling for operand types such as AC_ARNG, AC_PREG, AC_PREGZM, and AC_ZREG. Others are left as TODOs. The generated files in this CL are produced by the `instgen` tool in CL 755180. Original author Eric Fang (eric.fang@arm.com, CL 424137) Change-Id: I483f170c776fcd8edd8b8b04520f9d69ee0855dd Reviewed-on: https://go-review.googlesource.com/c/go/+/742620 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: David Chase <drchase@google.com>
2026-02-17cmd/internal/obj: move ARM64RegisterListOffset from cmd/asm/internal/archAlexander Musman
Change-Id: Ieaacd8c40495e7dad61a068125b1d0e0cee832c4 Reviewed-on: https://go-review.googlesource.com/c/go/+/713500 Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-10-15cmd/internal/obj: move ARM64RegisterExtension from cmd/asm/internal/archVasily Leonenko
Change-Id: Iab41674953655efa7be3d306dfb3f5be486be501 Reviewed-on: https://go-review.googlesource.com/c/go/+/701455 Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Keith Randall <khr@google.com>
2025-02-14cmd/asm,cmd/internal/obj/riscv: implement vector configuration setting ↵Joel Sing
instructions Implement vector configuration setting instructions (VSETVLI, VSETIVLI, VSETL). These allow the vector length (vl) and vector type (vtype) CSRs to be configured via a single instruction. Unfortunately each instruction has its own dedicated encoding. In the case of VSETVLI/VSETIVLI, the vector type is specified via a series of special operands, which specify the selected element width (E8, E16, E32, E64), the vector register group multiplier (M1, M2, M4, M8, MF2, MF4, MF8), the vector tail policy (TU, TA) and vector mask policy (MU, MA). Note that the order of these special operands matches non-Go assemblers. Partially based on work by Pengcheng Wang <wangpengcheng.pp@bytedance.com>. Cq-Include-Trybots: luci.golang.try:gotip-linux-riscv64 Change-Id: I431f59c1e048a3e84754f0643a963da473a741fe Reviewed-on: https://go-review.googlesource.com/c/go/+/631936 Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2022-09-29cmd/asm: optimize if statement to return directlycuiweixie
Change-Id: Ieb8fb7c623ecd8b9ddd15cdb6eb2c6326a9bbd3b Reviewed-on: https://go-review.googlesource.com/c/go/+/435941 Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> TryBot-Result: Gopher Robot <gobot@golang.org> Run-TryBot: Ian Lance Taylor <iant@google.com> Run-TryBot: Cherry Mui <cherryyz@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Auto-Submit: Ian Lance Taylor <iant@google.com>
2022-09-29cmd/asm: use opd.String() instead of fmt.Sprintfcuiweixie
Change-Id: Idbade74025bddb26ec3c10527de5af5dc2b8c1cd Reviewed-on: https://go-review.googlesource.com/c/go/+/435940 TryBot-Result: Gopher Robot <gobot@golang.org> Reviewed-by: Cherry Mui <cherryyz@google.com> Run-TryBot: Cherry Mui <cherryyz@google.com> Reviewed-by: Ian Lance Taylor <iant@google.com> Auto-Submit: Ian Lance Taylor <iant@google.com> Run-TryBot: Ian Lance Taylor <iant@google.com>
2022-08-09cmd/asm: add VTBX instruction on arm64Nick Ripley
Change-Id: Icd9eeb78bfc0c0bbe19dcb9841c9fdc0abc29cc9 Reviewed-on: https://go-review.googlesource.com/c/go/+/413314 TryBot-Result: Gopher Robot <gobot@golang.org> Reviewed-by: Than McIntosh <thanm@google.com> Run-TryBot: Cherry Mui <cherryyz@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2022-05-23cmd/internal/obj/arm64: fix encoding of ADR/ADRP instructionCherry Mui
The referenced address is p.From, not p.To. Separate from CL 403980, as this is a bug fix. Also, ADR is used in CL 387336. This is needed to make it work correctly. Change-Id: Ie0baaeb359b9a7f233458d2becf25dc6a1f8ecbf Reviewed-on: https://go-review.googlesource.com/c/go/+/407884 Reviewed-by: David Chase <drchase@google.com> Run-TryBot: Cherry Mui <cherryyz@google.com> TryBot-Result: Gopher Robot <gobot@golang.org>
2022-04-01cmd/asm: refactor some operands that are not special registers on arm64erifan01
The previous code treats some operands such as EQ, LT, etc. as special registers. However, they are not. This CL adds a new AddrType TYPE_SPOPD and a new class C_SPOPD to support this kind of special operands, and refactors the relevant code. This patch is a copy of CL 260861, contributed by Junchen Li(junchen.li@arm.com). Co-authored-by: Junchen Li(junchen.li@arm.com) Change-Id: I57b28da458ee3332f610602632e7eda03af435f5 Reviewed-on: https://go-review.googlesource.com/c/go/+/302849 Reviewed-by: Cherry Mui <cherryyz@google.com> Trust: Eric Fang <eric.fang@arm.com> Run-TryBot: Eric Fang <eric.fang@arm.com> TryBot-Result: Gopher Robot <gobot@golang.org>
2021-08-20cmd/asm/internal/arch: adds the missing type check for arm64 SXTB extensioneric fang
Operands of memory type do not support SXTB extension. This CL adds this missing check. Change-Id: I1fa438dd314fc8aeb889637079cc67b538e83a89 Reviewed-on: https://go-review.googlesource.com/c/go/+/342769 Reviewed-by: eric fang <eric.fang@arm.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Run-TryBot: eric fang <eric.fang@arm.com> TryBot-Result: Go Bot <gobot@golang.org> Trust: Michael Knyszek <mknyszek@google.com>
2021-04-28cmd/asm: add check for register and shift/extension combination on arm64eric fang
The current code lacks a check on whether the register and shift/extension combination is valid, for example the follow instructions also compiles. ADD F1<<1, R1, R3 ADD V1<<1, R1, R3 MOVW (R9)(F8.SXTW<<2), R19 VST1 R4.D[1], (R0) Actually only general registers can perform shift operations, and element and arrangement extensions are only applicable to vector registers. This CL adds a check for the register and shift/extension combination on arm64. Change-Id: I93dd9343e92a66899cba8eaf4e0ac5430e94692b Reviewed-on: https://go-review.googlesource.com/c/go/+/312571 Trust: eric fang <eric.fang@arm.com> Reviewed-by: eric fang <eric.fang@arm.com> Reviewed-by: Keith Randall <khr@golang.org> Run-TryBot: eric fang <eric.fang@arm.com> TryBot-Result: Go Bot <gobot@golang.org>
2020-10-29cmd/internal/obj/arm64: add CASx/CASPx instructionsfanzha02
This patch adds support for CASx and CASPx atomic instructions. go syntax gnu syntax CASD Rs, (Rn|RSP), Rt => cas Xs, Xt, (Xn|SP) CASALW Rs, (Rn|RSP), Rt => casal Ws, Wt, (Xn|SP) CASPD (Rs, Rs+1), (Rn|RSP), (Rt, Rt+1) => casp Xs, Xs+1, Xt, Xt+1, (Xn|SP) CASPW (Rs, Rs+1), (Rn|RSP), (Rt, Rt+1) => casp Ws, Ws+1, Wt, Wt+1, (Xn|SP) This patch changes the type of prog.RestArgs from "[]Addr" to "[]struct{Addr, Pos}", Pos is a enum, indicating the position of the operand. This patch also adds test cases. Change-Id: Ib971cfda7890b7aa895d17bab22dea326c7fcaa4 Reviewed-on: https://go-review.googlesource.com/c/go/+/233277 Trust: fannie zhang <Fannie.Zhang@arm.com> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2020-09-25cmd/asm: fix the issue of moving 128-bit integers to vector registers on arm64fanzha02
The CL 249758 added `FMOVQ $vcon, Vd` instruction and assembler used 128-bit simd literal-loading to load `$vcon` from pool into 128-bit vector register `Vd`. Because Go does not have 128-bit integers for now, the assembler will report an error of `immediate out of range` when assembleing `FMOVQ $0x123456789abcdef0123456789abcdef, V0` instruction. This patch lets 128-bit integers take two 64-bit operands, for the high and low parts separately and adds `VMOVQ $hi, $lo, Vd` instruction to move `$hi<<64+$lo' into 128-bit register `Vd`. In addition, this patch renames `FMOVQ/FMOVD/FMOVS` ops to 'VMOVQ/VMOVD/VMOVS' and uses them to move 128-bit, 64-bit and 32-bit constants into vector registers, respectively Update the go doc. Fixes #40725 Change-Id: Ia3c83bb6463f104d2bee960905053a97299e0a3a Reviewed-on: https://go-review.googlesource.com/c/go/+/255900 Trust: fannie zhang <Fannie.Zhang@arm.com> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2019-03-06cmd/asm: add arm64 v8.1 atomic instructionserifan01
This change adds several arm64 v8.1 atomic instructions and test cases. They are LDADDAx, LDADDLx, LDANDAx, LDANDALx, LDANDLx, LDEORAx, LDEORALx, LDEORLx, LDORAx, LDORALx, LDORLx, SWPAx and SWPLx. Their form is consistent with the form of the existing atomic instructions. For instructions STXRx, STLXRx, STXPx and STLXPx, the second destination register can't be RSP. This CL also adds a check for this. LDADDx Rs, (Rb), Rt: *Rb -> Rt, Rs + *Rb -> *Rb LDANDx Rs, (Rb), Rt: *Rb -> Rt, Rs AND NOT(*Rb) -> *Rb LDEORx Rs, (Rb), Rt: *Rb -> Rt, Rs EOR *Rb -> *Rb LDORx Rs, (Rb), Rt: *Rb -> Rt, Rs OR *Rb -> *Rb Change-Id: I9f9b0245958cb57ab7d88c66fb9159b23b9017fd Reviewed-on: https://go-review.googlesource.com/c/go/+/157001 Reviewed-by: Cherry Zhang <cherryyz@google.com> Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org>
2018-09-04cmd/internal/obj/arm64: support more atomic instructionsBen Shi
LDADDALD(64-bit) and LDADDALW(32-bit) are already supported. This CL adds supports of LDADDALH(16-bit) and LDADDALB(8-bit). Change-Id: I4eac61adcec226d618dfce88618a2b98f5f1afe7 Reviewed-on: https://go-review.googlesource.com/132135 Run-TryBot: Ben Shi <powerman1st@163.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2018-08-20cmd/internal/obj/arm64: add SWPALD/SWPALW/SWPALH/SWPALBBen Shi
Those new instructions have acquire/release semantics, besides normal atomic SWPD/SWPW/SWPH/SWPB. Change-Id: I24821a4d21aebc342897ae52903aef612c8d8a4a Reviewed-on: https://go-review.googlesource.com/128476 Run-TryBot: Ben Shi <powerman1st@163.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2018-06-21cmd/compile: improve atomic add intrinsics with ARMv8.1 new instructionWei Xiao
ARMv8.1 has added new instruction (LDADDAL) for atomic memory operations. This CL improves existing atomic add intrinsics with the new instruction. Since the new instruction is only guaranteed to be present after ARMv8.1, we guard its usage with a conditional on CPU feature. Performance result on ARMv8.1 machine: name old time/op new time/op delta Xadd-224 1.05µs ± 6% 0.02µs ± 4% -98.06% (p=0.000 n=10+8) Xadd64-224 1.05µs ± 3% 0.02µs ±13% -98.10% (p=0.000 n=9+10) [Geo mean] 1.05µs 0.02µs -98.08% Performance result on ARMv8.0 machine: name old time/op new time/op delta Xadd-46 538ns ± 1% 541ns ± 1% +0.62% (p=0.000 n=9+9) Xadd64-46 505ns ± 1% 508ns ± 0% +0.48% (p=0.003 n=9+8) [Geo mean] 521ns 524ns +0.55% Change-Id: If4b5d8d0e2d6f84fe1492a4f5de0789910ad0ee9 Reviewed-on: https://go-review.googlesource.com/81877 Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2018-05-03cmd/internal/obj/arm64: add more atomic instructionsBen Shi
More atomic instructions were introduced in ARMv8.1. And this CL adds support for them and corresponding test cases. LDADD Rs, (Rb), Rt: (Rb) -> Rt, Rs+(Rb) -> (Rb) LDAND Rs, (Rb), Rt: (Rb) -> Rt, Rs&(Rb) -> (Rb) LDEOR Rs, (Rb), Rt: (Rb) -> Rt, Rs^(Rb) -> (Rb) LDOR Rs, (Rb), Rt: (Rb) -> Rt, Rs|(Rb) -> (Rb) Change-Id: Ifb9df86583c4dc54fb96274852c3b93a197045e4 Reviewed-on: https://go-review.googlesource.com/110535 Reviewed-by: Cherry Zhang <cherryyz@google.com> Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org>
2018-04-30cmd/asm: add vector instructions for ChaCha20Poly1305 on ARM64Balaram Makam
This change provides VZIP1, VZIP2, VTBL instruction for supporting ChaCha20Poly1305 implementation later. Change-Id: Ife7c87b8ab1a6495a444478eeb9d906ae4c5ffa9 Reviewed-on: https://go-review.googlesource.com/110015 Reviewed-by: Cherry Zhang <cherryyz@google.com> Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org>
2018-04-18cmd/internal/obj/arm64: refactor the extended/shifted register encoding to ↵fanzha02
the backend The current code encodes the register and the shift/extension into a.Offset field and this is done in the frontend. The CL refactors it to have the frontend record the register/shift/extension information in a.Reg or a.Index and leave the encoding stuff for the backend. Change-Id: I600f456aec95377b7b79cd58e94afcb30aca5d19 Reviewed-on: https://go-review.googlesource.com/106815 Reviewed-by: Cherry Zhang <cherryyz@google.com> Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org>
2018-04-11cmd/internal/obj/arm64: support SWPD/SWPW/SWPH/SWPBBen Shi
SWPD/SWPW/SWPH/SWPB were introduced in ARMv8.1. They swap content of register and memory atomically. And their difference is SWPD: 64-bit double word data SWPW: 32-bit word data (zero extended to 64-bit) SWPH: 16-bit half word data (zero extended to 64-bit) SWPB: 8-bit byte data (zero extended to 64-bit) This CL implements them in the arm64 assembler. Change-Id: I2d9fb2310674bd92693531210e187143e7eed602 Reviewed-on: https://go-review.googlesource.com/101516 Reviewed-by: Cherry Zhang <cherryyz@google.com> Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org>
2018-04-09cmd/internal/obj/arm64: add assembler support for load with register offsetfanzha02
The patch adds support for LDR(register offset) instruction. And add the test cases and negative tests. Change-Id: I5b32c6a5065afc4571116d4896f7ebec3c0416d3 Reviewed-on: https://go-review.googlesource.com/87955 Reviewed-by: Cherry Zhang <cherryyz@google.com>
2018-04-06cmd/asm/internal/arch: unexport ParseARM64SuffixTobias Klauser
ParseARM64Suffix is not used outside cmd/asm/internal/arch. Change-Id: I8e7782dce11cf8cd2fd08dd17e555ced8d87ba24 Reviewed-on: https://go-review.googlesource.com/105115 Run-TryBot: Tobias Klauser <tobias.klauser@gmail.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Daniel Martí <mvdan@mvdan.cc> Reviewed-by: Brad Fitzpatrick <bradfitz@golang.org>
2018-04-03cmd/asm: add essential instructions for AES-GCM on ARM64Fangming.Fang
This change adds VLD1, VST1, VPMULL{2}, VEXT, VRBIT, VUSHR and VSHL instructions for supporting AES-GCM implementation later. Fixes #24400 Change-Id: I556feb88067f195cbe25629ec2b7a817acc58709 Reviewed-on: https://go-review.googlesource.com/101095 Reviewed-by: Cherry Zhang <cherryyz@google.com> Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org>
2018-03-12cmd/asm: fix ARM64 vector register arrangement encoding bugfanzha02
The current code assigns vector register arrangement a wrong value when the arrangement specifier is S2, which causes the incorrect assembly. The patch fixes the issue and adds the test cases. Fixes #24249 Change-Id: I9736df1279494003d0b178da1af9cee9cd85ce21 Reviewed-on: https://go-review.googlesource.com/98555 Reviewed-by: Cherry Zhang <cherryyz@google.com> Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org>
2018-02-28cmd/asm: enable several arm64 load & store instructionserifan01
Instructions LDARB, LDARH, LDAXPW, LDAXP, STLRB, STLRH, STLXP, STLXPW, STXP, STXPW have been added before, but they are not enabled. This CL enabled them. Change the form of LDXP and LDXPW to the form of LDP, and fix a bug of STLXP. Change-Id: I5d2b51494b92451bf6b072c65cfdd8acf07e9b54 Reviewed-on: https://go-review.googlesource.com/96215 Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2018-02-26cmd: avoid unnecessary type conversionsKunpei Sakai
CL generated mechanically with github.com/mdempsky/unconvert. Also updated cmd/compile/internal/ssa/gen/*.rules manually. Change-Id: If721ef73cf0771ae83ce7e2d11623fc8d9155768 Reviewed-on: https://go-review.googlesource.com/97075 Reviewed-by: Matthew Dempsky <mdempsky@google.com> Run-TryBot: Matthew Dempsky <mdempsky@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org>
2018-02-22cmd/asm: add arm64 instructions for math optimizationerifan01
Add arm64 HW instructions FMADDD, FMADDS, FMSUBD, FMSUBS, FNMADDD, FNMADDS, FNMSUBD, FNMSUBS, VFMLA, VFMLS, VMOV (element) for math optimization. Add check on register element index and test cases. Change-Id: Ice07c50b1a02d488ad2cde2a4e8aea93f3e3afff Reviewed-on: https://go-review.googlesource.com/90876 Reviewed-by: Cherry Zhang <cherryyz@google.com>
2018-02-20all: fix misspellingsShawn Smith
GitHub-Last-Rev: 468df242d07419c228656985702325aa78952d99 GitHub-Pull-Request: golang/go#23935 Change-Id: If751ce3ffa3a4d5e00a3138211383d12cb6b23fc Reviewed-on: https://go-review.googlesource.com/95577 Run-TryBot: Andrew Bonventre <andybons@golang.org> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Andrew Bonventre <andybons@golang.org>
2018-02-06cmd/internal/obj/arm64: fix assemble add/adds/sub/subs/cmp/cmn(extended ↵fanzha02
register) bug The current code encodes the wrong option value in the binary. The fix reconstructs the function opxrrr() that does not encode the option value into the binary value when arguments is sign or zero-extended register. Add the relevant test cases and negative tests. Fixes #23501 Change-Id: Ie5850ead2ad08d9a235a5664869aac5051762f1f Reviewed-on: https://go-review.googlesource.com/88876 Run-TryBot: Cherry Zhang <cherryyz@google.com> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2017-10-13cmd/asm: refine Go assembly for ARM64Wei Xiao
Some ARM64-specific instructions (such as SIMD instructions) are not supported. This patch adds support for the following: 1. Extended register, e.g.: ADD Rm.<ext>[<<amount], Rn, Rd <ext> can have the following values: UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW and SXTX 2. Arrangement for SIMD instructions, e.g.: VADDP Vm.<T>, Vn.<T>, Vd.<T> <T> can have the following values: B8, B16, H4, H8, S2, S4 and D2 3. Width specifier and element index for SIMD instructions, e.g.: VMOV Vn.<T>[index], Rd // MOV(to general register) <T> can have the following values: S and D 4. Register List, e.g.: VLD1 (Rn), [Vt1.<T>, Vt2.<T>, Vt3.<T>] 5. Register offset variant, e.g.: VLD1.P (Rn)(Rm), [Vt1.<T>, Vt2.<T>] // Rm is the post-index register 6. Go assembly for ARM64 reference manual new added instructions are required to have according explanation items in the manual and items for existed instructions will be added incrementally For more information about the refinement background, please refer to the discussion (https://groups.google.com/forum/#!topic/golang-dev/rWgDxCrL4GU) This patch only adds syntax and doesn't break any assembly that already exists. Change-Id: I34e90b7faae032820593a0e417022c354a882008 Reviewed-on: https://go-review.googlesource.com/41654 Run-TryBot: Cherry Zhang <cherryyz@google.com> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2017-08-23cmd/internal/obj/arm64: fix assemble fcmp/fcmpe bugfanzha02
The current code treats floating-point constant as integer and does not treat fcmp/fcmpe as the comparison instrucitons that requires special handling. The fix corrects the type of immediate arguments and adds fcmp/fcmpe in the special handing. Uncomment the fcmp/fcmpe cases. Fixes #21567 Change-Id: I6782520e2770f6ce70270b667dd5e68f71e2d5ad Reviewed-on: https://go-review.googlesource.com/57852 Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2017-08-15cmd/internal/obj/arm64: fix assemble stxr/stxrw/stxrb/stxrh bugfanzha02
The stxr/stxrw/stxrb/stxrh instructions belong to STLXR-like instructions set and they require special handling. The current code has no special handling for those instructions. The fix adds the special handling for those instructions. Uncomment stxr/stxrw/stxrb/stxrh test cases. Fixes #21397 Change-Id: I31cee29dd6b30b1c25badd5c7574dda7a01bf016 Reviewed-on: https://go-review.googlesource.com/54951 Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2017-03-24cmd/asm: fix TBZ/TBNZ instructions on arm64wei xiao
Fixes #18069 Also added a test in: cmd/asm/internal/asm/testdata/arm64.s Change-Id: Iee400bda4f30503ea3c1dc5bb8301568f19c92d1 Signed-off-by: Wei Xiao <wei.xiao@arm.com> Reviewed-on: https://go-review.googlesource.com/33594 Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2016-03-08cmd/internal/obj: add As type for assembly opcodesMatthew Dempsky
Passes toolstash/buildall. Fixes #14692. Change-Id: I4352678d8251309f2b8b7793674c550fac948006 Reviewed-on: https://go-review.googlesource.com/20350 Reviewed-by: Dave Cheney <dave@cheney.net> Reviewed-by: Brad Fitzpatrick <bradfitz@golang.org>
2015-07-28cmd/asm: fix and test CALL, JMP aliases on arm, arm64, ppc64Russ Cox
Fixes #11900. Change-Id: Idfc54e1fac833c8d646266128efe46214a82dfed Reviewed-on: https://go-review.googlesource.com/12741 Reviewed-by: David Crawshaw <crawshaw@golang.org> Reviewed-by: Rob Pike <r@golang.org>
2015-03-16cmd/asm: add support for ARM64Aram Hăvărneanu
Pre/post-index addressing modes with writeback use .W and .P instruction suffixes, like on ARM. Complex addressing modes are not supported yet. Change-Id: I537a1c3fe5b057c0812662677d0010bc8c468ffb Reviewed-on: https://go-review.googlesource.com/7047 Reviewed-by: Rob Pike <r@golang.org>
generated by cgit v1.3 (git 2.53.0) at 2026-04-15 06:13:54 +0000