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37 hourscmd/asm, cmd/internal/obj/arm64: support SVE register listsJunyang Shao
This CL adds the register list support for SVE: [Z1.B, Z2.B] [P1.B, P2.B] [Z1.D] [Z1.D, Z2.D, Z3.D] [Z1.D, Z2.D, Z3.D, Z4.D] This CL is generated by CL 763780. Change-Id: I92210097a8a7525a5a53a2dce0b7652397275dd6 Reviewed-on: https://go-review.googlesource.com/c/go/+/763820 Reviewed-by: David Chase <drchase@google.com> LUCI-TryBot-Result: golang-scoped@luci-project-accounts.iam.gserviceaccount.com <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2026-03-31cmd/internal/obj/riscv: add support for FENCE operands and FENCE.TSOwangboyao
Add support for fine-grained memory ordering flags in the RISC-V FENCE instruction to the assembler. This implements instruction validation and encoding for predecessor and successor flags (I, O, R, W) rather than always falling back to a full memory barrier. This allows more precise memory barriers like FENCE R, RW or FENCE W, W. Additionally, this adds assembly support for the FENCE.TSO, which is encoded as FENCE RW, RW with the fm field set to 1000. Change-Id: Ie9c6c8cd24b38b08013032972bd54515eaedd637 Reviewed-on: https://go-review.googlesource.com/c/go/+/758000 Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2026-03-20cmd/internal/obj/arm64: new arm64 assembling path for SVEJunyang Shao
This CL integrates a new assembling path specifically designed for SVE and other modern ARM64 instructions, utilizing generated instruction tables. It contains the foundational files and modifications to direct the assembling pipeline to use this new data-driven path. In a.out.go, it registers new constants for registers and operand types used by SVE. A new file inst.go is added, which defines the instruction table data types and utility functions for the new path. The entry point from the upstream pipeline is `tryEncode`. `tryEncode` returns false upon an encoding failure, which allows the upstream matching logic to handle multiple potential matches. The exact match is not finalized until an instruction is actually encoded, as detailed in the comments for `elemEncoders`. This CL also introduces the core generated tables (`anames_gen.go`, `encoding_gen.go`, `goops_gen.go`, and `inst_gen.go`) which handle a wide variety of SVE instructions. A comprehensive end-to-end assembly test file (`arm64sveenc.s`) is added, containing hundreds of test cases for these SVE instructions to verify the new encoding path. To facilitate these encodings, this CL implements handling for operand types such as AC_ARNG, AC_PREG, AC_PREGZM, and AC_ZREG. Others are left as TODOs. The generated files in this CL are produced by the `instgen` tool in CL 755180. Original author Eric Fang (eric.fang@arm.com, CL 424137) Change-Id: I483f170c776fcd8edd8b8b04520f9d69ee0855dd Reviewed-on: https://go-review.googlesource.com/c/go/+/742620 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: David Chase <drchase@google.com>
2026-02-17cmd/internal/obj: move ARM64RegisterListOffset from cmd/asm/internal/archAlexander Musman
Change-Id: Ieaacd8c40495e7dad61a068125b1d0e0cee832c4 Reviewed-on: https://go-review.googlesource.com/c/go/+/713500 Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2026-02-14cmd/internal/obj/loong64: improve ARNG type register name conversionGuoqi Chen
When resolving ARNG type names, the base value was not subtracted when calculating the variable simd_type, causing its actual value to not match the expected meaning after the base value adjustment. Fixes #77414 Change-Id: I713bab849ecdb5610d2593ba9bd9e1169842f00e Reviewed-on: https://go-review.googlesource.com/c/go/+/742980 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Michael Pratt <mpratt@google.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Meidan Li <limeidan@loongson.cn>
2025-11-13cmd/asm,cmd/internal/obj/riscv: add support for riscv compressed instructionsJoel Sing
Add support for compressed instructions in the RISC-V assembler. This implements instruction validation and encoding for all instructions in the "C" extension. It is worth noting that the validation and encoding of these instructions is far more convoluted then the typical instruction validation and encoding. While the current model has been followed for now, it would be worth revisiting this in the future and potentially switching to a table based or even per-instruction implementation. Additionally, the current instruction encoding is lacking some of the bits needed for compressed instructions - this is solved by compressedEncoding, which provides the missing information. This will also be addressed in the future, likely by changing the instruction encoding format. Updates #71105 Change-Id: I0f9359d63f93ebbdc6e708e79429b2d61eae220d Reviewed-on: https://go-review.googlesource.com/c/go/+/713020 Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
2025-10-15cmd/internal/obj: move ARM64RegisterExtension from cmd/asm/internal/archVasily Leonenko
Change-Id: Iab41674953655efa7be3d306dfb3f5be486be501 Reviewed-on: https://go-review.googlesource.com/c/go/+/701455 Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Keith Randall <khr@google.com>
2025-09-12cmd/asm, cmd/internal/obj: add riscv64 generic CSR opsMark Ryan
Support is added for the generic RISC-V CSR operations; CSRRC, CSRRCI, CSRRS, CSRRSI, CSRRW, CSRRWI. These instructions require special handling as their second operand is a symbolic CSR register name and not an immediate value or a register. CSR names are implemented as special operands. RISC-V CSRs are not currently saved and restored when a go routine is asynchronously pre-empted so it is only safe to use these instructions in hand written assembler. Note that CSRRS was already partially supported by the assembler so this restriction predates this commit. We mention it here as this commit makes CSRRS much easier to use. Change-Id: I9ff8d804328b418a879d463e7d9cc31f489c7a00 Reviewed-on: https://go-review.googlesource.com/c/go/+/630519 Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Michael Pratt <mpratt@google.com>
2025-08-05cmd: remove dead codeqiulaidongfeng
Fixes #74076 Change-Id: Icc67b3d4e342f329584433bd1250c56ae8f5a73d Reviewed-on: https://go-review.googlesource.com/c/go/+/690635 Reviewed-by: Alan Donovan <adonovan@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Commit-Queue: Alan Donovan <adonovan@google.com> Reviewed-by: Keith Randall <khr@golang.org> Reviewed-by: Keith Randall <khr@google.com> Auto-Submit: Alan Donovan <adonovan@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2025-05-12cmd/internal/obj/loong64: Add preld{,x} instructions supportGuoqi Chen
Go asm syntax: PRELD 16(R4), $8 PRELDX (R4)(R5), $8 Equivalent platform assembler syntax: preld $8, $r4, 16 preldx $8, $r4, $r5 Change-Id: Ie81d22ebaf4153388a7e9d8fa0f618a0ae7a1c9f Reviewed-on: https://go-review.googlesource.com/c/go/+/671875 Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Michael Knyszek <mknyszek@google.com>
2025-02-14cmd/asm,cmd/internal/obj/riscv: implement vector configuration setting ↵Joel Sing
instructions Implement vector configuration setting instructions (VSETVLI, VSETIVLI, VSETL). These allow the vector length (vl) and vector type (vtype) CSRs to be configured via a single instruction. Unfortunately each instruction has its own dedicated encoding. In the case of VSETVLI/VSETIVLI, the vector type is specified via a series of special operands, which specify the selected element width (E8, E16, E32, E64), the vector register group multiplier (M1, M2, M4, M8, MF2, MF4, MF8), the vector tail policy (TU, TA) and vector mask policy (MU, MA). Note that the order of these special operands matches non-Go assemblers. Partially based on work by Pengcheng Wang <wangpengcheng.pp@bytedance.com>. Cq-Include-Trybots: luci.golang.try:gotip-linux-riscv64 Change-Id: I431f59c1e048a3e84754f0643a963da473a741fe Reviewed-on: https://go-review.googlesource.com/c/go/+/631936 Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2024-11-21cmd/internal/obj/ppc64: support for decimal floating point instructionsJayanth Krishnamurthy jayanth.krishnamurthy@ibm.com
1. Support for decimal arithmetic quad instructions of powerpc: DADDQ, DSUBQ, DMULQ and DDIVQ. 2. Support for decimal compare ordered, unordered, quad instructions of powerpc: DCMPU, DCMPO, DCMPUQ, and DCMPOQ. Change-Id: I32a15a7f0a127b022b1f43d376e0ab0f7e9dd108 Cq-Include-Trybots: luci.golang.try:gotip-linux-ppc64_power10,gotip-linux-ppc64_power8,gotip-linux-ppc64le_power8,gotip-linux-ppc64le_power9,gotip-linux-ppc64le_power10 Reviewed-on: https://go-review.googlesource.com/c/go/+/623036 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Auto-Submit: Paul Murphy <murp@ibm.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Paul Murphy <murp@ibm.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2024-11-13cmd/asm: fix format string so vet doesn't complainKeith Randall
Fixes #70309 Change-Id: I4a3e27e89bdfda66d64f2efbb4c08a5ddde34a52 Reviewed-on: https://go-review.googlesource.com/c/go/+/626040 Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Auto-Submit: Keith Randall <khr@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Russ Cox <rsc@golang.org> Reviewed-by: Keith Randall <khr@golang.org> Reviewed-by: Keith Randall <khr@google.com>
2024-11-13cmd/internal/obj/loong64: add support of VMOVQ and XVMOVQGuoqi Chen
This CL refers to the implementation of ARM64 and adds support for the following types of SIMD instructions: 1. Move general-purpose register to a vector element, e.g.: VMOVQ Rj, <Vd>.<T>[index] <T> can have the following values: B, H, W, V 2. Move vector element to general-purpose register, e.g.: VMOVQ <Vj>.<T>[index], Rd <T> can have the following values: B, BU, H, HU, W, WU, VU 3. Duplicate general-purpose register to vector, e.g.: VMOVQ Rj, <Vd>.<T> <T> can have the following values: B16, H8, W4, V2, B32, H16, W8, V4 4. Move vector, e.g.: XVMOVQ Xj, <Xd>.<T> <T> can have the following values: B16, H8, W4, V2, Q1 5. Move vector element to scalar, e.g.: XVMOVQ Xj, <Xd>.<T>[index] XVMOVQ Xj.<T>[index], Xd <T> can have the following values: W, V 6. Move vector element to vector register, e.g.: VMOVQ <Vn>.<T>[index], Vn.<T> <T> can have the following values: B, H, W, V This CL only adds syntax and doesn't break any assembly that already exists. Change-Id: I7656efac6def54da6c5ae182f39c2a21bfdf92bb Reviewed-on: https://go-review.googlesource.com/c/go/+/616258 Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2024-11-07cmd/internal/obj/loong64: add {V,XV}LD/{V,XV}LDX/{V,XV}ST/{V,XV}STX ↵Guoqi Chen
instructions support This CL adding primitive asm support of Loong64 LSX [1] and LASX [2], by introducing new sets of register V0-V31 (C_VREG), X0-X31 (C_XREG) and 8 new instructions. On Loong64, VLD,XVLD,VST,XVST implement vector memory access operations using immediate values offset. VLDX, XVLDX, VSTX, XVSTX implement vector memory access operations using register offset. Go asm syntax: VMOVQ n(RJ), RV (128bit vector load) XVMOVQ n(RJ), RX (256bit vector load) VMOVQ RV, n(RJ) (128bit vector store) XVMOVQ RX, n(RJ) (256bit vector store) VMOVQ (RJ)(RK), RV (128bit vector load) XVMOVQ (RJ)(RK), RX (256bit vector load) VMOVQ RV, (RJ)(RK) (128bit vector store) XVMOVQ RX, (RJ)(RK) (256bit vector store) Equivalent platform assembler syntax: vld vd, rj, si12 xvld xd, rj, si12 vst vd, rj, si12 xvst xd, rj, si12 vldx vd, rj, rk xvldx xd, rj, rk vstx vd, rj, rk xvstx xd, rj, rk [1]: LSX: Loongson SIMD Extension, 128bit [2]: LASX: Loongson Advanced SIMD Extension, 256bit Change-Id: Ibaf5ddfd29b77670c3c44cc32bead36b2c8b8003 Reviewed-on: https://go-review.googlesource.com/c/go/+/616075 Reviewed-by: Qiqi Huang <huangqiqi@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2024-10-24cmd/internal/obj,cmd/asm: add vector registers to riscv64 assemblerJoel Sing
This adds V0 through V31 as vector registers, which are available on CPUs that support the V extension. Change-Id: Ibffee3f9a2cf1d062638715b3744431d72d451ce Reviewed-on: https://go-review.googlesource.com/c/go/+/595404 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Michael Pratt <mpratt@google.com> Reviewed-by: 鹏程汪 <wangpengcheng.pp@bytedance.com>
2024-10-23cmd/asm: add support for LDREXB/STREXBMauri de Souza Meneguzzo
These are 8-bit ARM Load/Store atomics and are available starting from armv6k. See https://developer.arm.com/documentation/dui0379/e/arm-and-thumb-instructions/strex For #69735 Change-Id: I12623433c89070495c178208ee4758b3cdefd368 GitHub-Last-Rev: d6a797836af1dccdcc6e6554725546b386d01615 GitHub-Pull-Request: golang/go#69959 Cq-Include-Trybots: luci.golang.try:gotip-linux-arm Reviewed-on: https://go-review.googlesource.com/c/go/+/621395 Reviewed-by: Keith Randall <khr@google.com> Reviewed-by: Keith Randall <khr@golang.org> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2024-07-29cmd/asm: change register type for loong64 floating-pointXiaolin Zhao
On Loong64, the two input operands and one output operand of the ADDF instruction are both floating-point registers; and the floating-point comparison instruction CMPEQ{F,D}, CMPGE{F,D}, CMPGT{F,D} both input operands are floating-point registers, and the output operation is a floating-point condition register, currently, only FCC0 is used as the floating-point condition register. Example: ADDF F0, F1, F0 CMPEQF F0, F1, FCC0 Change-Id: I4c1c453e522d43f294a8dcab7b6b5247f41c9c68 Reviewed-on: https://go-review.googlesource.com/c/go/+/580281 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Auto-Submit: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Michael Knyszek <mknyszek@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2024-05-22cmd/internal/obj/loong64: add atomic memory access instructions supportGuoqi Chen
The AM* atomic access instruction performs a sequence of “read-modify-write” operations on a memory cell atomically. Specifically, it retrieves the old value at the specified address in memory and writes it to the general register rd, performs some simple operations on the old value in memory and the value in the general register rk, and then write the result of the operation back to the memory address pointed to by general register rj. Go asm syntax: AM{SWAP/ADD/AND/OR/XOR/MAX/MIN}[DB]{W/V} RK, (RJ), RD AM{MAX/MIN}[DB]{WU/VU} RK, (RJ), RD Equivalent platform assembler syntax: am{swap/add/and/or/xor/max/min}[_db].{w/d} rd, rk, rj am{max/min}[_db].{wu/du} rd, rk, rj Ref: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html Change-Id: I99ea4553ae731675180d63691c19ef334e7e7817 Reviewed-on: https://go-review.googlesource.com/c/go/+/481577 Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Mauri de Souza Meneguzzo <mauri870@gmail.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Qiqi Huang <huangqiqi@loongson.cn> Reviewed-by: WANG Xuerui <git@xen0n.name> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2024-05-17cmd/asm: on PPC64, fix assembling of FCMPO opcodePaul E. Murphy
The assembler should pack 3 argument usage of FCMPO similar to other CMP-like opcodes. Fixes #67359 Change-Id: Icfb42a67d741431a70dd880806857b4c38f42d62 Reviewed-on: https://go-review.googlesource.com/c/go/+/585640 Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2023-03-21cmd/asm, runtime: remove the RSB register from loong64WANG Xuerui
It was carryover from the mips64 port (where it represented the platform GP register) but LoongArch platform ABI doesn't have the GP concept. Change-Id: Iea326ae13676e95b040b52aaadc08d311b507bd3 Reviewed-on: https://go-review.googlesource.com/c/go/+/475815 Reviewed-by: abner chenc <chenguoqi@loongson.cn> TryBot-Result: Gopher Robot <gobot@golang.org> Run-TryBot: Cherry Mui <cherryyz@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2023-02-06cmd/asm: add RDTIME{L,H}.W, RDTIME.D support for loong64Guoqi Chen
Instruction formats: rdtime rd, rj The RDTIME family of instructions are used to read constant frequency timer information, the stable counter value is written into the general register rd, and the counter id information is written into the general register rj. (Note: both of its register operands are outputs). Ref: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html Change-Id: Ida5bbb28316ef70b5f616dac3e6fa6f2e77875b5 Reviewed-on: https://go-review.googlesource.com/c/go/+/421655 Reviewed-by: xiaodong liu <teaofmoli@gmail.com> Reviewed-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Wayne Zuo <wdvxdr@golangcn.org> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> Run-TryBot: Wayne Zuo <wdvxdr@golangcn.org> TryBot-Result: Gopher Robot <gobot@golang.org> Reviewed-by: Meidan Li <limeidan@loongson.cn>
2022-11-18all: add missing periods in commentscui fliter
Change-Id: I69065f8adf101fdb28682c55997f503013a50e29 Reviewed-on: https://go-review.googlesource.com/c/go/+/449757 Auto-Submit: Ian Lance Taylor <iant@google.com> Reviewed-by: Joedian Reid <joedian@golang.org> Reviewed-by: Keith Randall <khr@google.com> Reviewed-by: Keith Randall <khr@golang.org> TryBot-Result: Gopher Robot <gobot@golang.org> Run-TryBot: Joedian Reid <joedian@golang.org> Run-TryBot: Ian Lance Taylor <iant@google.com> Reviewed-by: Ian Lance Taylor <iant@google.com>
2022-09-29cmd/asm: optimize if statement to return directlycuiweixie
Change-Id: Ieb8fb7c623ecd8b9ddd15cdb6eb2c6326a9bbd3b Reviewed-on: https://go-review.googlesource.com/c/go/+/435941 Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> TryBot-Result: Gopher Robot <gobot@golang.org> Run-TryBot: Ian Lance Taylor <iant@google.com> Run-TryBot: Cherry Mui <cherryyz@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Auto-Submit: Ian Lance Taylor <iant@google.com>
2022-09-29cmd/asm: use opd.String() instead of fmt.Sprintfcuiweixie
Change-Id: Idbade74025bddb26ec3c10527de5af5dc2b8c1cd Reviewed-on: https://go-review.googlesource.com/c/go/+/435940 TryBot-Result: Gopher Robot <gobot@golang.org> Reviewed-by: Cherry Mui <cherryyz@google.com> Run-TryBot: Cherry Mui <cherryyz@google.com> Reviewed-by: Ian Lance Taylor <iant@google.com> Auto-Submit: Ian Lance Taylor <iant@google.com> Run-TryBot: Ian Lance Taylor <iant@google.com>
2022-09-15cmd/internal/obj/ppc64: add ISA 3.1 instructionsPaul E. Murphy
Use ppc64map (from x/arch) to generate ISA 3.1 support for the assembler. A new file asm9_gtables.go is added which contains generated code to encode ISA 3.1 instructions, a function to assist filling out the oprange structure, a lookup table for the fixed bits of each instructions, and a slice of string name. Generated functions are shared if their bitwise encoding match, and the translation from an obj.Prog structure matches. The generated file is entirely self-contained, and does not require regenerating any other files for changes within it. If opcodes in a.out.go are reordered or changed, anames.go must be updated in the same way as before. Future improvements could shrink the generated opcode table to 32 bit entries as there is much less variation of the encoding of the prefix word, but it is not always identical for instructions which share a similar encoding of arguments (e.g PLWA and PLWZ). Updates #44549 Change-Id: Ie83fa02497c9ad2280678d68391043d3aae63175 Reviewed-on: https://go-review.googlesource.com/c/go/+/419535 Run-TryBot: Paul Murphy <murp@ibm.com> TryBot-Result: Gopher Robot <gobot@golang.org> Run-TryBot: Jenny Rakoczy <jenny@golang.org> Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com> Reviewed-by: Jenny Rakoczy <jenny@golang.org> Reviewed-by: Michael Pratt <mpratt@google.com> Auto-Submit: Jenny Rakoczy <jenny@golang.org>
2022-09-07cmd/asm: improve argument to obj.Prog assignment on PPC64Paul E. Murphy
These can be simplified with the knowledge of how arguments are assigned to obj.Prog objects on PPC64. If the argument is not a register type, the Reg argument (a2 in optab) of obj.Prog is not used, and those arguments are placed into RestArgs (a3, a4, a5 in optab). This relaxes the special case handling enforced by IsPPC64RLD and IsPPC64ISEL. Instead, arguments are assigned as noted above, and incorrect usage of such opcodes is checked by optab rules, not by the assembler front-end. Likewise, add support for handling 6 argument opcodes, these do not exist today, but will be added with ISA 3.1 (Power10). Finally, to maintain backwards compatibility, some 4-arg opcodes whose middle arguments are a register and immediate, could swap these arguments and generate identical machine code. This likely wasn't intended, but is possible. These are explicitly fixed up in the backend, and the asm tests are extended to check these. Change-Id: I5f8190212427dfe8e6f062185bfefb5fa4fd0e75 Reviewed-on: https://go-review.googlesource.com/c/go/+/427516 Reviewed-by: Cherry Mui <cherryyz@google.com> Run-TryBot: Paul Murphy <murp@ibm.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> TryBot-Result: Gopher Robot <gobot@golang.org> Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com>
2022-09-07cmd/asm,cmd/internal/obj/ppc64: recognize ppc64 ISA 3.1 MMA registersPaul E. Murphy
Allow the assembler frontend to match MMA register arguments added by ISA 3.1. The prefix "A" (for accumulator) is chosen to identify them. Updates #44549 Change-Id: I363e7d1103aee19d7966829d2079c3d876621efc Reviewed-on: https://go-review.googlesource.com/c/go/+/419534 Reviewed-by: Cherry Mui <cherryyz@google.com> Run-TryBot: Paul Murphy <murp@ibm.com> Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com> TryBot-Result: Gopher Robot <gobot@golang.org> Reviewed-by: Michael Knyszek <mknyszek@google.com>
2022-08-09cmd/asm: add VTBX instruction on arm64Nick Ripley
Change-Id: Icd9eeb78bfc0c0bbe19dcb9841c9fdc0abc29cc9 Reviewed-on: https://go-review.googlesource.com/c/go/+/413314 TryBot-Result: Gopher Robot <gobot@golang.org> Reviewed-by: Than McIntosh <thanm@google.com> Run-TryBot: Cherry Mui <cherryyz@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2022-05-23cmd/internal/obj/arm64: fix encoding of ADR/ADRP instructionCherry Mui
The referenced address is p.From, not p.To. Separate from CL 403980, as this is a bug fix. Also, ADR is used in CL 387336. This is needed to make it work correctly. Change-Id: Ie0baaeb359b9a7f233458d2becf25dc6a1f8ecbf Reviewed-on: https://go-review.googlesource.com/c/go/+/407884 Reviewed-by: David Chase <drchase@google.com> Run-TryBot: Cherry Mui <cherryyz@google.com> TryBot-Result: Gopher Robot <gobot@golang.org>
2022-05-13cmd/asm/internal: configure assembler for loong64Xiaodong Liu
Contributors to the loong64 port are: Weining Lu <luweining@loongson.cn> Lei Wang <wanglei@loongson.cn> Lingqin Gong <gonglingqin@loongson.cn> Xiaolin Zhao <zhaoxiaolin@loongson.cn> Meidan Li <limeidan@loongson.cn> Xiaojuan Zhai <zhaixiaojuan@loongson.cn> Qiyuan Pu <puqiyuan@loongson.cn> Guoqi Chen <chenguoqi@loongson.cn> This port has been updated to Go 1.15.6: https://github.com/loongson/go Updates #46229 Change-Id: I4b0247a331256162b47fbd94589f46ba062d4d44 Reviewed-on: https://go-review.googlesource.com/c/go/+/387234 Auto-Submit: Ian Lance Taylor <iant@google.com> Run-TryBot: David Chase <drchase@google.com> Run-TryBot: Ian Lance Taylor <iant@google.com> TryBot-Result: Gopher Robot <gobot@golang.org> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Ian Lance Taylor <iant@google.com>
2022-04-01cmd/asm: refactor some operands that are not special registers on arm64erifan01
The previous code treats some operands such as EQ, LT, etc. as special registers. However, they are not. This CL adds a new AddrType TYPE_SPOPD and a new class C_SPOPD to support this kind of special operands, and refactors the relevant code. This patch is a copy of CL 260861, contributed by Junchen Li(junchen.li@arm.com). Co-authored-by: Junchen Li(junchen.li@arm.com) Change-Id: I57b28da458ee3332f610602632e7eda03af435f5 Reviewed-on: https://go-review.googlesource.com/c/go/+/302849 Reviewed-by: Cherry Mui <cherryyz@google.com> Trust: Eric Fang <eric.fang@arm.com> Run-TryBot: Eric Fang <eric.fang@arm.com> TryBot-Result: Gopher Robot <gobot@golang.org>
2022-03-11cmd/asm: add support for bdnz/bdz extended mnemonics on PPC64Paul E. Murphy
Support BDNZ and BDZ mnemonics, they are commonly used POWER instructions. The raw BC mnemonic is not easy to read. Likewise, cleanup code surrounding these changes. Change-Id: I72f1dad5013f7856bd0dd320bfb17b5a9f3c69ee Reviewed-on: https://go-review.googlesource.com/c/go/+/390696 Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com> Trust: Paul Murphy <murp@ibm.com> Run-TryBot: Paul Murphy <murp@ibm.com> TryBot-Result: Gopher Robot <gobot@golang.org>
2021-11-03cmd/asm,cmd/compile,runtime: stop using X3 (aka GP) on riscv64Joel Sing
The X3 (aka GP) register will potentially be loaded with the __global_pointer$ symbol during program start up (usually by the dynamic linker). As such, non-Go code may depend on the contents of GP and calculate offsets based on it, including code called via cgo and signal handlers installed by non-Go code. As such, stop using the X3 register so that there are fewer issues interacting between Go and non-Go code. While here remove the X4 (TP) name from the assembler such that any references must use the 'TP' name. This should reduce the likelihood of accidental use (like we do for the 'g' register). The same applies for X3 (GP) when the -shared flag is given. Updates #47100 Change-Id: I72e82b5ca3f80c46a781781345ca0432a4111b74 Reviewed-on: https://go-review.googlesource.com/c/go/+/351859 Trust: Joel Sing <joel@sing.id.au> Run-TryBot: Joel Sing <joel@sing.id.au> Reviewed-by: Cherry Mui <cherryyz@google.com> TryBot-Result: Go Bot <gobot@golang.org>
2021-10-26cmd/internal/obj/ppc64: fix usage of CR bit argumentsPaul E. Murphy
CR bits and CR fields should be treated separately. Some instructions modify an entire CR, a CR field, or a single CR bit. Add a new argument class for CR bits, and teach the assembler the recognize them as names like CR0LT or CR2SO, and update the CR bit logic instructions to use them. They will no longer accept register field (CRn) type arguments. Fixes #46422 Change-Id: Iaba127d88abada0c2a49b8d3b07a976180565ae4 Reviewed-on: https://go-review.googlesource.com/c/go/+/357774 Run-TryBot: Paul Murphy <murp@ibm.com> Trust: Lynn Boger <laboger@linux.vnet.ibm.com> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Cherry Mui <cherryyz@google.com>
2021-10-08cmd/internal/obj: rename MOVBE{LL,QQ,WW} to just MOVBE{L,Q,W}Matthew Dempsky
The double suffix doesn't seem to serve any purpose, and we can keep the old spelling as a backwards compatible alias in cmd/asm. Change-Id: I3f01fc7249fb093ac1b25bd75c1cb9f39b8f62a9 Reviewed-on: https://go-review.googlesource.com/c/go/+/354700 Run-TryBot: Matthew Dempsky <mdempsky@google.com> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Keith Randall <khr@golang.org> Trust: Matthew Dempsky <mdempsky@google.com>
2021-08-20cmd/asm/internal/arch: adds the missing type check for arm64 SXTB extensioneric fang
Operands of memory type do not support SXTB extension. This CL adds this missing check. Change-Id: I1fa438dd314fc8aeb889637079cc67b538e83a89 Reviewed-on: https://go-review.googlesource.com/c/go/+/342769 Reviewed-by: eric fang <eric.fang@arm.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Run-TryBot: eric fang <eric.fang@arm.com> TryBot-Result: Go Bot <gobot@golang.org> Trust: Michael Knyszek <mknyszek@google.com>
2021-04-28cmd/asm: add check for register and shift/extension combination on arm64eric fang
The current code lacks a check on whether the register and shift/extension combination is valid, for example the follow instructions also compiles. ADD F1<<1, R1, R3 ADD V1<<1, R1, R3 MOVW (R9)(F8.SXTW<<2), R19 VST1 R4.D[1], (R0) Actually only general registers can perform shift operations, and element and arrangement extensions are only applicable to vector registers. This CL adds a check for the register and shift/extension combination on arm64. Change-Id: I93dd9343e92a66899cba8eaf4e0ac5430e94692b Reviewed-on: https://go-review.googlesource.com/c/go/+/312571 Trust: eric fang <eric.fang@arm.com> Reviewed-by: eric fang <eric.fang@arm.com> Reviewed-by: Keith Randall <khr@golang.org> Run-TryBot: eric fang <eric.fang@arm.com> TryBot-Result: Go Bot <gobot@golang.org>
2021-02-05[dev.regabi] cmd/asm: define g register on AMD64Cherry Zhang
Define g register as R14 on AMD64. It is not used now, but will be in later CLs. The name "R14" is still recognized. Change-Id: I9a066b15bf1051113db8c6640605e350cea397b9 Reviewed-on: https://go-review.googlesource.com/c/go/+/289195 Trust: Cherry Zhang <cherryyz@google.com> Reviewed-by: Than McIntosh <thanm@google.com>
2020-10-29cmd/asm: remove X27 and S11 register names on riscv64Joel Sing
The X27 register (known as S11 via its ABI name) is the g register on riscv64. Prevent assembly from referring to it by either of these names. Change-Id: Iba389eb8e44e097c0142c5b3d92e72bcae8a244a Reviewed-on: https://go-review.googlesource.com/c/go/+/265519 Trust: Joel Sing <joel@sing.id.au> Reviewed-by: Cherry Zhang <cherryyz@google.com> Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Go Bot <gobot@golang.org>
2020-10-29cmd/internal/obj/arm64: add CASx/CASPx instructionsfanzha02
This patch adds support for CASx and CASPx atomic instructions. go syntax gnu syntax CASD Rs, (Rn|RSP), Rt => cas Xs, Xt, (Xn|SP) CASALW Rs, (Rn|RSP), Rt => casal Ws, Wt, (Xn|SP) CASPD (Rs, Rs+1), (Rn|RSP), (Rt, Rt+1) => casp Xs, Xs+1, Xt, Xt+1, (Xn|SP) CASPW (Rs, Rs+1), (Rn|RSP), (Rt, Rt+1) => casp Ws, Ws+1, Wt, Wt+1, (Xn|SP) This patch changes the type of prog.RestArgs from "[]Addr" to "[]struct{Addr, Pos}", Pos is a enum, indicating the position of the operand. This patch also adds test cases. Change-Id: Ib971cfda7890b7aa895d17bab22dea326c7fcaa4 Reviewed-on: https://go-review.googlesource.com/c/go/+/233277 Trust: fannie zhang <Fannie.Zhang@arm.com> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2020-09-25cmd/asm: fix the issue of moving 128-bit integers to vector registers on arm64fanzha02
The CL 249758 added `FMOVQ $vcon, Vd` instruction and assembler used 128-bit simd literal-loading to load `$vcon` from pool into 128-bit vector register `Vd`. Because Go does not have 128-bit integers for now, the assembler will report an error of `immediate out of range` when assembleing `FMOVQ $0x123456789abcdef0123456789abcdef, V0` instruction. This patch lets 128-bit integers take two 64-bit operands, for the high and low parts separately and adds `VMOVQ $hi, $lo, Vd` instruction to move `$hi<<64+$lo' into 128-bit register `Vd`. In addition, this patch renames `FMOVQ/FMOVD/FMOVS` ops to 'VMOVQ/VMOVD/VMOVS' and uses them to move 128-bit, 64-bit and 32-bit constants into vector registers, respectively Update the go doc. Fixes #40725 Change-Id: Ia3c83bb6463f104d2bee960905053a97299e0a3a Reviewed-on: https://go-review.googlesource.com/c/go/+/255900 Trust: fannie zhang <Fannie.Zhang@arm.com> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2020-03-31cmd/asm,cmd/internal/obj/riscv: provide branch pseudo-instructionsJoel Sing
Implement various branch pseudo-instructions for riscv64. These make it easier to read/write assembly and will also make it easier for the compiler to generate optimised code. Change-Id: Ic31a7748c0e1495522ebecf34b440842b8d12c04 Reviewed-on: https://go-review.googlesource.com/c/go/+/226397 Run-TryBot: Cherry Zhang <cherryyz@google.com> Reviewed-by: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org>
2020-03-15cmd/asm,cmd/internal/obj/riscv: add atomic memory operation instructionsJoel Sing
Use instructions in place of currently used defines. Updates #36765 Change-Id: I00bb59e77b1aace549d7857cc9721ba2cb4ac6ca Reviewed-on: https://go-review.googlesource.com/c/go/+/220541 Reviewed-by: Cherry Zhang <cherryyz@google.com>
2020-03-15cmd/asm,cmd/internal/obj/riscv: add LR/SC instructionsJoel Sing
Add support for Load-Reserved (LR) and Store-Conditional (SC) instructions. Use instructions in place of currently used defines. Updates #36765 Change-Id: I77e660639802293ece40cfde4865ac237e3308d6 Reviewed-on: https://go-review.googlesource.com/c/go/+/220540 Reviewed-by: Cherry Zhang <cherryyz@google.com>
2020-03-04cmd/asm: add MIPS MSA LD/ST/LDI support for mips64xMeng Zhuo
This CL adding primitive asm support of MIPS MSA by introducing new sets of register W0-W31 (C_WREG) and 12 new instructions: * VMOV{B,H,W,D} ADDCONST, WREG (Vector load immediate) * VMOV{B,H,W,D} SOREG, WREG (Vector load) * VMOV{B,H,W,D} WREG, SOREG (Vector store) Ref: MIPS Architecture for Programmers Volume IV-j: The MIPS64 SIMD Architecture Module Change-Id: I3362c59a73c82c94769c18a19a0bee7e5029217d Reviewed-on: https://go-review.googlesource.com/c/go/+/215723 Run-TryBot: Meng Zhuo <mengzhuo1203@gmail.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2019-10-17cmd/asm/internal/arch: delete unused s390x functionsMichael Munday
These functions are not necessary and are not called anywhere. Change-Id: I1c0d814ba3044c27e3626ac9e6052d8154140404 Reviewed-on: https://go-review.googlesource.com/c/go/+/201697 Run-TryBot: Michael Munday <mike.munday@ibm.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Brad Fitzpatrick <bradfitz@golang.org>
2019-10-10all: remove nacl (part 3, more amd64p32)Brad Fitzpatrick
Part 1: CL 199499 (GOOS nacl) Part 2: CL 200077 (amd64p32 files, toolchain) Part 3: stuff that arguably should've been part of Part 2, but I forgot one of my grep patterns when splitting the original CL up into two parts. This one might also have interesting stuff to resurrect for any future x32 ABI support. Updates #30439 Change-Id: I2b4143374a253a003666f3c69e776b7e456bdb9c Reviewed-on: https://go-review.googlesource.com/c/go/+/200318 Run-TryBot: Brad Fitzpatrick <bradfitz@golang.org> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Ian Lance Taylor <iant@golang.org>
2019-10-09cmd/asm: add s390x branch-on-count instructionsMichael Munday
The branch-on-count instructions on s390x decrement the input register and then compare its value to 0. If not equal the branch is taken. These instructions are useful for implementing loops with a set number of iterations (which might be in a register). For example, this for loop: for i := 0; i < n; i++ { ... // i is not used or modified in the loop } Could be implemented using this assembly: MOVD Rn, Ri loop: ... BRCTG Ri, loop Note that i will count down from n in the assembly whereas in the original for loop it counted up to n which is why we can't use i in the loop. These instructions will only be used in hand-written codegen and assembly for now since SSA blocks cannot currently modify values. We could look into this in the future though. Change-Id: Iaab93b8aa2699513b825439b8ea20d8fe2ea1ee6 Reviewed-on: https://go-review.googlesource.com/c/go/+/199977 Run-TryBot: Michael Munday <mike.munday@ibm.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Cherry Zhang <cherryyz@google.com>
2019-09-25cmd/asm: add masked branch and conditional load instructions to s390xMichael Munday
The branch-relative-on-condition (BRC) instruction allows us to use an immediate to specify under what conditions the branch is taken. For example, `BRC $7, L1` is equivalent to `BNE L1`. It is sometimes useful to specify branches in this way when either we don't have an extended mnemonic for a particular mask value or we want to generate the condition code mask programmatically. The new load-on-condition (LOCR and LOCGR) and compare-and-branch (CRJ, CGRJ, CLRJ, CLGRJ, CIJ, CGIJ, CLIJ and CLGIJ) instructions provide the same flexibility for conditional loads and combined compare and branch instructions. Change-Id: Ic6f5d399b0157e278b39bd3645f4ee0f4df8e5fc Reviewed-on: https://go-review.googlesource.com/c/go/+/196558 Run-TryBot: Michael Munday <mike.munday@ibm.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Cherry Zhang <cherryyz@google.com>
generated by cgit v1.3 (git 2.53.0) at 2026-04-15 09:26:19 +0000