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2025-10-20cmd/asm: fix typo in commentJoel Sing
Change-Id: I1a7933bce70bcae1f93a45c6810da60d269f48f3 Reviewed-on: https://go-review.googlesource.com/c/go/+/713000 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Michael Pratt <mpratt@google.com> Reviewed-by: Keith Randall <khr@google.com> Auto-Submit: Joel Sing <joel@sing.id.au>
2025-10-15cmd/internal/obj: move ARM64RegisterExtension from cmd/asm/internal/archVasily Leonenko
Change-Id: Iab41674953655efa7be3d306dfb3f5be486be501 Reviewed-on: https://go-review.googlesource.com/c/go/+/701455 Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Keith Randall <khr@google.com>
2025-10-14cmd/internal/obj/arm64: add support for PAC instructionsBill Roberts
Add support for the Pointer Authentication Code instructions required for the ELF ABI when enabling PAC aware binaries. This allows for assembly writers to add PAC instructions where needed to support this ABI. Follow up work is to enable the compiler to emit these instructions in the appropriate places. The TL;DR for the Linux ABI is that the prologue of a function that pushes the link register (LR) to the stack, signs the LR with a key managed by the operating system and hardware using a PAC instruction, like "paciasp". The function epilog, when restoring the LR from the stack will verify the signature, using an instruction like "autiasp". This helps prevents attackers from modifying the return address on the stack, a common technique for ROP attacks. Details on PAC can be found here: - https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/enabling-pac-and-bti-on-aarch64 - https://developer.arm.com/documentation/109576/0100/Pointer-Authentication-Code The ABI details can be found here: - https://github.com/ARM-software/abi-aa/blob/main/aaelf64/aaelf64.rst Change-Id: I4516ed1294d19f9ff9d278833d542821b6642aa9 Reviewed-on: https://go-review.googlesource.com/c/go/+/676675 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2025-09-24cmd/internal/obj/riscv: add support for vector unit-stride fault-only-first ↵wangboyao
load instructions Add support for vector unit-stride fault-only-first load instructions to the RISC-V assembler. This includes vle8ff, vle16ff, vle32ff and vle64ff. Change-Id: I5575a1ea155663852f92194fb79f08b5d52203de Reviewed-on: https://go-review.googlesource.com/c/go/+/690115 Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-09-17cmd/internal/obj/riscv: add support for Zicond instructionslxq015
This patch implement assembler for the Zicond extension: CZEROEQZ and CZERONEZ. Follow-up to CL 631576 Updates #75350 Change-Id: Icf4be131fe61c3b7a3bde4811cf42dc807660907 GitHub-Last-Rev: 6539cc86cbf3c49c3247ed935bcbbb31bb886dea GitHub-Pull-Request: golang/go#75408 Reviewed-on: https://go-review.googlesource.com/c/go/+/702677 Reviewed-by: Mark Freeman <markfreeman@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> TryBot-Bypass: Joel Sing <joel@sing.id.au>
2025-09-16cmd/internal/obj/riscv: improve handling of float point movesJoel Sing
Translate moves from an integer register to a floating point register, or from a floating point register to an integer register, to the appropriate move instruction (i.e. FMVXW/FMVWX/FMVXD/FMVDX). Add support for MOVF with a constant - we previously added support for MOVD but not for MOVF. Add special handling for 0.0, which we can translate to a move from the zero register to a floating point register (leveraging the above mentioned change). Change-Id: If8df2f5610e69b4ec0af85efb884951024685f5b Reviewed-on: https://go-review.googlesource.com/c/go/+/703216 Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Mark Freeman <markfreeman@google.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
2025-09-15cmd/internal/obj/riscv: implement vector segment load/store instructionswangboyao
https://github.com/riscv/riscv-opcodes/pull/361. After this pr was merged, riscv-opcode can generate RVV segment load/store instructions for Go. Implement vector segment load/store instuctions. Change-Id: I154bb75be70c0a45e2279a75c67f68b5bb57c36e Reviewed-on: https://go-review.googlesource.com/c/go/+/691695 Reviewed-by: Mark Freeman <markfreeman@google.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-09-15cmd/asm: add double precision comparision testcases for riscv64Meng Zhuo
Change-Id: If8e03dfdb332a22ec9c6a0021d7e7955520f3ddc Reviewed-on: https://go-review.googlesource.com/c/go/+/702136 Reviewed-by: Mark Freeman <markfreeman@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Joel Sing <joel@sing.id.au> Reviewed-by: Michael Knyszek <mknyszek@google.com>
2025-09-12cmd/asm, cmd/internal/obj: add riscv64 generic CSR opsMark Ryan
Support is added for the generic RISC-V CSR operations; CSRRC, CSRRCI, CSRRS, CSRRSI, CSRRW, CSRRWI. These instructions require special handling as their second operand is a symbolic CSR register name and not an immediate value or a register. CSR names are implemented as special operands. RISC-V CSRs are not currently saved and restored when a go routine is asynchronously pre-empted so it is only safe to use these instructions in hand written assembler. Note that CSRRS was already partially supported by the assembler so this restriction predates this commit. We mention it here as this commit makes CSRRS much easier to use. Change-Id: I9ff8d804328b418a879d463e7d9cc31f489c7a00 Reviewed-on: https://go-review.googlesource.com/c/go/+/630519 Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Michael Pratt <mpratt@google.com>
2025-09-04cmd/internal/obj/loong64: add ADDU16I.D instruction supportXiaolin Zhao
Go asm syntax: ADDV16 $(1<<16), R4, R5 Equivalent platform assembler syntax: addu16i.d r5, r4, $1 Change-Id: Ica4a4e779d0a107cda3eade86027abd6458779a4 Reviewed-on: https://go-review.googlesource.com/c/go/+/699056 Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Michael Pratt <mpratt@google.com> Auto-Submit: Michael Pratt <mpratt@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-09-04cmd/internal/obj/loong64: fix the usage of offset in the instructions ↵Xiaolin Zhao
[X]VLDREPL.{B/H/W/D} The previously defined usage of offset was ambiguous and not easy to understand. For example, to fetch 4 bytes of data from the address base+8 and broadcast it to each word element of vector register V5, the assembly implementation is as follows: previous: VMOVQ 2(base), V5.W4 current: VMOVQ 8(base), V5.W4 Change-Id: I8bc84e35033ab63bd10f4c61618789f94314f78c Reviewed-on: https://go-review.googlesource.com/c/go/+/699875 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Michael Pratt <mpratt@google.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Auto-Submit: Michael Pratt <mpratt@google.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-08-31cmd/internal/obj/loong64: add LDPTR.{W/D} and STPTR.{W/D} instructions supportXiaolin Zhao
Go asm syntax: MOVWP 4(R4), R5 MOVVP 8(R4), R5 MOVWP R4, 12(R5) MOVVP R4, 16(R5) Equivalent platform assembler syntax: ldptr.w r5, r4, $1 ldptr.d r5, r4, $2 stptr.w r4, r5, $3 stptr.d r4, r5, $4 Change-Id: I50a341cee2d875cb7c5da9db08b23799c9dc6c64 Reviewed-on: https://go-review.googlesource.com/c/go/+/699055 Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Meidan Li <limeidan@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-08-07cmd/internal/obj/loong64: change the immediate range of ALSL{W/WU/V}limeidan
When executing the alsl.w/wu/d family of instructions, the actual shift amount is the immediate value in the instruction encoding plus one. Therefore, this change is made to align the immediate value in the assembly code with the programmer's intended shift amount, and to include the result of the immediate value minus one in the final encoding. Change-Id: Ic82249251878eabde8372e183d841a03f963f9f9 Reviewed-on: https://go-review.googlesource.com/c/go/+/693475 Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Mark Freeman <markfreeman@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn>
2025-08-07cmd/internal/obj/loong64: add support for FSEL instructionXiaolin Zhao
Go asm syntax: FSEL FCC, FK, FJ, FD Equivalent platform assembler syntax: fsel fd, fj, fk, ca Change-Id: If75f16fca0adfc03f4952f8a5143d22da33ed425 Reviewed-on: https://go-review.googlesource.com/c/go/+/693457 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Mark Freeman <markfreeman@google.com>
2025-08-05cmd/internal/obj/loong64: add new instructions ALSL{W/WU/V} for loong64limeidan
Go asm syntax: ALSL{W/WU/V} $3, R4, R5, R6 Equivalent platform assembler syntax: alsl.{w/wu/d} $r6, $r4, $r5, 3 Change-Id: Ic8364dfe2753bcea7de6cffe656ca0dde6875766 Reviewed-on: https://go-review.googlesource.com/c/go/+/692136 Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Mark Freeman <markfreeman@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn>
2025-08-05cmd: remove dead codeqiulaidongfeng
Fixes #74076 Change-Id: Icc67b3d4e342f329584433bd1250c56ae8f5a73d Reviewed-on: https://go-review.googlesource.com/c/go/+/690635 Reviewed-by: Alan Donovan <adonovan@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Commit-Queue: Alan Donovan <adonovan@google.com> Reviewed-by: Keith Randall <khr@golang.org> Reviewed-by: Keith Randall <khr@google.com> Auto-Submit: Alan Donovan <adonovan@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2025-08-03cmd/internal/obj/loong64: add {V,XV}{BITCLR/BITSET/BITREV}[I].{B/H/W/D} ↵Xiaolin Zhao
instructions support Go asm syntax: V{BITCLR/BITSET/BITREV}{B/H/W/V} $1, V2, V3 XV{BITCLR/BITSET/BITREV}{B/H/W/V} $1, X2, X3 V{BITCLR/BITSET/BITREV}{B/H/W/V} VK, VJ, VD XV{BITCLR/BITSET/BITREV}{B/H/W/V} XK, XJ, XD Equivalent platform assembler syntax: v{bitclr/bitset/bitrev}i.{b/h/w/d} v3, v2, $1 xv{bitclr/bitset/bitrev}i.{b/h/w/d} x3, x2, $1 v{bitclr/bitset/bitrev}.{b/h/w/d} vd, vj, vk xv{bitclr/bitset/bitrev}.{b/h/w/d} xd, xj, xk Change-Id: I244f8ae316f72cc7ea01ca0139ac78c5616a3c5b Reviewed-on: https://go-review.googlesource.com/c/go/+/677435 Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Mark Freeman <mark@golang.org>
2025-08-03cmd/internal/obj/loong64: add [X]VLDREPL.{B/H/W/D} instructions supportXiaolin Zhao
Go asm syntax: VMOVQ offset(Rj), Vd.<T> XVMOVQ offset(Rj), Xd.<T> <T> can have the following values: B16, H8, W4, V2, B32, H16, W8, V4 Change-Id: I44af51d58bb62649d3fe360b3abb771565e78a8a Reviewed-on: https://go-review.googlesource.com/c/go/+/682895 Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Freeman <mark@golang.org>
2025-07-30cmd/compile: add floating point min/max intrinsics on s390xMichael Munday
Add the VECTOR FP (MINIMUM|MAXIMUM) instructions to the assembler and use them in the compiler to implement min and max. Note: I've allowed floating point registers to be used with the single element instructions (those with the W instead of V prefix) to allow easier integration into the compiler. Change-Id: I5f80a510bd248cf483cce95f1979bf63fbae7de6 Reviewed-on: https://go-review.googlesource.com/c/go/+/684715 Reviewed-by: Keith Randall <khr@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Freeman <mark@golang.org> Reviewed-by: Keith Randall <khr@google.com>
2025-07-24cmd/internal/obj/s390x: add MVCLE instructionkmvijay
MVCLE (Move Long Extended) instruction is used to move large data storage-to-storage. This change will add MVCLE into the Go asm for s390x architecture. Upcoming PR of runtime/memmove_s390x.s will use this instruction for performance improvement. Change-Id: I3bbb6668c736a36849917887398c74cebb1c3a99 Reviewed-on: https://go-review.googlesource.com/c/go/+/677455 Reviewed-by: Srinivas Pokala <Pokala.Srinivas@ibm.com> Reviewed-by: Keith Randall <khr@golang.org> Auto-Submit: Michael Knyszek <mknyszek@google.com> Reviewed-by: Keith Randall <khr@google.com> Reviewed-by: Michael Munday <mikemndy@gmail.com> Reviewed-by: Vishwanatha HD <vishwanatha.hd@ibm.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Michael Knyszek <mknyszek@google.com>
2025-05-21cmd/internal/obj/riscv: fix vector integer multiply addMark Ryan
The RISC-V integer vector multiply add instructions are not encoded correctly; the first and second arguments are swapped. For example, the instruction VMACCVV V1, V2, V3 encodes to b620a1d7 or vmacc.vv v3,v1,v2 and not b61121d7 or vmacc.vv v3,v2,v1 as expected. This is inconsistent with the argument ordering we use for 3 argument vector instructions, in which the argument order, as given in the RISC-V specifications, is reversed, and also with the vector FMA instructions which have the same argument ordering as the vector integer multiply add instructions in the "The RISC-V Instruction Set Manual Volume I". For example, in the ISA manual we have the following instruction definitions ; Integer multiply-add, overwrite addend vmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] ; FP multiply-accumulate, overwrites addend vfmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] It's reasonable to expect that the Go assembler would use the same argument ordering for both of these instructions. It currently does not. We fix the issue by switching the argument ordering for the vector integer multiply add instructions to match those of the vector FMA instructions. Change-Id: Ib98e9999617f991969e5c831734b3bb3324439f6 Reviewed-on: https://go-review.googlesource.com/c/go/+/670335 Reviewed-by: Carlos Amedee <carlos@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-05-15cmd/internal/obj/loong64: change the plan9 format of the prefetch ↵Guoqi Chen
instruction PRELDX before: MOVV $n + $offset, Roff PRELDX (Rbase)(Roff), $hint after: PRELDX offset(Rbase), $n, $hint This instruction is supported in CL 671875, but is not actually used Change-Id: I943d488ea6dc77781cd796ef480a89fede666bab Reviewed-on: https://go-review.googlesource.com/c/go/+/673155 Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Michael Knyszek <mknyszek@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-05-14cmd/intarnal/obj: add new assembly format for VANDV and VANDB on loong64Xiaolin Zhao
In order to make it easier to write in assembly and to be consistent with the usage of general instructions, a new assembly format is added for the instructions VANDV and VANDB. It also works for instructions XVAND{V,B}, [X]V{OR,XOR,NOR,ANDN,ORN}V and [X]V{OR,XOR,NOR}B. Change-Id: Ia75d607ac918950e58840ec627aaf0be45d837fe Reviewed-on: https://go-review.googlesource.com/c/go/+/671316 Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Michael Knyszek <mknyszek@google.com>
2025-05-12cmd/internal/obj/loong64: Add preld{,x} instructions supportGuoqi Chen
Go asm syntax: PRELD 16(R4), $8 PRELDX (R4)(R5), $8 Equivalent platform assembler syntax: preld $8, $r4, 16 preldx $8, $r4, $r5 Change-Id: Ie81d22ebaf4153388a7e9d8fa0f618a0ae7a1c9f Reviewed-on: https://go-review.googlesource.com/c/go/+/671875 Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Michael Knyszek <mknyszek@google.com>
2025-05-11cmd/internal/obj/loong64: add [X]VFCLASS.{S/D} instructionsXiaolin Zhao
Go asm syntax: VFCLASS{F/D} VJ, VD XVFCLASS{F/D} XJ, XD Equivalent platform assembler syntax: vfclass.{s/d} vd, vj xvfclass.{s/d} xd, xj Change-Id: Iec373f393be315696d1fefc747a4a5882f993195 Reviewed-on: https://go-review.googlesource.com/c/go/+/670256 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Dustin Turner <dustin.turner44@gmail.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: abner chenc <chenguoqi@loongson.cn>
2025-05-08cmd/internal/obj/loong64: add [X]VF{ADD/SUB/MUL/DIV}.{S/D} instructionsXiaolin Zhao
Go asm syntax: V{ADD/SUB/MUL/DIV}{F/D} VK, VJ, VD XV{ADD/SUB/MUL/DIV}{F/D} XK, XJ, XD Equivalent platform assembler syntax: vf{add/sub/mul/div}.{s/d} vd, vj, vk xvf{add/sub/mul/div}.{s/d} xd, xj, xk Change-Id: I4607884212167ac97d7b6448ea3c849fc0fdd506 Reviewed-on: https://go-review.googlesource.com/c/go/+/670255 Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Carlos Amedee <carlos@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-05-08cmd/internal/obj/riscv: reject invalid vadc/vsbc encodingsMark Ryan
The RISC-V Instruction Set Manual Volume states that "for vadc and vsbc, the instruction encoding is reserved if the destination vector register is v0". The assembler currently allows instructions like VADCVVM V1, V2, V0, V0 to be assembled. It's not clear what the behaviour of such instructions will be on target hardware so it's best to disallow them. For reference, binutils (2.44-3.fc42) allows the instruction vadc.vvm v0, v4, v8, v0 to be assembled and the instruction actually executes on a Banana PI F3 without crashing. However, clang (20.1.2) refuses to assemble the instruction, producing the following error. error: the destination vector register group cannot be V0 vadc.vvm v0, v4, v8, v0 ^ Change-Id: Ia913cbd864ae8dbcf9227f69b963c93a99481cff Reviewed-on: https://go-review.googlesource.com/c/go/+/669315 Reviewed-by: Carlos Amedee <carlos@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Joel Sing <joel@sing.id.au>
2025-05-08cmd/internal/obj/riscv: fix LMUL encoding for MF2 and MF8Mark Ryan
The encodings for the riscv64 special operands SPOP_MF2 and SPOP_MF8 are incorrect, i.e., their values are swapped. This leads to incorrect encodings for the VSETVLI and VSETIVLI instructions. The assembler currently encodes VSETVLI X10, E32, MF8, TA, MA, X12 as VSETVLI X10, E32, MF2, TA, MA, X12 We update the encodings for SPOP_MF2 and SPOP_MF8 so that they match the LMUL table in section "31.3.4. Vector type register, vtype" of the "RISC-V Instruction Set Manual Volume 1". Change-Id: Ic73355533d7c2a901ee060b35c2f7af6d58453e4 Reviewed-on: https://go-review.googlesource.com/c/go/+/670016 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Joel Sing <joel@sing.id.au>
2025-05-07cmd/internal/obj/loong64: add [X]VFRINT[{RNE/RZ/RP/RM}].{S/D} instructionsXiaolin Zhao
Go asm syntax: VFRINT[{RNE/RZ/RP/RM}]{F/D} VJ, VD XVFRINT[{RNE/RZ/RP/RM}]{F/D} XJ, XD Equivalent platform assembler syntax: vfrint[{rne/rz/rp/rm}].{s/d} vd, vj xvfrint[{rne/rz/rp/rm}].{s/d} xd, xj Change-Id: I4ed8782289ae3329d675239f799d5f75b1adc4ad Reviewed-on: https://go-review.googlesource.com/c/go/+/670235 Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Carlos Amedee <carlos@golang.org>
2025-05-02cmd/internal/obj/riscv: add support for vector permutation instructionsJoel Sing
Add support for vector permutation instructions to the RISC-V assembler. This includes integer scalar move, floating point scalar move, slide up and slide down, register gather, compression and whole vector register move instructions. Change-Id: I1da9f393091504fd81714006355725b8b9ecadea Reviewed-on: https://go-review.googlesource.com/c/go/+/646780 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
2025-05-02cmd/internal/obj/riscv: add support for vector mask instructionsJoel Sing
Add support for vector mask instructions to the RISC-V assembler. These allow manipulation of vector masks and include mask register logical instructions, population count and find-first bit set instructions. Change-Id: I3ab3aa0f918338aee9b37ac5a2b2fdc407875072 Reviewed-on: https://go-review.googlesource.com/c/go/+/646779 Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Junyang Shao <shaojunyang@google.com>
2025-05-02cmd/internal/obj/riscv: add support for vector reduction instructionsJoel Sing
Add support for vector reduction instructions to the RISC-V assembler, including single-width integer reduction, widening integer reduction, single-width floating-point reduction and widening floating-point reduction. Change-Id: I8f17bef11389f3a017e0430275023fc5d75936e3 Reviewed-on: https://go-review.googlesource.com/c/go/+/646778 Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2025-05-01cmd/internal/obj/riscv: add support for vector floating-point instructionsJoel Sing
Add support for vector floating-point instructions to the RISC-V assembler. This includes single-width and widening addition and subtraction, multiplication and division, fused multiply-addition, comparison, min/max, sign-injection, classification and type conversion instructions. Change-Id: I8bceb1c5d7eead0561ba5407ace00805a6144f51 Reviewed-on: https://go-review.googlesource.com/c/go/+/646777 Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Junyang Shao <shaojunyang@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
2025-04-24cmd/internal/obj: add new assembly format for BFPT and BFPF on loong64Guoqi Chen
On loong64, BFPT and BFPF are mapped to the platform assembly as follows: Go asm syntax: BFPT FCCx, offs21 BFPF FCCx, offs21 Equivalent platform assembler syntax: bcnez cj, offs21 bceqz cj, offs21 If the condition register is not specified, it defaults to FCC0. Change-Id: I2cc3df62a9c55d4b5eb124789358983c6737319c Reviewed-on: https://go-review.googlesource.com/c/go/+/667456 Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meidan Li <limeidan@loongson.cn>
2025-04-15cmd/internal/obj/loong64: add support for {V,XV}SET{EQ,NE}Z.V series ↵limeidan
instructions Change-Id: If3794dfde3ff461662c8a493ff51d0c779e81bca Reviewed-on: https://go-review.googlesource.com/c/go/+/664795 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Michael Pratt <mpratt@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2025-04-13cmd: fix DWARF gen bug with packages that use assemblyThan McIntosh
When the compiler builds a Go package with DWARF 5 generation enabled, it emits relocations into various generated DWARF symbols (ex: SDWARFFCN) that use the R_DWTXTADDR_* flavor of relocations. The specific size of this relocation is selected based on the total number of functions in the package -- if the package is tiny (just a couple funcs) we can use R_DWTXTADDR_U1 relocs (which target just a byte); if the package is larger we might need to use the 2-byte or 3-byte flavor of this reloc. Prior to this patch, the strategy used to pick the right relocation size was flawed in that it didn't take into account packages with assembly code. For example, if you have a package P with 200 funcs written in Go source and 200 funcs written in assembly, you can't use the R_DWTXTADDR_U1 reloc flavor for indirect text references since the real function count for the package (asm + go) exceeds 255. The new strategy (with this patch) is to have the compiler look at the "symabis" file to determine the count of assembly functions. For the assembler, rather than create additional plumbing to pass in the Go source func count we just use an dummy (artificially high) function count so as to select a relocation that will be large enough. Fixes #72810. Updates #26379. Change-Id: I98d04f3c6aacca1dafe1f1610c99c77db290d1d8 Reviewed-on: https://go-review.googlesource.com/c/go/+/663235 Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: David Chase <drchase@google.com>
2025-04-01cmd/internal/obj/riscv: add support for vector fixed-point arithmetic ↵Joel Sing
instructions Add support for vector fixed-point arithmetic instructions to the RISC-V assembler. This includes single width saturating addition and subtraction, averaging addition and subtraction and scaling shift instructions. Change-Id: I9aa27e9565ad016ba5bb2b479e1ba70db24e4ff5 Reviewed-on: https://go-review.googlesource.com/c/go/+/646776 Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-03-29cmd/internal/obj/riscv: add support for vector integer arithmetic instructionsJoel Sing
Add support for vector integer arithmetic instructions to the RISC-V assembler. This includes vector addition, subtraction, integer extension, add-with-carry, subtract-with-borrow, bitwise logical operations, comparison, min/max, integer division and multiplication instructions. Change-Id: I8c191ef8e31291e13743732903e4f12356133a46 Reviewed-on: https://go-review.googlesource.com/c/go/+/646775 Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
2025-03-27cmd/internal/obj/riscv,internal/bytealg: synthesize MIN/MAX/MINU/MAXU ↵Joel Sing
instructions Provide a synthesized version of the MIN/MAX/MINU/MAXU instructions if they're not natively available. This allows these instructions to be used in assembly unconditionally. Use MIN in internal/bytealg.compare. Cq-Include-Trybots: luci.golang.try:gotip-linux-riscv64 Change-Id: I8a5a3a59f0a9205e136fc3d673b23eaf3ca469f8 Reviewed-on: https://go-review.googlesource.com/c/go/+/653295 Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-03-27cmd/internal/obj/riscv: improve constant constructionJoel Sing
Attempt to construct large constants that have a consecutive sequence of ones from a small negative constant, with a logical right and/or left shift. This allows for a large range of mask like constants to be constructed with only two or three instructions, avoiding the need to load from memory. Change-Id: I35a77fecdd2df0ed3f33b772d518f85119d4ff66 Reviewed-on: https://go-review.googlesource.com/c/go/+/652778 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
2025-03-26cmd/internal/obj/arm64: add support for BTI instructionJoel Sing
Add support for the `BTI' instruction to the arm64 assembler. This instruction provides Branch Target Identification for targets of indirect branches. A BTI can be marked with a target type of 'C' (call), 'J' (jump) or 'JC' (jump or call). Updates #66054 Change-Id: I1cf31a0382207bb75b9b2deb49ac298a59c00d8a Reviewed-on: https://go-review.googlesource.com/c/go/+/646781 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2025-03-25cmd/internal/obj/loong64: add [X]VSHUF4I.{B/H/W/D} instructions supportXiaolin Zhao
Go asm syntax: VSHUF4I{B/H/W/V} $1, V1, V2 XVSHUF4I{B/H/W/V} $2, X1, X2 Equivalent platform assembler syntax: vshuf4i.{b/h/w/d} v2, v1, $1 xvshuf4i.{b/h/w/d} x2, x1, $2 Change-Id: I6a847ccbd2c93432d87bd1390b5cf1508da06496 Reviewed-on: https://go-review.googlesource.com/c/go/+/658376 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-03-25cmd/internal/obj/loong64: add [X]VMULW{EV/OD} series instructions supportXiaolin Zhao
Go asm syntax: VMULW{EV/OD}{HB/WH/VW/QV}[U] VK, VJ, VD XVMULW{EV/OD}{HB/WH/VW/QV}[U] XK, XJ, XD VMULW{EV/OD}{HBUB/WHUH/VWUW/QVUV} VK, VJ, VD XVMULW{EV/OD}{HBUB/WHUH/VWUW/QVUV} XK, XJ, XD Equivalent platform assembler syntax: vmulw{ev/od}.{h.b/w.h/d.w/q.d}[u] vd, vj, vk xvmulw{ev/od}.{h.b/w.h/d.w/q.d}[u] xd, xj, xk vmulw{ev/od}.{h.bu.b/w.hu.h/d.wu.w/q.du.d} vd, vj, vk xvmulw{ev/od}.{h.bu.b/w.hu.h/d.wu.w/q.du.d} xd, xj, xk Change-Id: Ib1b5fb9605417a2b81841deae40e0e2beb90d03c Reviewed-on: https://go-review.googlesource.com/c/go/+/658375 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: David Chase <drchase@google.com>
2025-03-24cmd/asm: add LCDBR instruction on s390xVishwanatha HD
This CL is to add LCDBR assembly instruction mnemonics, mainly used in math package. The LCDBR instruction has the same effect as the FNEG pseudo-instructions, just that it sets the flag. Change-Id: I3f00f1ed19148d074c3b6c5f64af0772289f2802 Reviewed-on: https://go-review.googlesource.com/c/go/+/648036 Reviewed-by: Srinivas Pokala <Pokala.Srinivas@ibm.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Michael Munday <mike.munday@lowrisc.org> Reviewed-by: Michael Pratt <mpratt@google.com> Run-TryBot: Michael Munday <mike.munday@lowrisc.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> TryBot-Result: Gopher Robot <gobot@golang.org>
2025-03-21cmd/asm/internal/asm: add additional tests for constant loads on riscv64Joel Sing
This improves test coverage around the various constant load edge cases. Change-Id: Ibafeec78e76d95e9f56b48fa6bd012772bf505c5 Reviewed-on: https://go-review.googlesource.com/c/go/+/652776 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
2025-03-19cmd/internal/obj/riscv: prevent panics on bad branchesMark Ryan
Syntactically incorrect branches, such as BEQ X5, X6, $1 BEQ X5, X6, 31(X10) cause the assembler to panic, which they shouldn't really do. It's better for the user to see a normal error, as reported for other syntax errors in riscv64 assembly. The panics also prevent us from writing negative tests for these sorts of errors. Here we fix the issue by ensuring we generate a normal error instead of panicking when the user provides an invalid branch target. We also add a couple of negative tests. Change-Id: I1da568999a75097484b61a01d418f5d4be3e04fa Reviewed-on: https://go-review.googlesource.com/c/go/+/637316 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
2025-03-18cmd/internal/obj/riscv: prevent duplicate error reportsMark Ryan
The riscv64 Go assembler can output certain errors, ones produced by instructionsForProg, multiple times. These errors are guaranteed to be output at least twice and can appear three or more times if a rescan is needed to recompute branch addresses. For example, the syntactically incorrect instruction MOV (X10), $1 will generate at least two identical errors asm: 86076 (asm.s:21524) MOV (X10), $1: unsupported MOV asm: 86076 (asm.s:21524) MOV (X10), $1: unsupported MOV asm: assembly failed In addition to confusing the user, these duplicate errors make it difficult to write negative tests for certain types of instructions, e.g., branches, whose duplicate errors are not always identical, and so not ignored by endtoend_test.go. We fix the issue by returning from preprocess if any errors have been generated by the time we reach the end of the rescan loop. One implication of this change is that validation errors will no longer be reported if an error is generated earlier in the preprocess stage. Negative test cases for validation errors are therefore moved to their own file as the existing riscv64error.s file contains errors generated by instructionsForProg that will now suppress the validation errors. Change-Id: Iffacdbefce28f44970dd5dda44990b822b8a23d4 Reviewed-on: https://go-review.googlesource.com/c/go/+/637315 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Joel Sing <joel@sing.id.au> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-03-16cmd/internal/obj/loong64: add {V,XV}NEG{B/H/W/V} instructions supportXiaolin Zhao
Go asm syntax: VNEG{B/H/W/V} VJ, VD XVNEG{B/H/W/V} XJ, XD Equivalent platform assembler syntax: vneg.{b/h/w/d} vd, vj xvneg.{b/h/w/d} xd, xj Change-Id: Ie0a82a434b0ffbcb77425a65b96eff56e030028c Reviewed-on: https://go-review.googlesource.com/c/go/+/635935 Reviewed-by: abner chenc <chenguoqi@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: David Chase <drchase@google.com>
2025-03-13cmd/internal/obj/loong64: add {V,XV}{FSQRT/FRECIP/FRSQRT}.{S/D} instructions ↵Xiaolin Zhao
support Go asm syntax: V{FSQRT/FRECIP/FRSQRT}{F/D} VJ, VD XV{FSQRT/FRECIP/FRSQRT}{F/D} XJ, XD Equivalent platform assembler syntax: v{fsqrt/frecip/frsqrt}.{s/d} vd, vj xv{fsqrt/frecip/frsqrt}.{s/d} xd, xj Change-Id: I3fdbe3193659d7532164451b087ccf725053172f Reviewed-on: https://go-review.googlesource.com/c/go/+/636395 Reviewed-by: David Chase <drchase@google.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Junyang Shao <shaojunyang@google.com>
2025-03-12cmd/internal/obj/loong64: add {V,XV}DIV{B/H/W/V}[U] and ↵Xiaolin Zhao
{V,XV}MOD{B/H/W/V}[U] instructions support Go asm syntax: VDIV{B/H/W/V}[U] VK, VJ, VD XVDIV{B/H/W/V}[U] XK, XJ, XD VMOD{B/H/W/V}[U] VK, VJ, VD XVMOD{B/H/W/V}[U] XK, XJ, XD Equivalent platform assembler syntax: vdiv.{b/h/w/d}[u] vd, vj, vk xvdiv.{b/h/w/d}[u] xd, xj, xk vmod.{b/h/w/d}[u] vd, vj, vk xvmod.{b/h/w/d}[u] xd, xj, xk Change-Id: I3676721c3c415de0f2ebbd480ecd1b2400a28dba Reviewed-on: https://go-review.googlesource.com/c/go/+/636376 Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: David Chase <drchase@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
generated by cgit v1.3 (git 2.53.0) at 2026-04-15 10:57:42 +0000