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| author | Xiaolin Zhao <zhaoxiaolin@loongson.cn> | 2025-05-30 11:20:32 +0800 |
|---|---|---|
| committer | abner chenc <chenguoqi@loongson.cn> | 2025-08-03 18:26:56 -0700 |
| commit | b2960e35804aafbbb0df9973f99b034bea8c150a (patch) | |
| tree | a4a5d3e0e422bf0da5b76b4563f01c6adf192332 /src/cmd/asm | |
| parent | abeeef1c08a589c2341f0d4e19ae49ec0892e797 (diff) | |
| download | go-b2960e35804aafbbb0df9973f99b034bea8c150a.tar.xz | |
cmd/internal/obj/loong64: add {V,XV}{BITCLR/BITSET/BITREV}[I].{B/H/W/D} instructions support
Go asm syntax:
V{BITCLR/BITSET/BITREV}{B/H/W/V} $1, V2, V3
XV{BITCLR/BITSET/BITREV}{B/H/W/V} $1, X2, X3
V{BITCLR/BITSET/BITREV}{B/H/W/V} VK, VJ, VD
XV{BITCLR/BITSET/BITREV}{B/H/W/V} XK, XJ, XD
Equivalent platform assembler syntax:
v{bitclr/bitset/bitrev}i.{b/h/w/d} v3, v2, $1
xv{bitclr/bitset/bitrev}i.{b/h/w/d} x3, x2, $1
v{bitclr/bitset/bitrev}.{b/h/w/d} vd, vj, vk
xv{bitclr/bitset/bitrev}.{b/h/w/d} xd, xj, xk
Change-Id: I244f8ae316f72cc7ea01ca0139ac78c5616a3c5b
Reviewed-on: https://go-review.googlesource.com/c/go/+/677435
Reviewed-by: Cherry Mui <cherryyz@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: abner chenc <chenguoqi@loongson.cn>
Reviewed-by: Mark Freeman <mark@golang.org>
Diffstat (limited to 'src/cmd/asm')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/loong64enc1.s | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/loong64enc1.s b/src/cmd/asm/internal/asm/testdata/loong64enc1.s index dfb2a2f177..8363996683 100644 --- a/src/cmd/asm/internal/asm/testdata/loong64enc1.s +++ b/src/cmd/asm/internal/asm/testdata/loong64enc1.s @@ -1045,3 +1045,53 @@ lable2: PRELD (R4), $0 // 8000c02a PRELD -1(R4), $8 // 88fcff2a PRELD 8(R4), $31 // 9f20c02a + + // [X]{VBITCLR/VBITSET/VBITREV}{B,H,W,V} instructions + VBITCLRB V1, V2, V3 // 43040c71 + VBITCLRH V1, V2, V3 // 43840c71 + VBITCLRW V1, V2, V3 // 43040d71 + VBITCLRV V1, V2, V3 // 43840d71 + VBITSETB V1, V2, V3 // 43040e71 + VBITSETH V1, V2, V3 // 43840e71 + VBITSETW V1, V2, V3 // 43040f71 + VBITSETV V1, V2, V3 // 43840f71 + VBITREVB V1, V2, V3 // 43041071 + VBITREVH V1, V2, V3 // 43841071 + VBITREVW V1, V2, V3 // 43041171 + VBITREVV V1, V2, V3 // 43841171 + XVBITCLRB X3, X2, X1 // 410c0c75 + XVBITCLRH X3, X2, X1 // 418c0c75 + XVBITCLRW X3, X2, X1 // 410c0d75 + XVBITCLRV X3, X2, X1 // 418c0d75 + XVBITSETB X3, X2, X1 // 410c0e75 + XVBITSETH X3, X2, X1 // 418c0e75 + XVBITSETW X3, X2, X1 // 410c0f75 + XVBITSETV X3, X2, X1 // 418c0f75 + XVBITREVB X3, X2, X1 // 410c1075 + XVBITREVH X3, X2, X1 // 418c1075 + XVBITREVW X3, X2, X1 // 410c1175 + XVBITREVV X3, X2, X1 // 418c1175 + VBITCLRB $7, V2, V3 // 433c1073 + VBITCLRH $15, V2, V3 // 437c1073 + VBITCLRW $31, V2, V3 // 43fc1073 + VBITCLRV $63, V2, V3 // 43fc1173 + VBITSETB $7, V2, V3 // 433c1473 + VBITSETH $15, V2, V3 // 437c1473 + VBITSETW $31, V2, V3 // 43fc1473 + VBITSETV $63, V2, V3 // 43fc1573 + VBITREVB $7, V2, V3 // 433c1873 + VBITREVH $15, V2, V3 // 437c1873 + VBITREVW $31, V2, V3 // 43fc1873 + VBITREVV $63, V2, V3 // 43fc1973 + XVBITCLRB $7, X2, X1 // 413c1077 + XVBITCLRH $15, X2, X1 // 417c1077 + XVBITCLRW $31, X2, X1 // 41fc1077 + XVBITCLRV $63, X2, X1 // 41fc1177 + XVBITSETB $7, X2, X1 // 413c1477 + XVBITSETH $15, X2, X1 // 417c1477 + XVBITSETW $31, X2, X1 // 41fc1477 + XVBITSETV $63, X2, X1 // 41fc1577 + XVBITREVB $7, X2, X1 // 413c1877 + XVBITREVH $15, X2, X1 // 417c1877 + XVBITREVW $31, X2, X1 // 41fc1877 + XVBITREVV $63, X2, X1 // 41fc1977 |