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| author | lxq015 <1824368278@qq.com> | 2025-09-17 04:10:13 +0000 |
|---|---|---|
| committer | Meng Zhuo <mengzhuo1203@gmail.com> | 2025-09-17 18:54:30 -0700 |
| commit | ef05b66d6115209361dd99ff8f3ab978695fd74a (patch) | |
| tree | ee258d594ddb30097e2e7758b6862352651289ba /src/cmd/asm | |
| parent | 78ef487a6f936a39e9d4ebf66ac421bb1244a7a9 (diff) | |
| download | go-ef05b66d6115209361dd99ff8f3ab978695fd74a.tar.xz | |
cmd/internal/obj/riscv: add support for Zicond instructions
This patch implement assembler for the Zicond extension: CZEROEQZ and CZERONEZ.
Follow-up to CL 631576
Updates #75350
Change-Id: Icf4be131fe61c3b7a3bde4811cf42dc807660907
GitHub-Last-Rev: 6539cc86cbf3c49c3247ed935bcbbb31bb886dea
GitHub-Pull-Request: golang/go#75408
Reviewed-on: https://go-review.googlesource.com/c/go/+/702677
Reviewed-by: Mark Freeman <markfreeman@google.com>
Reviewed-by: Joel Sing <joel@sing.id.au>
Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
Reviewed-by: Michael Knyszek <mknyszek@google.com>
Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
TryBot-Bypass: Joel Sing <joel@sing.id.au>
Diffstat (limited to 'src/cmd/asm')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/riscv64.s | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/riscv64.s b/src/cmd/asm/internal/asm/testdata/riscv64.s index 39d2faac25..07a898465f 100644 --- a/src/cmd/asm/internal/asm/testdata/riscv64.s +++ b/src/cmd/asm/internal/asm/testdata/riscv64.s @@ -195,6 +195,12 @@ start: RDTIME X5 // f32210c0 RDINSTRET X5 // f32220c0 + // 12.3: Integer Conditional Operations (Zicond) + CZEROEQZ X5, X6, X7 // b353530e + CZEROEQZ X5, X7 // b3d3530e + CZERONEZ X5, X6, X7 // b373530e + CZERONEZ X5, X7 // b3f3530e + // 13.1: Multiplication Operations MUL X5, X6, X7 // b3035302 MULH X5, X6, X7 // b3135302 |