diff options
Diffstat (limited to 'src/cmd/compile/internal/ssa')
67 files changed, 43366 insertions, 0 deletions
diff --git a/src/cmd/compile/internal/ssa/TODO b/src/cmd/compile/internal/ssa/TODO new file mode 100644 index 0000000000..a457e67101 --- /dev/null +++ b/src/cmd/compile/internal/ssa/TODO @@ -0,0 +1,68 @@ +This is a list of things that need to be worked on. It will hopefully +be complete soon. + +Coverage +-------- + +Correctness +----------- +- Debugging info (check & fix as much as we can) + +Optimizations (better compiled code) +------------------------------------ +- Reduce register pressure in scheduler +- More strength reduction: multiply -> shift/add combos (Worth doing?) +- Add a value range propagation pass (for bounds elim & bitwidth reduction) +- Make dead store pass inter-block +- redundant CMP in sequences like this: + SUBQ $8, AX + CMP AX, $0 + JEQ ... +- If there are a lot of MOVQ $0, ..., then load + 0 into a register and use the register as the source instead. +- Allow arrays of length 1 (or longer, with all constant indexes?) to be SSAable. +- Figure out how to make PARAMOUT variables ssa-able. + They need to get spilled automatically at end-of-function somehow. +- If strings are being passed around without being interpreted (ptr + and len fields being accessed) pass them in xmm registers? + Same for interfaces? +- OpArrayIndex should take its index in AuxInt, not a full value. +- remove FLAGS from REP instruction clobbers +- (x86) Combine loads into other ops + Note that this is challenging for ops that generate flags + because flagalloc wants to move those instructions around for + flag regeneration. +- Non-constant rotate detection. +- Do 0 <= x && x < n with one unsigned compare +- nil-check removal in indexed load/store case: + lea (%rdx,%rax,1),%rcx + test %al,(%rcx) // nil check + mov (%rdx,%rax,1),%cl // load to same address +- any pointer generated by unsafe arithmetic must be non-nil? + (Of course that may not be true in general, but it is for all uses + in the runtime, and we can play games with unsafe.) + +Optimizations (better compiler) +------------------------------- +- Smaller Value.Type (int32 or ptr)? Get rid of types altogether? +- OpStore uses 3 args. Increase the size of Value.argstorage to 3? +- Use a constant cache for OpConstNil, OpConstInterface, OpConstSlice, maybe OpConstString +- Handle signed division overflow and sign extension earlier +- Implement 64 bit const division with high multiply, maybe in the frontend? +- Add bit widths to complex ops + +Regalloc +-------- +- Make less arch-dependent +- Allow return values to be ssa-able +- Handle 2-address instructions +- Make liveness analysis non-quadratic + +Future/other +------------ +- Start another architecture (arm?) +- 64-bit ops on 32-bit machines +- Investigate type equality. During SSA generation, should we use n.Type or (say) TypeBool? +- Should we get rid of named types in favor of underlying types during SSA generation? +- Should we introduce a new type equality routine that is less strict than the frontend's? +- Infrastructure for enabling/disabling/configuring passes diff --git a/src/cmd/compile/internal/ssa/block.go b/src/cmd/compile/internal/ssa/block.go new file mode 100644 index 0000000000..7641811a5f --- /dev/null +++ b/src/cmd/compile/internal/ssa/block.go @@ -0,0 +1,118 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import "fmt" + +// Block represents a basic block in the control flow graph of a function. +type Block struct { + // A unique identifier for the block. The system will attempt to allocate + // these IDs densely, but no guarantees. + ID ID + + // The kind of block this is. + Kind BlockKind + + // Subsequent blocks, if any. The number and order depend on the block kind. + // All successors must be distinct (to make phi values in successors unambiguous). + Succs []*Block + + // Inverse of successors. + // The order is significant to Phi nodes in the block. + Preds []*Block + // TODO: predecessors is a pain to maintain. Can we somehow order phi + // arguments by block id and have this field computed explicitly when needed? + + // A value that determines how the block is exited. Its value depends on the kind + // of the block. For instance, a BlockIf has a boolean control value and BlockExit + // has a memory control value. + Control *Value + + // Auxiliary info for the block. Its value depends on the Kind. + Aux interface{} + + // The unordered set of Values that define the operation of this block. + // The list must include the control value, if any. (TODO: need this last condition?) + // After the scheduling pass, this list is ordered. + Values []*Value + + // The containing function + Func *Func + + // Line number for block's control operation + Line int32 + + // Likely direction for branches. + // If BranchLikely, Succs[0] is the most likely branch taken. + // If BranchUnlikely, Succs[1] is the most likely branch taken. + // Ignored if len(Succs) < 2. + // Fatal if not BranchUnknown and len(Succs) > 2. + Likely BranchPrediction + + // After flagalloc, records whether flags are live at the end of the block. + FlagsLiveAtEnd bool + + // Storage for Succs, Preds, and Values + succstorage [2]*Block + predstorage [4]*Block + valstorage [8]*Value +} + +// kind control successors +// ------------------------------------------ +// Exit return mem [] +// Plain nil [next] +// If a boolean Value [then, else] +// Call mem [nopanic, panic] (control opcode should be OpCall or OpStaticCall) +type BlockKind int32 + +// short form print +func (b *Block) String() string { + return fmt.Sprintf("b%d", b.ID) +} + +// long form print +func (b *Block) LongString() string { + s := b.Kind.String() + if b.Aux != nil { + s += fmt.Sprintf(" %s", b.Aux) + } + if b.Control != nil { + s += fmt.Sprintf(" %s", b.Control) + } + if len(b.Succs) > 0 { + s += " ->" + for _, c := range b.Succs { + s += " " + c.String() + } + } + switch b.Likely { + case BranchUnlikely: + s += " (unlikely)" + case BranchLikely: + s += " (likely)" + } + return s +} + +// AddEdgeTo adds an edge from block b to block c. Used during building of the +// SSA graph; do not use on an already-completed SSA graph. +func (b *Block) AddEdgeTo(c *Block) { + b.Succs = append(b.Succs, c) + c.Preds = append(c.Preds, b) +} + +func (b *Block) Logf(msg string, args ...interface{}) { b.Func.Logf(msg, args...) } +func (b *Block) Log() bool { return b.Func.Log() } +func (b *Block) Fatalf(msg string, args ...interface{}) { b.Func.Fatalf(msg, args...) } +func (b *Block) Unimplementedf(msg string, args ...interface{}) { b.Func.Unimplementedf(msg, args...) } + +type BranchPrediction int8 + +const ( + BranchUnlikely = BranchPrediction(-1) + BranchUnknown = BranchPrediction(0) + BranchLikely = BranchPrediction(+1) +) diff --git a/src/cmd/compile/internal/ssa/check.go b/src/cmd/compile/internal/ssa/check.go new file mode 100644 index 0000000000..54f774004e --- /dev/null +++ b/src/cmd/compile/internal/ssa/check.go @@ -0,0 +1,291 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +// checkFunc checks invariants of f. +func checkFunc(f *Func) { + blockMark := make([]bool, f.NumBlocks()) + valueMark := make([]bool, f.NumValues()) + + for _, b := range f.Blocks { + if blockMark[b.ID] { + f.Fatalf("block %s appears twice in %s!", b, f.Name) + } + blockMark[b.ID] = true + if b.Func != f { + f.Fatalf("%s.Func=%s, want %s", b, b.Func.Name, f.Name) + } + + if f.RegAlloc == nil { + for i, c := range b.Succs { + for j, d := range b.Succs { + if i != j && c == d { + f.Fatalf("%s.Succs has duplicate block %s", b, c) + } + } + } + } + // Note: duplicate successors are hard in the following case: + // if(...) goto x else goto x + // x: v = phi(a, b) + // If the conditional is true, does v get the value of a or b? + // We could solve this other ways, but the easiest is just to + // require (by possibly adding empty control-flow blocks) that + // all successors are distinct. They will need to be distinct + // anyway for register allocation (duplicate successors implies + // the existence of critical edges). + // After regalloc we can allow non-distinct predecessors. + + for _, p := range b.Preds { + var found bool + for _, c := range p.Succs { + if c == b { + found = true + break + } + } + if !found { + f.Fatalf("block %s is not a succ of its pred block %s", b, p) + } + } + + switch b.Kind { + case BlockExit: + if len(b.Succs) != 0 { + f.Fatalf("exit block %s has successors", b) + } + if b.Control == nil { + f.Fatalf("exit block %s has no control value", b) + } + if !b.Control.Type.IsMemory() { + f.Fatalf("exit block %s has non-memory control value %s", b, b.Control.LongString()) + } + case BlockRet: + if len(b.Succs) != 0 { + f.Fatalf("ret block %s has successors", b) + } + if b.Control == nil { + f.Fatalf("ret block %s has nil control %s", b) + } + if !b.Control.Type.IsMemory() { + f.Fatalf("ret block %s has non-memory control value %s", b, b.Control.LongString()) + } + case BlockRetJmp: + if len(b.Succs) != 0 { + f.Fatalf("retjmp block %s len(Succs)==%d, want 0", b, len(b.Succs)) + } + if b.Control == nil { + f.Fatalf("retjmp block %s has nil control %s", b) + } + if !b.Control.Type.IsMemory() { + f.Fatalf("retjmp block %s has non-memory control value %s", b, b.Control.LongString()) + } + if b.Aux == nil { + f.Fatalf("retjmp block %s has nil Aux field", b) + } + case BlockDead: + if len(b.Succs) != 0 { + f.Fatalf("dead block %s has successors", b) + } + if len(b.Preds) != 0 { + f.Fatalf("dead block %s has predecessors", b) + } + if len(b.Values) != 0 { + f.Fatalf("dead block %s has values", b) + } + if b.Control != nil { + f.Fatalf("dead block %s has a control value", b) + } + case BlockPlain: + if len(b.Succs) != 1 { + f.Fatalf("plain block %s len(Succs)==%d, want 1", b, len(b.Succs)) + } + if b.Control != nil { + f.Fatalf("plain block %s has non-nil control %s", b, b.Control.LongString()) + } + case BlockIf: + if len(b.Succs) != 2 { + f.Fatalf("if block %s len(Succs)==%d, want 2", b, len(b.Succs)) + } + if b.Control == nil { + f.Fatalf("if block %s has no control value", b) + } + if !b.Control.Type.IsBoolean() { + f.Fatalf("if block %s has non-bool control value %s", b, b.Control.LongString()) + } + case BlockCall: + if len(b.Succs) != 1 { + f.Fatalf("call block %s len(Succs)==%d, want 1", b, len(b.Succs)) + } + if b.Control == nil { + f.Fatalf("call block %s has no control value", b) + } + if !b.Control.Type.IsMemory() { + f.Fatalf("call block %s has non-memory control value %s", b, b.Control.LongString()) + } + case BlockCheck: + if len(b.Succs) != 1 { + f.Fatalf("check block %s len(Succs)==%d, want 1", b, len(b.Succs)) + } + if b.Control == nil { + f.Fatalf("check block %s has no control value", b) + } + if !b.Control.Type.IsVoid() { + f.Fatalf("check block %s has non-void control value %s", b, b.Control.LongString()) + } + case BlockFirst: + if len(b.Succs) != 2 { + f.Fatalf("plain/dead block %s len(Succs)==%d, want 2", b, len(b.Succs)) + } + if b.Control != nil { + f.Fatalf("plain/dead block %s has a control value", b) + } + } + if len(b.Succs) > 2 && b.Likely != BranchUnknown { + f.Fatalf("likeliness prediction %d for block %s with %d successors: %s", b.Likely, b, len(b.Succs)) + } + + for _, v := range b.Values { + // Check to make sure argument count makes sense (argLen of -1 indicates + // variable length args) + nArgs := opcodeTable[v.Op].argLen + if nArgs != -1 && int32(len(v.Args)) != nArgs { + f.Fatalf("value %v has %d args, expected %d", v.LongString(), + len(v.Args), nArgs) + } + + // Check to make sure aux values make sense. + canHaveAux := false + canHaveAuxInt := false + switch opcodeTable[v.Op].auxType { + case auxNone: + case auxBool, auxInt8, auxInt16, auxInt32, auxInt64, auxFloat: + canHaveAuxInt = true + case auxString, auxSym: + canHaveAux = true + case auxSymOff, auxSymValAndOff: + canHaveAuxInt = true + canHaveAux = true + default: + f.Fatalf("unknown aux type for %s", v.Op) + } + if !canHaveAux && v.Aux != nil { + f.Fatalf("value %v has an Aux value %v but shouldn't", v.LongString(), v.Aux) + } + if !canHaveAuxInt && v.AuxInt != 0 { + f.Fatalf("value %v has an AuxInt value %d but shouldn't", v.LongString(), v.AuxInt) + } + + for _, arg := range v.Args { + if arg == nil { + f.Fatalf("value %v has nil arg", v.LongString()) + } + } + + if valueMark[v.ID] { + f.Fatalf("value %s appears twice!", v.LongString()) + } + valueMark[v.ID] = true + + if v.Block != b { + f.Fatalf("%s.block != %s", v, b) + } + if v.Op == OpPhi && len(v.Args) != len(b.Preds) { + f.Fatalf("phi length %s does not match pred length %d for block %s", v.LongString(), len(b.Preds), b) + } + + if v.Op == OpAddr { + if len(v.Args) == 0 { + f.Fatalf("no args for OpAddr %s", v.LongString()) + } + if v.Args[0].Op != OpSP && v.Args[0].Op != OpSB { + f.Fatalf("bad arg to OpAddr %v", v) + } + } + + // TODO: check for cycles in values + // TODO: check type + } + } + + // Check to make sure all Blocks referenced are in the function. + if !blockMark[f.Entry.ID] { + f.Fatalf("entry block %v is missing", f.Entry) + } + for _, b := range f.Blocks { + for _, c := range b.Preds { + if !blockMark[c.ID] { + f.Fatalf("predecessor block %v for %v is missing", c, b) + } + } + for _, c := range b.Succs { + if !blockMark[c.ID] { + f.Fatalf("successor block %v for %v is missing", c, b) + } + } + } + + if len(f.Entry.Preds) > 0 { + f.Fatalf("entry block %s of %s has predecessor(s) %v", f.Entry, f.Name, f.Entry.Preds) + } + + // Check to make sure all Values referenced are in the function. + for _, b := range f.Blocks { + for _, v := range b.Values { + for i, a := range v.Args { + if !valueMark[a.ID] { + f.Fatalf("%v, arg %d of %v, is missing", a, i, v) + } + } + } + if b.Control != nil && !valueMark[b.Control.ID] { + f.Fatalf("control value for %s is missing: %v", b, b.Control) + } + } + for b := f.freeBlocks; b != nil; b = b.succstorage[0] { + if blockMark[b.ID] { + f.Fatalf("used block b%d in free list", b.ID) + } + } + for v := f.freeValues; v != nil; v = v.argstorage[0] { + if valueMark[v.ID] { + f.Fatalf("used value v%d in free list", v.ID) + } + } + + // Check to make sure all args dominate uses. + if f.RegAlloc == nil { + // Note: regalloc introduces non-dominating args. + // See TODO in regalloc.go. + idom := dominators(f) + sdom := newSparseTree(f, idom) + for _, b := range f.Blocks { + for _, v := range b.Values { + for i, arg := range v.Args { + x := arg.Block + y := b + if v.Op == OpPhi { + y = b.Preds[i] + } + if !domCheck(f, sdom, x, y) { + f.Fatalf("arg %d of value %s does not dominate, arg=%s", i, v.LongString(), arg.LongString()) + } + } + } + if b.Control != nil && !domCheck(f, sdom, b.Control.Block, b) { + f.Fatalf("control value %s for %s doesn't dominate", b.Control, b) + } + } + } +} + +// domCheck reports whether x dominates y (including x==y). +func domCheck(f *Func, sdom sparseTree, x, y *Block) bool { + if !sdom.isAncestorEq(y, f.Entry) { + // unreachable - ignore + return true + } + return sdom.isAncestorEq(x, y) +} diff --git a/src/cmd/compile/internal/ssa/compile.go b/src/cmd/compile/internal/ssa/compile.go new file mode 100644 index 0000000000..f68819c3c2 --- /dev/null +++ b/src/cmd/compile/internal/ssa/compile.go @@ -0,0 +1,261 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import ( + "fmt" + "log" + "runtime" + "strings" + "time" +) + +// Compile is the main entry point for this package. +// Compile modifies f so that on return: +// · all Values in f map to 0 or 1 assembly instructions of the target architecture +// · the order of f.Blocks is the order to emit the Blocks +// · the order of b.Values is the order to emit the Values in each Block +// · f has a non-nil regAlloc field +func Compile(f *Func) { + // TODO: debugging - set flags to control verbosity of compiler, + // which phases to dump IR before/after, etc. + if f.Log() { + f.Logf("compiling %s\n", f.Name) + } + + // hook to print function & phase if panic happens + phaseName := "init" + defer func() { + if phaseName != "" { + err := recover() + stack := make([]byte, 16384) + n := runtime.Stack(stack, false) + stack = stack[:n] + f.Fatalf("panic during %s while compiling %s:\n\n%v\n\n%s\n", phaseName, f.Name, err, stack) + } + }() + + // Run all the passes + printFunc(f) + f.Config.HTML.WriteFunc("start", f) + checkFunc(f) + const logMemStats = false + for _, p := range passes { + if !f.Config.optimize && !p.required { + continue + } + f.pass = &p + phaseName = p.name + if f.Log() { + f.Logf(" pass %s begin\n", p.name) + } + // TODO: capture logging during this pass, add it to the HTML + var mStart runtime.MemStats + if logMemStats || p.mem { + runtime.ReadMemStats(&mStart) + } + + tStart := time.Now() + p.fn(f) + tEnd := time.Now() + + // Need something less crude than "Log the whole intermediate result". + if f.Log() || f.Config.HTML != nil { + time := tEnd.Sub(tStart).Nanoseconds() + var stats string + if logMemStats { + var mEnd runtime.MemStats + runtime.ReadMemStats(&mEnd) + nBytes := mEnd.TotalAlloc - mStart.TotalAlloc + nAllocs := mEnd.Mallocs - mStart.Mallocs + stats = fmt.Sprintf("[%d ns %d allocs %d bytes]", time, nAllocs, nBytes) + } else { + stats = fmt.Sprintf("[%d ns]", time) + } + + f.Logf(" pass %s end %s\n", p.name, stats) + printFunc(f) + f.Config.HTML.WriteFunc(fmt.Sprintf("after %s <span class=\"stats\">%s</span>", phaseName, stats), f) + } + if p.time || p.mem { + // Surround timing information w/ enough context to allow comparisons. + time := tEnd.Sub(tStart).Nanoseconds() + if p.time { + f.logStat("TIME(ns)", time) + } + if p.mem { + var mEnd runtime.MemStats + runtime.ReadMemStats(&mEnd) + nBytes := mEnd.TotalAlloc - mStart.TotalAlloc + nAllocs := mEnd.Mallocs - mStart.Mallocs + f.logStat("TIME(ns):BYTES:ALLOCS", time, nBytes, nAllocs) + } + } + checkFunc(f) + } + + // Squash error printing defer + phaseName = "" +} + +type pass struct { + name string + fn func(*Func) + required bool + disabled bool + time bool // report time to run pass + mem bool // report mem stats to run pass + stats int // pass reports own "stats" (e.g., branches removed) + debug int // pass performs some debugging. =1 should be in error-testing-friendly Warnl format. + test int // pass-specific ad-hoc option, perhaps useful in development +} + +// PhaseOption sets the specified flag in the specified ssa phase, +// returning empty string if this was successful or a string explaining +// the error if it was not. A version of the phase name with "_" +// replaced by " " is also checked for a match. +// See gc/lex.go for dissection of the option string. Example use: +// GO_GCFLAGS=-d=ssa/generic_cse/time,ssa/generic_cse/stats,ssa/generic_cse/debug=3 ./make.bash ... +// +func PhaseOption(phase, flag string, val int) string { + underphase := strings.Replace(phase, "_", " ", -1) + for i, p := range passes { + if p.name == phase || p.name == underphase { + switch flag { + case "on": + p.disabled = val == 0 + case "off": + p.disabled = val != 0 + case "time": + p.time = val != 0 + case "mem": + p.mem = val != 0 + case "debug": + p.debug = val + case "stats": + p.stats = val + case "test": + p.test = val + default: + return fmt.Sprintf("Did not find a flag matching %s in -d=ssa/%s debug option", flag, phase) + } + if p.disabled && p.required { + return fmt.Sprintf("Cannot disable required SSA phase %s using -d=ssa/%s debug option", phase, phase) + } + passes[i] = p + return "" + } + } + return fmt.Sprintf("Did not find a phase matching %s in -d=ssa/... debug option", phase) +} + +// list of passes for the compiler +var passes = [...]pass{ + // TODO: combine phielim and copyelim into a single pass? + {name: "early phielim", fn: phielim}, + {name: "early copyelim", fn: copyelim}, + {name: "early deadcode", fn: deadcode}, // remove generated dead code to avoid doing pointless work during opt + {name: "short circuit", fn: shortcircuit}, + {name: "decompose user", fn: decomposeUser, required: true}, + {name: "decompose builtin", fn: decomposeBuiltIn, required: true}, + {name: "opt", fn: opt, required: true}, // TODO: split required rules and optimizing rules + {name: "zero arg cse", fn: zcse, required: true}, // required to merge OpSB values + {name: "opt deadcode", fn: deadcode}, // remove any blocks orphaned during opt + {name: "generic cse", fn: cse}, + {name: "phiopt", fn: phiopt}, + {name: "nilcheckelim", fn: nilcheckelim}, + {name: "prove", fn: prove}, + {name: "generic deadcode", fn: deadcode}, + {name: "fuse", fn: fuse}, + {name: "dse", fn: dse}, + {name: "tighten", fn: tighten}, // move values closer to their uses + {name: "lower", fn: lower, required: true}, + {name: "lowered cse", fn: cse}, + {name: "lowered deadcode", fn: deadcode, required: true}, + {name: "checkLower", fn: checkLower, required: true}, + {name: "late phielim", fn: phielim}, + {name: "late copyelim", fn: copyelim}, + {name: "late deadcode", fn: deadcode}, + {name: "critical", fn: critical, required: true}, // remove critical edges + {name: "likelyadjust", fn: likelyadjust}, + {name: "layout", fn: layout, required: true}, // schedule blocks + {name: "schedule", fn: schedule, required: true}, // schedule values + {name: "flagalloc", fn: flagalloc, required: true}, // allocate flags register + {name: "regalloc", fn: regalloc, required: true}, // allocate int & float registers + stack slots + {name: "trim", fn: trim}, // remove empty blocks +} + +// Double-check phase ordering constraints. +// This code is intended to document the ordering requirements +// between different phases. It does not override the passes +// list above. +type constraint struct { + a, b string // a must come before b +} + +var passOrder = [...]constraint{ + // prove reliese on common-subexpression elimination for maximum benefits. + {"generic cse", "prove"}, + // deadcode after prove to eliminate all new dead blocks. + {"prove", "generic deadcode"}, + // common-subexpression before dead-store elim, so that we recognize + // when two address expressions are the same. + {"generic cse", "dse"}, + // cse substantially improves nilcheckelim efficacy + {"generic cse", "nilcheckelim"}, + // allow deadcode to clean up after nilcheckelim + {"nilcheckelim", "generic deadcode"}, + // nilcheckelim generates sequences of plain basic blocks + {"nilcheckelim", "fuse"}, + // nilcheckelim relies on opt to rewrite user nil checks + {"opt", "nilcheckelim"}, + // tighten should happen before lowering to avoid splitting naturally paired instructions such as CMP/SET + {"tighten", "lower"}, + // tighten will be most effective when as many values have been removed as possible + {"generic deadcode", "tighten"}, + {"generic cse", "tighten"}, + // don't run optimization pass until we've decomposed builtin objects + {"decompose builtin", "opt"}, + // don't layout blocks until critical edges have been removed + {"critical", "layout"}, + // regalloc requires the removal of all critical edges + {"critical", "regalloc"}, + // regalloc requires all the values in a block to be scheduled + {"schedule", "regalloc"}, + // checkLower must run after lowering & subsequent dead code elim + {"lower", "checkLower"}, + {"lowered deadcode", "checkLower"}, + // flagalloc needs instructions to be scheduled. + {"schedule", "flagalloc"}, + // regalloc needs flags to be allocated first. + {"flagalloc", "regalloc"}, + // trim needs regalloc to be done first. + {"regalloc", "trim"}, +} + +func init() { + for _, c := range passOrder { + a, b := c.a, c.b + i := -1 + j := -1 + for k, p := range passes { + if p.name == a { + i = k + } + if p.name == b { + j = k + } + } + if i < 0 { + log.Panicf("pass %s not found", a) + } + if j < 0 { + log.Panicf("pass %s not found", b) + } + if i >= j { + log.Panicf("passes %s and %s out of order", a, b) + } + } +} diff --git a/src/cmd/compile/internal/ssa/config.go b/src/cmd/compile/internal/ssa/config.go new file mode 100644 index 0000000000..8657509c5c --- /dev/null +++ b/src/cmd/compile/internal/ssa/config.go @@ -0,0 +1,235 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import ( + "cmd/internal/obj" + "crypto/sha1" + "fmt" + "os" + "strings" +) + +type Config struct { + arch string // "amd64", etc. + IntSize int64 // 4 or 8 + PtrSize int64 // 4 or 8 + lowerBlock func(*Block) bool // lowering function + lowerValue func(*Value, *Config) bool // lowering function + fe Frontend // callbacks into compiler frontend + HTML *HTMLWriter // html writer, for debugging + ctxt *obj.Link // Generic arch information + optimize bool // Do optimization + curFunc *Func + + // TODO: more stuff. Compiler flags of interest, ... + + // Given an environment variable used for debug hash match, + // what file (if any) receives the yes/no logging? + logfiles map[string]*os.File + + // Storage for low-numbered values and blocks. + values [2000]Value + blocks [200]Block + + domblockstore []ID // scratch space for computing dominators + scrSparse []*sparseSet // scratch sparse sets to be re-used. +} + +type TypeSource interface { + TypeBool() Type + TypeInt8() Type + TypeInt16() Type + TypeInt32() Type + TypeInt64() Type + TypeUInt8() Type + TypeUInt16() Type + TypeUInt32() Type + TypeUInt64() Type + TypeInt() Type + TypeFloat32() Type + TypeFloat64() Type + TypeUintptr() Type + TypeString() Type + TypeBytePtr() Type // TODO: use unsafe.Pointer instead? + + CanSSA(t Type) bool +} + +type Logger interface { + // Logf logs a message from the compiler. + Logf(string, ...interface{}) + + // Log returns true if logging is not a no-op + // some logging calls account for more than a few heap allocations. + Log() bool + + // Fatal reports a compiler error and exits. + Fatalf(line int32, msg string, args ...interface{}) + + // Unimplemented reports that the function cannot be compiled. + // It will be removed once SSA work is complete. + Unimplementedf(line int32, msg string, args ...interface{}) + + // Warnl writes compiler messages in the form expected by "errorcheck" tests + Warnl(line int, fmt_ string, args ...interface{}) + + // Fowards the Debug_checknil flag from gc + Debug_checknil() bool +} + +type Frontend interface { + TypeSource + Logger + + // StringData returns a symbol pointing to the given string's contents. + StringData(string) interface{} // returns *gc.Sym + + // Auto returns a Node for an auto variable of the given type. + // The SSA compiler uses this function to allocate space for spills. + Auto(Type) GCNode + + // Line returns a string describing the given line number. + Line(int32) string +} + +// interface used to hold *gc.Node. We'd use *gc.Node directly but +// that would lead to an import cycle. +type GCNode interface { + Typ() Type + String() string +} + +// NewConfig returns a new configuration object for the given architecture. +func NewConfig(arch string, fe Frontend, ctxt *obj.Link, optimize bool) *Config { + c := &Config{arch: arch, fe: fe} + switch arch { + case "amd64": + c.IntSize = 8 + c.PtrSize = 8 + c.lowerBlock = rewriteBlockAMD64 + c.lowerValue = rewriteValueAMD64 + case "386": + c.IntSize = 4 + c.PtrSize = 4 + c.lowerBlock = rewriteBlockAMD64 + c.lowerValue = rewriteValueAMD64 // TODO(khr): full 32-bit support + default: + fe.Unimplementedf(0, "arch %s not implemented", arch) + } + c.ctxt = ctxt + c.optimize = optimize + + // Assign IDs to preallocated values/blocks. + for i := range c.values { + c.values[i].ID = ID(i) + } + for i := range c.blocks { + c.blocks[i].ID = ID(i) + } + + c.logfiles = make(map[string]*os.File) + + return c +} + +func (c *Config) Frontend() Frontend { return c.fe } + +// NewFunc returns a new, empty function object. +// Caller must call f.Free() before calling NewFunc again. +func (c *Config) NewFunc() *Func { + // TODO(khr): should this function take name, type, etc. as arguments? + if c.curFunc != nil { + c.Fatalf(0, "NewFunc called without previous Free") + } + f := &Func{Config: c, NamedValues: map[LocalSlot][]*Value{}} + c.curFunc = f + return f +} + +func (c *Config) Logf(msg string, args ...interface{}) { c.fe.Logf(msg, args...) } +func (c *Config) Log() bool { return c.fe.Log() } +func (c *Config) Fatalf(line int32, msg string, args ...interface{}) { c.fe.Fatalf(line, msg, args...) } +func (c *Config) Unimplementedf(line int32, msg string, args ...interface{}) { + c.fe.Unimplementedf(line, msg, args...) +} +func (c *Config) Warnl(line int, msg string, args ...interface{}) { c.fe.Warnl(line, msg, args...) } +func (c *Config) Debug_checknil() bool { return c.fe.Debug_checknil() } + +func (c *Config) logDebugHashMatch(evname, name string) { + var file *os.File + file = c.logfiles[evname] + if file == nil { + file = os.Stdout + tmpfile := os.Getenv("GSHS_LOGFILE") + if tmpfile != "" { + var ok error + file, ok = os.Create(tmpfile) + if ok != nil { + c.Fatalf(0, "Could not open hash-testing logfile %s", tmpfile) + } + } + c.logfiles[evname] = file + } + s := fmt.Sprintf("%s triggered %s\n", evname, name) + file.WriteString(s) + file.Sync() +} + +// DebugHashMatch returns true if environment variable evname +// 1) is empty (this is a special more-quickly implemented case of 3) +// 2) is "y" or "Y" +// 3) is a suffix of the sha1 hash of name +// 4) is a suffix of the environment variable +// fmt.Sprintf("%s%d", evname, n) +// provided that all such variables are nonempty for 0 <= i <= n +// Otherwise it returns false. +// When true is returned the message +// "%s triggered %s\n", evname, name +// is printed on the file named in environment variable +// GSHS_LOGFILE +// or standard out if that is empty or there is an error +// opening the file. + +func (c *Config) DebugHashMatch(evname, name string) bool { + evhash := os.Getenv(evname) + if evhash == "" { + return true // default behavior with no EV is "on" + } + if evhash == "y" || evhash == "Y" { + c.logDebugHashMatch(evname, name) + return true + } + if evhash == "n" || evhash == "N" { + return false + } + // Check the hash of the name against a partial input hash. + // We use this feature to do a binary search to + // find a function that is incorrectly compiled. + hstr := "" + for _, b := range sha1.Sum([]byte(name)) { + hstr += fmt.Sprintf("%08b", b) + } + + if strings.HasSuffix(hstr, evhash) { + c.logDebugHashMatch(evname, name) + return true + } + + // Iteratively try additional hashes to allow tests for multi-point + // failure. + for i := 0; true; i++ { + ev := fmt.Sprintf("%s%d", evname, i) + evv := os.Getenv(ev) + if evv == "" { + break + } + if strings.HasSuffix(hstr, evv) { + c.logDebugHashMatch(ev, name) + return true + } + } + return false +} diff --git a/src/cmd/compile/internal/ssa/copyelim.go b/src/cmd/compile/internal/ssa/copyelim.go new file mode 100644 index 0000000000..cfeff21e84 --- /dev/null +++ b/src/cmd/compile/internal/ssa/copyelim.go @@ -0,0 +1,60 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +// copyelim removes all copies from f. +func copyelim(f *Func) { + for _, b := range f.Blocks { + for _, v := range b.Values { + copyelimValue(v) + } + v := b.Control + if v != nil { + for v.Op == OpCopy { + v = v.Args[0] + } + b.Control = v + } + } + + // Update named values. + for _, name := range f.Names { + values := f.NamedValues[name] + for i, v := range values { + x := v + for x.Op == OpCopy { + x = x.Args[0] + } + if x != v { + values[i] = v + } + } + } +} + +func copyelimValue(v *Value) { + // elide any copies generated during rewriting + for i, a := range v.Args { + if a.Op != OpCopy { + continue + } + // Rewriting can generate OpCopy loops. + // They are harmless (see removePredecessor), + // but take care to stop if we find a cycle. + slow := a // advances every other iteration + var advance bool + for a.Op == OpCopy { + a = a.Args[0] + if slow == a { + break + } + if advance { + slow = slow.Args[0] + } + advance = !advance + } + v.Args[i] = a + } +} diff --git a/src/cmd/compile/internal/ssa/critical.go b/src/cmd/compile/internal/ssa/critical.go new file mode 100644 index 0000000000..9fea0ec1cd --- /dev/null +++ b/src/cmd/compile/internal/ssa/critical.go @@ -0,0 +1,39 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +// critical splits critical edges (those that go from a block with +// more than one outedge to a block with more than one inedge). +// Regalloc wants a critical-edge-free CFG so it can implement phi values. +func critical(f *Func) { + for _, b := range f.Blocks { + if len(b.Preds) <= 1 { + continue + } + + // split input edges coming from multi-output blocks. + for i, c := range b.Preds { + if c.Kind == BlockPlain { + continue // only single output block + } + + // allocate a new block to place on the edge + d := f.NewBlock(BlockPlain) + d.Line = c.Line + + // splice it in + d.Preds = append(d.Preds, c) + d.Succs = append(d.Succs, b) + b.Preds[i] = d + // replace b with d in c's successor list. + for j, b2 := range c.Succs { + if b2 == b { + c.Succs[j] = d + break + } + } + } + } +} diff --git a/src/cmd/compile/internal/ssa/cse.go b/src/cmd/compile/internal/ssa/cse.go new file mode 100644 index 0000000000..c44748535b --- /dev/null +++ b/src/cmd/compile/internal/ssa/cse.go @@ -0,0 +1,304 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import ( + "fmt" + "sort" +) + +const ( + cmpDepth = 4 +) + +// cse does common-subexpression elimination on the Function. +// Values are just relinked, nothing is deleted. A subsequent deadcode +// pass is required to actually remove duplicate expressions. +func cse(f *Func) { + // Two values are equivalent if they satisfy the following definition: + // equivalent(v, w): + // v.op == w.op + // v.type == w.type + // v.aux == w.aux + // v.auxint == w.auxint + // len(v.args) == len(w.args) + // v.block == w.block if v.op == OpPhi + // equivalent(v.args[i], w.args[i]) for i in 0..len(v.args)-1 + + // The algorithm searches for a partition of f's values into + // equivalence classes using the above definition. + // It starts with a coarse partition and iteratively refines it + // until it reaches a fixed point. + + // Make initial coarse partitions by using a subset of the conditions above. + a := make([]*Value, 0, f.NumValues()) + auxIDs := auxmap{} + for _, b := range f.Blocks { + for _, v := range b.Values { + if auxIDs[v.Aux] == 0 { + auxIDs[v.Aux] = int32(len(auxIDs)) + 1 + } + if v.Type.IsMemory() { + continue // memory values can never cse + } + if opcodeTable[v.Op].commutative && len(v.Args) == 2 && v.Args[1].ID < v.Args[0].ID { + // Order the arguments of binary commutative operations. + v.Args[0], v.Args[1] = v.Args[1], v.Args[0] + } + a = append(a, v) + } + } + partition := partitionValues(a, auxIDs) + + // map from value id back to eqclass id + valueEqClass := make([]ID, f.NumValues()) + for _, b := range f.Blocks { + for _, v := range b.Values { + // Use negative equivalence class #s for unique values. + valueEqClass[v.ID] = -v.ID + } + } + for i, e := range partition { + if f.pass.debug > 1 && len(e) > 500 { + fmt.Printf("CSE.large partition (%d): ", len(e)) + for j := 0; j < 3; j++ { + fmt.Printf("%s ", e[j].LongString()) + } + fmt.Println() + } + + for _, v := range e { + valueEqClass[v.ID] = ID(i) + } + if f.pass.debug > 2 && len(e) > 1 { + fmt.Printf("CSE.partition #%d:", i) + for _, v := range e { + fmt.Printf(" %s", v.String()) + } + fmt.Printf("\n") + } + } + + // Find an equivalence class where some members of the class have + // non-equivalent arguments. Split the equivalence class appropriately. + // Repeat until we can't find any more splits. + for { + changed := false + + // partition can grow in the loop. By not using a range loop here, + // we process new additions as they arrive, avoiding O(n^2) behavior. + for i := 0; i < len(partition); i++ { + e := partition[i] + v := e[0] + // all values in this equiv class that are not equivalent to v get moved + // into another equiv class. + // To avoid allocating while building that equivalence class, + // move the values equivalent to v to the beginning of e + // and other values to the end of e. + allvals := e + eqloop: + for j := 1; j < len(e); { + w := e[j] + equivalent := true + for i := 0; i < len(v.Args); i++ { + if valueEqClass[v.Args[i].ID] != valueEqClass[w.Args[i].ID] { + equivalent = false + break + } + } + if !equivalent || !v.Type.Equal(w.Type) { + // w is not equivalent to v. + // move it to the end and shrink e. + e[j], e[len(e)-1] = e[len(e)-1], e[j] + e = e[:len(e)-1] + valueEqClass[w.ID] = ID(len(partition)) + changed = true + continue eqloop + } + // v and w are equivalent. Keep w in e. + j++ + } + partition[i] = e + if len(e) < len(allvals) { + partition = append(partition, allvals[len(e):]) + } + } + + if !changed { + break + } + } + + // Compute dominator tree + idom := dominators(f) + sdom := newSparseTree(f, idom) + + // Compute substitutions we would like to do. We substitute v for w + // if v and w are in the same equivalence class and v dominates w. + rewrite := make([]*Value, f.NumValues()) + for _, e := range partition { + for len(e) > 1 { + // Find a maximal dominant element in e + v := e[0] + for _, w := range e[1:] { + if sdom.isAncestorEq(w.Block, v.Block) { + v = w + } + } + + // Replace all elements of e which v dominates + for i := 0; i < len(e); { + w := e[i] + if w == v { + e, e[i] = e[:len(e)-1], e[len(e)-1] + } else if sdom.isAncestorEq(v.Block, w.Block) { + rewrite[w.ID] = v + e, e[i] = e[:len(e)-1], e[len(e)-1] + } else { + i++ + } + } + } + } + + rewrites := int64(0) + + // Apply substitutions + for _, b := range f.Blocks { + for _, v := range b.Values { + for i, w := range v.Args { + if x := rewrite[w.ID]; x != nil { + v.SetArg(i, x) + rewrites++ + } + } + } + if v := b.Control; v != nil { + if x := rewrite[v.ID]; x != nil { + if v.Op == OpNilCheck { + // nilcheck pass will remove the nil checks and log + // them appropriately, so don't mess with them here. + continue + } + b.Control = x + } + } + } + if f.pass.stats > 0 { + f.logStat("CSE REWRITES", rewrites) + } +} + +// An eqclass approximates an equivalence class. During the +// algorithm it may represent the union of several of the +// final equivalence classes. +type eqclass []*Value + +// partitionValues partitions the values into equivalence classes +// based on having all the following features match: +// - opcode +// - type +// - auxint +// - aux +// - nargs +// - block # if a phi op +// - first two arg's opcodes and auxint +// - NOT first two arg's aux; that can break CSE. +// partitionValues returns a list of equivalence classes, each +// being a sorted by ID list of *Values. The eqclass slices are +// backed by the same storage as the input slice. +// Equivalence classes of size 1 are ignored. +func partitionValues(a []*Value, auxIDs auxmap) []eqclass { + sort.Sort(sortvalues{a, auxIDs}) + + var partition []eqclass + for len(a) > 0 { + v := a[0] + j := 1 + for ; j < len(a); j++ { + w := a[j] + if cmpVal(v, w, auxIDs, cmpDepth) != CMPeq { + break + } + } + if j > 1 { + partition = append(partition, a[:j]) + } + a = a[j:] + } + + return partition +} +func lt2Cmp(isLt bool) Cmp { + if isLt { + return CMPlt + } + return CMPgt +} + +type auxmap map[interface{}]int32 + +func cmpVal(v, w *Value, auxIDs auxmap, depth int) Cmp { + // Try to order these comparison by cost (cheaper first) + if v.Op != w.Op { + return lt2Cmp(v.Op < w.Op) + } + if v.AuxInt != w.AuxInt { + return lt2Cmp(v.AuxInt < w.AuxInt) + } + if len(v.Args) != len(w.Args) { + return lt2Cmp(len(v.Args) < len(w.Args)) + } + if v.Op == OpPhi && v.Block != w.Block { + return lt2Cmp(v.Block.ID < w.Block.ID) + } + + if tc := v.Type.Compare(w.Type); tc != CMPeq { + return tc + } + + if v.Aux != w.Aux { + if v.Aux == nil { + return CMPlt + } + if w.Aux == nil { + return CMPgt + } + return lt2Cmp(auxIDs[v.Aux] < auxIDs[w.Aux]) + } + + if depth > 0 { + for i := range v.Args { + if v.Args[i] == w.Args[i] { + // skip comparing equal args + continue + } + if ac := cmpVal(v.Args[i], w.Args[i], auxIDs, depth-1); ac != CMPeq { + return ac + } + } + } + + return CMPeq +} + +// Sort values to make the initial partition. +type sortvalues struct { + a []*Value // array of values + auxIDs auxmap // aux -> aux ID map +} + +func (sv sortvalues) Len() int { return len(sv.a) } +func (sv sortvalues) Swap(i, j int) { sv.a[i], sv.a[j] = sv.a[j], sv.a[i] } +func (sv sortvalues) Less(i, j int) bool { + v := sv.a[i] + w := sv.a[j] + if cmp := cmpVal(v, w, sv.auxIDs, cmpDepth); cmp != CMPeq { + return cmp == CMPlt + } + + // Sort by value ID last to keep the sort result deterministic. + return v.ID < w.ID +} diff --git a/src/cmd/compile/internal/ssa/cse_test.go b/src/cmd/compile/internal/ssa/cse_test.go new file mode 100644 index 0000000000..905939fc32 --- /dev/null +++ b/src/cmd/compile/internal/ssa/cse_test.go @@ -0,0 +1,123 @@ +// Copyright 2016 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import "testing" + +type tstAux struct { + s string +} + +// This tests for a bug found when partitioning, but not sorting by the Aux value. +func TestCSEAuxPartitionBug(t *testing.T) { + c := testConfig(t) + arg1Aux := &tstAux{"arg1-aux"} + arg2Aux := &tstAux{"arg2-aux"} + arg3Aux := &tstAux{"arg3-aux"} + + // construct lots of values with args that have aux values and place + // them in an order that triggers the bug + fun := Fun(c, "entry", + Bloc("entry", + Valu("start", OpInitMem, TypeMem, 0, nil), + Valu("sp", OpSP, TypeBytePtr, 0, nil), + Valu("r7", OpAdd64, TypeInt64, 0, nil, "arg3", "arg1"), + Valu("r1", OpAdd64, TypeInt64, 0, nil, "arg1", "arg2"), + Valu("arg1", OpArg, TypeInt64, 0, arg1Aux), + Valu("arg2", OpArg, TypeInt64, 0, arg2Aux), + Valu("arg3", OpArg, TypeInt64, 0, arg3Aux), + Valu("r9", OpAdd64, TypeInt64, 0, nil, "r7", "r8"), + Valu("r4", OpAdd64, TypeInt64, 0, nil, "r1", "r2"), + Valu("r8", OpAdd64, TypeInt64, 0, nil, "arg3", "arg2"), + Valu("r2", OpAdd64, TypeInt64, 0, nil, "arg1", "arg2"), + Valu("raddr", OpAddr, TypeInt64Ptr, 0, nil, "sp"), + Valu("raddrdef", OpVarDef, TypeMem, 0, nil, "start"), + Valu("r6", OpAdd64, TypeInt64, 0, nil, "r4", "r5"), + Valu("r3", OpAdd64, TypeInt64, 0, nil, "arg1", "arg2"), + Valu("r5", OpAdd64, TypeInt64, 0, nil, "r2", "r3"), + Valu("r10", OpAdd64, TypeInt64, 0, nil, "r6", "r9"), + Valu("rstore", OpStore, TypeMem, 8, nil, "raddr", "r10", "raddrdef"), + Goto("exit")), + Bloc("exit", + Exit("rstore"))) + + CheckFunc(fun.f) + cse(fun.f) + deadcode(fun.f) + CheckFunc(fun.f) + + s1Cnt := 2 + // r1 == r2 == r3, needs to remove two of this set + s2Cnt := 1 + // r4 == r5, needs to remove one of these + for k, v := range fun.values { + if v.Op == OpInvalid { + switch k { + case "r1": + fallthrough + case "r2": + fallthrough + case "r3": + if s1Cnt == 0 { + t.Errorf("cse removed all of r1,r2,r3") + } + s1Cnt-- + + case "r4": + fallthrough + case "r5": + if s2Cnt == 0 { + t.Errorf("cse removed all of r4,r5") + } + s2Cnt-- + default: + t.Errorf("cse removed %s, but shouldn't have", k) + } + } + } + + if s1Cnt != 0 || s2Cnt != 0 { + t.Errorf("%d values missed during cse", s1Cnt+s2Cnt) + } +} + +// TestZCSE tests the zero arg cse. +func TestZCSE(t *testing.T) { + c := testConfig(t) + + fun := Fun(c, "entry", + Bloc("entry", + Valu("start", OpInitMem, TypeMem, 0, nil), + Valu("sp", OpSP, TypeBytePtr, 0, nil), + Valu("sb1", OpSB, TypeBytePtr, 0, nil), + Valu("sb2", OpSB, TypeBytePtr, 0, nil), + Valu("addr1", OpAddr, TypeInt64Ptr, 0, nil, "sb1"), + Valu("addr2", OpAddr, TypeInt64Ptr, 0, nil, "sb2"), + Valu("a1ld", OpLoad, TypeInt64, 0, nil, "addr1", "start"), + Valu("a2ld", OpLoad, TypeInt64, 0, nil, "addr2", "start"), + Valu("c1", OpConst64, TypeInt64, 1, nil), + Valu("r1", OpAdd64, TypeInt64, 0, nil, "a1ld", "c1"), + Valu("c2", OpConst64, TypeInt64, 1, nil), + Valu("r2", OpAdd64, TypeInt64, 0, nil, "a2ld", "c2"), + Valu("r3", OpAdd64, TypeInt64, 0, nil, "r1", "r2"), + Valu("raddr", OpAddr, TypeInt64Ptr, 0, nil, "sp"), + Valu("raddrdef", OpVarDef, TypeMem, 0, nil, "start"), + Valu("rstore", OpStore, TypeMem, 8, nil, "raddr", "r3", "raddrdef"), + Goto("exit")), + Bloc("exit", + Exit("rstore"))) + + CheckFunc(fun.f) + zcse(fun.f) + deadcode(fun.f) + CheckFunc(fun.f) + + if fun.values["c1"].Op != OpInvalid && fun.values["c2"].Op != OpInvalid { + t.Errorf("zsce should have removed c1 or c2") + } + if fun.values["sb1"].Op != OpInvalid && fun.values["sb2"].Op != OpInvalid { + t.Errorf("zsce should have removed sb1 or sb2") + } +} diff --git a/src/cmd/compile/internal/ssa/deadcode.go b/src/cmd/compile/internal/ssa/deadcode.go new file mode 100644 index 0000000000..a33de438e2 --- /dev/null +++ b/src/cmd/compile/internal/ssa/deadcode.go @@ -0,0 +1,270 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +// findlive returns the reachable blocks and live values in f. +func findlive(f *Func) (reachable []bool, live []bool) { + reachable = reachableBlocks(f) + live = liveValues(f, reachable) + return +} + +// reachableBlocks returns the reachable blocks in f. +func reachableBlocks(f *Func) []bool { + reachable := make([]bool, f.NumBlocks()) + reachable[f.Entry.ID] = true + p := []*Block{f.Entry} // stack-like worklist + for len(p) > 0 { + // Pop a reachable block + b := p[len(p)-1] + p = p[:len(p)-1] + // Mark successors as reachable + s := b.Succs + if b.Kind == BlockFirst { + s = s[:1] + } + for _, c := range s { + if !reachable[c.ID] { + reachable[c.ID] = true + p = append(p, c) // push + } + } + } + return reachable +} + +// liveValues returns the live values in f. +// reachable is a map from block ID to whether the block is reachable. +func liveValues(f *Func, reachable []bool) []bool { + live := make([]bool, f.NumValues()) + + // After regalloc, consider all values to be live. + // See the comment at the top of regalloc.go and in deadcode for details. + if f.RegAlloc != nil { + for i := range live { + live[i] = true + } + return live + } + + // Find all live values + var q []*Value // stack-like worklist of unscanned values + + // Starting set: all control values of reachable blocks are live. + for _, b := range f.Blocks { + if !reachable[b.ID] { + continue + } + if v := b.Control; v != nil && !live[v.ID] { + live[v.ID] = true + q = append(q, v) + } + } + + // Compute transitive closure of live values. + for len(q) > 0 { + // pop a reachable value + v := q[len(q)-1] + q = q[:len(q)-1] + for i, x := range v.Args { + if v.Op == OpPhi && !reachable[v.Block.Preds[i].ID] { + continue + } + if !live[x.ID] { + live[x.ID] = true + q = append(q, x) // push + } + } + } + + return live +} + +// deadcode removes dead code from f. +func deadcode(f *Func) { + // deadcode after regalloc is forbidden for now. Regalloc + // doesn't quite generate legal SSA which will lead to some + // required moves being eliminated. See the comment at the + // top of regalloc.go for details. + if f.RegAlloc != nil { + f.Fatalf("deadcode after regalloc") + } + + // Find reachable blocks. + reachable := reachableBlocks(f) + + // Get rid of edges from dead to live code. + for _, b := range f.Blocks { + if reachable[b.ID] { + continue + } + for _, c := range b.Succs { + if reachable[c.ID] { + c.removePred(b) + } + } + } + + // Get rid of dead edges from live code. + for _, b := range f.Blocks { + if !reachable[b.ID] { + continue + } + if b.Kind != BlockFirst { + continue + } + c := b.Succs[1] + b.Succs[1] = nil + b.Succs = b.Succs[:1] + b.Kind = BlockPlain + b.Likely = BranchUnknown + + if reachable[c.ID] { + // Note: c must be reachable through some other edge. + c.removePred(b) + } + } + + // Splice out any copies introduced during dead block removal. + copyelim(f) + + // Find live values. + live := liveValues(f, reachable) + + // Remove dead & duplicate entries from namedValues map. + s := f.newSparseSet(f.NumValues()) + defer f.retSparseSet(s) + i := 0 + for _, name := range f.Names { + j := 0 + s.clear() + values := f.NamedValues[name] + for _, v := range values { + if live[v.ID] && !s.contains(v.ID) { + values[j] = v + j++ + s.add(v.ID) + } + } + if j == 0 { + delete(f.NamedValues, name) + } else { + f.Names[i] = name + i++ + for k := len(values) - 1; k >= j; k-- { + values[k] = nil + } + f.NamedValues[name] = values[:j] + } + } + for k := len(f.Names) - 1; k >= i; k-- { + f.Names[k] = LocalSlot{} + } + f.Names = f.Names[:i] + + // Remove dead values from blocks' value list. Return dead + // values to the allocator. + for _, b := range f.Blocks { + i := 0 + for _, v := range b.Values { + if live[v.ID] { + b.Values[i] = v + i++ + } else { + f.freeValue(v) + } + } + // aid GC + tail := b.Values[i:] + for j := range tail { + tail[j] = nil + } + b.Values = b.Values[:i] + } + + // Remove unreachable blocks. Return dead blocks to allocator. + i = 0 + for _, b := range f.Blocks { + if reachable[b.ID] { + f.Blocks[i] = b + i++ + } else { + if len(b.Values) > 0 { + b.Fatalf("live values in unreachable block %v: %v", b, b.Values) + } + f.freeBlock(b) + } + } + // zero remainder to help GC + tail := f.Blocks[i:] + for j := range tail { + tail[j] = nil + } + f.Blocks = f.Blocks[:i] +} + +// removePred removes the predecessor p from b's predecessor list. +func (b *Block) removePred(p *Block) { + var i int + found := false + for j, q := range b.Preds { + if q == p { + i = j + found = true + break + } + } + // TODO: the above loop could make the deadcode pass take quadratic time + if !found { + b.Fatalf("can't find predecessor %v of %v\n", p, b) + } + + n := len(b.Preds) - 1 + b.Preds[i] = b.Preds[n] + b.Preds[n] = nil // aid GC + b.Preds = b.Preds[:n] + + // rewrite phi ops to match the new predecessor list + for _, v := range b.Values { + if v.Op != OpPhi { + continue + } + v.Args[i] = v.Args[n] + v.Args[n] = nil // aid GC + v.Args = v.Args[:n] + phielimValue(v) + // Note: this is trickier than it looks. Replacing + // a Phi with a Copy can in general cause problems because + // Phi and Copy don't have exactly the same semantics. + // Phi arguments always come from a predecessor block, + // whereas copies don't. This matters in loops like: + // 1: x = (Phi y) + // y = (Add x 1) + // goto 1 + // If we replace Phi->Copy, we get + // 1: x = (Copy y) + // y = (Add x 1) + // goto 1 + // (Phi y) refers to the *previous* value of y, whereas + // (Copy y) refers to the *current* value of y. + // The modified code has a cycle and the scheduler + // will barf on it. + // + // Fortunately, this situation can only happen for dead + // code loops. We know the code we're working with is + // not dead, so we're ok. + // Proof: If we have a potential bad cycle, we have a + // situation like this: + // x = (Phi z) + // y = (op1 x ...) + // z = (op2 y ...) + // Where opX are not Phi ops. But such a situation + // implies a cycle in the dominator graph. In the + // example, x.Block dominates y.Block, y.Block dominates + // z.Block, and z.Block dominates x.Block (treating + // "dominates" as reflexive). Cycles in the dominator + // graph can only happen in an unreachable cycle. + } +} diff --git a/src/cmd/compile/internal/ssa/deadcode_test.go b/src/cmd/compile/internal/ssa/deadcode_test.go new file mode 100644 index 0000000000..24934d5ac4 --- /dev/null +++ b/src/cmd/compile/internal/ssa/deadcode_test.go @@ -0,0 +1,134 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import "testing" + +func TestDeadLoop(t *testing.T) { + c := testConfig(t) + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Goto("exit")), + Bloc("exit", + Exit("mem")), + // dead loop + Bloc("deadblock", + // dead value in dead block + Valu("deadval", OpConstBool, TypeBool, 1, nil), + If("deadval", "deadblock", "exit"))) + + CheckFunc(fun.f) + Deadcode(fun.f) + CheckFunc(fun.f) + + for _, b := range fun.f.Blocks { + if b == fun.blocks["deadblock"] { + t.Errorf("dead block not removed") + } + for _, v := range b.Values { + if v == fun.values["deadval"] { + t.Errorf("control value of dead block not removed") + } + } + } +} + +func TestDeadValue(t *testing.T) { + c := testConfig(t) + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("deadval", OpConst64, TypeInt64, 37, nil), + Goto("exit")), + Bloc("exit", + Exit("mem"))) + + CheckFunc(fun.f) + Deadcode(fun.f) + CheckFunc(fun.f) + + for _, b := range fun.f.Blocks { + for _, v := range b.Values { + if v == fun.values["deadval"] { + t.Errorf("dead value not removed") + } + } + } +} + +func TestNeverTaken(t *testing.T) { + c := testConfig(t) + fun := Fun(c, "entry", + Bloc("entry", + Valu("cond", OpConstBool, TypeBool, 0, nil), + Valu("mem", OpInitMem, TypeMem, 0, nil), + If("cond", "then", "else")), + Bloc("then", + Goto("exit")), + Bloc("else", + Goto("exit")), + Bloc("exit", + Exit("mem"))) + + CheckFunc(fun.f) + Opt(fun.f) + Deadcode(fun.f) + CheckFunc(fun.f) + + if fun.blocks["entry"].Kind != BlockPlain { + t.Errorf("if(false) not simplified") + } + for _, b := range fun.f.Blocks { + if b == fun.blocks["then"] { + t.Errorf("then block still present") + } + for _, v := range b.Values { + if v == fun.values["cond"] { + t.Errorf("constant condition still present") + } + } + } + +} + +func TestNestedDeadBlocks(t *testing.T) { + c := testConfig(t) + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("cond", OpConstBool, TypeBool, 0, nil), + If("cond", "b2", "b4")), + Bloc("b2", + If("cond", "b3", "b4")), + Bloc("b3", + If("cond", "b3", "b4")), + Bloc("b4", + If("cond", "b3", "exit")), + Bloc("exit", + Exit("mem"))) + + CheckFunc(fun.f) + Opt(fun.f) + CheckFunc(fun.f) + Deadcode(fun.f) + CheckFunc(fun.f) + if fun.blocks["entry"].Kind != BlockPlain { + t.Errorf("if(false) not simplified") + } + for _, b := range fun.f.Blocks { + if b == fun.blocks["b2"] { + t.Errorf("b2 block still present") + } + if b == fun.blocks["b3"] { + t.Errorf("b3 block still present") + } + for _, v := range b.Values { + if v == fun.values["cond"] { + t.Errorf("constant condition still present") + } + } + } +} diff --git a/src/cmd/compile/internal/ssa/deadstore.go b/src/cmd/compile/internal/ssa/deadstore.go new file mode 100644 index 0000000000..bad0e0096f --- /dev/null +++ b/src/cmd/compile/internal/ssa/deadstore.go @@ -0,0 +1,116 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +// dse does dead-store elimination on the Function. +// Dead stores are those which are unconditionally followed by +// another store to the same location, with no intervening load. +// This implementation only works within a basic block. TODO: use something more global. +func dse(f *Func) { + var stores []*Value + loadUse := f.newSparseSet(f.NumValues()) + defer f.retSparseSet(loadUse) + storeUse := f.newSparseSet(f.NumValues()) + defer f.retSparseSet(storeUse) + shadowed := f.newSparseSet(f.NumValues()) + defer f.retSparseSet(shadowed) + for _, b := range f.Blocks { + // Find all the stores in this block. Categorize their uses: + // loadUse contains stores which are used by a subsequent load. + // storeUse contains stores which are used by a subsequent store. + loadUse.clear() + storeUse.clear() + stores = stores[:0] + for _, v := range b.Values { + if v.Op == OpPhi { + // Ignore phis - they will always be first and can't be eliminated + continue + } + if v.Type.IsMemory() { + stores = append(stores, v) + for _, a := range v.Args { + if a.Block == b && a.Type.IsMemory() { + storeUse.add(a.ID) + if v.Op != OpStore && v.Op != OpZero && v.Op != OpVarDef && v.Op != OpVarKill { + // CALL, DUFFCOPY, etc. are both + // reads and writes. + loadUse.add(a.ID) + } + } + } + } else { + for _, a := range v.Args { + if a.Block == b && a.Type.IsMemory() { + loadUse.add(a.ID) + } + } + } + } + if len(stores) == 0 { + continue + } + + // find last store in the block + var last *Value + for _, v := range stores { + if storeUse.contains(v.ID) { + continue + } + if last != nil { + b.Fatalf("two final stores - simultaneous live stores %s %s", last, v) + } + last = v + } + if last == nil { + b.Fatalf("no last store found - cycle?") + } + + // Walk backwards looking for dead stores. Keep track of shadowed addresses. + // An "address" is an SSA Value which encodes both the address and size of + // the write. This code will not remove dead stores to the same address + // of different types. + shadowed.clear() + v := last + + walkloop: + if loadUse.contains(v.ID) { + // Someone might be reading this memory state. + // Clear all shadowed addresses. + shadowed.clear() + } + if v.Op == OpStore || v.Op == OpZero { + if shadowed.contains(v.Args[0].ID) { + // Modify store into a copy + if v.Op == OpStore { + // store addr value mem + v.SetArgs1(v.Args[2]) + } else { + // zero addr mem + sz := v.Args[0].Type.Elem().Size() + if v.AuxInt != sz { + f.Fatalf("mismatched zero/store sizes: %d and %d [%s]", + v.AuxInt, sz, v.LongString()) + } + v.SetArgs1(v.Args[1]) + } + v.Aux = nil + v.AuxInt = 0 + v.Op = OpCopy + } else { + shadowed.add(v.Args[0].ID) + } + } + // walk to previous store + if v.Op == OpPhi { + continue // At start of block. Move on to next block. + } + for _, a := range v.Args { + if a.Block == b && a.Type.IsMemory() { + v = a + goto walkloop + } + } + } +} diff --git a/src/cmd/compile/internal/ssa/deadstore_test.go b/src/cmd/compile/internal/ssa/deadstore_test.go new file mode 100644 index 0000000000..9ded8bd6e6 --- /dev/null +++ b/src/cmd/compile/internal/ssa/deadstore_test.go @@ -0,0 +1,97 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import "testing" + +func TestDeadStore(t *testing.T) { + c := testConfig(t) + elemType := &TypeImpl{Size_: 8, Name: "testtype"} + ptrType := &TypeImpl{Size_: 8, Ptr: true, Name: "testptr", Elem_: elemType} // dummy for testing + fun := Fun(c, "entry", + Bloc("entry", + Valu("start", OpInitMem, TypeMem, 0, nil), + Valu("sb", OpSB, TypeInvalid, 0, nil), + Valu("v", OpConstBool, TypeBool, 1, nil), + Valu("addr1", OpAddr, ptrType, 0, nil, "sb"), + Valu("addr2", OpAddr, ptrType, 0, nil, "sb"), + Valu("addr3", OpAddr, ptrType, 0, nil, "sb"), + Valu("zero1", OpZero, TypeMem, 8, nil, "addr3", "start"), + Valu("store1", OpStore, TypeMem, 1, nil, "addr1", "v", "zero1"), + Valu("store2", OpStore, TypeMem, 1, nil, "addr2", "v", "store1"), + Valu("store3", OpStore, TypeMem, 1, nil, "addr1", "v", "store2"), + Valu("store4", OpStore, TypeMem, 1, nil, "addr3", "v", "store3"), + Goto("exit")), + Bloc("exit", + Exit("store3"))) + + CheckFunc(fun.f) + dse(fun.f) + CheckFunc(fun.f) + + v1 := fun.values["store1"] + if v1.Op != OpCopy { + t.Errorf("dead store not removed") + } + + v2 := fun.values["zero1"] + if v2.Op != OpCopy { + t.Errorf("dead store (zero) not removed") + } +} +func TestDeadStorePhi(t *testing.T) { + // make sure we don't get into an infinite loop with phi values. + c := testConfig(t) + ptrType := &TypeImpl{Size_: 8, Ptr: true, Name: "testptr"} // dummy for testing + fun := Fun(c, "entry", + Bloc("entry", + Valu("start", OpInitMem, TypeMem, 0, nil), + Valu("sb", OpSB, TypeInvalid, 0, nil), + Valu("v", OpConstBool, TypeBool, 1, nil), + Valu("addr", OpAddr, ptrType, 0, nil, "sb"), + Goto("loop")), + Bloc("loop", + Valu("phi", OpPhi, TypeMem, 0, nil, "start", "store"), + Valu("store", OpStore, TypeMem, 1, nil, "addr", "v", "phi"), + If("v", "loop", "exit")), + Bloc("exit", + Exit("store"))) + + CheckFunc(fun.f) + dse(fun.f) + CheckFunc(fun.f) +} + +func TestDeadStoreTypes(t *testing.T) { + // Make sure a narrow store can't shadow a wider one. We test an even + // stronger restriction, that one store can't shadow another unless the + // types of the address fields are identical (where identicalness is + // decided by the CSE pass). + c := testConfig(t) + t1 := &TypeImpl{Size_: 8, Ptr: true, Name: "t1"} + t2 := &TypeImpl{Size_: 4, Ptr: true, Name: "t2"} + fun := Fun(c, "entry", + Bloc("entry", + Valu("start", OpInitMem, TypeMem, 0, nil), + Valu("sb", OpSB, TypeInvalid, 0, nil), + Valu("v", OpConstBool, TypeBool, 1, nil), + Valu("addr1", OpAddr, t1, 0, nil, "sb"), + Valu("addr2", OpAddr, t2, 0, nil, "sb"), + Valu("store1", OpStore, TypeMem, 1, nil, "addr1", "v", "start"), + Valu("store2", OpStore, TypeMem, 1, nil, "addr2", "v", "store1"), + Goto("exit")), + Bloc("exit", + Exit("store2"))) + + CheckFunc(fun.f) + cse(fun.f) + dse(fun.f) + CheckFunc(fun.f) + + v := fun.values["store1"] + if v.Op == OpCopy { + t.Errorf("store %s incorrectly removed", v) + } +} diff --git a/src/cmd/compile/internal/ssa/decompose.go b/src/cmd/compile/internal/ssa/decompose.go new file mode 100644 index 0000000000..826eff1ee0 --- /dev/null +++ b/src/cmd/compile/internal/ssa/decompose.go @@ -0,0 +1,261 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +// decompose converts phi ops on compound builtin types into phi +// ops on simple types. +// (The remaining compound ops are decomposed with rewrite rules.) +func decomposeBuiltIn(f *Func) { + for _, b := range f.Blocks { + for _, v := range b.Values { + if v.Op != OpPhi { + continue + } + decomposeBuiltInPhi(v) + } + } + + // Split up named values into their components. + // NOTE: the component values we are making are dead at this point. + // We must do the opt pass before any deadcode elimination or we will + // lose the name->value correspondence. + for _, name := range f.Names { + t := name.Type + switch { + case t.IsComplex(): + var elemType Type + if t.Size() == 16 { + elemType = f.Config.fe.TypeFloat64() + } else { + elemType = f.Config.fe.TypeFloat32() + } + rName := LocalSlot{name.N, elemType, name.Off} + iName := LocalSlot{name.N, elemType, name.Off + elemType.Size()} + f.Names = append(f.Names, rName, iName) + for _, v := range f.NamedValues[name] { + r := v.Block.NewValue1(v.Line, OpComplexReal, elemType, v) + i := v.Block.NewValue1(v.Line, OpComplexImag, elemType, v) + f.NamedValues[rName] = append(f.NamedValues[rName], r) + f.NamedValues[iName] = append(f.NamedValues[iName], i) + } + case t.IsString(): + ptrType := f.Config.fe.TypeBytePtr() + lenType := f.Config.fe.TypeInt() + ptrName := LocalSlot{name.N, ptrType, name.Off} + lenName := LocalSlot{name.N, lenType, name.Off + f.Config.PtrSize} + f.Names = append(f.Names, ptrName, lenName) + for _, v := range f.NamedValues[name] { + ptr := v.Block.NewValue1(v.Line, OpStringPtr, ptrType, v) + len := v.Block.NewValue1(v.Line, OpStringLen, lenType, v) + f.NamedValues[ptrName] = append(f.NamedValues[ptrName], ptr) + f.NamedValues[lenName] = append(f.NamedValues[lenName], len) + } + case t.IsSlice(): + ptrType := f.Config.fe.TypeBytePtr() + lenType := f.Config.fe.TypeInt() + ptrName := LocalSlot{name.N, ptrType, name.Off} + lenName := LocalSlot{name.N, lenType, name.Off + f.Config.PtrSize} + capName := LocalSlot{name.N, lenType, name.Off + 2*f.Config.PtrSize} + f.Names = append(f.Names, ptrName, lenName, capName) + for _, v := range f.NamedValues[name] { + ptr := v.Block.NewValue1(v.Line, OpSlicePtr, ptrType, v) + len := v.Block.NewValue1(v.Line, OpSliceLen, lenType, v) + cap := v.Block.NewValue1(v.Line, OpSliceCap, lenType, v) + f.NamedValues[ptrName] = append(f.NamedValues[ptrName], ptr) + f.NamedValues[lenName] = append(f.NamedValues[lenName], len) + f.NamedValues[capName] = append(f.NamedValues[capName], cap) + } + case t.IsInterface(): + ptrType := f.Config.fe.TypeBytePtr() + typeName := LocalSlot{name.N, ptrType, name.Off} + dataName := LocalSlot{name.N, ptrType, name.Off + f.Config.PtrSize} + f.Names = append(f.Names, typeName, dataName) + for _, v := range f.NamedValues[name] { + typ := v.Block.NewValue1(v.Line, OpITab, ptrType, v) + data := v.Block.NewValue1(v.Line, OpIData, ptrType, v) + f.NamedValues[typeName] = append(f.NamedValues[typeName], typ) + f.NamedValues[dataName] = append(f.NamedValues[dataName], data) + } + case t.Size() > f.Config.IntSize: + f.Unimplementedf("undecomposed named type %s", t) + } + } +} + +func decomposeBuiltInPhi(v *Value) { + // TODO: decompose 64-bit ops on 32-bit archs? + switch { + case v.Type.IsComplex(): + decomposeComplexPhi(v) + case v.Type.IsString(): + decomposeStringPhi(v) + case v.Type.IsSlice(): + decomposeSlicePhi(v) + case v.Type.IsInterface(): + decomposeInterfacePhi(v) + case v.Type.Size() > v.Block.Func.Config.IntSize: + v.Unimplementedf("undecomposed type %s", v.Type) + } +} + +func decomposeStringPhi(v *Value) { + fe := v.Block.Func.Config.fe + ptrType := fe.TypeBytePtr() + lenType := fe.TypeInt() + + ptr := v.Block.NewValue0(v.Line, OpPhi, ptrType) + len := v.Block.NewValue0(v.Line, OpPhi, lenType) + for _, a := range v.Args { + ptr.AddArg(a.Block.NewValue1(v.Line, OpStringPtr, ptrType, a)) + len.AddArg(a.Block.NewValue1(v.Line, OpStringLen, lenType, a)) + } + v.reset(OpStringMake) + v.AddArg(ptr) + v.AddArg(len) +} + +func decomposeSlicePhi(v *Value) { + fe := v.Block.Func.Config.fe + ptrType := fe.TypeBytePtr() + lenType := fe.TypeInt() + + ptr := v.Block.NewValue0(v.Line, OpPhi, ptrType) + len := v.Block.NewValue0(v.Line, OpPhi, lenType) + cap := v.Block.NewValue0(v.Line, OpPhi, lenType) + for _, a := range v.Args { + ptr.AddArg(a.Block.NewValue1(v.Line, OpSlicePtr, ptrType, a)) + len.AddArg(a.Block.NewValue1(v.Line, OpSliceLen, lenType, a)) + cap.AddArg(a.Block.NewValue1(v.Line, OpSliceCap, lenType, a)) + } + v.reset(OpSliceMake) + v.AddArg(ptr) + v.AddArg(len) + v.AddArg(cap) +} + +func decomposeComplexPhi(v *Value) { + fe := v.Block.Func.Config.fe + var partType Type + switch z := v.Type.Size(); z { + case 8: + partType = fe.TypeFloat32() + case 16: + partType = fe.TypeFloat64() + default: + v.Fatalf("decomposeComplexPhi: bad complex size %d", z) + } + + real := v.Block.NewValue0(v.Line, OpPhi, partType) + imag := v.Block.NewValue0(v.Line, OpPhi, partType) + for _, a := range v.Args { + real.AddArg(a.Block.NewValue1(v.Line, OpComplexReal, partType, a)) + imag.AddArg(a.Block.NewValue1(v.Line, OpComplexImag, partType, a)) + } + v.reset(OpComplexMake) + v.AddArg(real) + v.AddArg(imag) +} + +func decomposeInterfacePhi(v *Value) { + ptrType := v.Block.Func.Config.fe.TypeBytePtr() + + itab := v.Block.NewValue0(v.Line, OpPhi, ptrType) + data := v.Block.NewValue0(v.Line, OpPhi, ptrType) + for _, a := range v.Args { + itab.AddArg(a.Block.NewValue1(v.Line, OpITab, ptrType, a)) + data.AddArg(a.Block.NewValue1(v.Line, OpIData, ptrType, a)) + } + v.reset(OpIMake) + v.AddArg(itab) + v.AddArg(data) +} + +func decomposeUser(f *Func) { + for _, b := range f.Blocks { + for _, v := range b.Values { + if v.Op != OpPhi { + continue + } + decomposeUserPhi(v) + } + } + // Split up named values into their components. + // NOTE: the component values we are making are dead at this point. + // We must do the opt pass before any deadcode elimination or we will + // lose the name->value correspondence. + i := 0 + for _, name := range f.Names { + t := name.Type + switch { + case t.IsStruct(): + n := t.NumFields() + for _, v := range f.NamedValues[name] { + for i := int64(0); i < n; i++ { + fname := LocalSlot{name.N, t.FieldType(i), name.Off + t.FieldOff(i)} // TODO: use actual field name? + x := v.Block.NewValue1I(v.Line, OpStructSelect, t.FieldType(i), i, v) + f.NamedValues[fname] = append(f.NamedValues[fname], x) + } + } + delete(f.NamedValues, name) + default: + f.Names[i] = name + i++ + } + } + f.Names = f.Names[:i] +} + +func decomposeUserPhi(v *Value) { + switch { + case v.Type.IsStruct(): + decomposeStructPhi(v) + } + // TODO: Arrays of length 1? +} + +func decomposeStructPhi(v *Value) { + t := v.Type + n := t.NumFields() + var fields [MaxStruct]*Value + for i := int64(0); i < n; i++ { + fields[i] = v.Block.NewValue0(v.Line, OpPhi, t.FieldType(i)) + } + for _, a := range v.Args { + for i := int64(0); i < n; i++ { + fields[i].AddArg(a.Block.NewValue1I(v.Line, OpStructSelect, t.FieldType(i), i, a)) + } + } + v.reset(StructMakeOp(n)) + v.AddArgs(fields[:n]...) + + // Recursively decompose phis for each field. + for _, f := range fields[:n] { + if f.Type.IsStruct() { + decomposeStructPhi(f) + } + } +} + +// MaxStruct is the maximum number of fields a struct +// can have and still be SSAable. +const MaxStruct = 4 + +// StructMakeOp returns the opcode to construct a struct with the +// given number of fields. +func StructMakeOp(nf int64) Op { + switch nf { + case 0: + return OpStructMake0 + case 1: + return OpStructMake1 + case 2: + return OpStructMake2 + case 3: + return OpStructMake3 + case 4: + return OpStructMake4 + } + panic("too many fields in an SSAable struct") +} diff --git a/src/cmd/compile/internal/ssa/dom.go b/src/cmd/compile/internal/ssa/dom.go new file mode 100644 index 0000000000..2d53b5a957 --- /dev/null +++ b/src/cmd/compile/internal/ssa/dom.go @@ -0,0 +1,367 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +// mark values +const ( + notFound = 0 // block has not been discovered yet + notExplored = 1 // discovered and in queue, outedges not processed yet + explored = 2 // discovered and in queue, outedges processed + done = 3 // all done, in output ordering +) + +// This file contains code to compute the dominator tree +// of a control-flow graph. + +// postorder computes a postorder traversal ordering for the +// basic blocks in f. Unreachable blocks will not appear. +func postorder(f *Func) []*Block { + mark := make([]byte, f.NumBlocks()) + + // result ordering + var order []*Block + + // stack of blocks + var s []*Block + s = append(s, f.Entry) + mark[f.Entry.ID] = notExplored + for len(s) > 0 { + b := s[len(s)-1] + switch mark[b.ID] { + case explored: + // Children have all been visited. Pop & output block. + s = s[:len(s)-1] + mark[b.ID] = done + order = append(order, b) + case notExplored: + // Children have not been visited yet. Mark as explored + // and queue any children we haven't seen yet. + mark[b.ID] = explored + for _, c := range b.Succs { + if mark[c.ID] == notFound { + mark[c.ID] = notExplored + s = append(s, c) + } + } + default: + b.Fatalf("bad stack state %v %d", b, mark[b.ID]) + } + } + return order +} + +type linkedBlocks func(*Block) []*Block + +const nscratchslices = 8 + +// experimentally, functions with 512 or fewer blocks account +// for 75% of memory (size) allocation for dominator computation +// in make.bash. +const minscratchblocks = 512 + +func (cfg *Config) scratchBlocksForDom(maxBlockID int) (a, b, c, d, e, f, g, h []ID) { + tot := maxBlockID * nscratchslices + scratch := cfg.domblockstore + if len(scratch) < tot { + // req = min(1.5*tot, nscratchslices*minscratchblocks) + // 50% padding allows for graph growth in later phases. + req := (tot * 3) >> 1 + if req < nscratchslices*minscratchblocks { + req = nscratchslices * minscratchblocks + } + scratch = make([]ID, req) + cfg.domblockstore = scratch + } else { + // Clear as much of scratch as we will (re)use + scratch = scratch[0:tot] + for i := range scratch { + scratch[i] = 0 + } + } + + a = scratch[0*maxBlockID : 1*maxBlockID] + b = scratch[1*maxBlockID : 2*maxBlockID] + c = scratch[2*maxBlockID : 3*maxBlockID] + d = scratch[3*maxBlockID : 4*maxBlockID] + e = scratch[4*maxBlockID : 5*maxBlockID] + f = scratch[5*maxBlockID : 6*maxBlockID] + g = scratch[6*maxBlockID : 7*maxBlockID] + h = scratch[7*maxBlockID : 8*maxBlockID] + + return +} + +// dfs performs a depth first search over the blocks starting at the set of +// blocks in the entries list (in arbitrary order). dfnum contains a mapping +// from block id to an int indicating the order the block was reached or +// notFound if the block was not reached. order contains a mapping from dfnum +// to block. +func (f *Func) dfs(entries []*Block, succFn linkedBlocks, dfnum, order, parent []ID) (fromID []*Block) { + maxBlockID := entries[0].Func.NumBlocks() + + fromID = make([]*Block, maxBlockID) + + for _, entry := range entries[0].Func.Blocks { + eid := entry.ID + if fromID[eid] != nil { + panic("Colliding entry IDs") + } + fromID[eid] = entry + } + + n := ID(0) + s := make([]*Block, 0, 256) + for _, entry := range entries { + if dfnum[entry.ID] != notFound { + continue // already found from a previous entry + } + s = append(s, entry) + parent[entry.ID] = entry.ID + for len(s) > 0 { + node := s[len(s)-1] + s = s[:len(s)-1] + + n++ + for _, w := range succFn(node) { + // if it has a dfnum, we've already visited it + if dfnum[w.ID] == notFound { + s = append(s, w) + parent[w.ID] = node.ID + dfnum[w.ID] = notExplored + } + } + dfnum[node.ID] = n + order[n] = node.ID + } + } + + return +} + +// dominators computes the dominator tree for f. It returns a slice +// which maps block ID to the immediate dominator of that block. +// Unreachable blocks map to nil. The entry block maps to nil. +func dominators(f *Func) []*Block { + preds := func(b *Block) []*Block { return b.Preds } + succs := func(b *Block) []*Block { return b.Succs } + + //TODO: benchmark and try to find criteria for swapping between + // dominatorsSimple and dominatorsLT + return f.dominatorsLT([]*Block{f.Entry}, preds, succs) +} + +// postDominators computes the post-dominator tree for f. +func postDominators(f *Func) []*Block { + preds := func(b *Block) []*Block { return b.Preds } + succs := func(b *Block) []*Block { return b.Succs } + + if len(f.Blocks) == 0 { + return nil + } + + // find the exit blocks + var exits []*Block + for i := len(f.Blocks) - 1; i >= 0; i-- { + switch f.Blocks[i].Kind { + case BlockExit, BlockRet, BlockRetJmp, BlockCall, BlockCheck: + exits = append(exits, f.Blocks[i]) + break + } + } + + // infinite loop with no exit + if exits == nil { + return make([]*Block, f.NumBlocks()) + } + return f.dominatorsLT(exits, succs, preds) +} + +// dominatorsLt runs Lengauer-Tarjan to compute a dominator tree starting at +// entry and using predFn/succFn to find predecessors/successors to allow +// computing both dominator and post-dominator trees. +func (f *Func) dominatorsLT(entries []*Block, predFn linkedBlocks, succFn linkedBlocks) []*Block { + // Based on Lengauer-Tarjan from Modern Compiler Implementation in C - + // Appel with optimizations from Finding Dominators in Practice - + // Georgiadis + + maxBlockID := entries[0].Func.NumBlocks() + + dfnum, vertex, parent, semi, samedom, ancestor, best, bucket := f.Config.scratchBlocksForDom(maxBlockID) + + // dfnum := make([]ID, maxBlockID) // conceptually int32, but punning for allocation purposes. + // vertex := make([]ID, maxBlockID) + // parent := make([]ID, maxBlockID) + + // semi := make([]ID, maxBlockID) + // samedom := make([]ID, maxBlockID) + // ancestor := make([]ID, maxBlockID) + // best := make([]ID, maxBlockID) + // bucket := make([]ID, maxBlockID) + + // Step 1. Carry out a depth first search of the problem graph. Number + // the vertices from 1 to n as they are reached during the search. + fromID := f.dfs(entries, succFn, dfnum, vertex, parent) + + idom := make([]*Block, maxBlockID) + + // Step 2. Compute the semidominators of all vertices by applying + // Theorem 4. Carry out the computation vertex by vertex in decreasing + // order by number. + for i := maxBlockID - 1; i > 0; i-- { + w := vertex[i] + if w == 0 { + continue + } + + if dfnum[w] == notFound { + // skip unreachable node + continue + } + + // Step 3. Implicitly define the immediate dominator of each + // vertex by applying Corollary 1. (reordered) + for v := bucket[w]; v != 0; v = bucket[v] { + u := eval(v, ancestor, semi, dfnum, best) + if semi[u] == semi[v] { + idom[v] = fromID[w] // true dominator + } else { + samedom[v] = u // v has same dominator as u + } + } + + p := parent[w] + s := p // semidominator + + var sp ID + // calculate the semidominator of w + for _, v := range predFn(fromID[w]) { + if dfnum[v.ID] == notFound { + // skip unreachable predecessor + continue + } + + if dfnum[v.ID] <= dfnum[w] { + sp = v.ID + } else { + sp = semi[eval(v.ID, ancestor, semi, dfnum, best)] + } + + if dfnum[sp] < dfnum[s] { + s = sp + } + } + + // link + ancestor[w] = p + best[w] = w + + semi[w] = s + if semi[s] != parent[s] { + bucket[w] = bucket[s] + bucket[s] = w + } + } + + // Final pass of step 3 + for v := bucket[0]; v != 0; v = bucket[v] { + idom[v] = fromID[bucket[0]] + } + + // Step 4. Explictly define the immediate dominator of each vertex, + // carrying out the computation vertex by vertex in increasing order by + // number. + for i := 1; i < maxBlockID-1; i++ { + w := vertex[i] + if w == 0 { + continue + } + // w has the same dominator as samedom[w] + if samedom[w] != 0 { + idom[w] = idom[samedom[w]] + } + } + return idom +} + +// eval function from LT paper with path compression +func eval(v ID, ancestor []ID, semi []ID, dfnum []ID, best []ID) ID { + a := ancestor[v] + if ancestor[a] != 0 { + bid := eval(a, ancestor, semi, dfnum, best) + ancestor[v] = ancestor[a] + if dfnum[semi[bid]] < dfnum[semi[best[v]]] { + best[v] = bid + } + } + return best[v] +} + +// dominators computes the dominator tree for f. It returns a slice +// which maps block ID to the immediate dominator of that block. +// Unreachable blocks map to nil. The entry block maps to nil. +func dominatorsSimple(f *Func) []*Block { + // A simple algorithm for now + // Cooper, Harvey, Kennedy + idom := make([]*Block, f.NumBlocks()) + + // Compute postorder walk + post := postorder(f) + + // Make map from block id to order index (for intersect call) + postnum := make([]int, f.NumBlocks()) + for i, b := range post { + postnum[b.ID] = i + } + + // Make the entry block a self-loop + idom[f.Entry.ID] = f.Entry + if postnum[f.Entry.ID] != len(post)-1 { + f.Fatalf("entry block %v not last in postorder", f.Entry) + } + + // Compute relaxation of idom entries + for { + changed := false + + for i := len(post) - 2; i >= 0; i-- { + b := post[i] + var d *Block + for _, p := range b.Preds { + if idom[p.ID] == nil { + continue + } + if d == nil { + d = p + continue + } + d = intersect(d, p, postnum, idom) + } + if d != idom[b.ID] { + idom[b.ID] = d + changed = true + } + } + if !changed { + break + } + } + // Set idom of entry block to nil instead of itself. + idom[f.Entry.ID] = nil + return idom +} + +// intersect finds the closest dominator of both b and c. +// It requires a postorder numbering of all the blocks. +func intersect(b, c *Block, postnum []int, idom []*Block) *Block { + // TODO: This loop is O(n^2). See BenchmarkNilCheckDeep*. + for b != c { + if postnum[b.ID] < postnum[c.ID] { + b = idom[b.ID] + } else { + c = idom[c.ID] + } + } + return b +} diff --git a/src/cmd/compile/internal/ssa/dom_test.go b/src/cmd/compile/internal/ssa/dom_test.go new file mode 100644 index 0000000000..0328655b6a --- /dev/null +++ b/src/cmd/compile/internal/ssa/dom_test.go @@ -0,0 +1,422 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import "testing" + +func BenchmarkDominatorsLinear(b *testing.B) { benchmarkDominators(b, 10000, genLinear) } +func BenchmarkDominatorsFwdBack(b *testing.B) { benchmarkDominators(b, 10000, genFwdBack) } +func BenchmarkDominatorsManyPred(b *testing.B) { benchmarkDominators(b, 10000, genManyPred) } +func BenchmarkDominatorsMaxPred(b *testing.B) { benchmarkDominators(b, 10000, genMaxPred) } +func BenchmarkDominatorsMaxPredVal(b *testing.B) { benchmarkDominators(b, 10000, genMaxPredValue) } + +type blockGen func(size int) []bloc + +// genLinear creates an array of blocks that succeed one another +// b_n -> [b_n+1]. +func genLinear(size int) []bloc { + var blocs []bloc + blocs = append(blocs, + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Goto(blockn(0)), + ), + ) + for i := 0; i < size; i++ { + blocs = append(blocs, Bloc(blockn(i), + Goto(blockn(i+1)))) + } + + blocs = append(blocs, + Bloc(blockn(size), Goto("exit")), + Bloc("exit", Exit("mem")), + ) + + return blocs +} + +// genLinear creates an array of blocks that alternate between +// b_n -> [b_n+1], b_n -> [b_n+1, b_n-1] , b_n -> [b_n+1, b_n+2] +func genFwdBack(size int) []bloc { + var blocs []bloc + blocs = append(blocs, + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("p", OpConstBool, TypeBool, 1, nil), + Goto(blockn(0)), + ), + ) + for i := 0; i < size; i++ { + switch i % 2 { + case 0: + blocs = append(blocs, Bloc(blockn(i), + If("p", blockn(i+1), blockn(i+2)))) + case 1: + blocs = append(blocs, Bloc(blockn(i), + If("p", blockn(i+1), blockn(i-1)))) + } + } + + blocs = append(blocs, + Bloc(blockn(size), Goto("exit")), + Bloc("exit", Exit("mem")), + ) + + return blocs +} + +// genManyPred creates an array of blocks where 1/3rd have a sucessor of the +// first block, 1/3rd the last block, and the remaining third are plain. +func genManyPred(size int) []bloc { + var blocs []bloc + blocs = append(blocs, + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("p", OpConstBool, TypeBool, 1, nil), + Goto(blockn(0)), + ), + ) + + // We want predecessor lists to be long, so 2/3rds of the blocks have a + // sucessor of the first or last block. + for i := 0; i < size; i++ { + switch i % 3 { + case 0: + blocs = append(blocs, Bloc(blockn(i), + Valu("a", OpConstBool, TypeBool, 1, nil), + Goto(blockn(i+1)))) + case 1: + blocs = append(blocs, Bloc(blockn(i), + Valu("a", OpConstBool, TypeBool, 1, nil), + If("p", blockn(i+1), blockn(0)))) + case 2: + blocs = append(blocs, Bloc(blockn(i), + Valu("a", OpConstBool, TypeBool, 1, nil), + If("p", blockn(i+1), blockn(size)))) + } + } + + blocs = append(blocs, + Bloc(blockn(size), Goto("exit")), + Bloc("exit", Exit("mem")), + ) + + return blocs +} + +// genMaxPred maximizes the size of the 'exit' predecessor list. +func genMaxPred(size int) []bloc { + var blocs []bloc + blocs = append(blocs, + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("p", OpConstBool, TypeBool, 1, nil), + Goto(blockn(0)), + ), + ) + + for i := 0; i < size; i++ { + blocs = append(blocs, Bloc(blockn(i), + If("p", blockn(i+1), "exit"))) + } + + blocs = append(blocs, + Bloc(blockn(size), Goto("exit")), + Bloc("exit", Exit("mem")), + ) + + return blocs +} + +// genMaxPredValue is identical to genMaxPred but contains an +// additional value. +func genMaxPredValue(size int) []bloc { + var blocs []bloc + blocs = append(blocs, + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("p", OpConstBool, TypeBool, 1, nil), + Goto(blockn(0)), + ), + ) + + for i := 0; i < size; i++ { + blocs = append(blocs, Bloc(blockn(i), + Valu("a", OpConstBool, TypeBool, 1, nil), + If("p", blockn(i+1), "exit"))) + } + + blocs = append(blocs, + Bloc(blockn(size), Goto("exit")), + Bloc("exit", Exit("mem")), + ) + + return blocs +} + +// sink for benchmark +var domBenchRes []*Block + +func benchmarkDominators(b *testing.B, size int, bg blockGen) { + c := NewConfig("amd64", DummyFrontend{b}, nil, true) + fun := Fun(c, "entry", bg(size)...) + + CheckFunc(fun.f) + b.SetBytes(int64(size)) + b.ResetTimer() + for i := 0; i < b.N; i++ { + domBenchRes = dominators(fun.f) + } +} + +type domFunc func(f *Func) []*Block + +// verifyDominators verifies that the dominators of fut (function under test) +// as determined by domFn, match the map node->dominator +func verifyDominators(t *testing.T, fut fun, domFn domFunc, doms map[string]string) { + blockNames := map[*Block]string{} + for n, b := range fut.blocks { + blockNames[b] = n + } + + calcDom := domFn(fut.f) + + for n, d := range doms { + nblk, ok := fut.blocks[n] + if !ok { + t.Errorf("invalid block name %s", n) + } + dblk, ok := fut.blocks[d] + if !ok { + t.Errorf("invalid block name %s", d) + } + + domNode := calcDom[nblk.ID] + switch { + case calcDom[nblk.ID] == dblk: + calcDom[nblk.ID] = nil + continue + case calcDom[nblk.ID] != dblk: + t.Errorf("expected %s as dominator of %s, found %s", d, n, blockNames[domNode]) + default: + t.Fatal("unexpected dominator condition") + } + } + + for id, d := range calcDom { + // If nil, we've already verified it + if d == nil { + continue + } + for _, b := range fut.blocks { + if int(b.ID) == id { + t.Errorf("unexpected dominator of %s for %s", blockNames[d], blockNames[b]) + } + } + } + +} + +func TestDominatorsSingleBlock(t *testing.T) { + c := testConfig(t) + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Exit("mem"))) + + doms := map[string]string{} + + CheckFunc(fun.f) + verifyDominators(t, fun, dominators, doms) + verifyDominators(t, fun, dominatorsSimple, doms) + +} + +func TestDominatorsSimple(t *testing.T) { + c := testConfig(t) + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Goto("a")), + Bloc("a", + Goto("b")), + Bloc("b", + Goto("c")), + Bloc("c", + Goto("exit")), + Bloc("exit", + Exit("mem"))) + + doms := map[string]string{ + "a": "entry", + "b": "a", + "c": "b", + "exit": "c", + } + + CheckFunc(fun.f) + verifyDominators(t, fun, dominators, doms) + verifyDominators(t, fun, dominatorsSimple, doms) + +} + +func TestDominatorsMultPredFwd(t *testing.T) { + c := testConfig(t) + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("p", OpConstBool, TypeBool, 1, nil), + If("p", "a", "c")), + Bloc("a", + If("p", "b", "c")), + Bloc("b", + Goto("c")), + Bloc("c", + Goto("exit")), + Bloc("exit", + Exit("mem"))) + + doms := map[string]string{ + "a": "entry", + "b": "a", + "c": "entry", + "exit": "c", + } + + CheckFunc(fun.f) + verifyDominators(t, fun, dominators, doms) + verifyDominators(t, fun, dominatorsSimple, doms) +} + +func TestDominatorsDeadCode(t *testing.T) { + c := testConfig(t) + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("p", OpConstBool, TypeBool, 0, nil), + If("p", "b3", "b5")), + Bloc("b2", Exit("mem")), + Bloc("b3", Goto("b2")), + Bloc("b4", Goto("b2")), + Bloc("b5", Goto("b2"))) + + doms := map[string]string{ + "b2": "entry", + "b3": "entry", + "b5": "entry", + } + + CheckFunc(fun.f) + verifyDominators(t, fun, dominators, doms) + verifyDominators(t, fun, dominatorsSimple, doms) +} + +func TestDominatorsMultPredRev(t *testing.T) { + c := testConfig(t) + fun := Fun(c, "entry", + Bloc("entry", + Goto("first")), + Bloc("first", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("p", OpConstBool, TypeBool, 1, nil), + Goto("a")), + Bloc("a", + If("p", "b", "first")), + Bloc("b", + Goto("c")), + Bloc("c", + If("p", "exit", "b")), + Bloc("exit", + Exit("mem"))) + + doms := map[string]string{ + "first": "entry", + "a": "first", + "b": "a", + "c": "b", + "exit": "c", + } + + CheckFunc(fun.f) + verifyDominators(t, fun, dominators, doms) + verifyDominators(t, fun, dominatorsSimple, doms) +} + +func TestDominatorsMultPred(t *testing.T) { + c := testConfig(t) + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("p", OpConstBool, TypeBool, 1, nil), + If("p", "a", "c")), + Bloc("a", + If("p", "b", "c")), + Bloc("b", + Goto("c")), + Bloc("c", + If("p", "b", "exit")), + Bloc("exit", + Exit("mem"))) + + doms := map[string]string{ + "a": "entry", + "b": "entry", + "c": "entry", + "exit": "c", + } + + CheckFunc(fun.f) + verifyDominators(t, fun, dominators, doms) + verifyDominators(t, fun, dominatorsSimple, doms) +} + +func TestPostDominators(t *testing.T) { + c := testConfig(t) + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("p", OpConstBool, TypeBool, 1, nil), + If("p", "a", "c")), + Bloc("a", + If("p", "b", "c")), + Bloc("b", + Goto("c")), + Bloc("c", + If("p", "b", "exit")), + Bloc("exit", + Exit("mem"))) + + doms := map[string]string{"entry": "c", + "a": "c", + "b": "c", + "c": "exit", + } + + CheckFunc(fun.f) + verifyDominators(t, fun, postDominators, doms) +} + +func TestInfiniteLoop(t *testing.T) { + c := testConfig(t) + // note lack of an exit block + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("p", OpConstBool, TypeBool, 1, nil), + Goto("a")), + Bloc("a", + Goto("b")), + Bloc("b", + Goto("a"))) + + CheckFunc(fun.f) + doms := map[string]string{"a": "entry", + "b": "a"} + verifyDominators(t, fun, dominators, doms) + + // no exit block, so there are no post-dominators + postDoms := map[string]string{} + verifyDominators(t, fun, postDominators, postDoms) +} diff --git a/src/cmd/compile/internal/ssa/export_test.go b/src/cmd/compile/internal/ssa/export_test.go new file mode 100644 index 0000000000..dae9ed7de0 --- /dev/null +++ b/src/cmd/compile/internal/ssa/export_test.go @@ -0,0 +1,67 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import ( + "cmd/internal/obj" + "testing" +) + +var CheckFunc = checkFunc +var PrintFunc = printFunc +var Opt = opt +var Deadcode = deadcode + +func testConfig(t *testing.T) *Config { + testCtxt := &obj.Link{} + return NewConfig("amd64", DummyFrontend{t}, testCtxt, true) +} + +// DummyFrontend is a test-only frontend. +// It assumes 64 bit integers and pointers. +type DummyFrontend struct { + t testing.TB +} + +func (DummyFrontend) StringData(s string) interface{} { + return nil +} +func (DummyFrontend) Auto(t Type) GCNode { + return nil +} +func (DummyFrontend) Line(line int32) string { + return "unknown.go:0" +} + +func (d DummyFrontend) Logf(msg string, args ...interface{}) { d.t.Logf(msg, args...) } +func (d DummyFrontend) Log() bool { return true } + +func (d DummyFrontend) Fatalf(line int32, msg string, args ...interface{}) { d.t.Fatalf(msg, args...) } +func (d DummyFrontend) Unimplementedf(line int32, msg string, args ...interface{}) { + d.t.Fatalf(msg, args...) +} +func (d DummyFrontend) Warnl(line int, msg string, args ...interface{}) { d.t.Logf(msg, args...) } +func (d DummyFrontend) Debug_checknil() bool { return false } + +func (d DummyFrontend) TypeBool() Type { return TypeBool } +func (d DummyFrontend) TypeInt8() Type { return TypeInt8 } +func (d DummyFrontend) TypeInt16() Type { return TypeInt16 } +func (d DummyFrontend) TypeInt32() Type { return TypeInt32 } +func (d DummyFrontend) TypeInt64() Type { return TypeInt64 } +func (d DummyFrontend) TypeUInt8() Type { return TypeUInt8 } +func (d DummyFrontend) TypeUInt16() Type { return TypeUInt16 } +func (d DummyFrontend) TypeUInt32() Type { return TypeUInt32 } +func (d DummyFrontend) TypeUInt64() Type { return TypeUInt64 } +func (d DummyFrontend) TypeFloat32() Type { return TypeFloat32 } +func (d DummyFrontend) TypeFloat64() Type { return TypeFloat64 } +func (d DummyFrontend) TypeInt() Type { return TypeInt64 } +func (d DummyFrontend) TypeUintptr() Type { return TypeUInt64 } +func (d DummyFrontend) TypeString() Type { panic("unimplemented") } +func (d DummyFrontend) TypeBytePtr() Type { return TypeBytePtr } + +func (d DummyFrontend) CanSSA(t Type) bool { + // There are no un-SSAable types in dummy land. + return true +} diff --git a/src/cmd/compile/internal/ssa/flagalloc.go b/src/cmd/compile/internal/ssa/flagalloc.go new file mode 100644 index 0000000000..7ed1fe5908 --- /dev/null +++ b/src/cmd/compile/internal/ssa/flagalloc.go @@ -0,0 +1,131 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +const flagRegMask = regMask(1) << 33 // TODO: arch-specific + +// flagalloc allocates the flag register among all the flag-generating +// instructions. Flag values are recomputed if they need to be +// spilled/restored. +func flagalloc(f *Func) { + // Compute the in-register flag value we want at the end of + // each block. This is basically a best-effort live variable + // analysis, so it can be much simpler than a full analysis. + // TODO: do we really need to keep flag values live across blocks? + // Could we force the flags register to be unused at basic block + // boundaries? Then we wouldn't need this computation. + end := make([]*Value, f.NumBlocks()) + for n := 0; n < 2; n++ { + // Walk blocks backwards. Poor-man's postorder traversal. + for i := len(f.Blocks) - 1; i >= 0; i-- { + b := f.Blocks[i] + // Walk values backwards to figure out what flag + // value we want in the flag register at the start + // of the block. + flag := end[b.ID] + if b.Control != nil && b.Control.Type.IsFlags() { + flag = b.Control + } + for j := len(b.Values) - 1; j >= 0; j-- { + v := b.Values[j] + if v == flag { + flag = nil + } + if opcodeTable[v.Op].reg.clobbers&flagRegMask != 0 { + flag = nil + } + for _, a := range v.Args { + if a.Type.IsFlags() { + flag = a + } + } + } + if flag != nil { + for _, p := range b.Preds { + end[p.ID] = flag + } + } + } + } + + // For blocks which have a flags control value, that's the only value + // we can leave in the flags register at the end of the block. (There + // is no place to put a flag regeneration instruction.) + for _, b := range f.Blocks { + v := b.Control + if v != nil && v.Type.IsFlags() && end[b.ID] != v { + end[b.ID] = nil + } + } + + // Add flag recomputations where they are needed. + // TODO: Remove original instructions if they are never used. + var oldSched []*Value + for _, b := range f.Blocks { + oldSched = append(oldSched[:0], b.Values...) + b.Values = b.Values[:0] + // The current live flag value the pre-flagalloc copy). + var flag *Value + if len(b.Preds) > 0 { + flag = end[b.Preds[0].ID] + // Note: the following condition depends on the lack of critical edges. + for _, p := range b.Preds[1:] { + if end[p.ID] != flag { + f.Fatalf("live flag in %s's predecessors not consistent", b) + } + } + } + for _, v := range oldSched { + if v.Op == OpPhi && v.Type.IsFlags() { + f.Fatalf("phi of flags not supported: %s", v.LongString()) + } + // Make sure any flag arg of v is in the flags register. + // If not, recompute it. + for i, a := range v.Args { + if !a.Type.IsFlags() { + continue + } + if a == flag { + continue + } + // Recalculate a + c := a.copyInto(b) + // Update v. + v.SetArg(i, c) + // Remember the most-recently computed flag value. + flag = a + } + // Issue v. + b.Values = append(b.Values, v) + if opcodeTable[v.Op].reg.clobbers&flagRegMask != 0 { + flag = nil + } + if v.Type.IsFlags() { + flag = v + } + } + if v := b.Control; v != nil && v != flag && v.Type.IsFlags() { + // Recalculate control value. + c := v.copyInto(b) + b.Control = c + flag = v + } + if v := end[b.ID]; v != nil && v != flag { + // Need to reissue flag generator for use by + // subsequent blocks. + _ = v.copyInto(b) + // Note: this flag generator is not properly linked up + // with the flag users. This breaks the SSA representation. + // We could fix up the users with another pass, but for now + // we'll just leave it. (Regalloc has the same issue for + // standard regs, and it runs next.) + } + } + + // Save live flag state for later. + for _, b := range f.Blocks { + b.FlagsLiveAtEnd = end[b.ID] != nil + } +} diff --git a/src/cmd/compile/internal/ssa/func.go b/src/cmd/compile/internal/ssa/func.go new file mode 100644 index 0000000000..7cc5f6c8d9 --- /dev/null +++ b/src/cmd/compile/internal/ssa/func.go @@ -0,0 +1,352 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import ( + "fmt" + "math" +) + +// A Func represents a Go func declaration (or function literal) and +// its body. This package compiles each Func independently. +type Func struct { + Config *Config // architecture information + pass *pass // current pass information (name, options, etc.) + Name string // e.g. bytes·Compare + Type Type // type signature of the function. + StaticData interface{} // associated static data, untouched by the ssa package + Blocks []*Block // unordered set of all basic blocks (note: not indexable by ID) + Entry *Block // the entry basic block + bid idAlloc // block ID allocator + vid idAlloc // value ID allocator + + scheduled bool // Values in Blocks are in final order + + // when register allocation is done, maps value ids to locations + RegAlloc []Location + + // map from LocalSlot to set of Values that we want to store in that slot. + NamedValues map[LocalSlot][]*Value + // Names is a copy of NamedValues.Keys. We keep a separate list + // of keys to make iteration order deterministic. + Names []LocalSlot + + freeValues *Value // free Values linked by argstorage[0]. All other fields except ID are 0/nil. + freeBlocks *Block // free Blocks linked by succstorage[0]. All other fields except ID are 0/nil. + + constants map[int64][]*Value // constants cache, keyed by constant value; users must check value's Op and Type +} + +// NumBlocks returns an integer larger than the id of any Block in the Func. +func (f *Func) NumBlocks() int { + return f.bid.num() +} + +// NumValues returns an integer larger than the id of any Value in the Func. +func (f *Func) NumValues() int { + return f.vid.num() +} + +// newSparseSet returns a sparse set that can store at least up to n integers. +func (f *Func) newSparseSet(n int) *sparseSet { + for i, scr := range f.Config.scrSparse { + if scr != nil && scr.cap() >= n { + f.Config.scrSparse[i] = nil + scr.clear() + return scr + } + } + return newSparseSet(n) +} + +// retSparseSet returns a sparse set to the config's cache of sparse sets to be reused by f.newSparseSet. +func (f *Func) retSparseSet(ss *sparseSet) { + for i, scr := range f.Config.scrSparse { + if scr == nil { + f.Config.scrSparse[i] = ss + return + } + } + f.Config.scrSparse = append(f.Config.scrSparse, ss) +} + +// newValue allocates a new Value with the given fields and places it at the end of b.Values. +func (f *Func) newValue(op Op, t Type, b *Block, line int32) *Value { + var v *Value + if f.freeValues != nil { + v = f.freeValues + f.freeValues = v.argstorage[0] + v.argstorage[0] = nil + } else { + ID := f.vid.get() + if int(ID) < len(f.Config.values) { + v = &f.Config.values[ID] + } else { + v = &Value{ID: ID} + } + } + v.Op = op + v.Type = t + v.Block = b + v.Line = line + b.Values = append(b.Values, v) + return v +} + +// logPassStat writes a string key and int value as a warning in a +// tab-separated format easily handled by spreadsheets or awk. +// file names, lines, and function names are included to provide enough (?) +// context to allow item-by-item comparisons across runs. +// For example: +// awk 'BEGIN {FS="\t"} $3~/TIME/{sum+=$4} END{print "t(ns)=",sum}' t.log +func (f *Func) logStat(key string, args ...interface{}) { + value := "" + for _, a := range args { + value += fmt.Sprintf("\t%v", a) + } + f.Config.Warnl(int(f.Entry.Line), "\t%s\t%s%s\t%s", f.pass.name, key, value, f.Name) +} + +// freeValue frees a value. It must no longer be referenced. +func (f *Func) freeValue(v *Value) { + if v.Block == nil { + f.Fatalf("trying to free an already freed value") + } + // Clear everything but ID (which we reuse). + id := v.ID + *v = Value{} + v.ID = id + v.argstorage[0] = f.freeValues + f.freeValues = v +} + +// newBlock allocates a new Block of the given kind and places it at the end of f.Blocks. +func (f *Func) NewBlock(kind BlockKind) *Block { + var b *Block + if f.freeBlocks != nil { + b = f.freeBlocks + f.freeBlocks = b.succstorage[0] + b.succstorage[0] = nil + } else { + ID := f.bid.get() + if int(ID) < len(f.Config.blocks) { + b = &f.Config.blocks[ID] + } else { + b = &Block{ID: ID} + } + } + b.Kind = kind + b.Func = f + b.Preds = b.predstorage[:0] + b.Succs = b.succstorage[:0] + b.Values = b.valstorage[:0] + f.Blocks = append(f.Blocks, b) + return b +} + +func (f *Func) freeBlock(b *Block) { + if b.Func == nil { + f.Fatalf("trying to free an already freed block") + } + // Clear everything but ID (which we reuse). + id := b.ID + *b = Block{} + b.ID = id + b.succstorage[0] = f.freeBlocks + f.freeBlocks = b +} + +// NewValue0 returns a new value in the block with no arguments and zero aux values. +func (b *Block) NewValue0(line int32, op Op, t Type) *Value { + v := b.Func.newValue(op, t, b, line) + v.AuxInt = 0 + v.Args = v.argstorage[:0] + return v +} + +// NewValue returns a new value in the block with no arguments and an auxint value. +func (b *Block) NewValue0I(line int32, op Op, t Type, auxint int64) *Value { + v := b.Func.newValue(op, t, b, line) + v.AuxInt = auxint + v.Args = v.argstorage[:0] + return v +} + +// NewValue returns a new value in the block with no arguments and an aux value. +func (b *Block) NewValue0A(line int32, op Op, t Type, aux interface{}) *Value { + if _, ok := aux.(int64); ok { + // Disallow int64 aux values. They should be in the auxint field instead. + // Maybe we want to allow this at some point, but for now we disallow it + // to prevent errors like using NewValue1A instead of NewValue1I. + b.Fatalf("aux field has int64 type op=%s type=%s aux=%v", op, t, aux) + } + v := b.Func.newValue(op, t, b, line) + v.AuxInt = 0 + v.Aux = aux + v.Args = v.argstorage[:0] + return v +} + +// NewValue returns a new value in the block with no arguments and both an auxint and aux values. +func (b *Block) NewValue0IA(line int32, op Op, t Type, auxint int64, aux interface{}) *Value { + v := b.Func.newValue(op, t, b, line) + v.AuxInt = auxint + v.Aux = aux + v.Args = v.argstorage[:0] + return v +} + +// NewValue1 returns a new value in the block with one argument and zero aux values. +func (b *Block) NewValue1(line int32, op Op, t Type, arg *Value) *Value { + v := b.Func.newValue(op, t, b, line) + v.AuxInt = 0 + v.Args = v.argstorage[:1] + v.argstorage[0] = arg + return v +} + +// NewValue1I returns a new value in the block with one argument and an auxint value. +func (b *Block) NewValue1I(line int32, op Op, t Type, auxint int64, arg *Value) *Value { + v := b.Func.newValue(op, t, b, line) + v.AuxInt = auxint + v.Args = v.argstorage[:1] + v.argstorage[0] = arg + return v +} + +// NewValue1A returns a new value in the block with one argument and an aux value. +func (b *Block) NewValue1A(line int32, op Op, t Type, aux interface{}, arg *Value) *Value { + v := b.Func.newValue(op, t, b, line) + v.AuxInt = 0 + v.Aux = aux + v.Args = v.argstorage[:1] + v.argstorage[0] = arg + return v +} + +// NewValue1IA returns a new value in the block with one argument and both an auxint and aux values. +func (b *Block) NewValue1IA(line int32, op Op, t Type, auxint int64, aux interface{}, arg *Value) *Value { + v := b.Func.newValue(op, t, b, line) + v.AuxInt = auxint + v.Aux = aux + v.Args = v.argstorage[:1] + v.argstorage[0] = arg + return v +} + +// NewValue2 returns a new value in the block with two arguments and zero aux values. +func (b *Block) NewValue2(line int32, op Op, t Type, arg0, arg1 *Value) *Value { + v := b.Func.newValue(op, t, b, line) + v.AuxInt = 0 + v.Args = v.argstorage[:2] + v.argstorage[0] = arg0 + v.argstorage[1] = arg1 + return v +} + +// NewValue2I returns a new value in the block with two arguments and an auxint value. +func (b *Block) NewValue2I(line int32, op Op, t Type, auxint int64, arg0, arg1 *Value) *Value { + v := b.Func.newValue(op, t, b, line) + v.AuxInt = auxint + v.Args = v.argstorage[:2] + v.argstorage[0] = arg0 + v.argstorage[1] = arg1 + return v +} + +// NewValue3 returns a new value in the block with three arguments and zero aux values. +func (b *Block) NewValue3(line int32, op Op, t Type, arg0, arg1, arg2 *Value) *Value { + v := b.Func.newValue(op, t, b, line) + v.AuxInt = 0 + v.Args = []*Value{arg0, arg1, arg2} + return v +} + +// NewValue3I returns a new value in the block with three arguments and an auxint value. +func (b *Block) NewValue3I(line int32, op Op, t Type, auxint int64, arg0, arg1, arg2 *Value) *Value { + v := b.Func.newValue(op, t, b, line) + v.AuxInt = auxint + v.Args = []*Value{arg0, arg1, arg2} + return v +} + +// constVal returns a constant value for c. +func (f *Func) constVal(line int32, op Op, t Type, c int64) *Value { + if f.constants == nil { + f.constants = make(map[int64][]*Value) + } + vv := f.constants[c] + for _, v := range vv { + if v.Op == op && v.Type.Equal(t) { + return v + } + } + v := f.Entry.NewValue0I(line, op, t, c) + f.constants[c] = append(vv, v) + return v +} + +// ConstInt returns an int constant representing its argument. +func (f *Func) ConstBool(line int32, t Type, c bool) *Value { + i := int64(0) + if c { + i = 1 + } + return f.constVal(line, OpConstBool, t, i) +} +func (f *Func) ConstInt8(line int32, t Type, c int8) *Value { + return f.constVal(line, OpConst8, t, int64(c)) +} +func (f *Func) ConstInt16(line int32, t Type, c int16) *Value { + return f.constVal(line, OpConst16, t, int64(c)) +} +func (f *Func) ConstInt32(line int32, t Type, c int32) *Value { + return f.constVal(line, OpConst32, t, int64(c)) +} +func (f *Func) ConstInt64(line int32, t Type, c int64) *Value { + return f.constVal(line, OpConst64, t, c) +} +func (f *Func) ConstFloat32(line int32, t Type, c float64) *Value { + return f.constVal(line, OpConst32F, t, int64(math.Float64bits(c))) +} +func (f *Func) ConstFloat64(line int32, t Type, c float64) *Value { + return f.constVal(line, OpConst64F, t, int64(math.Float64bits(c))) +} + +func (f *Func) Logf(msg string, args ...interface{}) { f.Config.Logf(msg, args...) } +func (f *Func) Log() bool { return f.Config.Log() } +func (f *Func) Fatalf(msg string, args ...interface{}) { f.Config.Fatalf(f.Entry.Line, msg, args...) } +func (f *Func) Unimplementedf(msg string, args ...interface{}) { + f.Config.Unimplementedf(f.Entry.Line, msg, args...) +} + +func (f *Func) Free() { + // Clear values. + n := f.vid.num() + if n > len(f.Config.values) { + n = len(f.Config.values) + } + for i := 1; i < n; i++ { + f.Config.values[i] = Value{} + f.Config.values[i].ID = ID(i) + } + + // Clear blocks. + n = f.bid.num() + if n > len(f.Config.blocks) { + n = len(f.Config.blocks) + } + for i := 1; i < n; i++ { + f.Config.blocks[i] = Block{} + f.Config.blocks[i].ID = ID(i) + } + + // Unregister from config. + if f.Config.curFunc != f { + f.Fatalf("free of function which isn't the last one allocated") + } + f.Config.curFunc = nil + *f = Func{} // just in case +} diff --git a/src/cmd/compile/internal/ssa/func_test.go b/src/cmd/compile/internal/ssa/func_test.go new file mode 100644 index 0000000000..fa6a1a8751 --- /dev/null +++ b/src/cmd/compile/internal/ssa/func_test.go @@ -0,0 +1,445 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// This file contains some utility functions to help define Funcs for testing. +// As an example, the following func +// +// b1: +// v1 = InitMem <mem> +// Plain -> b2 +// b2: +// Exit v1 +// b3: +// v2 = Const <bool> [true] +// If v2 -> b3 b2 +// +// can be defined as +// +// fun := Fun("entry", +// Bloc("entry", +// Valu("mem", OpInitMem, TypeMem, 0, nil), +// Goto("exit")), +// Bloc("exit", +// Exit("mem")), +// Bloc("deadblock", +// Valu("deadval", OpConstBool, TypeBool, 0, true), +// If("deadval", "deadblock", "exit"))) +// +// and the Blocks or Values used in the Func can be accessed +// like this: +// fun.blocks["entry"] or fun.values["deadval"] + +package ssa + +// TODO(matloob): Choose better names for Fun, Bloc, Goto, etc. +// TODO(matloob): Write a parser for the Func disassembly. Maybe +// the parser can be used instead of Fun. + +import ( + "fmt" + "reflect" + "testing" +) + +// Compare two Funcs for equivalence. Their CFGs must be isomorphic, +// and their values must correspond. +// Requires that values and predecessors are in the same order, even +// though Funcs could be equivalent when they are not. +// TODO(matloob): Allow values and predecessors to be in different +// orders if the CFG are otherwise equivalent. +func Equiv(f, g *Func) bool { + valcor := make(map[*Value]*Value) + var checkVal func(fv, gv *Value) bool + checkVal = func(fv, gv *Value) bool { + if fv == nil && gv == nil { + return true + } + if valcor[fv] == nil && valcor[gv] == nil { + valcor[fv] = gv + valcor[gv] = fv + // Ignore ids. Ops and Types are compared for equality. + // TODO(matloob): Make sure types are canonical and can + // be compared for equality. + if fv.Op != gv.Op || fv.Type != gv.Type || fv.AuxInt != gv.AuxInt { + return false + } + if !reflect.DeepEqual(fv.Aux, gv.Aux) { + // This makes the assumption that aux values can be compared + // using DeepEqual. + // TODO(matloob): Aux values may be *gc.Sym pointers in the near + // future. Make sure they are canonical. + return false + } + if len(fv.Args) != len(gv.Args) { + return false + } + for i := range fv.Args { + if !checkVal(fv.Args[i], gv.Args[i]) { + return false + } + } + } + return valcor[fv] == gv && valcor[gv] == fv + } + blkcor := make(map[*Block]*Block) + var checkBlk func(fb, gb *Block) bool + checkBlk = func(fb, gb *Block) bool { + if blkcor[fb] == nil && blkcor[gb] == nil { + blkcor[fb] = gb + blkcor[gb] = fb + // ignore ids + if fb.Kind != gb.Kind { + return false + } + if len(fb.Values) != len(gb.Values) { + return false + } + for i := range fb.Values { + if !checkVal(fb.Values[i], gb.Values[i]) { + return false + } + } + if len(fb.Succs) != len(gb.Succs) { + return false + } + for i := range fb.Succs { + if !checkBlk(fb.Succs[i], gb.Succs[i]) { + return false + } + } + if len(fb.Preds) != len(gb.Preds) { + return false + } + for i := range fb.Preds { + if !checkBlk(fb.Preds[i], gb.Preds[i]) { + return false + } + } + return true + + } + return blkcor[fb] == gb && blkcor[gb] == fb + } + + return checkBlk(f.Entry, g.Entry) +} + +// fun is the return type of Fun. It contains the created func +// itself as well as indexes from block and value names into the +// corresponding Blocks and Values. +type fun struct { + f *Func + blocks map[string]*Block + values map[string]*Value +} + +var emptyPass pass = pass{ + name: "empty pass", +} + +// Fun takes the name of an entry bloc and a series of Bloc calls, and +// returns a fun containing the composed Func. entry must be a name +// supplied to one of the Bloc functions. Each of the bloc names and +// valu names should be unique across the Fun. +func Fun(c *Config, entry string, blocs ...bloc) fun { + f := c.NewFunc() + f.pass = &emptyPass + + blocks := make(map[string]*Block) + values := make(map[string]*Value) + // Create all the blocks and values. + for _, bloc := range blocs { + b := f.NewBlock(bloc.control.kind) + blocks[bloc.name] = b + for _, valu := range bloc.valus { + // args are filled in the second pass. + values[valu.name] = b.NewValue0IA(0, valu.op, valu.t, valu.auxint, valu.aux) + } + } + // Connect the blocks together and specify control values. + f.Entry = blocks[entry] + for _, bloc := range blocs { + b := blocks[bloc.name] + c := bloc.control + // Specify control values. + if c.control != "" { + cval, ok := values[c.control] + if !ok { + f.Fatalf("control value for block %s missing", bloc.name) + } + b.Control = cval + } + // Fill in args. + for _, valu := range bloc.valus { + v := values[valu.name] + for _, arg := range valu.args { + a, ok := values[arg] + if !ok { + b.Fatalf("arg %s missing for value %s in block %s", + arg, valu.name, bloc.name) + } + v.AddArg(a) + } + } + // Connect to successors. + for _, succ := range c.succs { + b.AddEdgeTo(blocks[succ]) + } + } + return fun{f, blocks, values} +} + +// Bloc defines a block for Fun. The bloc name should be unique +// across the containing Fun. entries should consist of calls to valu, +// as well as one call to Goto, If, or Exit to specify the block kind. +func Bloc(name string, entries ...interface{}) bloc { + b := bloc{} + b.name = name + seenCtrl := false + for _, e := range entries { + switch v := e.(type) { + case ctrl: + // there should be exactly one Ctrl entry. + if seenCtrl { + panic(fmt.Sprintf("already seen control for block %s", name)) + } + b.control = v + seenCtrl = true + case valu: + b.valus = append(b.valus, v) + } + } + if !seenCtrl { + panic(fmt.Sprintf("block %s doesn't have control", b.name)) + } + return b +} + +// Valu defines a value in a block. +func Valu(name string, op Op, t Type, auxint int64, aux interface{}, args ...string) valu { + return valu{name, op, t, auxint, aux, args} +} + +// Goto specifies that this is a BlockPlain and names the single successor. +// TODO(matloob): choose a better name. +func Goto(succ string) ctrl { + return ctrl{BlockPlain, "", []string{succ}} +} + +// If specifies a BlockIf. +func If(cond, sub, alt string) ctrl { + return ctrl{BlockIf, cond, []string{sub, alt}} +} + +// Exit specifies a BlockExit. +func Exit(arg string) ctrl { + return ctrl{BlockExit, arg, []string{}} +} + +// Eq specifies a BlockAMD64EQ. +func Eq(cond, sub, alt string) ctrl { + return ctrl{BlockAMD64EQ, cond, []string{sub, alt}} +} + +// bloc, ctrl, and valu are internal structures used by Bloc, Valu, Goto, +// If, and Exit to help define blocks. + +type bloc struct { + name string + control ctrl + valus []valu +} + +type ctrl struct { + kind BlockKind + control string + succs []string +} + +type valu struct { + name string + op Op + t Type + auxint int64 + aux interface{} + args []string +} + +func TestArgs(t *testing.T) { + c := testConfig(t) + fun := Fun(c, "entry", + Bloc("entry", + Valu("a", OpConst64, TypeInt64, 14, nil), + Valu("b", OpConst64, TypeInt64, 26, nil), + Valu("sum", OpAdd64, TypeInt64, 0, nil, "a", "b"), + Valu("mem", OpInitMem, TypeMem, 0, nil), + Goto("exit")), + Bloc("exit", + Exit("mem"))) + sum := fun.values["sum"] + for i, name := range []string{"a", "b"} { + if sum.Args[i] != fun.values[name] { + t.Errorf("arg %d for sum is incorrect: want %s, got %s", + i, sum.Args[i], fun.values[name]) + } + } +} + +func TestEquiv(t *testing.T) { + equivalentCases := []struct{ f, g fun }{ + // simple case + { + Fun(testConfig(t), "entry", + Bloc("entry", + Valu("a", OpConst64, TypeInt64, 14, nil), + Valu("b", OpConst64, TypeInt64, 26, nil), + Valu("sum", OpAdd64, TypeInt64, 0, nil, "a", "b"), + Valu("mem", OpInitMem, TypeMem, 0, nil), + Goto("exit")), + Bloc("exit", + Exit("mem"))), + Fun(testConfig(t), "entry", + Bloc("entry", + Valu("a", OpConst64, TypeInt64, 14, nil), + Valu("b", OpConst64, TypeInt64, 26, nil), + Valu("sum", OpAdd64, TypeInt64, 0, nil, "a", "b"), + Valu("mem", OpInitMem, TypeMem, 0, nil), + Goto("exit")), + Bloc("exit", + Exit("mem"))), + }, + // block order changed + { + Fun(testConfig(t), "entry", + Bloc("entry", + Valu("a", OpConst64, TypeInt64, 14, nil), + Valu("b", OpConst64, TypeInt64, 26, nil), + Valu("sum", OpAdd64, TypeInt64, 0, nil, "a", "b"), + Valu("mem", OpInitMem, TypeMem, 0, nil), + Goto("exit")), + Bloc("exit", + Exit("mem"))), + Fun(testConfig(t), "entry", + Bloc("exit", + Exit("mem")), + Bloc("entry", + Valu("a", OpConst64, TypeInt64, 14, nil), + Valu("b", OpConst64, TypeInt64, 26, nil), + Valu("sum", OpAdd64, TypeInt64, 0, nil, "a", "b"), + Valu("mem", OpInitMem, TypeMem, 0, nil), + Goto("exit"))), + }, + } + for _, c := range equivalentCases { + if !Equiv(c.f.f, c.g.f) { + t.Error("expected equivalence. Func definitions:") + t.Error(c.f.f) + t.Error(c.g.f) + } + } + + differentCases := []struct{ f, g fun }{ + // different shape + { + Fun(testConfig(t), "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Goto("exit")), + Bloc("exit", + Exit("mem"))), + Fun(testConfig(t), "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Exit("mem"))), + }, + // value order changed + { + Fun(testConfig(t), "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("b", OpConst64, TypeInt64, 26, nil), + Valu("a", OpConst64, TypeInt64, 14, nil), + Exit("mem"))), + Fun(testConfig(t), "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("a", OpConst64, TypeInt64, 14, nil), + Valu("b", OpConst64, TypeInt64, 26, nil), + Exit("mem"))), + }, + // value auxint different + { + Fun(testConfig(t), "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("a", OpConst64, TypeInt64, 14, nil), + Exit("mem"))), + Fun(testConfig(t), "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("a", OpConst64, TypeInt64, 26, nil), + Exit("mem"))), + }, + // value aux different + { + Fun(testConfig(t), "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("a", OpConst64, TypeInt64, 0, 14), + Exit("mem"))), + Fun(testConfig(t), "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("a", OpConst64, TypeInt64, 0, 26), + Exit("mem"))), + }, + // value args different + { + Fun(testConfig(t), "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("a", OpConst64, TypeInt64, 14, nil), + Valu("b", OpConst64, TypeInt64, 26, nil), + Valu("sum", OpAdd64, TypeInt64, 0, nil, "a", "b"), + Exit("mem"))), + Fun(testConfig(t), "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("a", OpConst64, TypeInt64, 0, nil), + Valu("b", OpConst64, TypeInt64, 14, nil), + Valu("sum", OpAdd64, TypeInt64, 0, nil, "b", "a"), + Exit("mem"))), + }, + } + for _, c := range differentCases { + if Equiv(c.f.f, c.g.f) { + t.Error("expected difference. Func definitions:") + t.Error(c.f.f) + t.Error(c.g.f) + } + } +} + +// opcodeMap returns a map from opcode to the number of times that opcode +// appears in the function. +func opcodeMap(f *Func) map[Op]int { + m := map[Op]int{} + for _, b := range f.Blocks { + for _, v := range b.Values { + m[v.Op]++ + } + } + return m +} + +// opcodeCounts checks that the number of opcodes listed in m agree with the +// number of opcodes that appear in the function. +func checkOpcodeCounts(t *testing.T, f *Func, m map[Op]int) { + n := opcodeMap(f) + for op, cnt := range m { + if n[op] != cnt { + t.Errorf("%s appears %d times, want %d times", op, n[op], cnt) + } + } +} diff --git a/src/cmd/compile/internal/ssa/fuse.go b/src/cmd/compile/internal/ssa/fuse.go new file mode 100644 index 0000000000..3f81e452b6 --- /dev/null +++ b/src/cmd/compile/internal/ssa/fuse.go @@ -0,0 +1,158 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +// fuse simplifies control flow by joining basic blocks. +func fuse(f *Func) { + for changed := true; changed; { + changed = false + for _, b := range f.Blocks { + changed = fuseBlockIf(b) || changed + changed = fuseBlockPlain(b) || changed + } + } +} + +// fuseBlockIf handles the following cases where s0 and s1 are empty blocks. +// +// b b b b +// / \ | \ / | | | +// s0 s1 | s1 s0 | | | +// \ / | / \ | | | +// ss ss ss ss +// +// If all Phi ops in ss have identical variables for slots corresponding to +// s0, s1 and b then the branch can be dropped. +// TODO: If ss doesn't contain any OpPhis, are s0 and s1 dead code anyway. +func fuseBlockIf(b *Block) bool { + if b.Kind != BlockIf { + return false + } + + var ss0, ss1 *Block + s0 := b.Succs[0] + if s0.Kind != BlockPlain || len(s0.Preds) != 1 || len(s0.Values) != 0 { + s0, ss0 = b, s0 + } else { + ss0 = s0.Succs[0] + } + s1 := b.Succs[1] + if s1.Kind != BlockPlain || len(s1.Preds) != 1 || len(s1.Values) != 0 { + s1, ss1 = b, s1 + } else { + ss1 = s1.Succs[0] + } + + if ss0 != ss1 { + return false + } + ss := ss0 + + // s0 and s1 are equal with b if the corresponding block is missing + // (2nd, 3rd and 4th case in the figure). + i0, i1 := -1, -1 + for i, p := range ss.Preds { + if p == s0 { + i0 = i + } + if p == s1 { + i1 = i + } + } + if i0 == -1 || i1 == -1 { + b.Fatalf("invalid predecessors") + } + for _, v := range ss.Values { + if v.Op == OpPhi && v.Args[i0] != v.Args[i1] { + return false + } + } + + // Now we have two of following b->ss, b->s0->ss and b->s1->ss, + // with s0 and s1 empty if exist. + // We can replace it with b->ss without if all OpPhis in ss + // have identical predecessors (verified above). + // No critical edge is introduced because b will have one successor. + if s0 != b && s1 != b { + ss.removePred(s0) + + // Replace edge b->s1->ss with b->ss. + // We need to keep a slot for Phis corresponding to b. + for i := range b.Succs { + if b.Succs[i] == s1 { + b.Succs[i] = ss + } + } + for i := range ss.Preds { + if ss.Preds[i] == s1 { + ss.Preds[i] = b + } + } + } else if s0 != b { + ss.removePred(s0) + } else if s1 != b { + ss.removePred(s1) + } + b.Kind = BlockPlain + b.Control = nil + b.Succs = append(b.Succs[:0], ss) + + // Trash the empty blocks s0 & s1. + if s0 != b { + s0.Kind = BlockInvalid + s0.Values = nil + s0.Succs = nil + s0.Preds = nil + } + if s1 != b { + s1.Kind = BlockInvalid + s1.Values = nil + s1.Succs = nil + s1.Preds = nil + } + return true +} + +func fuseBlockPlain(b *Block) bool { + if b.Kind != BlockPlain { + return false + } + + c := b.Succs[0] + if len(c.Preds) != 1 { + return false + } + + // move all of b'c values to c. + for _, v := range b.Values { + v.Block = c + c.Values = append(c.Values, v) + } + + // replace b->c edge with preds(b) -> c + c.predstorage[0] = nil + if len(b.Preds) > len(b.predstorage) { + c.Preds = b.Preds + } else { + c.Preds = append(c.predstorage[:0], b.Preds...) + } + for _, p := range c.Preds { + for i, q := range p.Succs { + if q == b { + p.Succs[i] = c + } + } + } + if f := b.Func; f.Entry == b { + f.Entry = c + } + + // trash b, just in case + b.Kind = BlockInvalid + b.Values = nil + b.Preds = nil + b.Succs = nil + return true +} diff --git a/src/cmd/compile/internal/ssa/fuse_test.go b/src/cmd/compile/internal/ssa/fuse_test.go new file mode 100644 index 0000000000..937fb71031 --- /dev/null +++ b/src/cmd/compile/internal/ssa/fuse_test.go @@ -0,0 +1,129 @@ +package ssa + +import ( + "testing" +) + +func TestFuseEliminatesOneBranch(t *testing.T) { + ptrType := &TypeImpl{Size_: 8, Ptr: true, Name: "testptr"} // dummy for testing + c := NewConfig("amd64", DummyFrontend{t}, nil, true) + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("sb", OpSB, TypeInvalid, 0, nil), + Goto("checkPtr")), + Bloc("checkPtr", + Valu("ptr1", OpLoad, ptrType, 0, nil, "sb", "mem"), + Valu("nilptr", OpConstNil, ptrType, 0, nil), + Valu("bool1", OpNeqPtr, TypeBool, 0, nil, "ptr1", "nilptr"), + If("bool1", "then", "exit")), + Bloc("then", + Goto("exit")), + Bloc("exit", + Exit("mem"))) + + CheckFunc(fun.f) + fuse(fun.f) + + for _, b := range fun.f.Blocks { + if b == fun.blocks["then"] && b.Kind != BlockInvalid { + t.Errorf("then was not eliminated, but should have") + } + } +} + +func TestFuseEliminatesBothBranches(t *testing.T) { + ptrType := &TypeImpl{Size_: 8, Ptr: true, Name: "testptr"} // dummy for testing + c := NewConfig("amd64", DummyFrontend{t}, nil, true) + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("sb", OpSB, TypeInvalid, 0, nil), + Goto("checkPtr")), + Bloc("checkPtr", + Valu("ptr1", OpLoad, ptrType, 0, nil, "sb", "mem"), + Valu("nilptr", OpConstNil, ptrType, 0, nil), + Valu("bool1", OpNeqPtr, TypeBool, 0, nil, "ptr1", "nilptr"), + If("bool1", "then", "else")), + Bloc("then", + Goto("exit")), + Bloc("else", + Goto("exit")), + Bloc("exit", + Exit("mem"))) + + CheckFunc(fun.f) + fuse(fun.f) + + for _, b := range fun.f.Blocks { + if b == fun.blocks["then"] && b.Kind != BlockInvalid { + t.Errorf("then was not eliminated, but should have") + } + if b == fun.blocks["else"] && b.Kind != BlockInvalid { + t.Errorf("then was not eliminated, but should have") + } + } +} + +func TestFuseHandlesPhis(t *testing.T) { + ptrType := &TypeImpl{Size_: 8, Ptr: true, Name: "testptr"} // dummy for testing + c := NewConfig("amd64", DummyFrontend{t}, nil, true) + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("sb", OpSB, TypeInvalid, 0, nil), + Goto("checkPtr")), + Bloc("checkPtr", + Valu("ptr1", OpLoad, ptrType, 0, nil, "sb", "mem"), + Valu("nilptr", OpConstNil, ptrType, 0, nil), + Valu("bool1", OpNeqPtr, TypeBool, 0, nil, "ptr1", "nilptr"), + If("bool1", "then", "else")), + Bloc("then", + Goto("exit")), + Bloc("else", + Goto("exit")), + Bloc("exit", + Valu("phi", OpPhi, ptrType, 0, nil, "ptr1", "ptr1"), + Exit("mem"))) + + CheckFunc(fun.f) + fuse(fun.f) + + for _, b := range fun.f.Blocks { + if b == fun.blocks["then"] && b.Kind != BlockInvalid { + t.Errorf("then was not eliminated, but should have") + } + if b == fun.blocks["else"] && b.Kind != BlockInvalid { + t.Errorf("then was not eliminated, but should have") + } + } +} + +func TestFuseEliminatesEmptyBlocks(t *testing.T) { + c := NewConfig("amd64", DummyFrontend{t}, nil, true) + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("sb", OpSB, TypeInvalid, 0, nil), + Goto("z0")), + Bloc("z1", + Goto("z2")), + Bloc("z3", + Goto("exit")), + Bloc("z2", + Goto("z3")), + Bloc("z0", + Goto("z1")), + Bloc("exit", + Exit("mem"), + )) + + CheckFunc(fun.f) + fuse(fun.f) + + for k, b := range fun.blocks { + if k[:1] == "z" && b.Kind != BlockInvalid { + t.Errorf("%s was not eliminated, but should have", k) + } + } +} diff --git a/src/cmd/compile/internal/ssa/gen/AMD64.rules b/src/cmd/compile/internal/ssa/gen/AMD64.rules new file mode 100644 index 0000000000..167ec82d18 --- /dev/null +++ b/src/cmd/compile/internal/ssa/gen/AMD64.rules @@ -0,0 +1,1164 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// x86 register conventions: +// - Integer types live in the low portion of registers. Upper portions are junk. +// - Boolean types use the low-order byte of a register. Upper bytes are junk. +// - We do not use AH,BH,CH,DH registers. +// - Floating-point types will live in the low natural slot of an sse2 register. +// Unused portions are junk. + +// Lowering arithmetic +(Add64 x y) -> (ADDQ x y) +(AddPtr x y) -> (ADDQ x y) +(Add32 x y) -> (ADDL x y) +(Add16 x y) -> (ADDW x y) +(Add8 x y) -> (ADDB x y) +(Add32F x y) -> (ADDSS x y) +(Add64F x y) -> (ADDSD x y) + +(Sub64 x y) -> (SUBQ x y) +(SubPtr x y) -> (SUBQ x y) +(Sub32 x y) -> (SUBL x y) +(Sub16 x y) -> (SUBW x y) +(Sub8 x y) -> (SUBB x y) +(Sub32F x y) -> (SUBSS x y) +(Sub64F x y) -> (SUBSD x y) + +(Mul64 x y) -> (MULQ x y) +(Mul32 x y) -> (MULL x y) +(Mul16 x y) -> (MULW x y) +(Mul8 x y) -> (MULB x y) +(Mul32F x y) -> (MULSS x y) +(Mul64F x y) -> (MULSD x y) + +(Div32F x y) -> (DIVSS x y) +(Div64F x y) -> (DIVSD x y) + +(Div64 x y) -> (DIVQ x y) +(Div64u x y) -> (DIVQU x y) +(Div32 x y) -> (DIVL x y) +(Div32u x y) -> (DIVLU x y) +(Div16 x y) -> (DIVW x y) +(Div16u x y) -> (DIVWU x y) +(Div8 x y) -> (DIVW (SignExt8to16 x) (SignExt8to16 y)) +(Div8u x y) -> (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y)) + +(Hmul64 x y) -> (HMULQ x y) +(Hmul64u x y) -> (HMULQU x y) +(Hmul32 x y) -> (HMULL x y) +(Hmul32u x y) -> (HMULLU x y) +(Hmul16 x y) -> (HMULW x y) +(Hmul16u x y) -> (HMULWU x y) +(Hmul8 x y) -> (HMULB x y) +(Hmul8u x y) -> (HMULBU x y) + +(Avg64u x y) -> (AVGQU x y) + +(Mod64 x y) -> (MODQ x y) +(Mod64u x y) -> (MODQU x y) +(Mod32 x y) -> (MODL x y) +(Mod32u x y) -> (MODLU x y) +(Mod16 x y) -> (MODW x y) +(Mod16u x y) -> (MODWU x y) +(Mod8 x y) -> (MODW (SignExt8to16 x) (SignExt8to16 y)) +(Mod8u x y) -> (MODWU (ZeroExt8to16 x) (ZeroExt8to16 y)) + +(And64 x y) -> (ANDQ x y) +(And32 x y) -> (ANDL x y) +(And16 x y) -> (ANDW x y) +(And8 x y) -> (ANDB x y) + +(Or64 x y) -> (ORQ x y) +(Or32 x y) -> (ORL x y) +(Or16 x y) -> (ORW x y) +(Or8 x y) -> (ORB x y) + +(Xor64 x y) -> (XORQ x y) +(Xor32 x y) -> (XORL x y) +(Xor16 x y) -> (XORW x y) +(Xor8 x y) -> (XORB x y) + +(Neg64 x) -> (NEGQ x) +(Neg32 x) -> (NEGL x) +(Neg16 x) -> (NEGW x) +(Neg8 x) -> (NEGB x) +(Neg32F x) -> (PXOR x (MOVSSconst <config.Frontend().TypeFloat32()> [f2i(math.Copysign(0, -1))])) +(Neg64F x) -> (PXOR x (MOVSDconst <config.Frontend().TypeFloat64()> [f2i(math.Copysign(0, -1))])) + +(Com64 x) -> (NOTQ x) +(Com32 x) -> (NOTL x) +(Com16 x) -> (NOTW x) +(Com8 x) -> (NOTB x) + +(Sqrt x) -> (SQRTSD x) + +// Note: we always extend to 64 bits even though some ops don't need that many result bits. +(SignExt8to16 x) -> (MOVBQSX x) +(SignExt8to32 x) -> (MOVBQSX x) +(SignExt8to64 x) -> (MOVBQSX x) +(SignExt16to32 x) -> (MOVWQSX x) +(SignExt16to64 x) -> (MOVWQSX x) +(SignExt32to64 x) -> (MOVLQSX x) + +(ZeroExt8to16 x) -> (MOVBQZX x) +(ZeroExt8to32 x) -> (MOVBQZX x) +(ZeroExt8to64 x) -> (MOVBQZX x) +(ZeroExt16to32 x) -> (MOVWQZX x) +(ZeroExt16to64 x) -> (MOVWQZX x) +(ZeroExt32to64 x) -> (MOVLQZX x) + +(Cvt32to32F x) -> (CVTSL2SS x) +(Cvt32to64F x) -> (CVTSL2SD x) +(Cvt64to32F x) -> (CVTSQ2SS x) +(Cvt64to64F x) -> (CVTSQ2SD x) + +(Cvt32Fto32 x) -> (CVTTSS2SL x) +(Cvt32Fto64 x) -> (CVTTSS2SQ x) +(Cvt64Fto32 x) -> (CVTTSD2SL x) +(Cvt64Fto64 x) -> (CVTTSD2SQ x) + +(Cvt32Fto64F x) -> (CVTSS2SD x) +(Cvt64Fto32F x) -> (CVTSD2SS x) + +// Because we ignore high parts of registers, truncates are just copies. +(Trunc16to8 x) -> x +(Trunc32to8 x) -> x +(Trunc32to16 x) -> x +(Trunc64to8 x) -> x +(Trunc64to16 x) -> x +(Trunc64to32 x) -> x + +// Lowering shifts +// Unsigned shifts need to return 0 if shift amount is >= width of shifted value. +// result = (arg << shift) & (shift >= argbits ? 0 : 0xffffffffffffffff) +// Note: for small shifts we generate 32 bits of mask even when we don't need it all. +(Lsh64x64 <t> x y) -> (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPQconst y [64]))) +(Lsh64x32 <t> x y) -> (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPLconst y [64]))) +(Lsh64x16 <t> x y) -> (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPWconst y [64]))) +(Lsh64x8 <t> x y) -> (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPBconst y [64]))) + +(Lsh32x64 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPQconst y [32]))) +(Lsh32x32 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32]))) +(Lsh32x16 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32]))) +(Lsh32x8 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32]))) + +(Lsh16x64 <t> x y) -> (ANDW (SHLW <t> x y) (SBBLcarrymask <t> (CMPQconst y [16]))) +(Lsh16x32 <t> x y) -> (ANDW (SHLW <t> x y) (SBBLcarrymask <t> (CMPLconst y [16]))) +(Lsh16x16 <t> x y) -> (ANDW (SHLW <t> x y) (SBBLcarrymask <t> (CMPWconst y [16]))) +(Lsh16x8 <t> x y) -> (ANDW (SHLW <t> x y) (SBBLcarrymask <t> (CMPBconst y [16]))) + +(Lsh8x64 <t> x y) -> (ANDB (SHLB <t> x y) (SBBLcarrymask <t> (CMPQconst y [8]))) +(Lsh8x32 <t> x y) -> (ANDB (SHLB <t> x y) (SBBLcarrymask <t> (CMPLconst y [8]))) +(Lsh8x16 <t> x y) -> (ANDB (SHLB <t> x y) (SBBLcarrymask <t> (CMPWconst y [8]))) +(Lsh8x8 <t> x y) -> (ANDB (SHLB <t> x y) (SBBLcarrymask <t> (CMPBconst y [8]))) + +(Lrot64 <t> x [c]) -> (ROLQconst <t> [c&63] x) +(Lrot32 <t> x [c]) -> (ROLLconst <t> [c&31] x) +(Lrot16 <t> x [c]) -> (ROLWconst <t> [c&15] x) +(Lrot8 <t> x [c]) -> (ROLBconst <t> [c&7] x) + +(Rsh64Ux64 <t> x y) -> (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPQconst y [64]))) +(Rsh64Ux32 <t> x y) -> (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPLconst y [64]))) +(Rsh64Ux16 <t> x y) -> (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPWconst y [64]))) +(Rsh64Ux8 <t> x y) -> (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPBconst y [64]))) + +(Rsh32Ux64 <t> x y) -> (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPQconst y [32]))) +(Rsh32Ux32 <t> x y) -> (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32]))) +(Rsh32Ux16 <t> x y) -> (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32]))) +(Rsh32Ux8 <t> x y) -> (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32]))) + +(Rsh16Ux64 <t> x y) -> (ANDW (SHRW <t> x y) (SBBLcarrymask <t> (CMPQconst y [16]))) +(Rsh16Ux32 <t> x y) -> (ANDW (SHRW <t> x y) (SBBLcarrymask <t> (CMPLconst y [16]))) +(Rsh16Ux16 <t> x y) -> (ANDW (SHRW <t> x y) (SBBLcarrymask <t> (CMPWconst y [16]))) +(Rsh16Ux8 <t> x y) -> (ANDW (SHRW <t> x y) (SBBLcarrymask <t> (CMPBconst y [16]))) + +(Rsh8Ux64 <t> x y) -> (ANDB (SHRB <t> x y) (SBBLcarrymask <t> (CMPQconst y [8]))) +(Rsh8Ux32 <t> x y) -> (ANDB (SHRB <t> x y) (SBBLcarrymask <t> (CMPLconst y [8]))) +(Rsh8Ux16 <t> x y) -> (ANDB (SHRB <t> x y) (SBBLcarrymask <t> (CMPWconst y [8]))) +(Rsh8Ux8 <t> x y) -> (ANDB (SHRB <t> x y) (SBBLcarrymask <t> (CMPBconst y [8]))) + +// Signed right shift needs to return 0/-1 if shift amount is >= width of shifted value. +// We implement this by setting the shift value to -1 (all ones) if the shift value is >= width. +// Note: for small shift widths we generate 32 bits of mask even when we don't need it all. +(Rsh64x64 <t> x y) -> (SARQ <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [64]))))) +(Rsh64x32 <t> x y) -> (SARQ <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [64]))))) +(Rsh64x16 <t> x y) -> (SARQ <t> x (ORW <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [64]))))) +(Rsh64x8 <t> x y) -> (SARQ <t> x (ORB <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [64]))))) + +(Rsh32x64 <t> x y) -> (SARL <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [32]))))) +(Rsh32x32 <t> x y) -> (SARL <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [32]))))) +(Rsh32x16 <t> x y) -> (SARL <t> x (ORW <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [32]))))) +(Rsh32x8 <t> x y) -> (SARL <t> x (ORB <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [32]))))) + +(Rsh16x64 <t> x y) -> (SARW <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [16]))))) +(Rsh16x32 <t> x y) -> (SARW <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [16]))))) +(Rsh16x16 <t> x y) -> (SARW <t> x (ORW <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [16]))))) +(Rsh16x8 <t> x y) -> (SARW <t> x (ORB <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [16]))))) + +(Rsh8x64 <t> x y) -> (SARB <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [8]))))) +(Rsh8x32 <t> x y) -> (SARB <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [8]))))) +(Rsh8x16 <t> x y) -> (SARB <t> x (ORW <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [8]))))) +(Rsh8x8 <t> x y) -> (SARB <t> x (ORB <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [8]))))) + +(Less64 x y) -> (SETL (CMPQ x y)) +(Less32 x y) -> (SETL (CMPL x y)) +(Less16 x y) -> (SETL (CMPW x y)) +(Less8 x y) -> (SETL (CMPB x y)) +(Less64U x y) -> (SETB (CMPQ x y)) +(Less32U x y) -> (SETB (CMPL x y)) +(Less16U x y) -> (SETB (CMPW x y)) +(Less8U x y) -> (SETB (CMPB x y)) +// Use SETGF with reversed operands to dodge NaN case +(Less64F x y) -> (SETGF (UCOMISD y x)) +(Less32F x y) -> (SETGF (UCOMISS y x)) + +(Leq64 x y) -> (SETLE (CMPQ x y)) +(Leq32 x y) -> (SETLE (CMPL x y)) +(Leq16 x y) -> (SETLE (CMPW x y)) +(Leq8 x y) -> (SETLE (CMPB x y)) +(Leq64U x y) -> (SETBE (CMPQ x y)) +(Leq32U x y) -> (SETBE (CMPL x y)) +(Leq16U x y) -> (SETBE (CMPW x y)) +(Leq8U x y) -> (SETBE (CMPB x y)) +// Use SETGEF with reversed operands to dodge NaN case +(Leq64F x y) -> (SETGEF (UCOMISD y x)) +(Leq32F x y) -> (SETGEF (UCOMISS y x)) + +(Greater64 x y) -> (SETG (CMPQ x y)) +(Greater32 x y) -> (SETG (CMPL x y)) +(Greater16 x y) -> (SETG (CMPW x y)) +(Greater8 x y) -> (SETG (CMPB x y)) +(Greater64U x y) -> (SETA (CMPQ x y)) +(Greater32U x y) -> (SETA (CMPL x y)) +(Greater16U x y) -> (SETA (CMPW x y)) +(Greater8U x y) -> (SETA (CMPB x y)) +// Note Go assembler gets UCOMISx operand order wrong, but it is right here +// Bug is accommodated at generation of assembly language. +(Greater64F x y) -> (SETGF (UCOMISD x y)) +(Greater32F x y) -> (SETGF (UCOMISS x y)) + +(Geq64 x y) -> (SETGE (CMPQ x y)) +(Geq32 x y) -> (SETGE (CMPL x y)) +(Geq16 x y) -> (SETGE (CMPW x y)) +(Geq8 x y) -> (SETGE (CMPB x y)) +(Geq64U x y) -> (SETAE (CMPQ x y)) +(Geq32U x y) -> (SETAE (CMPL x y)) +(Geq16U x y) -> (SETAE (CMPW x y)) +(Geq8U x y) -> (SETAE (CMPB x y)) +// Note Go assembler gets UCOMISx operand order wrong, but it is right here +// Bug is accommodated at generation of assembly language. +(Geq64F x y) -> (SETGEF (UCOMISD x y)) +(Geq32F x y) -> (SETGEF (UCOMISS x y)) + +(Eq64 x y) -> (SETEQ (CMPQ x y)) +(Eq32 x y) -> (SETEQ (CMPL x y)) +(Eq16 x y) -> (SETEQ (CMPW x y)) +(Eq8 x y) -> (SETEQ (CMPB x y)) +(EqPtr x y) -> (SETEQ (CMPQ x y)) +(Eq64F x y) -> (SETEQF (UCOMISD x y)) +(Eq32F x y) -> (SETEQF (UCOMISS x y)) + +(Neq64 x y) -> (SETNE (CMPQ x y)) +(Neq32 x y) -> (SETNE (CMPL x y)) +(Neq16 x y) -> (SETNE (CMPW x y)) +(Neq8 x y) -> (SETNE (CMPB x y)) +(NeqPtr x y) -> (SETNE (CMPQ x y)) +(Neq64F x y) -> (SETNEF (UCOMISD x y)) +(Neq32F x y) -> (SETNEF (UCOMISS x y)) + +(Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) -> (MOVQload ptr mem) +(Load <t> ptr mem) && is32BitInt(t) -> (MOVLload ptr mem) +(Load <t> ptr mem) && is16BitInt(t) -> (MOVWload ptr mem) +(Load <t> ptr mem) && (t.IsBoolean() || is8BitInt(t)) -> (MOVBload ptr mem) +(Load <t> ptr mem) && is32BitFloat(t) -> (MOVSSload ptr mem) +(Load <t> ptr mem) && is64BitFloat(t) -> (MOVSDload ptr mem) + +// These more-specific FP versions of Store pattern should come first. +(Store [8] ptr val mem) && is64BitFloat(val.Type) -> (MOVSDstore ptr val mem) +(Store [4] ptr val mem) && is32BitFloat(val.Type) -> (MOVSSstore ptr val mem) + +(Store [8] ptr val mem) -> (MOVQstore ptr val mem) +(Store [4] ptr val mem) -> (MOVLstore ptr val mem) +(Store [2] ptr val mem) -> (MOVWstore ptr val mem) +(Store [1] ptr val mem) -> (MOVBstore ptr val mem) + +// We want this to stick out so the to/from ptr conversion is obvious +(Convert <t> x mem) -> (MOVQconvert <t> x mem) + +// checks +(IsNonNil p) -> (SETNE (TESTQ p p)) +(IsInBounds idx len) -> (SETB (CMPQ idx len)) +(IsSliceInBounds idx len) -> (SETBE (CMPQ idx len)) +(NilCheck ptr mem) -> (LoweredNilCheck ptr mem) + +(GetG mem) -> (LoweredGetG mem) +(GetClosurePtr) -> (LoweredGetClosurePtr) + +// Small moves +(Move [0] _ _ mem) -> mem +(Move [1] dst src mem) -> (MOVBstore dst (MOVBload src mem) mem) +(Move [2] dst src mem) -> (MOVWstore dst (MOVWload src mem) mem) +(Move [4] dst src mem) -> (MOVLstore dst (MOVLload src mem) mem) +(Move [8] dst src mem) -> (MOVQstore dst (MOVQload src mem) mem) +(Move [16] dst src mem) -> (MOVOstore dst (MOVOload src mem) mem) +(Move [3] dst src mem) -> + (MOVBstore [2] dst (MOVBload [2] src mem) + (MOVWstore dst (MOVWload src mem) mem)) +(Move [5] dst src mem) -> + (MOVBstore [4] dst (MOVBload [4] src mem) + (MOVLstore dst (MOVLload src mem) mem)) +(Move [6] dst src mem) -> + (MOVWstore [4] dst (MOVWload [4] src mem) + (MOVLstore dst (MOVLload src mem) mem)) +(Move [7] dst src mem) -> + (MOVLstore [3] dst (MOVLload [3] src mem) + (MOVLstore dst (MOVLload src mem) mem)) +(Move [size] dst src mem) && size > 8 && size < 16 -> + (MOVQstore [size-8] dst (MOVQload [size-8] src mem) + (MOVQstore dst (MOVQload src mem) mem)) + +// Adjust moves to be a multiple of 16 bytes. +(Move [size] dst src mem) && size > 16 && size%16 != 0 && size%16 <= 8 -> + (Move [size-size%16] (ADDQconst <dst.Type> dst [size%16]) (ADDQconst <src.Type> src [size%16]) + (MOVQstore dst (MOVQload src mem) mem)) +(Move [size] dst src mem) && size > 16 && size%16 != 0 && size%16 > 8 -> + (Move [size-size%16] (ADDQconst <dst.Type> dst [size%16]) (ADDQconst <src.Type> src [size%16]) + (MOVOstore dst (MOVOload src mem) mem)) + +// Medium copying uses a duff device. +(Move [size] dst src mem) && size >= 32 && size <= 16*64 && size%16 == 0 -> + (DUFFCOPY [14*(64-size/16)] dst src mem) +// 14 and 64 are magic constants. 14 is the number of bytes to encode: +// MOVUPS (SI), X0 +// ADDQ $16, SI +// MOVUPS X0, (DI) +// ADDQ $16, DI +// and 64 is the number of such blocks. See src/runtime/duff_amd64.s:duffcopy. + +// Large copying uses REP MOVSQ. +(Move [size] dst src mem) && size > 16*64 && size%8 == 0 -> + (REPMOVSQ dst src (MOVQconst [size/8]) mem) + +(Not x) -> (XORBconst [1] x) + +(OffPtr [off] ptr) -> (ADDQconst [off] ptr) + +(Const8 [val]) -> (MOVBconst [val]) +(Const16 [val]) -> (MOVWconst [val]) +(Const32 [val]) -> (MOVLconst [val]) +(Const64 [val]) -> (MOVQconst [val]) +(Const32F [val]) -> (MOVSSconst [val]) +(Const64F [val]) -> (MOVSDconst [val]) +(ConstNil) -> (MOVQconst [0]) +(ConstBool [b]) -> (MOVBconst [b]) + +(Addr {sym} base) -> (LEAQ {sym} base) + +(ITab (Load ptr mem)) -> (MOVQload ptr mem) + +// block rewrites +(If (SETL cmp) yes no) -> (LT cmp yes no) +(If (SETLE cmp) yes no) -> (LE cmp yes no) +(If (SETG cmp) yes no) -> (GT cmp yes no) +(If (SETGE cmp) yes no) -> (GE cmp yes no) +(If (SETEQ cmp) yes no) -> (EQ cmp yes no) +(If (SETNE cmp) yes no) -> (NE cmp yes no) +(If (SETB cmp) yes no) -> (ULT cmp yes no) +(If (SETBE cmp) yes no) -> (ULE cmp yes no) +(If (SETA cmp) yes no) -> (UGT cmp yes no) +(If (SETAE cmp) yes no) -> (UGE cmp yes no) + +// Special case for floating point - LF/LEF not generated +(If (SETGF cmp) yes no) -> (UGT cmp yes no) +(If (SETGEF cmp) yes no) -> (UGE cmp yes no) +(If (SETEQF cmp) yes no) -> (EQF cmp yes no) +(If (SETNEF cmp) yes no) -> (NEF cmp yes no) + +(If cond yes no) -> (NE (TESTB cond cond) yes no) + +(NE (TESTB (SETL cmp)) yes no) -> (LT cmp yes no) +(NE (TESTB (SETLE cmp)) yes no) -> (LE cmp yes no) +(NE (TESTB (SETG cmp)) yes no) -> (GT cmp yes no) +(NE (TESTB (SETGE cmp)) yes no) -> (GE cmp yes no) +(NE (TESTB (SETEQ cmp)) yes no) -> (EQ cmp yes no) +(NE (TESTB (SETNE cmp)) yes no) -> (NE cmp yes no) +(NE (TESTB (SETB cmp)) yes no) -> (ULT cmp yes no) +(NE (TESTB (SETBE cmp)) yes no) -> (ULE cmp yes no) +(NE (TESTB (SETA cmp)) yes no) -> (UGT cmp yes no) +(NE (TESTB (SETAE cmp)) yes no) -> (UGE cmp yes no) + +// Special case for floating point - LF/LEF not generated +(NE (TESTB (SETGF cmp)) yes no) -> (UGT cmp yes no) +(NE (TESTB (SETGEF cmp)) yes no) -> (UGE cmp yes no) +(NE (TESTB (SETEQF cmp)) yes no) -> (EQF cmp yes no) +(NE (TESTB (SETNEF cmp)) yes no) -> (NEF cmp yes no) + +// Disabled because it interferes with the pattern match above and makes worse code. +// (SETNEF x) -> (ORQ (SETNE <config.Frontend().TypeInt8()> x) (SETNAN <config.Frontend().TypeInt8()> x)) +// (SETEQF x) -> (ANDQ (SETEQ <config.Frontend().TypeInt8()> x) (SETORD <config.Frontend().TypeInt8()> x)) + +(StaticCall [argwid] {target} mem) -> (CALLstatic [argwid] {target} mem) +(ClosureCall [argwid] entry closure mem) -> (CALLclosure [argwid] entry closure mem) +(DeferCall [argwid] mem) -> (CALLdefer [argwid] mem) +(GoCall [argwid] mem) -> (CALLgo [argwid] mem) +(InterCall [argwid] entry mem) -> (CALLinter [argwid] entry mem) + +// Rules below here apply some simple optimizations after lowering. +// TODO: Should this be a separate pass? + +// fold constants into instructions +(ADDQ x (MOVQconst [c])) && is32Bit(c) -> (ADDQconst [c] x) +(ADDQ (MOVQconst [c]) x) && is32Bit(c) -> (ADDQconst [c] x) +(ADDL x (MOVLconst [c])) -> (ADDLconst [c] x) +(ADDL (MOVLconst [c]) x) -> (ADDLconst [c] x) +(ADDW x (MOVWconst [c])) -> (ADDWconst [c] x) +(ADDW (MOVWconst [c]) x) -> (ADDWconst [c] x) +(ADDB x (MOVBconst [c])) -> (ADDBconst [c] x) +(ADDB (MOVBconst [c]) x) -> (ADDBconst [c] x) + +(SUBQ x (MOVQconst [c])) && is32Bit(c) -> (SUBQconst x [c]) +(SUBQ (MOVQconst [c]) x) && is32Bit(c) -> (NEGQ (SUBQconst <v.Type> x [c])) +(SUBL x (MOVLconst [c])) -> (SUBLconst x [c]) +(SUBL (MOVLconst [c]) x) -> (NEGL (SUBLconst <v.Type> x [c])) +(SUBW x (MOVWconst [c])) -> (SUBWconst x [c]) +(SUBW (MOVWconst [c]) x) -> (NEGW (SUBWconst <v.Type> x [c])) +(SUBB x (MOVBconst [c])) -> (SUBBconst x [c]) +(SUBB (MOVBconst [c]) x) -> (NEGB (SUBBconst <v.Type> x [c])) + +(MULQ x (MOVQconst [c])) && is32Bit(c) -> (MULQconst [c] x) +(MULQ (MOVQconst [c]) x) && is32Bit(c) -> (MULQconst [c] x) +(MULL x (MOVLconst [c])) -> (MULLconst [c] x) +(MULL (MOVLconst [c]) x) -> (MULLconst [c] x) +(MULW x (MOVWconst [c])) -> (MULWconst [c] x) +(MULW (MOVWconst [c]) x) -> (MULWconst [c] x) +(MULB x (MOVBconst [c])) -> (MULBconst [c] x) +(MULB (MOVBconst [c]) x) -> (MULBconst [c] x) + +(ANDQ x (MOVQconst [c])) && is32Bit(c) -> (ANDQconst [c] x) +(ANDQ (MOVQconst [c]) x) && is32Bit(c) -> (ANDQconst [c] x) +(ANDL x (MOVLconst [c])) -> (ANDLconst [c] x) +(ANDL (MOVLconst [c]) x) -> (ANDLconst [c] x) +(ANDW x (MOVLconst [c])) -> (ANDWconst [c] x) +(ANDW (MOVLconst [c]) x) -> (ANDWconst [c] x) +(ANDW x (MOVWconst [c])) -> (ANDWconst [c] x) +(ANDW (MOVWconst [c]) x) -> (ANDWconst [c] x) +(ANDB x (MOVLconst [c])) -> (ANDBconst [c] x) +(ANDB (MOVLconst [c]) x) -> (ANDBconst [c] x) +(ANDB x (MOVBconst [c])) -> (ANDBconst [c] x) +(ANDB (MOVBconst [c]) x) -> (ANDBconst [c] x) + +(ORQ x (MOVQconst [c])) && is32Bit(c) -> (ORQconst [c] x) +(ORQ (MOVQconst [c]) x) && is32Bit(c) -> (ORQconst [c] x) +(ORL x (MOVLconst [c])) -> (ORLconst [c] x) +(ORL (MOVLconst [c]) x) -> (ORLconst [c] x) +(ORW x (MOVWconst [c])) -> (ORWconst [c] x) +(ORW (MOVWconst [c]) x) -> (ORWconst [c] x) +(ORB x (MOVBconst [c])) -> (ORBconst [c] x) +(ORB (MOVBconst [c]) x) -> (ORBconst [c] x) + +(XORQ x (MOVQconst [c])) && is32Bit(c) -> (XORQconst [c] x) +(XORQ (MOVQconst [c]) x) && is32Bit(c) -> (XORQconst [c] x) +(XORL x (MOVLconst [c])) -> (XORLconst [c] x) +(XORL (MOVLconst [c]) x) -> (XORLconst [c] x) +(XORW x (MOVWconst [c])) -> (XORWconst [c] x) +(XORW (MOVWconst [c]) x) -> (XORWconst [c] x) +(XORB x (MOVBconst [c])) -> (XORBconst [c] x) +(XORB (MOVBconst [c]) x) -> (XORBconst [c] x) + +(SHLQ x (MOVQconst [c])) -> (SHLQconst [c&63] x) +(SHLQ x (MOVLconst [c])) -> (SHLQconst [c&63] x) +(SHLQ x (MOVWconst [c])) -> (SHLQconst [c&63] x) +(SHLQ x (MOVBconst [c])) -> (SHLQconst [c&63] x) + +(SHLL x (MOVQconst [c])) -> (SHLLconst [c&31] x) +(SHLL x (MOVLconst [c])) -> (SHLLconst [c&31] x) +(SHLL x (MOVWconst [c])) -> (SHLLconst [c&31] x) +(SHLL x (MOVBconst [c])) -> (SHLLconst [c&31] x) + +(SHLW x (MOVQconst [c])) -> (SHLWconst [c&31] x) +(SHLW x (MOVLconst [c])) -> (SHLWconst [c&31] x) +(SHLW x (MOVWconst [c])) -> (SHLWconst [c&31] x) +(SHLW x (MOVBconst [c])) -> (SHLWconst [c&31] x) + +(SHLB x (MOVQconst [c])) -> (SHLBconst [c&31] x) +(SHLB x (MOVLconst [c])) -> (SHLBconst [c&31] x) +(SHLB x (MOVWconst [c])) -> (SHLBconst [c&31] x) +(SHLB x (MOVBconst [c])) -> (SHLBconst [c&31] x) + +(SHRQ x (MOVQconst [c])) -> (SHRQconst [c&63] x) +(SHRQ x (MOVLconst [c])) -> (SHRQconst [c&63] x) +(SHRQ x (MOVWconst [c])) -> (SHRQconst [c&63] x) +(SHRQ x (MOVBconst [c])) -> (SHRQconst [c&63] x) + +(SHRL x (MOVQconst [c])) -> (SHRLconst [c&31] x) +(SHRL x (MOVLconst [c])) -> (SHRLconst [c&31] x) +(SHRL x (MOVWconst [c])) -> (SHRLconst [c&31] x) +(SHRL x (MOVBconst [c])) -> (SHRLconst [c&31] x) + +(SHRW x (MOVQconst [c])) -> (SHRWconst [c&31] x) +(SHRW x (MOVLconst [c])) -> (SHRWconst [c&31] x) +(SHRW x (MOVWconst [c])) -> (SHRWconst [c&31] x) +(SHRW x (MOVBconst [c])) -> (SHRWconst [c&31] x) + +(SHRB x (MOVQconst [c])) -> (SHRBconst [c&31] x) +(SHRB x (MOVLconst [c])) -> (SHRBconst [c&31] x) +(SHRB x (MOVWconst [c])) -> (SHRBconst [c&31] x) +(SHRB x (MOVBconst [c])) -> (SHRBconst [c&31] x) + +(SARQ x (MOVQconst [c])) -> (SARQconst [c&63] x) +(SARQ x (MOVLconst [c])) -> (SARQconst [c&63] x) +(SARQ x (MOVWconst [c])) -> (SARQconst [c&63] x) +(SARQ x (MOVBconst [c])) -> (SARQconst [c&63] x) + +(SARL x (MOVQconst [c])) -> (SARLconst [c&31] x) +(SARL x (MOVLconst [c])) -> (SARLconst [c&31] x) +(SARL x (MOVWconst [c])) -> (SARLconst [c&31] x) +(SARL x (MOVBconst [c])) -> (SARLconst [c&31] x) + +(SARW x (MOVQconst [c])) -> (SARWconst [c&31] x) +(SARW x (MOVLconst [c])) -> (SARWconst [c&31] x) +(SARW x (MOVWconst [c])) -> (SARWconst [c&31] x) +(SARW x (MOVBconst [c])) -> (SARWconst [c&31] x) + +(SARB x (MOVQconst [c])) -> (SARBconst [c&31] x) +(SARB x (MOVLconst [c])) -> (SARBconst [c&31] x) +(SARB x (MOVWconst [c])) -> (SARBconst [c&31] x) +(SARB x (MOVBconst [c])) -> (SARBconst [c&31] x) + +// Note: the word and byte shifts keep the low 5 bits (not the low 4 or 3 bits) +// because the x86 instructions are defined to use all 5 bits of the shift even +// for the small shifts. I don't think we'll ever generate a weird shift (e.g. +// (SHLW x (MOVWconst [24])), but just in case. + +(CMPQ x (MOVQconst [c])) && is32Bit(c) -> (CMPQconst x [c]) +(CMPQ (MOVQconst [c]) x) && is32Bit(c) -> (InvertFlags (CMPQconst x [c])) +(CMPL x (MOVLconst [c])) -> (CMPLconst x [c]) +(CMPL (MOVLconst [c]) x) -> (InvertFlags (CMPLconst x [c])) +(CMPW x (MOVWconst [c])) -> (CMPWconst x [c]) +(CMPW (MOVWconst [c]) x) -> (InvertFlags (CMPWconst x [c])) +(CMPB x (MOVBconst [c])) -> (CMPBconst x [c]) +(CMPB (MOVBconst [c]) x) -> (InvertFlags (CMPBconst x [c])) + +// strength reduction +(MULQconst [-1] x) -> (NEGQ x) +(MULQconst [0] _) -> (MOVQconst [0]) +(MULQconst [1] x) -> x +(MULQconst [3] x) -> (LEAQ2 x x) +(MULQconst [5] x) -> (LEAQ4 x x) +(MULQconst [9] x) -> (LEAQ8 x x) +(MULQconst [c] x) && isPowerOfTwo(c) -> (SHLQconst [log2(c)] x) + +// combine add/shift into LEAQ +(ADDQ x (SHLQconst [3] y)) -> (LEAQ8 x y) +(ADDQ x (SHLQconst [2] y)) -> (LEAQ4 x y) +(ADDQ x (SHLQconst [1] y)) -> (LEAQ2 x y) +(ADDQ x (ADDQ y y)) -> (LEAQ2 x y) +(ADDQ x (ADDQ x y)) -> (LEAQ2 y x) +(ADDQ x (ADDQ y x)) -> (LEAQ2 y x) + +// combine ADDQ/ADDQconst into LEAQ1 +(ADDQconst [c] (ADDQ x y)) -> (LEAQ1 [c] x y) +(ADDQ (ADDQconst [c] x) y) -> (LEAQ1 [c] x y) +(ADDQ x (ADDQconst [c] y)) -> (LEAQ1 [c] x y) + +// fold ADDQ into LEAQ +(ADDQconst [c] (LEAQ [d] {s} x)) -> (LEAQ [c+d] {s} x) +(LEAQ [c] {s} (ADDQconst [d] x)) -> (LEAQ [c+d] {s} x) +(LEAQ [c] {s} (ADDQ x y)) && x.Op != OpSB && y.Op != OpSB -> (LEAQ1 [c] {s} x y) +(ADDQ x (LEAQ [c] {s} y)) && x.Op != OpSB && y.Op != OpSB -> (LEAQ1 [c] {s} x y) +(ADDQ (LEAQ [c] {s} x) y) && x.Op != OpSB && y.Op != OpSB -> (LEAQ1 [c] {s} x y) + +// fold ADDQconst into leaqX +(ADDQconst [c] (LEAQ1 [d] {s} x y)) -> (LEAQ1 [c+d] {s} x y) +(ADDQconst [c] (LEAQ2 [d] {s} x y)) -> (LEAQ2 [c+d] {s} x y) +(ADDQconst [c] (LEAQ4 [d] {s} x y)) -> (LEAQ4 [c+d] {s} x y) +(ADDQconst [c] (LEAQ8 [d] {s} x y)) -> (LEAQ8 [c+d] {s} x y) +(LEAQ1 [c] {s} (ADDQconst [d] x) y) && x.Op != OpSB -> (LEAQ1 [c+d] {s} x y) +(LEAQ1 [c] {s} x (ADDQconst [d] y)) && y.Op != OpSB -> (LEAQ1 [c+d] {s} x y) +(LEAQ2 [c] {s} (ADDQconst [d] x) y) && x.Op != OpSB -> (LEAQ2 [c+d] {s} x y) +(LEAQ2 [c] {s} x (ADDQconst [d] y)) && y.Op != OpSB -> (LEAQ2 [c+2*d] {s} x y) +(LEAQ4 [c] {s} (ADDQconst [d] x) y) && x.Op != OpSB -> (LEAQ4 [c+d] {s} x y) +(LEAQ4 [c] {s} x (ADDQconst [d] y)) && y.Op != OpSB -> (LEAQ4 [c+4*d] {s} x y) +(LEAQ8 [c] {s} (ADDQconst [d] x) y) && x.Op != OpSB -> (LEAQ8 [c+d] {s} x y) +(LEAQ8 [c] {s} x (ADDQconst [d] y)) && y.Op != OpSB -> (LEAQ8 [c+8*d] {s} x y) + +// reverse ordering of compare instruction +(SETL (InvertFlags x)) -> (SETG x) +(SETG (InvertFlags x)) -> (SETL x) +(SETB (InvertFlags x)) -> (SETA x) +(SETA (InvertFlags x)) -> (SETB x) +(SETLE (InvertFlags x)) -> (SETGE x) +(SETGE (InvertFlags x)) -> (SETLE x) +(SETBE (InvertFlags x)) -> (SETAE x) +(SETAE (InvertFlags x)) -> (SETBE x) +(SETEQ (InvertFlags x)) -> (SETEQ x) +(SETNE (InvertFlags x)) -> (SETNE x) + +// sign extended loads +// Note: The combined instruction must end up in the same block +// as the original load. If not, we end up making a value with +// memory type live in two different blocks, which can lead to +// multiple memory values alive simultaneously. +(MOVBQSX (MOVBload [off] {sym} ptr mem)) -> @v.Args[0].Block (MOVBQSXload <v.Type> [off] {sym} ptr mem) +(MOVBQZX (MOVBload [off] {sym} ptr mem)) -> @v.Args[0].Block (MOVBQZXload <v.Type> [off] {sym} ptr mem) +(MOVWQSX (MOVWload [off] {sym} ptr mem)) -> @v.Args[0].Block (MOVWQSXload <v.Type> [off] {sym} ptr mem) +(MOVWQZX (MOVWload [off] {sym} ptr mem)) -> @v.Args[0].Block (MOVWQZXload <v.Type> [off] {sym} ptr mem) +(MOVLQSX (MOVLload [off] {sym} ptr mem)) -> @v.Args[0].Block (MOVLQSXload <v.Type> [off] {sym} ptr mem) +(MOVLQZX (MOVLload [off] {sym} ptr mem)) -> @v.Args[0].Block (MOVLQZXload <v.Type> [off] {sym} ptr mem) + +// replace load from same location as preceding store with copy +(MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x +(MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x +(MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x +(MOVQload [off] {sym} ptr (MOVQstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x + +// Fold extensions and ANDs together. +(MOVBQZX (ANDBconst [c] x)) -> (ANDQconst [c & 0xff] x) +(MOVWQZX (ANDWconst [c] x)) -> (ANDQconst [c & 0xffff] x) +(MOVLQZX (ANDLconst [c] x)) -> (ANDQconst [c & 0xffffffff] x) +(MOVBQSX (ANDBconst [c] x)) && c & 0x80 == 0 -> (ANDQconst [c & 0x7f] x) +(MOVWQSX (ANDWconst [c] x)) && c & 0x8000 == 0 -> (ANDQconst [c & 0x7fff] x) +(MOVLQSX (ANDLconst [c] x)) && c & 0x80000000 == 0 -> (ANDQconst [c & 0x7fffffff] x) + +// Don't extend before storing +(MOVLstore [off] {sym} ptr (MOVLQSX x) mem) -> (MOVLstore [off] {sym} ptr x mem) +(MOVWstore [off] {sym} ptr (MOVWQSX x) mem) -> (MOVWstore [off] {sym} ptr x mem) +(MOVBstore [off] {sym} ptr (MOVBQSX x) mem) -> (MOVBstore [off] {sym} ptr x mem) +(MOVLstore [off] {sym} ptr (MOVLQZX x) mem) -> (MOVLstore [off] {sym} ptr x mem) +(MOVWstore [off] {sym} ptr (MOVWQZX x) mem) -> (MOVWstore [off] {sym} ptr x mem) +(MOVBstore [off] {sym} ptr (MOVBQZX x) mem) -> (MOVBstore [off] {sym} ptr x mem) + +// fold constants into memory operations +// Note that this is not always a good idea because if not all the uses of +// the ADDQconst get eliminated, we still have to compute the ADDQconst and we now +// have potentially two live values (ptr and (ADDQconst [off] ptr)) instead of one. +// Nevertheless, let's do it! +(MOVQload [off1] {sym} (ADDQconst [off2] ptr) mem) -> (MOVQload [addOff(off1, off2)] {sym} ptr mem) +(MOVLload [off1] {sym} (ADDQconst [off2] ptr) mem) -> (MOVLload [addOff(off1, off2)] {sym} ptr mem) +(MOVWload [off1] {sym} (ADDQconst [off2] ptr) mem) -> (MOVWload [addOff(off1, off2)] {sym} ptr mem) +(MOVBload [off1] {sym} (ADDQconst [off2] ptr) mem) -> (MOVBload [addOff(off1, off2)] {sym} ptr mem) +(MOVSSload [off1] {sym} (ADDQconst [off2] ptr) mem) -> (MOVSSload [addOff(off1, off2)] {sym} ptr mem) +(MOVSDload [off1] {sym} (ADDQconst [off2] ptr) mem) -> (MOVSDload [addOff(off1, off2)] {sym} ptr mem) +(MOVOload [off1] {sym} (ADDQconst [off2] ptr) mem) -> (MOVOload [addOff(off1, off2)] {sym} ptr mem) + +(MOVQstore [off1] {sym} (ADDQconst [off2] ptr) val mem) -> (MOVQstore [addOff(off1, off2)] {sym} ptr val mem) +(MOVLstore [off1] {sym} (ADDQconst [off2] ptr) val mem) -> (MOVLstore [addOff(off1, off2)] {sym} ptr val mem) +(MOVWstore [off1] {sym} (ADDQconst [off2] ptr) val mem) -> (MOVWstore [addOff(off1, off2)] {sym} ptr val mem) +(MOVBstore [off1] {sym} (ADDQconst [off2] ptr) val mem) -> (MOVBstore [addOff(off1, off2)] {sym} ptr val mem) +(MOVSSstore [off1] {sym} (ADDQconst [off2] ptr) val mem) -> (MOVSSstore [addOff(off1, off2)] {sym} ptr val mem) +(MOVSDstore [off1] {sym} (ADDQconst [off2] ptr) val mem) -> (MOVSDstore [addOff(off1, off2)] {sym} ptr val mem) +(MOVOstore [off1] {sym} (ADDQconst [off2] ptr) val mem) -> (MOVOstore [addOff(off1, off2)] {sym} ptr val mem) + +// Fold constants into stores. +(MOVQstore [off] {sym} ptr (MOVQconst [c]) mem) && validValAndOff(c,off) -> + (MOVQstoreconst [makeValAndOff(c,off)] {sym} ptr mem) +(MOVLstore [off] {sym} ptr (MOVLconst [c]) mem) && validOff(off) -> + (MOVLstoreconst [makeValAndOff(int64(int32(c)),off)] {sym} ptr mem) +(MOVWstore [off] {sym} ptr (MOVWconst [c]) mem) && validOff(off) -> + (MOVWstoreconst [makeValAndOff(int64(int16(c)),off)] {sym} ptr mem) +(MOVBstore [off] {sym} ptr (MOVBconst [c]) mem) && validOff(off) -> + (MOVBstoreconst [makeValAndOff(int64(int8(c)),off)] {sym} ptr mem) + +// Fold address offsets into constant stores. +(MOVQstoreconst [sc] {s} (ADDQconst [off] ptr) mem) && ValAndOff(sc).canAdd(off) -> + (MOVQstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) +(MOVLstoreconst [sc] {s} (ADDQconst [off] ptr) mem) && ValAndOff(sc).canAdd(off) -> + (MOVLstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) +(MOVWstoreconst [sc] {s} (ADDQconst [off] ptr) mem) && ValAndOff(sc).canAdd(off) -> + (MOVWstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) +(MOVBstoreconst [sc] {s} (ADDQconst [off] ptr) mem) && ValAndOff(sc).canAdd(off) -> + (MOVBstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) + +// We need to fold LEAQ into the MOVx ops so that the live variable analysis knows +// what variables are being read/written by the ops. +(MOVQload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && canMergeSym(sym1, sym2) -> + (MOVQload [addOff(off1,off2)] {mergeSym(sym1,sym2)} base mem) +(MOVLload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && canMergeSym(sym1, sym2) -> + (MOVLload [addOff(off1,off2)] {mergeSym(sym1,sym2)} base mem) +(MOVWload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && canMergeSym(sym1, sym2) -> + (MOVWload [addOff(off1,off2)] {mergeSym(sym1,sym2)} base mem) +(MOVBload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && canMergeSym(sym1, sym2) -> + (MOVBload [addOff(off1,off2)] {mergeSym(sym1,sym2)} base mem) +(MOVSSload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && canMergeSym(sym1, sym2) -> + (MOVSSload [addOff(off1,off2)] {mergeSym(sym1,sym2)} base mem) +(MOVSDload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && canMergeSym(sym1, sym2) -> + (MOVSDload [addOff(off1,off2)] {mergeSym(sym1,sym2)} base mem) +(MOVOload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && canMergeSym(sym1, sym2) -> + (MOVOload [addOff(off1,off2)] {mergeSym(sym1,sym2)} base mem) + +(MOVQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) && canMergeSym(sym1, sym2) -> + (MOVQstore [addOff(off1,off2)] {mergeSym(sym1,sym2)} base val mem) +(MOVLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) && canMergeSym(sym1, sym2) -> + (MOVLstore [addOff(off1,off2)] {mergeSym(sym1,sym2)} base val mem) +(MOVWstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) && canMergeSym(sym1, sym2) -> + (MOVWstore [addOff(off1,off2)] {mergeSym(sym1,sym2)} base val mem) +(MOVBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) && canMergeSym(sym1, sym2) -> + (MOVBstore [addOff(off1,off2)] {mergeSym(sym1,sym2)} base val mem) +(MOVSSstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) && canMergeSym(sym1, sym2) -> + (MOVSSstore [addOff(off1,off2)] {mergeSym(sym1,sym2)} base val mem) +(MOVSDstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) && canMergeSym(sym1, sym2) -> + (MOVSDstore [addOff(off1,off2)] {mergeSym(sym1,sym2)} base val mem) +(MOVOstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) && canMergeSym(sym1, sym2) -> + (MOVOstore [addOff(off1,off2)] {mergeSym(sym1,sym2)} base val mem) + +(MOVQstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) -> + (MOVQstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) +(MOVLstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) -> + (MOVLstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) +(MOVWstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) -> + (MOVWstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) +(MOVBstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) -> + (MOVBstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) + +// generating indexed loads and stores +(MOVBload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) -> + (MOVBloadidx1 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx mem) +(MOVWload [off1] {sym1} (LEAQ2 [off2] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) -> + (MOVWloadidx2 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx mem) +(MOVLload [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) -> + (MOVLloadidx4 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx mem) +(MOVQload [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) -> + (MOVQloadidx8 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx mem) +(MOVSSload [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) -> + (MOVSSloadidx4 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx mem) +(MOVSDload [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) -> + (MOVSDloadidx8 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx mem) + +(MOVBstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) && canMergeSym(sym1, sym2) -> + (MOVBstoreidx1 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx val mem) +(MOVWstore [off1] {sym1} (LEAQ2 [off2] {sym2} ptr idx) val mem) && canMergeSym(sym1, sym2) -> + (MOVWstoreidx2 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx val mem) +(MOVLstore [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) val mem) && canMergeSym(sym1, sym2) -> + (MOVLstoreidx4 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx val mem) +(MOVQstore [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) val mem) && canMergeSym(sym1, sym2) -> + (MOVQstoreidx8 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx val mem) +(MOVSSstore [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) val mem) && canMergeSym(sym1, sym2) -> + (MOVSSstoreidx4 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx val mem) +(MOVSDstore [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) val mem) && canMergeSym(sym1, sym2) -> + (MOVSDstoreidx8 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx val mem) + +(MOVBload [off] {sym} (ADDQ ptr idx) mem) && ptr.Op != OpSB -> (MOVBloadidx1 [off] {sym} ptr idx mem) +(MOVBstore [off] {sym} (ADDQ ptr idx) val mem) && ptr.Op != OpSB -> (MOVBstoreidx1 [off] {sym} ptr idx val mem) + +(MOVBstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) -> + (MOVBstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) +(MOVWstoreconst [x] {sym1} (LEAQ2 [off] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) -> + (MOVWstoreconstidx2 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) +(MOVLstoreconst [x] {sym1} (LEAQ4 [off] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) -> + (MOVLstoreconstidx4 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) +(MOVQstoreconst [x] {sym1} (LEAQ8 [off] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) -> + (MOVQstoreconstidx8 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) +(MOVBstoreconst [x] {sym} (ADDQ ptr idx) mem) -> (MOVBstoreconstidx1 [x] {sym} ptr idx mem) + +// combine ADDQ into indexed loads and stores +(MOVBloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) -> (MOVBloadidx1 [c+d] {sym} ptr idx mem) +(MOVWloadidx2 [c] {sym} (ADDQconst [d] ptr) idx mem) -> (MOVWloadidx2 [c+d] {sym} ptr idx mem) +(MOVLloadidx4 [c] {sym} (ADDQconst [d] ptr) idx mem) -> (MOVLloadidx4 [c+d] {sym} ptr idx mem) +(MOVQloadidx8 [c] {sym} (ADDQconst [d] ptr) idx mem) -> (MOVQloadidx8 [c+d] {sym} ptr idx mem) +(MOVSSloadidx4 [c] {sym} (ADDQconst [d] ptr) idx mem) -> (MOVSSloadidx4 [c+d] {sym} ptr idx mem) +(MOVSDloadidx8 [c] {sym} (ADDQconst [d] ptr) idx mem) -> (MOVSDloadidx8 [c+d] {sym} ptr idx mem) + +(MOVBstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) -> (MOVBstoreidx1 [c+d] {sym} ptr idx val mem) +(MOVWstoreidx2 [c] {sym} (ADDQconst [d] ptr) idx val mem) -> (MOVWstoreidx2 [c+d] {sym} ptr idx val mem) +(MOVLstoreidx4 [c] {sym} (ADDQconst [d] ptr) idx val mem) -> (MOVLstoreidx4 [c+d] {sym} ptr idx val mem) +(MOVQstoreidx8 [c] {sym} (ADDQconst [d] ptr) idx val mem) -> (MOVQstoreidx8 [c+d] {sym} ptr idx val mem) +(MOVSSstoreidx4 [c] {sym} (ADDQconst [d] ptr) idx val mem) -> (MOVSSstoreidx4 [c+d] {sym} ptr idx val mem) +(MOVSDstoreidx8 [c] {sym} (ADDQconst [d] ptr) idx val mem) -> (MOVSDstoreidx8 [c+d] {sym} ptr idx val mem) + +(MOVBloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) -> (MOVBloadidx1 [c+d] {sym} ptr idx mem) +(MOVWloadidx2 [c] {sym} ptr (ADDQconst [d] idx) mem) -> (MOVWloadidx2 [c+2*d] {sym} ptr idx mem) +(MOVLloadidx4 [c] {sym} ptr (ADDQconst [d] idx) mem) -> (MOVLloadidx4 [c+4*d] {sym} ptr idx mem) +(MOVQloadidx8 [c] {sym} ptr (ADDQconst [d] idx) mem) -> (MOVQloadidx8 [c+8*d] {sym} ptr idx mem) +(MOVSSloadidx4 [c] {sym} ptr (ADDQconst [d] idx) mem) -> (MOVSSloadidx4 [c+4*d] {sym} ptr idx mem) +(MOVSDloadidx8 [c] {sym} ptr (ADDQconst [d] idx) mem) -> (MOVSDloadidx8 [c+8*d] {sym} ptr idx mem) + +(MOVBstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) -> (MOVBstoreidx1 [c+d] {sym} ptr idx val mem) +(MOVWstoreidx2 [c] {sym} ptr (ADDQconst [d] idx) val mem) -> (MOVWstoreidx2 [c+2*d] {sym} ptr idx val mem) +(MOVLstoreidx4 [c] {sym} ptr (ADDQconst [d] idx) val mem) -> (MOVLstoreidx4 [c+4*d] {sym} ptr idx val mem) +(MOVQstoreidx8 [c] {sym} ptr (ADDQconst [d] idx) val mem) -> (MOVQstoreidx8 [c+8*d] {sym} ptr idx val mem) +(MOVSSstoreidx4 [c] {sym} ptr (ADDQconst [d] idx) val mem) -> (MOVSSstoreidx4 [c+4*d] {sym} ptr idx val mem) +(MOVSDstoreidx8 [c] {sym} ptr (ADDQconst [d] idx) val mem) -> (MOVSDstoreidx8 [c+8*d] {sym} ptr idx val mem) + +(MOVBstoreconstidx1 [x] {sym} (ADDQconst [c] ptr) idx mem) -> + (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) +(MOVWstoreconstidx2 [x] {sym} (ADDQconst [c] ptr) idx mem) -> + (MOVWstoreconstidx2 [ValAndOff(x).add(c)] {sym} ptr idx mem) +(MOVLstoreconstidx4 [x] {sym} (ADDQconst [c] ptr) idx mem) -> + (MOVLstoreconstidx4 [ValAndOff(x).add(c)] {sym} ptr idx mem) +(MOVQstoreconstidx8 [x] {sym} (ADDQconst [c] ptr) idx mem) -> + (MOVQstoreconstidx8 [ValAndOff(x).add(c)] {sym} ptr idx mem) + +(MOVBstoreconstidx1 [x] {sym} ptr (ADDQconst [c] idx) mem) -> + (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) +(MOVWstoreconstidx2 [x] {sym} ptr (ADDQconst [c] idx) mem) -> + (MOVWstoreconstidx2 [ValAndOff(x).add(2*c)] {sym} ptr idx mem) +(MOVLstoreconstidx4 [x] {sym} ptr (ADDQconst [c] idx) mem) -> + (MOVLstoreconstidx4 [ValAndOff(x).add(4*c)] {sym} ptr idx mem) +(MOVQstoreconstidx8 [x] {sym} ptr (ADDQconst [c] idx) mem) -> + (MOVQstoreconstidx8 [ValAndOff(x).add(8*c)] {sym} ptr idx mem) + +// fold LEAQs together +(LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) && canMergeSym(sym1, sym2) -> + (LEAQ [addOff(off1,off2)] {mergeSym(sym1,sym2)} x) + +// LEAQ into LEAQ1 +(LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && canMergeSym(sym1, sym2) && x.Op != OpSB -> + (LEAQ1 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y) +(LEAQ1 [off1] {sym1} x (LEAQ [off2] {sym2} y)) && canMergeSym(sym1, sym2) && y.Op != OpSB -> + (LEAQ1 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y) + +// LEAQ1 into LEAQ +(LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y)) && canMergeSym(sym1, sym2) -> + (LEAQ1 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y) + +// LEAQ into LEAQ[248] +(LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && canMergeSym(sym1, sym2) && x.Op != OpSB -> + (LEAQ2 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y) +(LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && canMergeSym(sym1, sym2) && x.Op != OpSB -> + (LEAQ4 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y) +(LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && canMergeSym(sym1, sym2) && x.Op != OpSB -> + (LEAQ8 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y) + +// LEAQ[248] into LEAQ +(LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y)) && canMergeSym(sym1, sym2) -> + (LEAQ2 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y) +(LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y)) && canMergeSym(sym1, sym2) -> + (LEAQ4 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y) +(LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y)) && canMergeSym(sym1, sym2) -> + (LEAQ8 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y) + +// lower Zero instructions with word sizes +(Zero [0] _ mem) -> mem +(Zero [1] destptr mem) -> (MOVBstoreconst [0] destptr mem) +(Zero [2] destptr mem) -> (MOVWstoreconst [0] destptr mem) +(Zero [4] destptr mem) -> (MOVLstoreconst [0] destptr mem) +(Zero [8] destptr mem) -> (MOVQstoreconst [0] destptr mem) + +(Zero [3] destptr mem) -> + (MOVBstoreconst [makeValAndOff(0,2)] destptr + (MOVWstoreconst [0] destptr mem)) +(Zero [5] destptr mem) -> + (MOVBstoreconst [makeValAndOff(0,4)] destptr + (MOVLstoreconst [0] destptr mem)) +(Zero [6] destptr mem) -> + (MOVWstoreconst [makeValAndOff(0,4)] destptr + (MOVLstoreconst [0] destptr mem)) +(Zero [7] destptr mem) -> + (MOVLstoreconst [makeValAndOff(0,3)] destptr + (MOVLstoreconst [0] destptr mem)) + +// Strip off any fractional word zeroing. +(Zero [size] destptr mem) && size%8 != 0 && size > 8 -> + (Zero [size-size%8] (ADDQconst destptr [size%8]) + (MOVQstoreconst [0] destptr mem)) + +// Zero small numbers of words directly. +(Zero [16] destptr mem) -> + (MOVQstoreconst [makeValAndOff(0,8)] destptr + (MOVQstoreconst [0] destptr mem)) +(Zero [24] destptr mem) -> + (MOVQstoreconst [makeValAndOff(0,16)] destptr + (MOVQstoreconst [makeValAndOff(0,8)] destptr + (MOVQstoreconst [0] destptr mem))) +(Zero [32] destptr mem) -> + (MOVQstoreconst [makeValAndOff(0,24)] destptr + (MOVQstoreconst [makeValAndOff(0,16)] destptr + (MOVQstoreconst [makeValAndOff(0,8)] destptr + (MOVQstoreconst [0] destptr mem)))) + +// Medium zeroing uses a duff device. +(Zero [size] destptr mem) && size <= 1024 && size%8 == 0 && size%16 != 0 -> + (Zero [size-8] (ADDQconst [8] destptr) (MOVQstore destptr (MOVQconst [0]) mem)) +(Zero [size] destptr mem) && size <= 1024 && size%16 == 0 -> + (DUFFZERO [duffStart(size)] (ADDQconst [duffAdj(size)] destptr) (MOVOconst [0]) mem) + +// Large zeroing uses REP STOSQ. +(Zero [size] destptr mem) && size > 1024 && size%8 == 0 -> + (REPSTOSQ destptr (MOVQconst [size/8]) (MOVQconst [0]) mem) + +// Absorb InvertFlags into branches. +(LT (InvertFlags cmp) yes no) -> (GT cmp yes no) +(GT (InvertFlags cmp) yes no) -> (LT cmp yes no) +(LE (InvertFlags cmp) yes no) -> (GE cmp yes no) +(GE (InvertFlags cmp) yes no) -> (LE cmp yes no) +(ULT (InvertFlags cmp) yes no) -> (UGT cmp yes no) +(UGT (InvertFlags cmp) yes no) -> (ULT cmp yes no) +(ULE (InvertFlags cmp) yes no) -> (UGE cmp yes no) +(UGE (InvertFlags cmp) yes no) -> (ULE cmp yes no) +(EQ (InvertFlags cmp) yes no) -> (EQ cmp yes no) +(NE (InvertFlags cmp) yes no) -> (NE cmp yes no) + +// Constant comparisons. +(CMPQconst (MOVQconst [x]) [y]) && x==y -> (FlagEQ) +(CMPQconst (MOVQconst [x]) [y]) && x<y && uint64(x)<uint64(y) -> (FlagLT_ULT) +(CMPQconst (MOVQconst [x]) [y]) && x<y && uint64(x)>uint64(y) -> (FlagLT_UGT) +(CMPQconst (MOVQconst [x]) [y]) && x>y && uint64(x)<uint64(y) -> (FlagGT_ULT) +(CMPQconst (MOVQconst [x]) [y]) && x>y && uint64(x)>uint64(y) -> (FlagGT_UGT) +(CMPLconst (MOVLconst [x]) [y]) && int32(x)==int32(y) -> (FlagEQ) +(CMPLconst (MOVLconst [x]) [y]) && int32(x)<int32(y) && uint32(x)<uint32(y) -> (FlagLT_ULT) +(CMPLconst (MOVLconst [x]) [y]) && int32(x)<int32(y) && uint32(x)>uint32(y) -> (FlagLT_UGT) +(CMPLconst (MOVLconst [x]) [y]) && int32(x)>int32(y) && uint32(x)<uint32(y) -> (FlagGT_ULT) +(CMPLconst (MOVLconst [x]) [y]) && int32(x)>int32(y) && uint32(x)>uint32(y) -> (FlagGT_UGT) +(CMPWconst (MOVWconst [x]) [y]) && int16(x)==int16(y) -> (FlagEQ) +(CMPWconst (MOVWconst [x]) [y]) && int16(x)<int16(y) && uint16(x)<uint16(y) -> (FlagLT_ULT) +(CMPWconst (MOVWconst [x]) [y]) && int16(x)<int16(y) && uint16(x)>uint16(y) -> (FlagLT_UGT) +(CMPWconst (MOVWconst [x]) [y]) && int16(x)>int16(y) && uint16(x)<uint16(y) -> (FlagGT_ULT) +(CMPWconst (MOVWconst [x]) [y]) && int16(x)>int16(y) && uint16(x)>uint16(y) -> (FlagGT_UGT) +(CMPBconst (MOVBconst [x]) [y]) && int8(x)==int8(y) -> (FlagEQ) +(CMPBconst (MOVBconst [x]) [y]) && int8(x)<int8(y) && uint8(x)<uint8(y) -> (FlagLT_ULT) +(CMPBconst (MOVBconst [x]) [y]) && int8(x)<int8(y) && uint8(x)>uint8(y) -> (FlagLT_UGT) +(CMPBconst (MOVBconst [x]) [y]) && int8(x)>int8(y) && uint8(x)<uint8(y) -> (FlagGT_ULT) +(CMPBconst (MOVBconst [x]) [y]) && int8(x)>int8(y) && uint8(x)>uint8(y) -> (FlagGT_UGT) + +// Other known comparisons. +(CMPQconst (ANDQconst _ [m]) [n]) && m+1==n && isPowerOfTwo(n) -> (FlagLT_ULT) +(CMPLconst (ANDLconst _ [m]) [n]) && int32(m)+1==int32(n) && isPowerOfTwo(int64(int32(n))) -> (FlagLT_ULT) +(CMPWconst (ANDWconst _ [m]) [n]) && int16(m)+1==int16(n) && isPowerOfTwo(int64(int16(n))) -> (FlagLT_ULT) +(CMPBconst (ANDBconst _ [m]) [n]) && int8(m)+1==int8(n) && isPowerOfTwo(int64(int8(n))) -> (FlagLT_ULT) +// TODO: DIVxU also. + +// Absorb flag constants into SBB ops. +(SBBQcarrymask (FlagEQ)) -> (MOVQconst [0]) +(SBBQcarrymask (FlagLT_ULT)) -> (MOVQconst [-1]) +(SBBQcarrymask (FlagLT_UGT)) -> (MOVQconst [0]) +(SBBQcarrymask (FlagGT_ULT)) -> (MOVQconst [-1]) +(SBBQcarrymask (FlagGT_UGT)) -> (MOVQconst [0]) +(SBBLcarrymask (FlagEQ)) -> (MOVLconst [0]) +(SBBLcarrymask (FlagLT_ULT)) -> (MOVLconst [-1]) +(SBBLcarrymask (FlagLT_UGT)) -> (MOVLconst [0]) +(SBBLcarrymask (FlagGT_ULT)) -> (MOVLconst [-1]) +(SBBLcarrymask (FlagGT_UGT)) -> (MOVLconst [0]) + +// Absorb flag constants into branches. +(EQ (FlagEQ) yes no) -> (First nil yes no) +(EQ (FlagLT_ULT) yes no) -> (First nil no yes) +(EQ (FlagLT_UGT) yes no) -> (First nil no yes) +(EQ (FlagGT_ULT) yes no) -> (First nil no yes) +(EQ (FlagGT_UGT) yes no) -> (First nil no yes) + +(NE (FlagEQ) yes no) -> (First nil no yes) +(NE (FlagLT_ULT) yes no) -> (First nil yes no) +(NE (FlagLT_UGT) yes no) -> (First nil yes no) +(NE (FlagGT_ULT) yes no) -> (First nil yes no) +(NE (FlagGT_UGT) yes no) -> (First nil yes no) + +(LT (FlagEQ) yes no) -> (First nil no yes) +(LT (FlagLT_ULT) yes no) -> (First nil yes no) +(LT (FlagLT_UGT) yes no) -> (First nil yes no) +(LT (FlagGT_ULT) yes no) -> (First nil no yes) +(LT (FlagGT_UGT) yes no) -> (First nil no yes) + +(LE (FlagEQ) yes no) -> (First nil yes no) +(LE (FlagLT_ULT) yes no) -> (First nil yes no) +(LE (FlagLT_UGT) yes no) -> (First nil yes no) +(LE (FlagGT_ULT) yes no) -> (First nil no yes) +(LE (FlagGT_UGT) yes no) -> (First nil no yes) + +(GT (FlagEQ) yes no) -> (First nil no yes) +(GT (FlagLT_ULT) yes no) -> (First nil no yes) +(GT (FlagLT_UGT) yes no) -> (First nil no yes) +(GT (FlagGT_ULT) yes no) -> (First nil yes no) +(GT (FlagGT_UGT) yes no) -> (First nil yes no) + +(GE (FlagEQ) yes no) -> (First nil yes no) +(GE (FlagLT_ULT) yes no) -> (First nil no yes) +(GE (FlagLT_UGT) yes no) -> (First nil no yes) +(GE (FlagGT_ULT) yes no) -> (First nil yes no) +(GE (FlagGT_UGT) yes no) -> (First nil yes no) + +(ULT (FlagEQ) yes no) -> (First nil no yes) +(ULT (FlagLT_ULT) yes no) -> (First nil yes no) +(ULT (FlagLT_UGT) yes no) -> (First nil no yes) +(ULT (FlagGT_ULT) yes no) -> (First nil yes no) +(ULT (FlagGT_UGT) yes no) -> (First nil no yes) + +(ULE (FlagEQ) yes no) -> (First nil yes no) +(ULE (FlagLT_ULT) yes no) -> (First nil yes no) +(ULE (FlagLT_UGT) yes no) -> (First nil no yes) +(ULE (FlagGT_ULT) yes no) -> (First nil yes no) +(ULE (FlagGT_UGT) yes no) -> (First nil no yes) + +(UGT (FlagEQ) yes no) -> (First nil no yes) +(UGT (FlagLT_ULT) yes no) -> (First nil no yes) +(UGT (FlagLT_UGT) yes no) -> (First nil yes no) +(UGT (FlagGT_ULT) yes no) -> (First nil no yes) +(UGT (FlagGT_UGT) yes no) -> (First nil yes no) + +(UGE (FlagEQ) yes no) -> (First nil yes no) +(UGE (FlagLT_ULT) yes no) -> (First nil no yes) +(UGE (FlagLT_UGT) yes no) -> (First nil yes no) +(UGE (FlagGT_ULT) yes no) -> (First nil no yes) +(UGE (FlagGT_UGT) yes no) -> (First nil yes no) + +// Absorb flag constants into SETxx ops. +(SETEQ (FlagEQ)) -> (MOVBconst [1]) +(SETEQ (FlagLT_ULT)) -> (MOVBconst [0]) +(SETEQ (FlagLT_UGT)) -> (MOVBconst [0]) +(SETEQ (FlagGT_ULT)) -> (MOVBconst [0]) +(SETEQ (FlagGT_UGT)) -> (MOVBconst [0]) + +(SETNE (FlagEQ)) -> (MOVBconst [0]) +(SETNE (FlagLT_ULT)) -> (MOVBconst [1]) +(SETNE (FlagLT_UGT)) -> (MOVBconst [1]) +(SETNE (FlagGT_ULT)) -> (MOVBconst [1]) +(SETNE (FlagGT_UGT)) -> (MOVBconst [1]) + +(SETL (FlagEQ)) -> (MOVBconst [0]) +(SETL (FlagLT_ULT)) -> (MOVBconst [1]) +(SETL (FlagLT_UGT)) -> (MOVBconst [1]) +(SETL (FlagGT_ULT)) -> (MOVBconst [0]) +(SETL (FlagGT_UGT)) -> (MOVBconst [0]) + +(SETLE (FlagEQ)) -> (MOVBconst [1]) +(SETLE (FlagLT_ULT)) -> (MOVBconst [1]) +(SETLE (FlagLT_UGT)) -> (MOVBconst [1]) +(SETLE (FlagGT_ULT)) -> (MOVBconst [0]) +(SETLE (FlagGT_UGT)) -> (MOVBconst [0]) + +(SETG (FlagEQ)) -> (MOVBconst [0]) +(SETG (FlagLT_ULT)) -> (MOVBconst [0]) +(SETG (FlagLT_UGT)) -> (MOVBconst [0]) +(SETG (FlagGT_ULT)) -> (MOVBconst [1]) +(SETG (FlagGT_UGT)) -> (MOVBconst [1]) + +(SETGE (FlagEQ)) -> (MOVBconst [1]) +(SETGE (FlagLT_ULT)) -> (MOVBconst [0]) +(SETGE (FlagLT_UGT)) -> (MOVBconst [0]) +(SETGE (FlagGT_ULT)) -> (MOVBconst [1]) +(SETGE (FlagGT_UGT)) -> (MOVBconst [1]) + +(SETB (FlagEQ)) -> (MOVBconst [0]) +(SETB (FlagLT_ULT)) -> (MOVBconst [1]) +(SETB (FlagLT_UGT)) -> (MOVBconst [0]) +(SETB (FlagGT_ULT)) -> (MOVBconst [1]) +(SETB (FlagGT_UGT)) -> (MOVBconst [0]) + +(SETBE (FlagEQ)) -> (MOVBconst [1]) +(SETBE (FlagLT_ULT)) -> (MOVBconst [1]) +(SETBE (FlagLT_UGT)) -> (MOVBconst [0]) +(SETBE (FlagGT_ULT)) -> (MOVBconst [1]) +(SETBE (FlagGT_UGT)) -> (MOVBconst [0]) + +(SETA (FlagEQ)) -> (MOVBconst [0]) +(SETA (FlagLT_ULT)) -> (MOVBconst [0]) +(SETA (FlagLT_UGT)) -> (MOVBconst [1]) +(SETA (FlagGT_ULT)) -> (MOVBconst [0]) +(SETA (FlagGT_UGT)) -> (MOVBconst [1]) + +(SETAE (FlagEQ)) -> (MOVBconst [1]) +(SETAE (FlagLT_ULT)) -> (MOVBconst [0]) +(SETAE (FlagLT_UGT)) -> (MOVBconst [1]) +(SETAE (FlagGT_ULT)) -> (MOVBconst [0]) +(SETAE (FlagGT_UGT)) -> (MOVBconst [1]) + +// Remove redundant *const ops +(ADDQconst [0] x) -> x +(ADDLconst [c] x) && int32(c)==0 -> x +(ADDWconst [c] x) && int16(c)==0 -> x +(ADDBconst [c] x) && int8(c)==0 -> x +(SUBQconst [0] x) -> x +(SUBLconst [c] x) && int32(c) == 0 -> x +(SUBWconst [c] x) && int16(c) == 0 -> x +(SUBBconst [c] x) && int8(c) == 0 -> x +(ANDQconst [0] _) -> (MOVQconst [0]) +(ANDLconst [c] _) && int32(c)==0 -> (MOVLconst [0]) +(ANDWconst [c] _) && int16(c)==0 -> (MOVWconst [0]) +(ANDBconst [c] _) && int8(c)==0 -> (MOVBconst [0]) +(ANDQconst [-1] x) -> x +(ANDLconst [c] x) && int32(c)==-1 -> x +(ANDWconst [c] x) && int16(c)==-1 -> x +(ANDBconst [c] x) && int8(c)==-1 -> x +(ORQconst [0] x) -> x +(ORLconst [c] x) && int32(c)==0 -> x +(ORWconst [c] x) && int16(c)==0 -> x +(ORBconst [c] x) && int8(c)==0 -> x +(ORQconst [-1] _) -> (MOVQconst [-1]) +(ORLconst [c] _) && int32(c)==-1 -> (MOVLconst [-1]) +(ORWconst [c] _) && int16(c)==-1 -> (MOVWconst [-1]) +(ORBconst [c] _) && int8(c)==-1 -> (MOVBconst [-1]) +(XORQconst [0] x) -> x +(XORLconst [c] x) && int32(c)==0 -> x +(XORWconst [c] x) && int16(c)==0 -> x +(XORBconst [c] x) && int8(c)==0 -> x + +// generic constant folding +// TODO: more of this +(ADDQconst [c] (MOVQconst [d])) -> (MOVQconst [c+d]) +(ADDLconst [c] (MOVLconst [d])) -> (MOVLconst [c+d]) +(ADDWconst [c] (MOVWconst [d])) -> (MOVWconst [c+d]) +(ADDBconst [c] (MOVBconst [d])) -> (MOVBconst [c+d]) +(ADDQconst [c] (ADDQconst [d] x)) -> (ADDQconst [c+d] x) +(ADDLconst [c] (ADDLconst [d] x)) -> (ADDLconst [c+d] x) +(ADDWconst [c] (ADDWconst [d] x)) -> (ADDWconst [c+d] x) +(ADDBconst [c] (ADDBconst [d] x)) -> (ADDBconst [c+d] x) +(SUBQconst [c] (MOVQconst [d])) -> (MOVQconst [d-c]) +(SUBLconst [c] (MOVLconst [d])) -> (MOVLconst [d-c]) +(SUBWconst [c] (MOVWconst [d])) -> (MOVWconst [d-c]) +(SUBBconst [c] (MOVBconst [d])) -> (MOVBconst [d-c]) +(SUBQconst [c] (SUBQconst [d] x)) -> (ADDQconst [-c-d] x) +(SUBLconst [c] (SUBLconst [d] x)) -> (ADDLconst [-c-d] x) +(SUBWconst [c] (SUBWconst [d] x)) -> (ADDWconst [-c-d] x) +(SUBBconst [c] (SUBBconst [d] x)) -> (ADDBconst [-c-d] x) +(SARQconst [c] (MOVQconst [d])) -> (MOVQconst [d>>uint64(c)]) +(SARLconst [c] (MOVQconst [d])) -> (MOVQconst [d>>uint64(c)]) +(SARWconst [c] (MOVQconst [d])) -> (MOVQconst [d>>uint64(c)]) +(SARBconst [c] (MOVQconst [d])) -> (MOVQconst [d>>uint64(c)]) +(NEGQ (MOVQconst [c])) -> (MOVQconst [-c]) +(NEGL (MOVLconst [c])) -> (MOVLconst [-c]) +(NEGW (MOVWconst [c])) -> (MOVWconst [-c]) +(NEGB (MOVBconst [c])) -> (MOVBconst [-c]) +(MULQconst [c] (MOVQconst [d])) -> (MOVQconst [c*d]) +(MULLconst [c] (MOVLconst [d])) -> (MOVLconst [c*d]) +(MULWconst [c] (MOVWconst [d])) -> (MOVWconst [c*d]) +(MULBconst [c] (MOVBconst [d])) -> (MOVBconst [c*d]) +(ANDQconst [c] (MOVQconst [d])) -> (MOVQconst [c&d]) +(ANDLconst [c] (MOVLconst [d])) -> (MOVLconst [c&d]) +(ANDWconst [c] (MOVWconst [d])) -> (MOVWconst [c&d]) +(ANDBconst [c] (MOVBconst [d])) -> (MOVBconst [c&d]) +(ORQconst [c] (MOVQconst [d])) -> (MOVQconst [c|d]) +(ORLconst [c] (MOVLconst [d])) -> (MOVLconst [c|d]) +(ORWconst [c] (MOVWconst [d])) -> (MOVWconst [c|d]) +(ORBconst [c] (MOVBconst [d])) -> (MOVBconst [c|d]) +(XORQconst [c] (MOVQconst [d])) -> (MOVQconst [c^d]) +(XORLconst [c] (MOVLconst [d])) -> (MOVLconst [c^d]) +(XORWconst [c] (MOVWconst [d])) -> (MOVWconst [c^d]) +(XORBconst [c] (MOVBconst [d])) -> (MOVBconst [c^d]) +(NOTQ (MOVQconst [c])) -> (MOVQconst [^c]) +(NOTL (MOVLconst [c])) -> (MOVLconst [^c]) +(NOTW (MOVWconst [c])) -> (MOVWconst [^c]) +(NOTB (MOVBconst [c])) -> (MOVBconst [^c]) + +// generic simplifications +// TODO: more of this +(ADDQ x (NEGQ y)) -> (SUBQ x y) +(ADDL x (NEGL y)) -> (SUBL x y) +(ADDW x (NEGW y)) -> (SUBW x y) +(ADDB x (NEGB y)) -> (SUBB x y) +(SUBQ x x) -> (MOVQconst [0]) +(SUBL x x) -> (MOVLconst [0]) +(SUBW x x) -> (MOVWconst [0]) +(SUBB x x) -> (MOVBconst [0]) +(ANDQ x x) -> x +(ANDL x x) -> x +(ANDW x x) -> x +(ANDB x x) -> x +(ORQ x x) -> x +(ORL x x) -> x +(ORW x x) -> x +(ORB x x) -> x +(XORQ x x) -> (MOVQconst [0]) +(XORL x x) -> (MOVLconst [0]) +(XORW x x) -> (MOVWconst [0]) +(XORB x x) -> (MOVBconst [0]) + +// checking AND against 0. +(CMPQconst (ANDQ x y) [0]) -> (TESTQ x y) +(CMPLconst (ANDL x y) [0]) -> (TESTL x y) +(CMPWconst (ANDW x y) [0]) -> (TESTW x y) +(CMPBconst (ANDB x y) [0]) -> (TESTB x y) +(CMPQconst (ANDQconst [c] x) [0]) -> (TESTQconst [c] x) +(CMPLconst (ANDLconst [c] x) [0]) -> (TESTLconst [c] x) +(CMPWconst (ANDWconst [c] x) [0]) -> (TESTWconst [c] x) +(CMPBconst (ANDBconst [c] x) [0]) -> (TESTBconst [c] x) diff --git a/src/cmd/compile/internal/ssa/gen/AMD64Ops.go b/src/cmd/compile/internal/ssa/gen/AMD64Ops.go new file mode 100644 index 0000000000..af08d18978 --- /dev/null +++ b/src/cmd/compile/internal/ssa/gen/AMD64Ops.go @@ -0,0 +1,535 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package main + +import "strings" + +// copied from ../../amd64/reg.go +var regNamesAMD64 = []string{ + ".AX", + ".CX", + ".DX", + ".BX", + ".SP", + ".BP", + ".SI", + ".DI", + ".R8", + ".R9", + ".R10", + ".R11", + ".R12", + ".R13", + ".R14", + ".R15", + ".X0", + ".X1", + ".X2", + ".X3", + ".X4", + ".X5", + ".X6", + ".X7", + ".X8", + ".X9", + ".X10", + ".X11", + ".X12", + ".X13", + ".X14", + ".X15", + + // pseudo-registers + ".SB", + ".FLAGS", +} + +func init() { + // Make map from reg names to reg integers. + if len(regNamesAMD64) > 64 { + panic("too many registers") + } + num := map[string]int{} + for i, name := range regNamesAMD64 { + if name[0] != '.' { + panic("register name " + name + " does not start with '.'") + } + num[name[1:]] = i + } + buildReg := func(s string) regMask { + m := regMask(0) + for _, r := range strings.Split(s, " ") { + if n, ok := num[r]; ok { + m |= regMask(1) << uint(n) + continue + } + panic("register " + r + " not found") + } + return m + } + + // Common individual register masks + var ( + ax = buildReg("AX") + cx = buildReg("CX") + dx = buildReg("DX") + x15 = buildReg("X15") + gp = buildReg("AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15") + fp = buildReg("X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15") + gpsp = gp | buildReg("SP") + gpspsb = gpsp | buildReg("SB") + flags = buildReg("FLAGS") + callerSave = gp | fp | flags + ) + // Common slices of register masks + var ( + gponly = []regMask{gp} + fponly = []regMask{fp} + flagsonly = []regMask{flags} + ) + + // Common regInfo + var ( + gp01 = regInfo{inputs: []regMask{}, outputs: gponly} + gp11 = regInfo{inputs: []regMask{gpsp}, outputs: gponly, clobbers: flags} + gp11nf = regInfo{inputs: []regMask{gpsp}, outputs: gponly} // nf: no flags clobbered + gp11sb = regInfo{inputs: []regMask{gpspsb}, outputs: gponly} + gp21 = regInfo{inputs: []regMask{gpsp, gpsp}, outputs: gponly, clobbers: flags} + gp21sb = regInfo{inputs: []regMask{gpspsb, gpsp}, outputs: gponly} + gp21shift = regInfo{inputs: []regMask{gpsp, cx}, outputs: []regMask{gp &^ cx}, clobbers: flags} + gp11div = regInfo{inputs: []regMask{ax, gpsp &^ dx}, outputs: []regMask{ax}, + clobbers: dx | flags} + gp11hmul = regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx}, + clobbers: ax | flags} + gp11mod = regInfo{inputs: []regMask{ax, gpsp &^ dx}, outputs: []regMask{dx}, + clobbers: ax | flags} + + gp2flags = regInfo{inputs: []regMask{gpsp, gpsp}, outputs: flagsonly} + gp1flags = regInfo{inputs: []regMask{gpsp}, outputs: flagsonly} + flagsgp = regInfo{inputs: flagsonly, outputs: gponly} + readflags = regInfo{inputs: flagsonly, outputs: gponly} + flagsgpax = regInfo{inputs: flagsonly, clobbers: ax | flags, outputs: []regMask{gp &^ ax}} + + gpload = regInfo{inputs: []regMask{gpspsb, 0}, outputs: gponly} + gploadidx = regInfo{inputs: []regMask{gpspsb, gpsp, 0}, outputs: gponly} + + gpstore = regInfo{inputs: []regMask{gpspsb, gpsp, 0}} + gpstoreconst = regInfo{inputs: []regMask{gpspsb, 0}} + gpstoreidx = regInfo{inputs: []regMask{gpspsb, gpsp, gpsp, 0}} + gpstoreconstidx = regInfo{inputs: []regMask{gpspsb, gpsp, 0}} + + fp01 = regInfo{inputs: []regMask{}, outputs: fponly} + fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: fponly} + fp21x15 = regInfo{inputs: []regMask{fp &^ x15, fp &^ x15}, + clobbers: x15, outputs: []regMask{fp &^ x15}} + fpgp = regInfo{inputs: fponly, outputs: gponly} + gpfp = regInfo{inputs: gponly, outputs: fponly} + fp11 = regInfo{inputs: fponly, outputs: fponly} + fp2flags = regInfo{inputs: []regMask{fp, fp}, outputs: flagsonly} + // fp1flags = regInfo{inputs: fponly, outputs: flagsonly} + + fpload = regInfo{inputs: []regMask{gpspsb, 0}, outputs: fponly} + fploadidx = regInfo{inputs: []regMask{gpspsb, gpsp, 0}, outputs: fponly} + + fpstore = regInfo{inputs: []regMask{gpspsb, fp, 0}} + fpstoreidx = regInfo{inputs: []regMask{gpspsb, gpsp, fp, 0}} + ) + // TODO: most ops clobber flags + + // Suffixes encode the bit width of various instructions. + // Q = 64 bit, L = 32 bit, W = 16 bit, B = 8 bit + + // TODO: 2-address instructions. Mark ops as needing matching input/output regs. + var AMD64ops = []opData{ + // fp ops + {name: "ADDSS", argLength: 2, reg: fp21, asm: "ADDSS"}, // fp32 add + {name: "ADDSD", argLength: 2, reg: fp21, asm: "ADDSD"}, // fp64 add + {name: "SUBSS", argLength: 2, reg: fp21x15, asm: "SUBSS"}, // fp32 sub + {name: "SUBSD", argLength: 2, reg: fp21x15, asm: "SUBSD"}, // fp64 sub + {name: "MULSS", argLength: 2, reg: fp21, asm: "MULSS"}, // fp32 mul + {name: "MULSD", argLength: 2, reg: fp21, asm: "MULSD"}, // fp64 mul + {name: "DIVSS", argLength: 2, reg: fp21x15, asm: "DIVSS"}, // fp32 div + {name: "DIVSD", argLength: 2, reg: fp21x15, asm: "DIVSD"}, // fp64 div + + {name: "MOVSSload", argLength: 2, reg: fpload, asm: "MOVSS", aux: "SymOff"}, // fp32 load + {name: "MOVSDload", argLength: 2, reg: fpload, asm: "MOVSD", aux: "SymOff"}, // fp64 load + {name: "MOVSSconst", reg: fp01, asm: "MOVSS", aux: "Float", rematerializeable: true}, // fp32 constant + {name: "MOVSDconst", reg: fp01, asm: "MOVSD", aux: "Float", rematerializeable: true}, // fp64 constant + {name: "MOVSSloadidx4", argLength: 3, reg: fploadidx, asm: "MOVSS", aux: "SymOff"}, // fp32 load + {name: "MOVSDloadidx8", argLength: 3, reg: fploadidx, asm: "MOVSD", aux: "SymOff"}, // fp64 load + + {name: "MOVSSstore", argLength: 3, reg: fpstore, asm: "MOVSS", aux: "SymOff"}, // fp32 store + {name: "MOVSDstore", argLength: 3, reg: fpstore, asm: "MOVSD", aux: "SymOff"}, // fp64 store + {name: "MOVSSstoreidx4", argLength: 4, reg: fpstoreidx, asm: "MOVSS", aux: "SymOff"}, // fp32 indexed by 4i store + {name: "MOVSDstoreidx8", argLength: 4, reg: fpstoreidx, asm: "MOVSD", aux: "SymOff"}, // fp64 indexed by 8i store + + // binary ops + {name: "ADDQ", argLength: 2, reg: gp21, asm: "ADDQ"}, // arg0 + arg1 + {name: "ADDL", argLength: 2, reg: gp21, asm: "ADDL"}, // arg0 + arg1 + {name: "ADDW", argLength: 2, reg: gp21, asm: "ADDL"}, // arg0 + arg1 + {name: "ADDB", argLength: 2, reg: gp21, asm: "ADDL"}, // arg0 + arg1 + {name: "ADDQconst", argLength: 1, reg: gp11, asm: "ADDQ", aux: "Int64", typ: "UInt64"}, // arg0 + auxint + {name: "ADDLconst", argLength: 1, reg: gp11, asm: "ADDL", aux: "Int32"}, // arg0 + auxint + {name: "ADDWconst", argLength: 1, reg: gp11, asm: "ADDL", aux: "Int16"}, // arg0 + auxint + {name: "ADDBconst", argLength: 1, reg: gp11, asm: "ADDL", aux: "Int8"}, // arg0 + auxint + + {name: "SUBQ", argLength: 2, reg: gp21, asm: "SUBQ"}, // arg0 - arg1 + {name: "SUBL", argLength: 2, reg: gp21, asm: "SUBL"}, // arg0 - arg1 + {name: "SUBW", argLength: 2, reg: gp21, asm: "SUBL"}, // arg0 - arg1 + {name: "SUBB", argLength: 2, reg: gp21, asm: "SUBL"}, // arg0 - arg1 + {name: "SUBQconst", argLength: 1, reg: gp11, asm: "SUBQ", aux: "Int64"}, // arg0 - auxint + {name: "SUBLconst", argLength: 1, reg: gp11, asm: "SUBL", aux: "Int32"}, // arg0 - auxint + {name: "SUBWconst", argLength: 1, reg: gp11, asm: "SUBL", aux: "Int16"}, // arg0 - auxint + {name: "SUBBconst", argLength: 1, reg: gp11, asm: "SUBL", aux: "Int8"}, // arg0 - auxint + + {name: "MULQ", argLength: 2, reg: gp21, asm: "IMULQ"}, // arg0 * arg1 + {name: "MULL", argLength: 2, reg: gp21, asm: "IMULL"}, // arg0 * arg1 + {name: "MULW", argLength: 2, reg: gp21, asm: "IMULW"}, // arg0 * arg1 + {name: "MULB", argLength: 2, reg: gp21, asm: "IMULW"}, // arg0 * arg1 + {name: "MULQconst", argLength: 1, reg: gp11, asm: "IMULQ", aux: "Int64"}, // arg0 * auxint + {name: "MULLconst", argLength: 1, reg: gp11, asm: "IMULL", aux: "Int32"}, // arg0 * auxint + {name: "MULWconst", argLength: 1, reg: gp11, asm: "IMULW", aux: "Int16"}, // arg0 * auxint + {name: "MULBconst", argLength: 1, reg: gp11, asm: "IMULW", aux: "Int8"}, // arg0 * auxint + + {name: "HMULQ", argLength: 2, reg: gp11hmul, asm: "IMULQ"}, // (arg0 * arg1) >> width + {name: "HMULL", argLength: 2, reg: gp11hmul, asm: "IMULL"}, // (arg0 * arg1) >> width + {name: "HMULW", argLength: 2, reg: gp11hmul, asm: "IMULW"}, // (arg0 * arg1) >> width + {name: "HMULB", argLength: 2, reg: gp11hmul, asm: "IMULB"}, // (arg0 * arg1) >> width + {name: "HMULQU", argLength: 2, reg: gp11hmul, asm: "MULQ"}, // (arg0 * arg1) >> width + {name: "HMULLU", argLength: 2, reg: gp11hmul, asm: "MULL"}, // (arg0 * arg1) >> width + {name: "HMULWU", argLength: 2, reg: gp11hmul, asm: "MULW"}, // (arg0 * arg1) >> width + {name: "HMULBU", argLength: 2, reg: gp11hmul, asm: "MULB"}, // (arg0 * arg1) >> width + + {name: "AVGQU", argLength: 2, reg: gp21}, // (arg0 + arg1) / 2 as unsigned, all 64 result bits + + {name: "DIVQ", argLength: 2, reg: gp11div, asm: "IDIVQ"}, // arg0 / arg1 + {name: "DIVL", argLength: 2, reg: gp11div, asm: "IDIVL"}, // arg0 / arg1 + {name: "DIVW", argLength: 2, reg: gp11div, asm: "IDIVW"}, // arg0 / arg1 + {name: "DIVQU", argLength: 2, reg: gp11div, asm: "DIVQ"}, // arg0 / arg1 + {name: "DIVLU", argLength: 2, reg: gp11div, asm: "DIVL"}, // arg0 / arg1 + {name: "DIVWU", argLength: 2, reg: gp11div, asm: "DIVW"}, // arg0 / arg1 + + {name: "MODQ", argLength: 2, reg: gp11mod, asm: "IDIVQ"}, // arg0 % arg1 + {name: "MODL", argLength: 2, reg: gp11mod, asm: "IDIVL"}, // arg0 % arg1 + {name: "MODW", argLength: 2, reg: gp11mod, asm: "IDIVW"}, // arg0 % arg1 + {name: "MODQU", argLength: 2, reg: gp11mod, asm: "DIVQ"}, // arg0 % arg1 + {name: "MODLU", argLength: 2, reg: gp11mod, asm: "DIVL"}, // arg0 % arg1 + {name: "MODWU", argLength: 2, reg: gp11mod, asm: "DIVW"}, // arg0 % arg1 + + {name: "ANDQ", argLength: 2, reg: gp21, asm: "ANDQ"}, // arg0 & arg1 + {name: "ANDL", argLength: 2, reg: gp21, asm: "ANDL"}, // arg0 & arg1 + {name: "ANDW", argLength: 2, reg: gp21, asm: "ANDL"}, // arg0 & arg1 + {name: "ANDB", argLength: 2, reg: gp21, asm: "ANDL"}, // arg0 & arg1 + {name: "ANDQconst", argLength: 1, reg: gp11, asm: "ANDQ", aux: "Int64"}, // arg0 & auxint + {name: "ANDLconst", argLength: 1, reg: gp11, asm: "ANDL", aux: "Int32"}, // arg0 & auxint + {name: "ANDWconst", argLength: 1, reg: gp11, asm: "ANDL", aux: "Int16"}, // arg0 & auxint + {name: "ANDBconst", argLength: 1, reg: gp11, asm: "ANDL", aux: "Int8"}, // arg0 & auxint + + {name: "ORQ", argLength: 2, reg: gp21, asm: "ORQ"}, // arg0 | arg1 + {name: "ORL", argLength: 2, reg: gp21, asm: "ORL"}, // arg0 | arg1 + {name: "ORW", argLength: 2, reg: gp21, asm: "ORL"}, // arg0 | arg1 + {name: "ORB", argLength: 2, reg: gp21, asm: "ORL"}, // arg0 | arg1 + {name: "ORQconst", argLength: 1, reg: gp11, asm: "ORQ", aux: "Int64"}, // arg0 | auxint + {name: "ORLconst", argLength: 1, reg: gp11, asm: "ORL", aux: "Int32"}, // arg0 | auxint + {name: "ORWconst", argLength: 1, reg: gp11, asm: "ORL", aux: "Int16"}, // arg0 | auxint + {name: "ORBconst", argLength: 1, reg: gp11, asm: "ORL", aux: "Int8"}, // arg0 | auxint + + {name: "XORQ", argLength: 2, reg: gp21, asm: "XORQ"}, // arg0 ^ arg1 + {name: "XORL", argLength: 2, reg: gp21, asm: "XORL"}, // arg0 ^ arg1 + {name: "XORW", argLength: 2, reg: gp21, asm: "XORL"}, // arg0 ^ arg1 + {name: "XORB", argLength: 2, reg: gp21, asm: "XORL"}, // arg0 ^ arg1 + {name: "XORQconst", argLength: 1, reg: gp11, asm: "XORQ", aux: "Int64"}, // arg0 ^ auxint + {name: "XORLconst", argLength: 1, reg: gp11, asm: "XORL", aux: "Int32"}, // arg0 ^ auxint + {name: "XORWconst", argLength: 1, reg: gp11, asm: "XORL", aux: "Int16"}, // arg0 ^ auxint + {name: "XORBconst", argLength: 1, reg: gp11, asm: "XORL", aux: "Int8"}, // arg0 ^ auxint + + {name: "CMPQ", argLength: 2, reg: gp2flags, asm: "CMPQ", typ: "Flags"}, // arg0 compare to arg1 + {name: "CMPL", argLength: 2, reg: gp2flags, asm: "CMPL", typ: "Flags"}, // arg0 compare to arg1 + {name: "CMPW", argLength: 2, reg: gp2flags, asm: "CMPW", typ: "Flags"}, // arg0 compare to arg1 + {name: "CMPB", argLength: 2, reg: gp2flags, asm: "CMPB", typ: "Flags"}, // arg0 compare to arg1 + {name: "CMPQconst", argLength: 1, reg: gp1flags, asm: "CMPQ", typ: "Flags", aux: "Int64"}, // arg0 compare to auxint + {name: "CMPLconst", argLength: 1, reg: gp1flags, asm: "CMPL", typ: "Flags", aux: "Int32"}, // arg0 compare to auxint + {name: "CMPWconst", argLength: 1, reg: gp1flags, asm: "CMPW", typ: "Flags", aux: "Int16"}, // arg0 compare to auxint + {name: "CMPBconst", argLength: 1, reg: gp1flags, asm: "CMPB", typ: "Flags", aux: "Int8"}, // arg0 compare to auxint + + {name: "UCOMISS", argLength: 2, reg: fp2flags, asm: "UCOMISS", typ: "Flags"}, // arg0 compare to arg1, f32 + {name: "UCOMISD", argLength: 2, reg: fp2flags, asm: "UCOMISD", typ: "Flags"}, // arg0 compare to arg1, f64 + + {name: "TESTQ", argLength: 2, reg: gp2flags, asm: "TESTQ", typ: "Flags"}, // (arg0 & arg1) compare to 0 + {name: "TESTL", argLength: 2, reg: gp2flags, asm: "TESTL", typ: "Flags"}, // (arg0 & arg1) compare to 0 + {name: "TESTW", argLength: 2, reg: gp2flags, asm: "TESTW", typ: "Flags"}, // (arg0 & arg1) compare to 0 + {name: "TESTB", argLength: 2, reg: gp2flags, asm: "TESTB", typ: "Flags"}, // (arg0 & arg1) compare to 0 + {name: "TESTQconst", argLength: 1, reg: gp1flags, asm: "TESTQ", typ: "Flags", aux: "Int64"}, // (arg0 & auxint) compare to 0 + {name: "TESTLconst", argLength: 1, reg: gp1flags, asm: "TESTL", typ: "Flags", aux: "Int32"}, // (arg0 & auxint) compare to 0 + {name: "TESTWconst", argLength: 1, reg: gp1flags, asm: "TESTW", typ: "Flags", aux: "Int16"}, // (arg0 & auxint) compare to 0 + {name: "TESTBconst", argLength: 1, reg: gp1flags, asm: "TESTB", typ: "Flags", aux: "Int8"}, // (arg0 & auxint) compare to 0 + + {name: "SHLQ", argLength: 2, reg: gp21shift, asm: "SHLQ"}, // arg0 << arg1, shift amount is mod 64 + {name: "SHLL", argLength: 2, reg: gp21shift, asm: "SHLL"}, // arg0 << arg1, shift amount is mod 32 + {name: "SHLW", argLength: 2, reg: gp21shift, asm: "SHLL"}, // arg0 << arg1, shift amount is mod 32 + {name: "SHLB", argLength: 2, reg: gp21shift, asm: "SHLL"}, // arg0 << arg1, shift amount is mod 32 + {name: "SHLQconst", argLength: 1, reg: gp11, asm: "SHLQ", aux: "Int64"}, // arg0 << auxint, shift amount 0-63 + {name: "SHLLconst", argLength: 1, reg: gp11, asm: "SHLL", aux: "Int32"}, // arg0 << auxint, shift amount 0-31 + {name: "SHLWconst", argLength: 1, reg: gp11, asm: "SHLL", aux: "Int16"}, // arg0 << auxint, shift amount 0-31 + {name: "SHLBconst", argLength: 1, reg: gp11, asm: "SHLL", aux: "Int8"}, // arg0 << auxint, shift amount 0-31 + // Note: x86 is weird, the 16 and 8 byte shifts still use all 5 bits of shift amount! + + {name: "SHRQ", argLength: 2, reg: gp21shift, asm: "SHRQ"}, // unsigned arg0 >> arg1, shift amount is mod 64 + {name: "SHRL", argLength: 2, reg: gp21shift, asm: "SHRL"}, // unsigned arg0 >> arg1, shift amount is mod 32 + {name: "SHRW", argLength: 2, reg: gp21shift, asm: "SHRW"}, // unsigned arg0 >> arg1, shift amount is mod 32 + {name: "SHRB", argLength: 2, reg: gp21shift, asm: "SHRB"}, // unsigned arg0 >> arg1, shift amount is mod 32 + {name: "SHRQconst", argLength: 1, reg: gp11, asm: "SHRQ", aux: "Int64"}, // unsigned arg0 >> auxint, shift amount 0-63 + {name: "SHRLconst", argLength: 1, reg: gp11, asm: "SHRL", aux: "Int32"}, // unsigned arg0 >> auxint, shift amount 0-31 + {name: "SHRWconst", argLength: 1, reg: gp11, asm: "SHRW", aux: "Int16"}, // unsigned arg0 >> auxint, shift amount 0-31 + {name: "SHRBconst", argLength: 1, reg: gp11, asm: "SHRB", aux: "Int8"}, // unsigned arg0 >> auxint, shift amount 0-31 + + {name: "SARQ", argLength: 2, reg: gp21shift, asm: "SARQ"}, // signed arg0 >> arg1, shift amount is mod 64 + {name: "SARL", argLength: 2, reg: gp21shift, asm: "SARL"}, // signed arg0 >> arg1, shift amount is mod 32 + {name: "SARW", argLength: 2, reg: gp21shift, asm: "SARW"}, // signed arg0 >> arg1, shift amount is mod 32 + {name: "SARB", argLength: 2, reg: gp21shift, asm: "SARB"}, // signed arg0 >> arg1, shift amount is mod 32 + {name: "SARQconst", argLength: 1, reg: gp11, asm: "SARQ", aux: "Int64"}, // signed arg0 >> auxint, shift amount 0-63 + {name: "SARLconst", argLength: 1, reg: gp11, asm: "SARL", aux: "Int32"}, // signed arg0 >> auxint, shift amount 0-31 + {name: "SARWconst", argLength: 1, reg: gp11, asm: "SARW", aux: "Int16"}, // signed arg0 >> auxint, shift amount 0-31 + {name: "SARBconst", argLength: 1, reg: gp11, asm: "SARB", aux: "Int8"}, // signed arg0 >> auxint, shift amount 0-31 + + {name: "ROLQconst", argLength: 1, reg: gp11, asm: "ROLQ", aux: "Int64"}, // arg0 rotate left auxint, rotate amount 0-63 + {name: "ROLLconst", argLength: 1, reg: gp11, asm: "ROLL", aux: "Int32"}, // arg0 rotate left auxint, rotate amount 0-31 + {name: "ROLWconst", argLength: 1, reg: gp11, asm: "ROLW", aux: "Int16"}, // arg0 rotate left auxint, rotate amount 0-15 + {name: "ROLBconst", argLength: 1, reg: gp11, asm: "ROLB", aux: "Int8"}, // arg0 rotate left auxint, rotate amount 0-7 + + // unary ops + {name: "NEGQ", argLength: 1, reg: gp11, asm: "NEGQ"}, // -arg0 + {name: "NEGL", argLength: 1, reg: gp11, asm: "NEGL"}, // -arg0 + {name: "NEGW", argLength: 1, reg: gp11, asm: "NEGL"}, // -arg0 + {name: "NEGB", argLength: 1, reg: gp11, asm: "NEGL"}, // -arg0 + + {name: "NOTQ", argLength: 1, reg: gp11, asm: "NOTQ"}, // ^arg0 + {name: "NOTL", argLength: 1, reg: gp11, asm: "NOTL"}, // ^arg0 + {name: "NOTW", argLength: 1, reg: gp11, asm: "NOTL"}, // ^arg0 + {name: "NOTB", argLength: 1, reg: gp11, asm: "NOTL"}, // ^arg0 + + {name: "SQRTSD", argLength: 1, reg: fp11, asm: "SQRTSD"}, // sqrt(arg0) + + {name: "SBBQcarrymask", argLength: 1, reg: flagsgp, asm: "SBBQ"}, // (int64)(-1) if carry is set, 0 if carry is clear. + {name: "SBBLcarrymask", argLength: 1, reg: flagsgp, asm: "SBBL"}, // (int32)(-1) if carry is set, 0 if carry is clear. + // Note: SBBW and SBBB are subsumed by SBBL + + {name: "SETEQ", argLength: 1, reg: readflags, asm: "SETEQ"}, // extract == condition from arg0 + {name: "SETNE", argLength: 1, reg: readflags, asm: "SETNE"}, // extract != condition from arg0 + {name: "SETL", argLength: 1, reg: readflags, asm: "SETLT"}, // extract signed < condition from arg0 + {name: "SETLE", argLength: 1, reg: readflags, asm: "SETLE"}, // extract signed <= condition from arg0 + {name: "SETG", argLength: 1, reg: readflags, asm: "SETGT"}, // extract signed > condition from arg0 + {name: "SETGE", argLength: 1, reg: readflags, asm: "SETGE"}, // extract signed >= condition from arg0 + {name: "SETB", argLength: 1, reg: readflags, asm: "SETCS"}, // extract unsigned < condition from arg0 + {name: "SETBE", argLength: 1, reg: readflags, asm: "SETLS"}, // extract unsigned <= condition from arg0 + {name: "SETA", argLength: 1, reg: readflags, asm: "SETHI"}, // extract unsigned > condition from arg0 + {name: "SETAE", argLength: 1, reg: readflags, asm: "SETCC"}, // extract unsigned >= condition from arg0 + // Need different opcodes for floating point conditions because + // any comparison involving a NaN is always FALSE and thus + // the patterns for inverting conditions cannot be used. + {name: "SETEQF", argLength: 1, reg: flagsgpax, asm: "SETEQ"}, // extract == condition from arg0 + {name: "SETNEF", argLength: 1, reg: flagsgpax, asm: "SETNE"}, // extract != condition from arg0 + {name: "SETORD", argLength: 1, reg: flagsgp, asm: "SETPC"}, // extract "ordered" (No Nan present) condition from arg0 + {name: "SETNAN", argLength: 1, reg: flagsgp, asm: "SETPS"}, // extract "unordered" (Nan present) condition from arg0 + + {name: "SETGF", argLength: 1, reg: flagsgp, asm: "SETHI"}, // extract floating > condition from arg0 + {name: "SETGEF", argLength: 1, reg: flagsgp, asm: "SETCC"}, // extract floating >= condition from arg0 + + {name: "MOVBQSX", argLength: 1, reg: gp11nf, asm: "MOVBQSX"}, // sign extend arg0 from int8 to int64 + {name: "MOVBQZX", argLength: 1, reg: gp11nf, asm: "MOVBQZX"}, // zero extend arg0 from int8 to int64 + {name: "MOVWQSX", argLength: 1, reg: gp11nf, asm: "MOVWQSX"}, // sign extend arg0 from int16 to int64 + {name: "MOVWQZX", argLength: 1, reg: gp11nf, asm: "MOVWQZX"}, // zero extend arg0 from int16 to int64 + {name: "MOVLQSX", argLength: 1, reg: gp11nf, asm: "MOVLQSX"}, // sign extend arg0 from int32 to int64 + {name: "MOVLQZX", argLength: 1, reg: gp11nf, asm: "MOVLQZX"}, // zero extend arg0 from int32 to int64 + + {name: "MOVBconst", reg: gp01, asm: "MOVB", typ: "UInt8", aux: "Int8", rematerializeable: true}, // 8 low bits of auxint + {name: "MOVWconst", reg: gp01, asm: "MOVW", typ: "UInt16", aux: "Int16", rematerializeable: true}, // 16 low bits of auxint + {name: "MOVLconst", reg: gp01, asm: "MOVL", typ: "UInt32", aux: "Int32", rematerializeable: true}, // 32 low bits of auxint + {name: "MOVQconst", reg: gp01, asm: "MOVQ", typ: "UInt64", aux: "Int64", rematerializeable: true}, // auxint + + {name: "CVTTSD2SL", argLength: 1, reg: fpgp, asm: "CVTTSD2SL"}, // convert float64 to int32 + {name: "CVTTSD2SQ", argLength: 1, reg: fpgp, asm: "CVTTSD2SQ"}, // convert float64 to int64 + {name: "CVTTSS2SL", argLength: 1, reg: fpgp, asm: "CVTTSS2SL"}, // convert float32 to int32 + {name: "CVTTSS2SQ", argLength: 1, reg: fpgp, asm: "CVTTSS2SQ"}, // convert float32 to int64 + {name: "CVTSL2SS", argLength: 1, reg: gpfp, asm: "CVTSL2SS"}, // convert int32 to float32 + {name: "CVTSL2SD", argLength: 1, reg: gpfp, asm: "CVTSL2SD"}, // convert int32 to float64 + {name: "CVTSQ2SS", argLength: 1, reg: gpfp, asm: "CVTSQ2SS"}, // convert int64 to float32 + {name: "CVTSQ2SD", argLength: 1, reg: gpfp, asm: "CVTSQ2SD"}, // convert int64 to float64 + {name: "CVTSD2SS", argLength: 1, reg: fp11, asm: "CVTSD2SS"}, // convert float64 to float32 + {name: "CVTSS2SD", argLength: 1, reg: fp11, asm: "CVTSS2SD"}, // convert float32 to float64 + + {name: "PXOR", argLength: 2, reg: fp21, asm: "PXOR"}, // exclusive or, applied to X regs for float negation. + + {name: "LEAQ", argLength: 1, reg: gp11sb, aux: "SymOff", rematerializeable: true}, // arg0 + auxint + offset encoded in aux + {name: "LEAQ1", argLength: 2, reg: gp21sb, aux: "SymOff"}, // arg0 + arg1 + auxint + aux + {name: "LEAQ2", argLength: 2, reg: gp21sb, aux: "SymOff"}, // arg0 + 2*arg1 + auxint + aux + {name: "LEAQ4", argLength: 2, reg: gp21sb, aux: "SymOff"}, // arg0 + 4*arg1 + auxint + aux + {name: "LEAQ8", argLength: 2, reg: gp21sb, aux: "SymOff"}, // arg0 + 8*arg1 + auxint + aux + // Note: LEAQ{1,2,4,8} must not have OpSB as either argument. + + // auxint+aux == add auxint and the offset of the symbol in aux (if any) to the effective address + {name: "MOVBload", argLength: 2, reg: gpload, asm: "MOVBLZX", aux: "SymOff", typ: "UInt8"}, // load byte from arg0+auxint+aux. arg1=mem + {name: "MOVBQSXload", argLength: 2, reg: gpload, asm: "MOVBQSX", aux: "SymOff"}, // ditto, extend to int64 + {name: "MOVBQZXload", argLength: 2, reg: gpload, asm: "MOVBQZX", aux: "SymOff"}, // ditto, extend to uint64 + {name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVWLZX", aux: "SymOff", typ: "UInt16"}, // load 2 bytes from arg0+auxint+aux. arg1=mem + {name: "MOVWQSXload", argLength: 2, reg: gpload, asm: "MOVWQSX", aux: "SymOff"}, // ditto, extend to int64 + {name: "MOVWQZXload", argLength: 2, reg: gpload, asm: "MOVWQZX", aux: "SymOff"}, // ditto, extend to uint64 + {name: "MOVLload", argLength: 2, reg: gpload, asm: "MOVL", aux: "SymOff", typ: "UInt32"}, // load 4 bytes from arg0+auxint+aux. arg1=mem + {name: "MOVLQSXload", argLength: 2, reg: gpload, asm: "MOVLQSX", aux: "SymOff"}, // ditto, extend to int64 + {name: "MOVLQZXload", argLength: 2, reg: gpload, asm: "MOVLQZX", aux: "SymOff"}, // ditto, extend to uint64 + {name: "MOVQload", argLength: 2, reg: gpload, asm: "MOVQ", aux: "SymOff", typ: "UInt64"}, // load 8 bytes from arg0+auxint+aux. arg1=mem + {name: "MOVBstore", argLength: 3, reg: gpstore, asm: "MOVB", aux: "SymOff", typ: "Mem"}, // store byte in arg1 to arg0+auxint+aux. arg2=mem + {name: "MOVWstore", argLength: 3, reg: gpstore, asm: "MOVW", aux: "SymOff", typ: "Mem"}, // store 2 bytes in arg1 to arg0+auxint+aux. arg2=mem + {name: "MOVLstore", argLength: 3, reg: gpstore, asm: "MOVL", aux: "SymOff", typ: "Mem"}, // store 4 bytes in arg1 to arg0+auxint+aux. arg2=mem + {name: "MOVQstore", argLength: 3, reg: gpstore, asm: "MOVQ", aux: "SymOff", typ: "Mem"}, // store 8 bytes in arg1 to arg0+auxint+aux. arg2=mem + {name: "MOVOload", argLength: 2, reg: fpload, asm: "MOVUPS", aux: "SymOff", typ: "Int128"}, // load 16 bytes from arg0+auxint+aux. arg1=mem + {name: "MOVOstore", argLength: 3, reg: fpstore, asm: "MOVUPS", aux: "SymOff", typ: "Mem"}, // store 16 bytes in arg1 to arg0+auxint+aux. arg2=mem + + // indexed loads/stores + {name: "MOVBloadidx1", argLength: 3, reg: gploadidx, asm: "MOVBLZX", aux: "SymOff"}, // load a byte from arg0+arg1+auxint+aux. arg2=mem + {name: "MOVWloadidx2", argLength: 3, reg: gploadidx, asm: "MOVWLZX", aux: "SymOff"}, // load 2 bytes from arg0+2*arg1+auxint+aux. arg2=mem + {name: "MOVLloadidx4", argLength: 3, reg: gploadidx, asm: "MOVL", aux: "SymOff"}, // load 4 bytes from arg0+4*arg1+auxint+aux. arg2=mem + {name: "MOVQloadidx8", argLength: 3, reg: gploadidx, asm: "MOVQ", aux: "SymOff"}, // load 8 bytes from arg0+8*arg1+auxint+aux. arg2=mem + // TODO: sign-extending indexed loads + {name: "MOVBstoreidx1", argLength: 4, reg: gpstoreidx, asm: "MOVB", aux: "SymOff"}, // store byte in arg2 to arg0+arg1+auxint+aux. arg3=mem + {name: "MOVWstoreidx2", argLength: 4, reg: gpstoreidx, asm: "MOVW", aux: "SymOff"}, // store 2 bytes in arg2 to arg0+2*arg1+auxint+aux. arg3=mem + {name: "MOVLstoreidx4", argLength: 4, reg: gpstoreidx, asm: "MOVL", aux: "SymOff"}, // store 4 bytes in arg2 to arg0+4*arg1+auxint+aux. arg3=mem + {name: "MOVQstoreidx8", argLength: 4, reg: gpstoreidx, asm: "MOVQ", aux: "SymOff"}, // store 8 bytes in arg2 to arg0+8*arg1+auxint+aux. arg3=mem + // TODO: add size-mismatched indexed loads, like MOVBstoreidx4. + + // For storeconst ops, the AuxInt field encodes both + // the value to store and an address offset of the store. + // Cast AuxInt to a ValAndOff to extract Val and Off fields. + {name: "MOVBstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVB", aux: "SymValAndOff", typ: "Mem"}, // store low byte of ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux. arg1=mem + {name: "MOVWstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVW", aux: "SymValAndOff", typ: "Mem"}, // store low 2 bytes of ... + {name: "MOVLstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVL", aux: "SymValAndOff", typ: "Mem"}, // store low 4 bytes of ... + {name: "MOVQstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVQ", aux: "SymValAndOff", typ: "Mem"}, // store 8 bytes of ... + + {name: "MOVBstoreconstidx1", argLength: 3, reg: gpstoreconstidx, asm: "MOVB", aux: "SymValAndOff", typ: "Mem"}, // store low byte of ValAndOff(AuxInt).Val() to arg0+1*arg1+ValAndOff(AuxInt).Off()+aux. arg2=mem + {name: "MOVWstoreconstidx2", argLength: 3, reg: gpstoreconstidx, asm: "MOVW", aux: "SymValAndOff", typ: "Mem"}, // store low 2 bytes of ... 2*arg1 ... + {name: "MOVLstoreconstidx4", argLength: 3, reg: gpstoreconstidx, asm: "MOVL", aux: "SymValAndOff", typ: "Mem"}, // store low 4 bytes of ... 4*arg1 ... + {name: "MOVQstoreconstidx8", argLength: 3, reg: gpstoreconstidx, asm: "MOVQ", aux: "SymValAndOff", typ: "Mem"}, // store 8 bytes of ... 8*arg1 ... + + // arg0 = (duff-adjusted) pointer to start of memory to zero + // arg1 = value to store (will always be zero) + // arg2 = mem + // auxint = offset into duffzero code to start executing + // returns mem + { + name: "DUFFZERO", + aux: "Int64", + argLength: 3, + reg: regInfo{ + inputs: []regMask{buildReg("DI"), buildReg("X0")}, + clobbers: buildReg("DI FLAGS"), + }, + }, + {name: "MOVOconst", reg: regInfo{nil, 0, []regMask{fp}}, typ: "Int128", rematerializeable: true}, + + // arg0 = address of memory to zero + // arg1 = # of 8-byte words to zero + // arg2 = value to store (will always be zero) + // arg3 = mem + // returns mem + { + name: "REPSTOSQ", + argLength: 4, + reg: regInfo{ + inputs: []regMask{buildReg("DI"), buildReg("CX"), buildReg("AX")}, + clobbers: buildReg("DI CX FLAGS"), + }, + }, + + {name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "SymOff"}, // call static function aux.(*gc.Sym). arg0=mem, auxint=argsize, returns mem + {name: "CALLclosure", argLength: 3, reg: regInfo{[]regMask{gpsp, buildReg("DX"), 0}, callerSave, nil}, aux: "Int64"}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem + {name: "CALLdefer", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64"}, // call deferproc. arg0=mem, auxint=argsize, returns mem + {name: "CALLgo", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64"}, // call newproc. arg0=mem, auxint=argsize, returns mem + {name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "Int64"}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem + + // arg0 = destination pointer + // arg1 = source pointer + // arg2 = mem + // auxint = offset from duffcopy symbol to call + // returns memory + { + name: "DUFFCOPY", + aux: "Int64", + argLength: 3, + reg: regInfo{ + inputs: []regMask{buildReg("DI"), buildReg("SI")}, + clobbers: buildReg("DI SI X0 FLAGS"), // uses X0 as a temporary + }, + }, + + // arg0 = destination pointer + // arg1 = source pointer + // arg2 = # of 8-byte words to copy + // arg3 = mem + // returns memory + { + name: "REPMOVSQ", + argLength: 4, + reg: regInfo{ + inputs: []regMask{buildReg("DI"), buildReg("SI"), buildReg("CX")}, + clobbers: buildReg("DI SI CX"), + }, + }, + + // (InvertFlags (CMPQ a b)) == (CMPQ b a) + // So if we want (SETL (CMPQ a b)) but we can't do that because a is a constant, + // then we do (SETL (InvertFlags (CMPQ b a))) instead. + // Rewrites will convert this to (SETG (CMPQ b a)). + // InvertFlags is a pseudo-op which can't appear in assembly output. + {name: "InvertFlags", argLength: 1}, // reverse direction of arg0 + + // Pseudo-ops + {name: "LoweredGetG", argLength: 1, reg: gp01}, // arg0=mem + // Scheduler ensures LoweredGetClosurePtr occurs only in entry block, + // and sorts it to the very beginning of the block to prevent other + // use of DX (the closure pointer) + {name: "LoweredGetClosurePtr", reg: regInfo{outputs: []regMask{buildReg("DX")}}}, + //arg0=ptr,arg1=mem, returns void. Faults if ptr is nil. + {name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gpsp}, clobbers: flags}}, + + // MOVQconvert converts between pointers and integers. + // We have a special op for this so as to not confuse GC + // (particularly stack maps). It takes a memory arg so it + // gets correctly ordered with respect to GC safepoints. + // arg0=ptr/int arg1=mem, output=int/ptr + {name: "MOVQconvert", argLength: 2, reg: gp11nf, asm: "MOVQ"}, + + // Constant flag values. For any comparison, there are 5 possible + // outcomes: the three from the signed total order (<,==,>) and the + // three from the unsigned total order. The == cases overlap. + // Note: there's a sixth "unordered" outcome for floating-point + // comparisons, but we don't use such a beast yet. + // These ops are for temporary use by rewrite rules. They + // cannot appear in the generated assembly. + {name: "FlagEQ"}, // equal + {name: "FlagLT_ULT"}, // signed < and unsigned < + {name: "FlagLT_UGT"}, // signed < and unsigned > + {name: "FlagGT_UGT"}, // signed > and unsigned < + {name: "FlagGT_ULT"}, // signed > and unsigned > + } + + var AMD64blocks = []blockData{ + {name: "EQ"}, + {name: "NE"}, + {name: "LT"}, + {name: "LE"}, + {name: "GT"}, + {name: "GE"}, + {name: "ULT"}, + {name: "ULE"}, + {name: "UGT"}, + {name: "UGE"}, + {name: "EQF"}, + {name: "NEF"}, + {name: "ORD"}, // FP, ordered comparison (parity zero) + {name: "NAN"}, // FP, unordered comparison (parity one) + } + + archs = append(archs, arch{"AMD64", AMD64ops, AMD64blocks, regNamesAMD64}) +} diff --git a/src/cmd/compile/internal/ssa/gen/README b/src/cmd/compile/internal/ssa/gen/README new file mode 100644 index 0000000000..6731b970b3 --- /dev/null +++ b/src/cmd/compile/internal/ssa/gen/README @@ -0,0 +1,7 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +This package generates opcode tables, rewrite rules, etc. for the ssa compiler. +Run it with: + go run *.go diff --git a/src/cmd/compile/internal/ssa/gen/generic.rules b/src/cmd/compile/internal/ssa/gen/generic.rules new file mode 100644 index 0000000000..11c7b9d7a1 --- /dev/null +++ b/src/cmd/compile/internal/ssa/gen/generic.rules @@ -0,0 +1,740 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// values are specified using the following format: +// (op <type> [auxint] {aux} arg0 arg1 ...) +// the type and aux fields are optional +// on the matching side +// - the type, aux, and auxint fields must match if they are specified. +// on the generated side +// - the type of the top-level expression is the same as the one on the left-hand side. +// - the type of any subexpressions must be specified explicitly. +// - auxint will be 0 if not specified. +// - aux will be nil if not specified. + +// blocks are specified using the following format: +// (kind controlvalue succ0 succ1 ...) +// controlvalue must be "nil" or a value expression +// succ* fields must be variables +// For now, the generated successors must be a permutation of the matched successors. + +// constant folding +(Trunc16to8 (Const16 [c])) -> (Const8 [int64(int8(c))]) +(Trunc32to8 (Const32 [c])) -> (Const8 [int64(int8(c))]) +(Trunc32to16 (Const32 [c])) -> (Const16 [int64(int16(c))]) +(Trunc64to8 (Const64 [c])) -> (Const8 [int64(int8(c))]) +(Trunc64to16 (Const64 [c])) -> (Const16 [int64(int16(c))]) +(Trunc64to32 (Const64 [c])) -> (Const32 [int64(int32(c))]) + +(Neg8 (Const8 [c])) -> (Const8 [-c]) +(Neg16 (Const16 [c])) -> (Const16 [-c]) +(Neg32 (Const32 [c])) -> (Const32 [-c]) +(Neg64 (Const64 [c])) -> (Const64 [-c]) + +(Add8 (Const8 [c]) (Const8 [d])) -> (Const8 [c+d]) +(Add16 (Const16 [c]) (Const16 [d])) -> (Const16 [c+d]) +(Add32 (Const32 [c]) (Const32 [d])) -> (Const32 [c+d]) +(Add64 (Const64 [c]) (Const64 [d])) -> (Const64 [c+d]) + +(Sub8 (Const8 [c]) (Const8 [d])) -> (Const8 [c-d]) +(Sub16 (Const16 [c]) (Const16 [d])) -> (Const16 [c-d]) +(Sub32 (Const32 [c]) (Const32 [d])) -> (Const32 [c-d]) +(Sub64 (Const64 [c]) (Const64 [d])) -> (Const64 [c-d]) + +(Mul8 (Const8 [c]) (Const8 [d])) -> (Const8 [c*d]) +(Mul16 (Const16 [c]) (Const16 [d])) -> (Const16 [c*d]) +(Mul32 (Const32 [c]) (Const32 [d])) -> (Const32 [c*d]) +(Mul64 (Const64 [c]) (Const64 [d])) -> (Const64 [c*d]) + +(Lsh64x64 (Const64 [c]) (Const64 [d])) -> (Const64 [c << uint64(d)]) +(Rsh64x64 (Const64 [c]) (Const64 [d])) -> (Const64 [c >> uint64(d)]) +(Rsh64Ux64 (Const64 [c]) (Const64 [d])) -> (Const64 [int64(uint64(c) >> uint64(d))]) +(Lsh32x64 (Const32 [c]) (Const64 [d])) -> (Const32 [int64(int32(c) << uint64(d))]) +(Rsh32x64 (Const32 [c]) (Const64 [d])) -> (Const32 [int64(int32(c) >> uint64(d))]) +(Rsh32Ux64 (Const32 [c]) (Const64 [d])) -> (Const32 [int64(uint32(c) >> uint64(d))]) +(Lsh16x64 (Const16 [c]) (Const64 [d])) -> (Const16 [int64(int16(c) << uint64(d))]) +(Rsh16x64 (Const16 [c]) (Const64 [d])) -> (Const16 [int64(int16(c) >> uint64(d))]) +(Rsh16Ux64 (Const16 [c]) (Const64 [d])) -> (Const16 [int64(uint16(c) >> uint64(d))]) +(Lsh8x64 (Const8 [c]) (Const64 [d])) -> (Const8 [int64(int8(c) << uint64(d))]) +(Rsh8x64 (Const8 [c]) (Const64 [d])) -> (Const8 [int64(int8(c) >> uint64(d))]) +(Rsh8Ux64 (Const8 [c]) (Const64 [d])) -> (Const8 [int64(uint8(c) >> uint64(d))]) + +(Lsh64x64 (Const64 [0]) _) -> (Const64 [0]) +(Rsh64x64 (Const64 [0]) _) -> (Const64 [0]) +(Rsh64Ux64 (Const64 [0]) _) -> (Const64 [0]) +(Lsh32x64 (Const32 [0]) _) -> (Const32 [0]) +(Rsh32x64 (Const32 [0]) _) -> (Const32 [0]) +(Rsh32Ux64 (Const32 [0]) _) -> (Const32 [0]) +(Lsh16x64 (Const16 [0]) _) -> (Const16 [0]) +(Rsh16x64 (Const16 [0]) _) -> (Const16 [0]) +(Rsh16Ux64 (Const16 [0]) _) -> (Const16 [0]) +(Lsh8x64 (Const8 [0]) _) -> (Const8 [0]) +(Rsh8x64 (Const8 [0]) _) -> (Const8 [0]) +(Rsh8Ux64 (Const8 [0]) _) -> (Const8 [0]) + +(IsInBounds (Const32 [c]) (Const32 [d])) -> (ConstBool [b2i(inBounds32(c,d))]) +(IsInBounds (Const64 [c]) (Const64 [d])) -> (ConstBool [b2i(inBounds64(c,d))]) +(IsSliceInBounds (Const32 [c]) (Const32 [d])) -> (ConstBool [b2i(sliceInBounds32(c,d))]) +(IsSliceInBounds (Const64 [c]) (Const64 [d])) -> (ConstBool [b2i(sliceInBounds64(c,d))]) + +(Eq64 x x) -> (ConstBool [1]) +(Eq32 x x) -> (ConstBool [1]) +(Eq16 x x) -> (ConstBool [1]) +(Eq8 x x) -> (ConstBool [1]) +(Eq8 (ConstBool [c]) (ConstBool [d])) -> (ConstBool [b2i((int8(c) != 0) == (int8(d) != 0))]) +(Eq8 (ConstBool [0]) x) -> (Not x) +(Eq8 (ConstBool [1]) x) -> x + +(Neq64 x x) -> (ConstBool [0]) +(Neq32 x x) -> (ConstBool [0]) +(Neq16 x x) -> (ConstBool [0]) +(Neq8 x x) -> (ConstBool [0]) +(Neq8 (ConstBool [c]) (ConstBool [d])) -> (ConstBool [b2i((int8(c) != 0) != (int8(d) != 0))]) +(Neq8 (ConstBool [0]) x) -> x +(Neq8 (ConstBool [1]) x) -> (Not x) + +(Eq64 (Const64 <t> [c]) (Add64 (Const64 <t> [d]) x)) -> (Eq64 (Const64 <t> [c-d]) x) +(Eq32 (Const32 <t> [c]) (Add32 (Const32 <t> [d]) x)) -> (Eq32 (Const32 <t> [c-d]) x) +(Eq16 (Const16 <t> [c]) (Add16 (Const16 <t> [d]) x)) -> (Eq16 (Const16 <t> [c-d]) x) +(Eq8 (Const8 <t> [c]) (Add8 (Const8 <t> [d]) x)) -> (Eq8 (Const8 <t> [c-d]) x) + +(Neq64 (Const64 <t> [c]) (Add64 (Const64 <t> [d]) x)) -> (Neq64 (Const64 <t> [c-d]) x) +(Neq32 (Const32 <t> [c]) (Add32 (Const32 <t> [d]) x)) -> (Neq32 (Const32 <t> [c-d]) x) +(Neq16 (Const16 <t> [c]) (Add16 (Const16 <t> [d]) x)) -> (Neq16 (Const16 <t> [c-d]) x) +(Neq8 (Const8 <t> [c]) (Add8 (Const8 <t> [d]) x)) -> (Neq8 (Const8 <t> [c-d]) x) + +// canonicalize: swap arguments for commutative operations when one argument is a constant. +(Eq64 x (Const64 <t> [c])) && x.Op != OpConst64 -> (Eq64 (Const64 <t> [c]) x) +(Eq32 x (Const32 <t> [c])) && x.Op != OpConst32 -> (Eq32 (Const32 <t> [c]) x) +(Eq16 x (Const16 <t> [c])) && x.Op != OpConst16 -> (Eq16 (Const16 <t> [c]) x) +(Eq8 x (Const8 <t> [c])) && x.Op != OpConst8 -> (Eq8 (Const8 <t> [c]) x) +(Eq8 x (ConstBool <t> [c])) && x.Op != OpConstBool -> (Eq8 (ConstBool <t> [c]) x) + +(Neq64 x (Const64 <t> [c])) && x.Op != OpConst64 -> (Neq64 (Const64 <t> [c]) x) +(Neq32 x (Const32 <t> [c])) && x.Op != OpConst32 -> (Neq32 (Const32 <t> [c]) x) +(Neq16 x (Const16 <t> [c])) && x.Op != OpConst16 -> (Neq16 (Const16 <t> [c]) x) +(Neq8 x (Const8 <t> [c])) && x.Op != OpConst8 -> (Neq8 (Const8 <t> [c]) x) +(Neq8 x (ConstBool <t> [c])) && x.Op != OpConstBool -> (Neq8 (ConstBool <t> [c]) x) + +(Add64 x (Const64 <t> [c])) && x.Op != OpConst64 -> (Add64 (Const64 <t> [c]) x) +(Add32 x (Const32 <t> [c])) && x.Op != OpConst32 -> (Add32 (Const32 <t> [c]) x) +(Add16 x (Const16 <t> [c])) && x.Op != OpConst16 -> (Add16 (Const16 <t> [c]) x) +(Add8 x (Const8 <t> [c])) && x.Op != OpConst8 -> (Add8 (Const8 <t> [c]) x) + +(Mul64 x (Const64 <t> [c])) && x.Op != OpConst64 -> (Mul64 (Const64 <t> [c]) x) +(Mul32 x (Const32 <t> [c])) && x.Op != OpConst32 -> (Mul32 (Const32 <t> [c]) x) +(Mul16 x (Const16 <t> [c])) && x.Op != OpConst16 -> (Mul16 (Const16 <t> [c]) x) +(Mul8 x (Const8 <t> [c])) && x.Op != OpConst8 -> (Mul8 (Const8 <t> [c]) x) + +(Sub64 x (Const64 <t> [c])) && x.Op != OpConst64 -> (Add64 (Const64 <t> [-c]) x) +(Sub32 x (Const32 <t> [c])) && x.Op != OpConst32 -> (Add32 (Const32 <t> [-c]) x) +(Sub16 x (Const16 <t> [c])) && x.Op != OpConst16 -> (Add16 (Const16 <t> [-c]) x) +(Sub8 x (Const8 <t> [c])) && x.Op != OpConst8 -> (Add8 (Const8 <t> [-c]) x) + +(And64 x (Const64 <t> [c])) && x.Op != OpConst64 -> (And64 (Const64 <t> [c]) x) +(And32 x (Const32 <t> [c])) && x.Op != OpConst32 -> (And32 (Const32 <t> [c]) x) +(And16 x (Const16 <t> [c])) && x.Op != OpConst16 -> (And16 (Const16 <t> [c]) x) +(And8 x (Const8 <t> [c])) && x.Op != OpConst8 -> (And8 (Const8 <t> [c]) x) + +(Or64 x (Const64 <t> [c])) && x.Op != OpConst64 -> (Or64 (Const64 <t> [c]) x) +(Or32 x (Const32 <t> [c])) && x.Op != OpConst32 -> (Or32 (Const32 <t> [c]) x) +(Or16 x (Const16 <t> [c])) && x.Op != OpConst16 -> (Or16 (Const16 <t> [c]) x) +(Or8 x (Const8 <t> [c])) && x.Op != OpConst8 -> (Or8 (Const8 <t> [c]) x) + +(Xor64 x (Const64 <t> [c])) && x.Op != OpConst64 -> (Xor64 (Const64 <t> [c]) x) +(Xor32 x (Const32 <t> [c])) && x.Op != OpConst32 -> (Xor32 (Const32 <t> [c]) x) +(Xor16 x (Const16 <t> [c])) && x.Op != OpConst16 -> (Xor16 (Const16 <t> [c]) x) +(Xor8 x (Const8 <t> [c])) && x.Op != OpConst8 -> (Xor8 (Const8 <t> [c]) x) + +// Distribute multiplication c * (d+x) -> c*d + c*x. Useful for: +// a[i].b = ...; a[i+1].b = ... +(Mul64 (Const64 <t> [c]) (Add64 <t> (Const64 <t> [d]) x)) -> (Add64 (Const64 <t> [c*d]) (Mul64 <t> (Const64 <t> [c]) x)) +(Mul32 (Const32 <t> [c]) (Add32 <t> (Const32 <t> [d]) x)) -> (Add32 (Const32 <t> [c*d]) (Mul32 <t> (Const32 <t> [c]) x)) + +// rewrite shifts of 8/16/32 bit consts into 64 bit consts to reduce +// the number of the other rewrite rules for const shifts +(Lsh64x32 <t> x (Const32 [c])) -> (Lsh64x64 x (Const64 <t> [int64(uint32(c))])) +(Lsh64x16 <t> x (Const16 [c])) -> (Lsh64x64 x (Const64 <t> [int64(uint16(c))])) +(Lsh64x8 <t> x (Const8 [c])) -> (Lsh64x64 x (Const64 <t> [int64(uint8(c))])) +(Rsh64x32 <t> x (Const32 [c])) -> (Rsh64x64 x (Const64 <t> [int64(uint32(c))])) +(Rsh64x16 <t> x (Const16 [c])) -> (Rsh64x64 x (Const64 <t> [int64(uint16(c))])) +(Rsh64x8 <t> x (Const8 [c])) -> (Rsh64x64 x (Const64 <t> [int64(uint8(c))])) +(Rsh64Ux32 <t> x (Const32 [c])) -> (Rsh64Ux64 x (Const64 <t> [int64(uint32(c))])) +(Rsh64Ux16 <t> x (Const16 [c])) -> (Rsh64Ux64 x (Const64 <t> [int64(uint16(c))])) +(Rsh64Ux8 <t> x (Const8 [c])) -> (Rsh64Ux64 x (Const64 <t> [int64(uint8(c))])) + +(Lsh32x32 <t> x (Const32 [c])) -> (Lsh32x64 x (Const64 <t> [int64(uint32(c))])) +(Lsh32x16 <t> x (Const16 [c])) -> (Lsh32x64 x (Const64 <t> [int64(uint16(c))])) +(Lsh32x8 <t> x (Const8 [c])) -> (Lsh32x64 x (Const64 <t> [int64(uint8(c))])) +(Rsh32x32 <t> x (Const32 [c])) -> (Rsh32x64 x (Const64 <t> [int64(uint32(c))])) +(Rsh32x16 <t> x (Const16 [c])) -> (Rsh32x64 x (Const64 <t> [int64(uint16(c))])) +(Rsh32x8 <t> x (Const8 [c])) -> (Rsh32x64 x (Const64 <t> [int64(uint8(c))])) +(Rsh32Ux32 <t> x (Const32 [c])) -> (Rsh32Ux64 x (Const64 <t> [int64(uint32(c))])) +(Rsh32Ux16 <t> x (Const16 [c])) -> (Rsh32Ux64 x (Const64 <t> [int64(uint16(c))])) +(Rsh32Ux8 <t> x (Const8 [c])) -> (Rsh32Ux64 x (Const64 <t> [int64(uint8(c))])) + +(Lsh16x32 <t> x (Const32 [c])) -> (Lsh16x64 x (Const64 <t> [int64(uint32(c))])) +(Lsh16x16 <t> x (Const16 [c])) -> (Lsh16x64 x (Const64 <t> [int64(uint16(c))])) +(Lsh16x8 <t> x (Const8 [c])) -> (Lsh16x64 x (Const64 <t> [int64(uint8(c))])) +(Rsh16x32 <t> x (Const32 [c])) -> (Rsh16x64 x (Const64 <t> [int64(uint32(c))])) +(Rsh16x16 <t> x (Const16 [c])) -> (Rsh16x64 x (Const64 <t> [int64(uint16(c))])) +(Rsh16x8 <t> x (Const8 [c])) -> (Rsh16x64 x (Const64 <t> [int64(uint8(c))])) +(Rsh16Ux32 <t> x (Const32 [c])) -> (Rsh16Ux64 x (Const64 <t> [int64(uint32(c))])) +(Rsh16Ux16 <t> x (Const16 [c])) -> (Rsh16Ux64 x (Const64 <t> [int64(uint16(c))])) +(Rsh16Ux8 <t> x (Const8 [c])) -> (Rsh16Ux64 x (Const64 <t> [int64(uint8(c))])) + +(Lsh8x32 <t> x (Const32 [c])) -> (Lsh8x64 x (Const64 <t> [int64(uint32(c))])) +(Lsh8x16 <t> x (Const16 [c])) -> (Lsh8x64 x (Const64 <t> [int64(uint16(c))])) +(Lsh8x8 <t> x (Const8 [c])) -> (Lsh8x64 x (Const64 <t> [int64(uint8(c))])) +(Rsh8x32 <t> x (Const32 [c])) -> (Rsh8x64 x (Const64 <t> [int64(uint32(c))])) +(Rsh8x16 <t> x (Const16 [c])) -> (Rsh8x64 x (Const64 <t> [int64(uint16(c))])) +(Rsh8x8 <t> x (Const8 [c])) -> (Rsh8x64 x (Const64 <t> [int64(uint8(c))])) +(Rsh8Ux32 <t> x (Const32 [c])) -> (Rsh8Ux64 x (Const64 <t> [int64(uint32(c))])) +(Rsh8Ux16 <t> x (Const16 [c])) -> (Rsh8Ux64 x (Const64 <t> [int64(uint16(c))])) +(Rsh8Ux8 <t> x (Const8 [c])) -> (Rsh8Ux64 x (Const64 <t> [int64(uint8(c))])) + +// shifts by zero +(Lsh64x64 x (Const64 [0])) -> x +(Rsh64x64 x (Const64 [0])) -> x +(Rsh64Ux64 x (Const64 [0])) -> x +(Lsh32x64 x (Const64 [0])) -> x +(Rsh32x64 x (Const64 [0])) -> x +(Rsh32Ux64 x (Const64 [0])) -> x +(Lsh16x64 x (Const64 [0])) -> x +(Rsh16x64 x (Const64 [0])) -> x +(Rsh16Ux64 x (Const64 [0])) -> x +(Lsh8x64 x (Const64 [0])) -> x +(Rsh8x64 x (Const64 [0])) -> x +(Rsh8Ux64 x (Const64 [0])) -> x + +// zero shifted. +// TODO: other bit sizes. +(Lsh64x64 (Const64 [0]) _) -> (Const64 [0]) +(Rsh64x64 (Const64 [0]) _) -> (Const64 [0]) +(Rsh64Ux64 (Const64 [0]) _) -> (Const64 [0]) +(Lsh64x32 (Const64 [0]) _) -> (Const64 [0]) +(Rsh64x32 (Const64 [0]) _) -> (Const64 [0]) +(Rsh64Ux32 (Const64 [0]) _) -> (Const64 [0]) +(Lsh64x16 (Const64 [0]) _) -> (Const64 [0]) +(Rsh64x16 (Const64 [0]) _) -> (Const64 [0]) +(Rsh64Ux16 (Const64 [0]) _) -> (Const64 [0]) +(Lsh64x8 (Const64 [0]) _) -> (Const64 [0]) +(Rsh64x8 (Const64 [0]) _) -> (Const64 [0]) +(Rsh64Ux8 (Const64 [0]) _) -> (Const64 [0]) + +// large left shifts of all values, and right shifts of unsigned values +(Lsh64x64 _ (Const64 [c])) && uint64(c) >= 64 -> (Const64 [0]) +(Rsh64Ux64 _ (Const64 [c])) && uint64(c) >= 64 -> (Const64 [0]) +(Lsh32x64 _ (Const64 [c])) && uint64(c) >= 32 -> (Const32 [0]) +(Rsh32Ux64 _ (Const64 [c])) && uint64(c) >= 32 -> (Const32 [0]) +(Lsh16x64 _ (Const64 [c])) && uint64(c) >= 16 -> (Const16 [0]) +(Rsh16Ux64 _ (Const64 [c])) && uint64(c) >= 16 -> (Const16 [0]) +(Lsh8x64 _ (Const64 [c])) && uint64(c) >= 8 -> (Const8 [0]) +(Rsh8Ux64 _ (Const64 [c])) && uint64(c) >= 8 -> (Const8 [0]) + + +// combine const shifts +(Lsh64x64 <t> (Lsh64x64 x (Const64 [c])) (Const64 [d])) && !uaddOvf(c,d) -> (Lsh64x64 x (Const64 <t> [c+d])) +(Lsh32x64 <t> (Lsh32x64 x (Const64 [c])) (Const64 [d])) && !uaddOvf(c,d) -> (Lsh32x64 x (Const64 <t> [c+d])) +(Lsh16x64 <t> (Lsh16x64 x (Const64 [c])) (Const64 [d])) && !uaddOvf(c,d) -> (Lsh16x64 x (Const64 <t> [c+d])) +(Lsh8x64 <t> (Lsh8x64 x (Const64 [c])) (Const64 [d])) && !uaddOvf(c,d) -> (Lsh8x64 x (Const64 <t> [c+d])) + +(Rsh64x64 <t> (Rsh64x64 x (Const64 [c])) (Const64 [d])) && !uaddOvf(c,d) -> (Rsh64x64 x (Const64 <t> [c+d])) +(Rsh32x64 <t> (Rsh32x64 x (Const64 [c])) (Const64 [d])) && !uaddOvf(c,d) -> (Rsh32x64 x (Const64 <t> [c+d])) +(Rsh16x64 <t> (Rsh16x64 x (Const64 [c])) (Const64 [d])) && !uaddOvf(c,d) -> (Rsh16x64 x (Const64 <t> [c+d])) +(Rsh8x64 <t> (Rsh8x64 x (Const64 [c])) (Const64 [d])) && !uaddOvf(c,d) -> (Rsh8x64 x (Const64 <t> [c+d])) + +(Rsh64Ux64 <t> (Rsh64Ux64 x (Const64 [c])) (Const64 [d])) && !uaddOvf(c,d) -> (Rsh64Ux64 x (Const64 <t> [c+d])) +(Rsh32Ux64 <t> (Rsh32Ux64 x (Const64 [c])) (Const64 [d])) && !uaddOvf(c,d) -> (Rsh32Ux64 x (Const64 <t> [c+d])) +(Rsh16Ux64 <t> (Rsh16Ux64 x (Const64 [c])) (Const64 [d])) && !uaddOvf(c,d) -> (Rsh16Ux64 x (Const64 <t> [c+d])) +(Rsh8Ux64 <t> (Rsh8Ux64 x (Const64 [c])) (Const64 [d])) && !uaddOvf(c,d) -> (Rsh8Ux64 x (Const64 <t> [c+d])) + +// constant comparisons +(Eq64 (Const64 [c]) (Const64 [d])) -> (ConstBool [b2i(int64(c) == int64(d))]) +(Eq32 (Const32 [c]) (Const32 [d])) -> (ConstBool [b2i(int32(c) == int32(d))]) +(Eq16 (Const16 [c]) (Const16 [d])) -> (ConstBool [b2i(int16(c) == int16(d))]) +(Eq8 (Const8 [c]) (Const8 [d])) -> (ConstBool [b2i(int8(c) == int8(d))]) + +(Neq64 (Const64 [c]) (Const64 [d])) -> (ConstBool [b2i(int64(c) != int64(d))]) +(Neq32 (Const32 [c]) (Const32 [d])) -> (ConstBool [b2i(int32(c) != int32(d))]) +(Neq16 (Const16 [c]) (Const16 [d])) -> (ConstBool [b2i(int16(c) != int16(d))]) +(Neq8 (Const8 [c]) (Const8 [d])) -> (ConstBool [b2i(int8(c) != int8(d))]) + +(Greater64 (Const64 [c]) (Const64 [d])) -> (ConstBool [b2i(int64(c) > int64(d))]) +(Greater32 (Const32 [c]) (Const32 [d])) -> (ConstBool [b2i(int32(c) > int32(d))]) +(Greater16 (Const16 [c]) (Const16 [d])) -> (ConstBool [b2i(int16(c) > int16(d))]) +(Greater8 (Const8 [c]) (Const8 [d])) -> (ConstBool [b2i(int8(c) > int8(d))]) + +(Greater64U (Const64 [c]) (Const64 [d])) -> (ConstBool [b2i(uint64(c) > uint64(d))]) +(Greater32U (Const32 [c]) (Const32 [d])) -> (ConstBool [b2i(uint32(c) > uint32(d))]) +(Greater16U (Const16 [c]) (Const16 [d])) -> (ConstBool [b2i(uint16(c) > uint16(d))]) +(Greater8U (Const8 [c]) (Const8 [d])) -> (ConstBool [b2i(uint8(c) > uint8(d))]) + +(Geq64 (Const64 [c]) (Const64 [d])) -> (ConstBool [b2i(int64(c) >= int64(d))]) +(Geq32 (Const32 [c]) (Const32 [d])) -> (ConstBool [b2i(int32(c) >= int32(d))]) +(Geq16 (Const16 [c]) (Const16 [d])) -> (ConstBool [b2i(int16(c) >= int16(d))]) +(Geq8 (Const8 [c]) (Const8 [d])) -> (ConstBool [b2i(int8(c) >= int8(d))]) + +(Geq64U (Const64 [c]) (Const64 [d])) -> (ConstBool [b2i(uint64(c) >= uint64(d))]) +(Geq32U (Const32 [c]) (Const32 [d])) -> (ConstBool [b2i(uint32(c) >= uint32(d))]) +(Geq16U (Const16 [c]) (Const16 [d])) -> (ConstBool [b2i(uint16(c) >= uint16(d))]) +(Geq8U (Const8 [c]) (Const8 [d])) -> (ConstBool [b2i(uint8(c) >= uint8(d))]) + +(Less64 (Const64 [c]) (Const64 [d])) -> (ConstBool [b2i(int64(c) < int64(d))]) +(Less32 (Const32 [c]) (Const32 [d])) -> (ConstBool [b2i(int32(c) < int32(d))]) +(Less16 (Const16 [c]) (Const16 [d])) -> (ConstBool [b2i(int16(c) < int16(d))]) +(Less8 (Const8 [c]) (Const8 [d])) -> (ConstBool [b2i(int8(c) < int8(d))]) + +(Less64U (Const64 [c]) (Const64 [d])) -> (ConstBool [b2i(uint64(c) < uint64(d))]) +(Less32U (Const32 [c]) (Const32 [d])) -> (ConstBool [b2i(uint32(c) < uint32(d))]) +(Less16U (Const16 [c]) (Const16 [d])) -> (ConstBool [b2i(uint16(c) < uint16(d))]) +(Less8U (Const8 [c]) (Const8 [d])) -> (ConstBool [b2i(uint8(c) < uint8(d))]) + +(Leq64 (Const64 [c]) (Const64 [d])) -> (ConstBool [b2i(int64(c) <= int64(d))]) +(Leq32 (Const32 [c]) (Const32 [d])) -> (ConstBool [b2i(int32(c) <= int32(d))]) +(Leq16 (Const16 [c]) (Const16 [d])) -> (ConstBool [b2i(int16(c) <= int16(d))]) +(Leq8 (Const8 [c]) (Const8 [d])) -> (ConstBool [b2i(int8(c) <= int8(d))]) + +(Leq64U (Const64 [c]) (Const64 [d])) -> (ConstBool [b2i(uint64(c) <= uint64(d))]) +(Leq32U (Const32 [c]) (Const32 [d])) -> (ConstBool [b2i(uint32(c) <= uint32(d))]) +(Leq16U (Const16 [c]) (Const16 [d])) -> (ConstBool [b2i(uint16(c) <= uint16(d))]) +(Leq8U (Const8 [c]) (Const8 [d])) -> (ConstBool [b2i(uint8(c) <= uint8(d))]) + +// simplifications +(Or64 x x) -> x +(Or32 x x) -> x +(Or16 x x) -> x +(Or8 x x) -> x +(Or64 (Const64 [0]) x) -> x +(Or32 (Const32 [0]) x) -> x +(Or16 (Const16 [0]) x) -> x +(Or8 (Const8 [0]) x) -> x +(Or64 (Const64 [-1]) _) -> (Const64 [-1]) +(Or32 (Const32 [-1]) _) -> (Const32 [-1]) +(Or16 (Const16 [-1]) _) -> (Const16 [-1]) +(Or8 (Const8 [-1]) _) -> (Const8 [-1]) +(And64 x x) -> x +(And32 x x) -> x +(And16 x x) -> x +(And8 x x) -> x +(And64 (Const64 [-1]) x) -> x +(And32 (Const32 [-1]) x) -> x +(And16 (Const16 [-1]) x) -> x +(And8 (Const8 [-1]) x) -> x +(And64 (Const64 [0]) _) -> (Const64 [0]) +(And32 (Const32 [0]) _) -> (Const32 [0]) +(And16 (Const16 [0]) _) -> (Const16 [0]) +(And8 (Const8 [0]) _) -> (Const8 [0]) +(Xor64 x x) -> (Const64 [0]) +(Xor32 x x) -> (Const32 [0]) +(Xor16 x x) -> (Const16 [0]) +(Xor8 x x) -> (Const8 [0]) +(Xor64 (Const64 [0]) x) -> x +(Xor32 (Const32 [0]) x) -> x +(Xor16 (Const16 [0]) x) -> x +(Xor8 (Const8 [0]) x) -> x +(Add64 (Const64 [0]) x) -> x +(Add32 (Const32 [0]) x) -> x +(Add16 (Const16 [0]) x) -> x +(Add8 (Const8 [0]) x) -> x +(Sub64 x x) -> (Const64 [0]) +(Sub32 x x) -> (Const32 [0]) +(Sub16 x x) -> (Const16 [0]) +(Sub8 x x) -> (Const8 [0]) +(Mul64 (Const64 [0]) _) -> (Const64 [0]) +(Mul32 (Const32 [0]) _) -> (Const32 [0]) +(Mul16 (Const16 [0]) _) -> (Const16 [0]) +(Mul8 (Const8 [0]) _) -> (Const8 [0]) +(Com8 (Com8 x)) -> x +(Com16 (Com16 x)) -> x +(Com32 (Com32 x)) -> x +(Com64 (Com64 x)) -> x +(Neg8 (Sub8 x y)) -> (Sub8 y x) +(Neg16 (Sub16 x y)) -> (Sub16 y x) +(Neg32 (Sub32 x y)) -> (Sub32 y x) +(Neg64 (Sub64 x y)) -> (Sub64 y x) + +// Rewrite AND of consts as shifts if possible, slightly faster for 32/64 bit operands +// leading zeros can be shifted left, then right +(And64 <t> (Const64 [y]) x) && nlz(y) + nto(y) == 64 -> (Rsh64Ux64 (Lsh64x64 <t> x (Const64 <t> [nlz(y)])) (Const64 <t> [nlz(y)])) +(And32 <t> (Const32 [y]) x) && nlz(int64(int32(y))) + nto(int64(int32(y))) == 64 -> (Rsh32Ux32 (Lsh32x32 <t> x (Const32 <t> [nlz(int64(int32(y)))-32])) (Const32 <t> [nlz(int64(int32(y)))-32])) +// trailing zeros can be shifted right, then left +(And64 <t> (Const64 [y]) x) && nlo(y) + ntz(y) == 64 -> (Lsh64x64 (Rsh64Ux64 <t> x (Const64 <t> [ntz(y)])) (Const64 <t> [ntz(y)])) +(And32 <t> (Const32 [y]) x) && nlo(int64(int32(y))) + ntz(int64(int32(y))) == 64 -> (Lsh32x32 (Rsh32Ux32 <t> x (Const32 <t> [ntz(int64(int32(y)))])) (Const32 <t> [ntz(int64(int32(y)))])) + +// simplifications often used for lengths. e.g. len(s[i:i+5])==5 +(Sub64 (Add64 x y) x) -> y +(Sub64 (Add64 x y) y) -> x +(Sub32 (Add32 x y) x) -> y +(Sub32 (Add32 x y) y) -> x +(Sub16 (Add16 x y) x) -> y +(Sub16 (Add16 x y) y) -> x +(Sub8 (Add8 x y) x) -> y +(Sub8 (Add8 x y) y) -> x + +// basic phi simplifications +(Phi (Const8 [c]) (Const8 [d])) && int8(c) == int8(d) -> (Const8 [c]) +(Phi (Const16 [c]) (Const16 [d])) && int16(c) == int16(d) -> (Const16 [c]) +(Phi (Const32 [c]) (Const32 [d])) && int32(c) == int32(d) -> (Const32 [c]) +(Phi (Const64 [c]) (Const64 [c])) -> (Const64 [c]) + +// user nil checks +(NeqPtr p (ConstNil)) -> (IsNonNil p) +(NeqPtr (ConstNil) p) -> (IsNonNil p) +(EqPtr p (ConstNil)) -> (Not (IsNonNil p)) +(EqPtr (ConstNil) p) -> (Not (IsNonNil p)) + +// slice and interface comparisons +// The frontend ensures that we can only compare against nil, +// so we need only compare the first word (interface type or slice ptr). +(EqInter x y) -> (EqPtr (ITab x) (ITab y)) +(NeqInter x y) -> (NeqPtr (ITab x) (ITab y)) +(EqSlice x y) -> (EqPtr (SlicePtr x) (SlicePtr y)) +(NeqSlice x y) -> (NeqPtr (SlicePtr x) (SlicePtr y)) + + +// Load of store of same address, with compatibly typed value and same size +(Load <t1> p1 (Store [w] p2 x _)) && isSamePtr(p1,p2) && t1.Compare(x.Type)==CMPeq && w == t1.Size() -> x + + +// indexing operations +// Note: bounds check has already been done +(ArrayIndex (Load ptr mem) idx) && b == v.Args[0].Block -> (Load (PtrIndex <v.Type.PtrTo()> ptr idx) mem) +(PtrIndex <t> ptr idx) && config.PtrSize == 4 -> (AddPtr ptr (Mul32 <config.fe.TypeInt()> idx (Const32 <config.fe.TypeInt()> [t.Elem().Size()]))) +(PtrIndex <t> ptr idx) && config.PtrSize == 8 -> (AddPtr ptr (Mul64 <config.fe.TypeInt()> idx (Const64 <config.fe.TypeInt()> [t.Elem().Size()]))) + +// struct operations +(StructSelect (StructMake1 x)) -> x +(StructSelect [0] (StructMake2 x _)) -> x +(StructSelect [1] (StructMake2 _ x)) -> x +(StructSelect [0] (StructMake3 x _ _)) -> x +(StructSelect [1] (StructMake3 _ x _)) -> x +(StructSelect [2] (StructMake3 _ _ x)) -> x +(StructSelect [0] (StructMake4 x _ _ _)) -> x +(StructSelect [1] (StructMake4 _ x _ _)) -> x +(StructSelect [2] (StructMake4 _ _ x _)) -> x +(StructSelect [3] (StructMake4 _ _ _ x)) -> x + +(Load <t> _ _) && t.IsStruct() && t.NumFields() == 0 && config.fe.CanSSA(t) -> + (StructMake0) +(Load <t> ptr mem) && t.IsStruct() && t.NumFields() == 1 && config.fe.CanSSA(t) -> + (StructMake1 + (Load <t.FieldType(0)> ptr mem)) +(Load <t> ptr mem) && t.IsStruct() && t.NumFields() == 2 && config.fe.CanSSA(t) -> + (StructMake2 + (Load <t.FieldType(0)> ptr mem) + (Load <t.FieldType(1)> (OffPtr <t.FieldType(1).PtrTo()> [t.FieldOff(1)] ptr) mem)) +(Load <t> ptr mem) && t.IsStruct() && t.NumFields() == 3 && config.fe.CanSSA(t) -> + (StructMake3 + (Load <t.FieldType(0)> ptr mem) + (Load <t.FieldType(1)> (OffPtr <t.FieldType(1).PtrTo()> [t.FieldOff(1)] ptr) mem) + (Load <t.FieldType(2)> (OffPtr <t.FieldType(2).PtrTo()> [t.FieldOff(2)] ptr) mem)) +(Load <t> ptr mem) && t.IsStruct() && t.NumFields() == 4 && config.fe.CanSSA(t) -> + (StructMake4 + (Load <t.FieldType(0)> ptr mem) + (Load <t.FieldType(1)> (OffPtr <t.FieldType(1).PtrTo()> [t.FieldOff(1)] ptr) mem) + (Load <t.FieldType(2)> (OffPtr <t.FieldType(2).PtrTo()> [t.FieldOff(2)] ptr) mem) + (Load <t.FieldType(3)> (OffPtr <t.FieldType(3).PtrTo()> [t.FieldOff(3)] ptr) mem)) + +(StructSelect [i] (Load <t> ptr mem)) && !config.fe.CanSSA(t) -> + @v.Args[0].Block (Load <v.Type> (OffPtr <v.Type.PtrTo()> [t.FieldOff(i)] ptr) mem) + +(Store _ (StructMake0) mem) -> mem +(Store dst (StructMake1 <t> f0) mem) -> + (Store [t.FieldType(0).Size()] dst f0 mem) +(Store dst (StructMake2 <t> f0 f1) mem) -> + (Store [t.FieldType(1).Size()] + (OffPtr <t.FieldType(1).PtrTo()> [t.FieldOff(1)] dst) + f1 + (Store [t.FieldType(0).Size()] dst f0 mem)) +(Store dst (StructMake3 <t> f0 f1 f2) mem) -> + (Store [t.FieldType(2).Size()] + (OffPtr <t.FieldType(2).PtrTo()> [t.FieldOff(2)] dst) + f2 + (Store [t.FieldType(1).Size()] + (OffPtr <t.FieldType(1).PtrTo()> [t.FieldOff(1)] dst) + f1 + (Store [t.FieldType(0).Size()] dst f0 mem))) +(Store dst (StructMake4 <t> f0 f1 f2 f3) mem) -> + (Store [t.FieldType(3).Size()] + (OffPtr <t.FieldType(3).PtrTo()> [t.FieldOff(3)] dst) + f3 + (Store [t.FieldType(2).Size()] + (OffPtr <t.FieldType(2).PtrTo()> [t.FieldOff(2)] dst) + f2 + (Store [t.FieldType(1).Size()] + (OffPtr <t.FieldType(1).PtrTo()> [t.FieldOff(1)] dst) + f1 + (Store [t.FieldType(0).Size()] dst f0 mem)))) + +// complex ops +(ComplexReal (ComplexMake real _ )) -> real +(ComplexImag (ComplexMake _ imag )) -> imag + +(Load <t> ptr mem) && t.IsComplex() && t.Size() == 8 -> + (ComplexMake + (Load <config.fe.TypeFloat32()> ptr mem) + (Load <config.fe.TypeFloat32()> + (OffPtr <config.fe.TypeFloat32().PtrTo()> [4] ptr) + mem) + ) +(Store [8] dst (ComplexMake real imag) mem) -> + (Store [4] + (OffPtr <config.fe.TypeFloat32().PtrTo()> [4] dst) + imag + (Store [4] dst real mem)) + +(Load <t> ptr mem) && t.IsComplex() && t.Size() == 16 -> + (ComplexMake + (Load <config.fe.TypeFloat64()> ptr mem) + (Load <config.fe.TypeFloat64()> + (OffPtr <config.fe.TypeFloat64().PtrTo()> [8] ptr) + mem) + ) +(Store [16] dst (ComplexMake real imag) mem) -> + (Store [8] + (OffPtr <config.fe.TypeFloat64().PtrTo()> [8] dst) + imag + (Store [8] dst real mem)) + +// string ops +(StringPtr (StringMake ptr _)) -> ptr +(StringLen (StringMake _ len)) -> len +(ConstString {s}) && config.PtrSize == 4 && s.(string) == "" -> + (StringMake (ConstNil) (Const32 <config.fe.TypeInt()> [0])) +(ConstString {s}) && config.PtrSize == 8 && s.(string) == "" -> + (StringMake (ConstNil) (Const64 <config.fe.TypeInt()> [0])) +(ConstString {s}) && config.PtrSize == 4 && s.(string) != "" -> + (StringMake + (Addr <config.fe.TypeBytePtr()> {config.fe.StringData(s.(string))} + (SB)) + (Const32 <config.fe.TypeInt()> [int64(len(s.(string)))])) +(ConstString {s}) && config.PtrSize == 8 && s.(string) != "" -> + (StringMake + (Addr <config.fe.TypeBytePtr()> {config.fe.StringData(s.(string))} + (SB)) + (Const64 <config.fe.TypeInt()> [int64(len(s.(string)))])) +(Load <t> ptr mem) && t.IsString() -> + (StringMake + (Load <config.fe.TypeBytePtr()> ptr mem) + (Load <config.fe.TypeInt()> + (OffPtr <config.fe.TypeInt().PtrTo()> [config.PtrSize] ptr) + mem)) +(Store [2*config.PtrSize] dst (StringMake ptr len) mem) -> + (Store [config.PtrSize] + (OffPtr <config.fe.TypeInt().PtrTo()> [config.PtrSize] dst) + len + (Store [config.PtrSize] dst ptr mem)) + +// slice ops +(SlicePtr (SliceMake ptr _ _ )) -> ptr +(SliceLen (SliceMake _ len _)) -> len +(SliceCap (SliceMake _ _ cap)) -> cap +(ConstSlice) && config.PtrSize == 4 -> + (SliceMake + (ConstNil <config.fe.TypeBytePtr()>) + (Const32 <config.fe.TypeInt()> [0]) + (Const32 <config.fe.TypeInt()> [0])) +(ConstSlice) && config.PtrSize == 8 -> + (SliceMake + (ConstNil <config.fe.TypeBytePtr()>) + (Const64 <config.fe.TypeInt()> [0]) + (Const64 <config.fe.TypeInt()> [0])) + +(Load <t> ptr mem) && t.IsSlice() -> + (SliceMake + (Load <config.fe.TypeBytePtr()> ptr mem) + (Load <config.fe.TypeInt()> + (OffPtr <config.fe.TypeInt().PtrTo()> [config.PtrSize] ptr) + mem) + (Load <config.fe.TypeInt()> + (OffPtr <config.fe.TypeInt().PtrTo()> [2*config.PtrSize] ptr) + mem)) +(Store [3*config.PtrSize] dst (SliceMake ptr len cap) mem) -> + (Store [config.PtrSize] + (OffPtr <config.fe.TypeInt().PtrTo()> [2*config.PtrSize] dst) + cap + (Store [config.PtrSize] + (OffPtr <config.fe.TypeInt().PtrTo()> [config.PtrSize] dst) + len + (Store [config.PtrSize] dst ptr mem))) + +// interface ops +(ITab (IMake itab _)) -> itab +(IData (IMake _ data)) -> data +(ConstInterface) -> + (IMake + (ConstNil <config.fe.TypeBytePtr()>) + (ConstNil <config.fe.TypeBytePtr()>)) +(Load <t> ptr mem) && t.IsInterface() -> + (IMake + (Load <config.fe.TypeBytePtr()> ptr mem) + (Load <config.fe.TypeBytePtr()> + (OffPtr <config.fe.TypeBytePtr().PtrTo()> [config.PtrSize] ptr) + mem)) +(Store [2*config.PtrSize] dst (IMake itab data) mem) -> + (Store [config.PtrSize] + (OffPtr <config.fe.TypeBytePtr().PtrTo()> [config.PtrSize] dst) + data + (Store [config.PtrSize] dst itab mem)) + +// un-SSAable values use mem->mem copies +(Store [size] dst (Load <t> src mem) mem) && !config.fe.CanSSA(t) -> (Move [size] dst src mem) +(Store [size] dst (Load <t> src mem) (VarDef {x} mem)) && !config.fe.CanSSA(t) -> (Move [size] dst src (VarDef {x} mem)) + +(Check (NilCheck (GetG _) _) next) -> (Plain nil next) + +(If (Not cond) yes no) -> (If cond no yes) +(If (ConstBool [c]) yes no) && c == 1 -> (First nil yes no) +(If (ConstBool [c]) yes no) && c == 0 -> (First nil no yes) + +// Get rid of Convert ops for pointer arithmetic on unsafe.Pointer. +(Convert (Add64 (Convert ptr mem) off) mem) -> (Add64 ptr off) +(Convert (Add64 off (Convert ptr mem)) mem) -> (Add64 ptr off) +(Convert (Convert ptr mem) mem) -> ptr + +// Decompose compound argument values +(Arg {n} [off]) && v.Type.IsString() -> + (StringMake + (Arg <config.fe.TypeBytePtr()> {n} [off]) + (Arg <config.fe.TypeInt()> {n} [off+config.PtrSize])) + +(Arg {n} [off]) && v.Type.IsSlice() -> + (SliceMake + (Arg <config.fe.TypeBytePtr()> {n} [off]) + (Arg <config.fe.TypeInt()> {n} [off+config.PtrSize]) + (Arg <config.fe.TypeInt()> {n} [off+2*config.PtrSize])) + +(Arg {n} [off]) && v.Type.IsInterface() -> + (IMake + (Arg <config.fe.TypeBytePtr()> {n} [off]) + (Arg <config.fe.TypeBytePtr()> {n} [off+config.PtrSize])) + +(Arg {n} [off]) && v.Type.IsComplex() && v.Type.Size() == 16 -> + (ComplexMake + (Arg <config.fe.TypeFloat64()> {n} [off]) + (Arg <config.fe.TypeFloat64()> {n} [off+8])) + +(Arg {n} [off]) && v.Type.IsComplex() && v.Type.Size() == 8 -> + (ComplexMake + (Arg <config.fe.TypeFloat32()> {n} [off]) + (Arg <config.fe.TypeFloat32()> {n} [off+4])) + +(Arg <t>) && t.IsStruct() && t.NumFields() == 0 && config.fe.CanSSA(t) -> + (StructMake0) +(Arg <t> {n} [off]) && t.IsStruct() && t.NumFields() == 1 && config.fe.CanSSA(t) -> + (StructMake1 + (Arg <t.FieldType(0)> {n} [off+t.FieldOff(0)])) +(Arg <t> {n} [off]) && t.IsStruct() && t.NumFields() == 2 && config.fe.CanSSA(t) -> + (StructMake2 + (Arg <t.FieldType(0)> {n} [off+t.FieldOff(0)]) + (Arg <t.FieldType(1)> {n} [off+t.FieldOff(1)])) +(Arg <t> {n} [off]) && t.IsStruct() && t.NumFields() == 3 && config.fe.CanSSA(t) -> + (StructMake3 + (Arg <t.FieldType(0)> {n} [off+t.FieldOff(0)]) + (Arg <t.FieldType(1)> {n} [off+t.FieldOff(1)]) + (Arg <t.FieldType(2)> {n} [off+t.FieldOff(2)])) +(Arg <t> {n} [off]) && t.IsStruct() && t.NumFields() == 4 && config.fe.CanSSA(t) -> + (StructMake4 + (Arg <t.FieldType(0)> {n} [off+t.FieldOff(0)]) + (Arg <t.FieldType(1)> {n} [off+t.FieldOff(1)]) + (Arg <t.FieldType(2)> {n} [off+t.FieldOff(2)]) + (Arg <t.FieldType(3)> {n} [off+t.FieldOff(3)])) + +// strength reduction of divide by a constant. +// Note: frontend does <=32 bits. We only need to do 64 bits here. +// TODO: Do them all here? + +// Div/mod by 1. Currently handled by frontend. +//(Div64 n (Const64 [1])) -> n +//(Div64u n (Const64 [1])) -> n +//(Mod64 n (Const64 [1])) -> (Const64 [0]) +//(Mod64u n (Const64 [1])) -> (Const64 [0]) + +// Unsigned divide by power of 2. Currently handled by frontend. +//(Div64u <t> n (Const64 [c])) && isPowerOfTwo(c) -> (Rsh64Ux64 n (Const64 <t> [log2(c)])) +//(Mod64u <t> n (Const64 [c])) && isPowerOfTwo(c) -> (And64 n (Const64 <t> [c-1])) + +// Signed divide by power of 2. Currently handled by frontend. +// n / c = n >> log(c) if n >= 0 +// = (n+c-1) >> log(c) if n < 0 +// We conditionally add c-1 by adding n>>63>>(64-log(c)) (first shift signed, second shift unsigned). +//(Div64 <t> n (Const64 [c])) && isPowerOfTwo(c) -> +// (Rsh64x64 +// (Add64 <t> +// n +// (Rsh64Ux64 <t> +// (Rsh64x64 <t> n (Const64 <t> [63])) +// (Const64 <t> [64-log2(c)]))) +// (Const64 <t> [log2(c)])) + +// Unsigned divide, not a power of 2. Strength reduce to a multiply. +(Div64u <t> x (Const64 [c])) && umagic64ok(c) && !umagic64a(c) -> + (Rsh64Ux64 + (Hmul64u <t> + (Const64 <t> [umagic64m(c)]) + x) + (Const64 <t> [umagic64s(c)])) +(Div64u <t> x (Const64 [c])) && umagic64ok(c) && umagic64a(c) -> + (Rsh64Ux64 + (Avg64u <t> + (Hmul64u <t> + x + (Const64 <t> [umagic64m(c)])) + x) + (Const64 <t> [umagic64s(c)-1])) + +// Signed divide, not a power of 2. Strength reduce to a multiply. +(Div64 <t> x (Const64 [c])) && c > 0 && smagic64ok(c) && smagic64m(c) > 0 -> + (Sub64 <t> + (Rsh64x64 <t> + (Hmul64 <t> + (Const64 <t> [smagic64m(c)]) + x) + (Const64 <t> [smagic64s(c)])) + (Rsh64x64 <t> + x + (Const64 <t> [63]))) +(Div64 <t> x (Const64 [c])) && c > 0 && smagic64ok(c) && smagic64m(c) < 0 -> + (Sub64 <t> + (Rsh64x64 <t> + (Add64 <t> + (Hmul64 <t> + (Const64 <t> [smagic64m(c)]) + x) + x) + (Const64 <t> [smagic64s(c)])) + (Rsh64x64 <t> + x + (Const64 <t> [63]))) +(Div64 <t> x (Const64 [c])) && c < 0 && smagic64ok(c) && smagic64m(c) > 0 -> + (Neg64 <t> + (Sub64 <t> + (Rsh64x64 <t> + (Hmul64 <t> + (Const64 <t> [smagic64m(c)]) + x) + (Const64 <t> [smagic64s(c)])) + (Rsh64x64 <t> + x + (Const64 <t> [63])))) +(Div64 <t> x (Const64 [c])) && c < 0 && smagic64ok(c) && smagic64m(c) < 0 -> + (Neg64 <t> + (Sub64 <t> + (Rsh64x64 <t> + (Add64 <t> + (Hmul64 <t> + (Const64 <t> [smagic64m(c)]) + x) + x) + (Const64 <t> [smagic64s(c)])) + (Rsh64x64 <t> + x + (Const64 <t> [63])))) + +// A%B = A-(A/B*B). +// This implements % with two * and a bunch of ancillary ops. +// One of the * is free if the user's code also computes A/B. +(Mod64 <t> x (Const64 [c])) && smagic64ok(c) -> (Sub64 x (Mul64 <t> (Div64 <t> x (Const64 <t> [c])) (Const64 <t> [c]))) +(Mod64u <t> x (Const64 [c])) && umagic64ok(c) -> (Sub64 x (Mul64 <t> (Div64u <t> x (Const64 <t> [c])) (Const64 <t> [c]))) diff --git a/src/cmd/compile/internal/ssa/gen/genericOps.go b/src/cmd/compile/internal/ssa/gen/genericOps.go new file mode 100644 index 0000000000..31e45c45ea --- /dev/null +++ b/src/cmd/compile/internal/ssa/gen/genericOps.go @@ -0,0 +1,416 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package main + +var genericOps = []opData{ + // 2-input arithmetic + // Types must be consistent with Go typing. Add, for example, must take two values + // of the same type and produces that same type. + {name: "Add8", argLength: 2, commutative: true}, // arg0 + arg1 + {name: "Add16", argLength: 2, commutative: true}, + {name: "Add32", argLength: 2, commutative: true}, + {name: "Add64", argLength: 2, commutative: true}, + {name: "AddPtr", argLength: 2}, // For address calculations. arg0 is a pointer and arg1 is an int. + {name: "Add32F", argLength: 2}, + {name: "Add64F", argLength: 2}, + // TODO: Add64C, Add128C + + {name: "Sub8", argLength: 2}, // arg0 - arg1 + {name: "Sub16", argLength: 2}, + {name: "Sub32", argLength: 2}, + {name: "Sub64", argLength: 2}, + {name: "SubPtr", argLength: 2}, + {name: "Sub32F", argLength: 2}, + {name: "Sub64F", argLength: 2}, + + {name: "Mul8", argLength: 2, commutative: true}, // arg0 * arg1 + {name: "Mul16", argLength: 2, commutative: true}, + {name: "Mul32", argLength: 2, commutative: true}, + {name: "Mul64", argLength: 2, commutative: true}, + {name: "Mul32F", argLength: 2}, + {name: "Mul64F", argLength: 2}, + + {name: "Div32F", argLength: 2}, // arg0 / arg1 + {name: "Div64F", argLength: 2}, + + {name: "Hmul8", argLength: 2}, // (arg0 * arg1) >> width + {name: "Hmul8u", argLength: 2}, + {name: "Hmul16", argLength: 2}, + {name: "Hmul16u", argLength: 2}, + {name: "Hmul32", argLength: 2}, + {name: "Hmul32u", argLength: 2}, + {name: "Hmul64", argLength: 2}, + {name: "Hmul64u", argLength: 2}, + + // Weird special instruction for strength reduction of divides. + {name: "Avg64u", argLength: 2}, // (uint64(arg0) + uint64(arg1)) / 2, correct to all 64 bits. + + {name: "Div8", argLength: 2}, // arg0 / arg1 + {name: "Div8u", argLength: 2}, + {name: "Div16", argLength: 2}, + {name: "Div16u", argLength: 2}, + {name: "Div32", argLength: 2}, + {name: "Div32u", argLength: 2}, + {name: "Div64", argLength: 2}, + {name: "Div64u", argLength: 2}, + + {name: "Mod8", argLength: 2}, // arg0 % arg1 + {name: "Mod8u", argLength: 2}, + {name: "Mod16", argLength: 2}, + {name: "Mod16u", argLength: 2}, + {name: "Mod32", argLength: 2}, + {name: "Mod32u", argLength: 2}, + {name: "Mod64", argLength: 2}, + {name: "Mod64u", argLength: 2}, + + {name: "And8", argLength: 2, commutative: true}, // arg0 & arg1 + {name: "And16", argLength: 2, commutative: true}, + {name: "And32", argLength: 2, commutative: true}, + {name: "And64", argLength: 2, commutative: true}, + + {name: "Or8", argLength: 2, commutative: true}, // arg0 | arg1 + {name: "Or16", argLength: 2, commutative: true}, + {name: "Or32", argLength: 2, commutative: true}, + {name: "Or64", argLength: 2, commutative: true}, + + {name: "Xor8", argLength: 2, commutative: true}, // arg0 ^ arg1 + {name: "Xor16", argLength: 2, commutative: true}, + {name: "Xor32", argLength: 2, commutative: true}, + {name: "Xor64", argLength: 2, commutative: true}, + + // For shifts, AxB means the shifted value has A bits and the shift amount has B bits. + {name: "Lsh8x8", argLength: 2}, // arg0 << arg1 + {name: "Lsh8x16", argLength: 2}, + {name: "Lsh8x32", argLength: 2}, + {name: "Lsh8x64", argLength: 2}, + {name: "Lsh16x8", argLength: 2}, + {name: "Lsh16x16", argLength: 2}, + {name: "Lsh16x32", argLength: 2}, + {name: "Lsh16x64", argLength: 2}, + {name: "Lsh32x8", argLength: 2}, + {name: "Lsh32x16", argLength: 2}, + {name: "Lsh32x32", argLength: 2}, + {name: "Lsh32x64", argLength: 2}, + {name: "Lsh64x8", argLength: 2}, + {name: "Lsh64x16", argLength: 2}, + {name: "Lsh64x32", argLength: 2}, + {name: "Lsh64x64", argLength: 2}, + + {name: "Rsh8x8", argLength: 2}, // arg0 >> arg1, signed + {name: "Rsh8x16", argLength: 2}, + {name: "Rsh8x32", argLength: 2}, + {name: "Rsh8x64", argLength: 2}, + {name: "Rsh16x8", argLength: 2}, + {name: "Rsh16x16", argLength: 2}, + {name: "Rsh16x32", argLength: 2}, + {name: "Rsh16x64", argLength: 2}, + {name: "Rsh32x8", argLength: 2}, + {name: "Rsh32x16", argLength: 2}, + {name: "Rsh32x32", argLength: 2}, + {name: "Rsh32x64", argLength: 2}, + {name: "Rsh64x8", argLength: 2}, + {name: "Rsh64x16", argLength: 2}, + {name: "Rsh64x32", argLength: 2}, + {name: "Rsh64x64", argLength: 2}, + + {name: "Rsh8Ux8", argLength: 2}, // arg0 >> arg1, unsigned + {name: "Rsh8Ux16", argLength: 2}, + {name: "Rsh8Ux32", argLength: 2}, + {name: "Rsh8Ux64", argLength: 2}, + {name: "Rsh16Ux8", argLength: 2}, + {name: "Rsh16Ux16", argLength: 2}, + {name: "Rsh16Ux32", argLength: 2}, + {name: "Rsh16Ux64", argLength: 2}, + {name: "Rsh32Ux8", argLength: 2}, + {name: "Rsh32Ux16", argLength: 2}, + {name: "Rsh32Ux32", argLength: 2}, + {name: "Rsh32Ux64", argLength: 2}, + {name: "Rsh64Ux8", argLength: 2}, + {name: "Rsh64Ux16", argLength: 2}, + {name: "Rsh64Ux32", argLength: 2}, + {name: "Rsh64Ux64", argLength: 2}, + + // (Left) rotates replace pattern matches in the front end + // of (arg0 << arg1) ^ (arg0 >> (A-arg1)) + // where A is the bit width of arg0 and result. + // Note that because rotates are pattern-matched from + // shifts, that a rotate of arg1=A+k (k > 0) bits originated from + // (arg0 << A+k) ^ (arg0 >> -k) = + // 0 ^ arg0>>huge_unsigned = + // 0 ^ 0 = 0 + // which is not the same as a rotation by A+k + // + // However, in the specific case of k = 0, the result of + // the shift idiom is the same as the result for the + // rotate idiom, i.e., result=arg0. + // This is different from shifts, where + // arg0 << A is defined to be zero. + // + // Because of this, and also because the primary use case + // for rotates is hashing and crypto code with constant + // distance, rotate instructions are only substituted + // when arg1 is a constant between 1 and A-1, inclusive. + {name: "Lrot8", argLength: 1, aux: "Int64"}, + {name: "Lrot16", argLength: 1, aux: "Int64"}, + {name: "Lrot32", argLength: 1, aux: "Int64"}, + {name: "Lrot64", argLength: 1, aux: "Int64"}, + + // 2-input comparisons + {name: "Eq8", argLength: 2, commutative: true}, // arg0 == arg1 + {name: "Eq16", argLength: 2, commutative: true}, + {name: "Eq32", argLength: 2, commutative: true}, + {name: "Eq64", argLength: 2, commutative: true}, + {name: "EqPtr", argLength: 2, commutative: true}, + {name: "EqInter", argLength: 2}, // arg0 or arg1 is nil; other cases handled by frontend + {name: "EqSlice", argLength: 2}, // arg0 or arg1 is nil; other cases handled by frontend + {name: "Eq32F", argLength: 2}, + {name: "Eq64F", argLength: 2}, + + {name: "Neq8", argLength: 2, commutative: true}, // arg0 != arg1 + {name: "Neq16", argLength: 2, commutative: true}, + {name: "Neq32", argLength: 2, commutative: true}, + {name: "Neq64", argLength: 2, commutative: true}, + {name: "NeqPtr", argLength: 2, commutative: true}, + {name: "NeqInter", argLength: 2}, // arg0 or arg1 is nil; other cases handled by frontend + {name: "NeqSlice", argLength: 2}, // arg0 or arg1 is nil; other cases handled by frontend + {name: "Neq32F", argLength: 2}, + {name: "Neq64F", argLength: 2}, + + {name: "Less8", argLength: 2}, // arg0 < arg1 + {name: "Less8U", argLength: 2}, + {name: "Less16", argLength: 2}, + {name: "Less16U", argLength: 2}, + {name: "Less32", argLength: 2}, + {name: "Less32U", argLength: 2}, + {name: "Less64", argLength: 2}, + {name: "Less64U", argLength: 2}, + {name: "Less32F", argLength: 2}, + {name: "Less64F", argLength: 2}, + + {name: "Leq8", argLength: 2}, // arg0 <= arg1 + {name: "Leq8U", argLength: 2}, + {name: "Leq16", argLength: 2}, + {name: "Leq16U", argLength: 2}, + {name: "Leq32", argLength: 2}, + {name: "Leq32U", argLength: 2}, + {name: "Leq64", argLength: 2}, + {name: "Leq64U", argLength: 2}, + {name: "Leq32F", argLength: 2}, + {name: "Leq64F", argLength: 2}, + + {name: "Greater8", argLength: 2}, // arg0 > arg1 + {name: "Greater8U", argLength: 2}, + {name: "Greater16", argLength: 2}, + {name: "Greater16U", argLength: 2}, + {name: "Greater32", argLength: 2}, + {name: "Greater32U", argLength: 2}, + {name: "Greater64", argLength: 2}, + {name: "Greater64U", argLength: 2}, + {name: "Greater32F", argLength: 2}, + {name: "Greater64F", argLength: 2}, + + {name: "Geq8", argLength: 2}, // arg0 <= arg1 + {name: "Geq8U", argLength: 2}, + {name: "Geq16", argLength: 2}, + {name: "Geq16U", argLength: 2}, + {name: "Geq32", argLength: 2}, + {name: "Geq32U", argLength: 2}, + {name: "Geq64", argLength: 2}, + {name: "Geq64U", argLength: 2}, + {name: "Geq32F", argLength: 2}, + {name: "Geq64F", argLength: 2}, + + // 1-input ops + {name: "Not", argLength: 1}, // !arg0 + + {name: "Neg8", argLength: 1}, // -arg0 + {name: "Neg16", argLength: 1}, + {name: "Neg32", argLength: 1}, + {name: "Neg64", argLength: 1}, + {name: "Neg32F", argLength: 1}, + {name: "Neg64F", argLength: 1}, + + {name: "Com8", argLength: 1}, // ^arg0 + {name: "Com16", argLength: 1}, + {name: "Com32", argLength: 1}, + {name: "Com64", argLength: 1}, + + {name: "Sqrt", argLength: 1}, // sqrt(arg0), float64 only + + // Data movement, max argument length for Phi is indefinite so just pick + // a really large number + {name: "Phi", argLength: -1}, // select an argument based on which predecessor block we came from + {name: "Copy", argLength: 1}, // output = arg0 + // Convert converts between pointers and integers. + // We have a special op for this so as to not confuse GC + // (particularly stack maps). It takes a memory arg so it + // gets correctly ordered with respect to GC safepoints. + // arg0=ptr/int arg1=mem, output=int/ptr + {name: "Convert", argLength: 2}, + + // constants. Constant values are stored in the aux or + // auxint fields. + {name: "ConstBool", aux: "Bool"}, // auxint is 0 for false and 1 for true + {name: "ConstString", aux: "String"}, // value is aux.(string) + {name: "ConstNil", typ: "BytePtr"}, // nil pointer + {name: "Const8", aux: "Int8"}, // value is low 8 bits of auxint + {name: "Const16", aux: "Int16"}, // value is low 16 bits of auxint + {name: "Const32", aux: "Int32"}, // value is low 32 bits of auxint + {name: "Const64", aux: "Int64"}, // value is auxint + {name: "Const32F", aux: "Float"}, // value is math.Float64frombits(uint64(auxint)) + {name: "Const64F", aux: "Float"}, // value is math.Float64frombits(uint64(auxint)) + {name: "ConstInterface"}, // nil interface + {name: "ConstSlice"}, // nil slice + + // Constant-like things + {name: "InitMem"}, // memory input to the function. + {name: "Arg", aux: "SymOff"}, // argument to the function. aux=GCNode of arg, off = offset in that arg. + + // The address of a variable. arg0 is the base pointer (SB or SP, depending + // on whether it is a global or stack variable). The Aux field identifies the + // variable. It will be either an *ExternSymbol (with arg0=SB), *ArgSymbol (arg0=SP), + // or *AutoSymbol (arg0=SP). + {name: "Addr", argLength: 1, aux: "Sym"}, // Address of a variable. Arg0=SP or SB. Aux identifies the variable. + + {name: "SP"}, // stack pointer + {name: "SB", typ: "Uintptr"}, // static base pointer (a.k.a. globals pointer) + {name: "Func", aux: "Sym"}, // entry address of a function + + // Memory operations + {name: "Load", argLength: 2}, // Load from arg0. arg1=memory + {name: "Store", argLength: 3, typ: "Mem", aux: "Int64"}, // Store arg1 to arg0. arg2=memory, auxint=size. Returns memory. + {name: "Move", argLength: 3, aux: "Int64"}, // arg0=destptr, arg1=srcptr, arg2=mem, auxint=size. Returns memory. + {name: "Zero", argLength: 2, aux: "Int64"}, // arg0=destptr, arg1=mem, auxint=size. Returns memory. + + // Function calls. Arguments to the call have already been written to the stack. + // Return values appear on the stack. The method receiver, if any, is treated + // as a phantom first argument. + {name: "ClosureCall", argLength: 3, aux: "Int64"}, // arg0=code pointer, arg1=context ptr, arg2=memory. auxint=arg size. Returns memory. + {name: "StaticCall", argLength: 1, aux: "SymOff"}, // call function aux.(*gc.Sym), arg0=memory. auxint=arg size. Returns memory. + {name: "DeferCall", argLength: 1, aux: "Int64"}, // defer call. arg0=memory, auxint=arg size. Returns memory. + {name: "GoCall", argLength: 1, aux: "Int64"}, // go call. arg0=memory, auxint=arg size. Returns memory. + {name: "InterCall", argLength: 2, aux: "Int64"}, // interface call. arg0=code pointer, arg1=memory, auxint=arg size. Returns memory. + + // Conversions: signed extensions, zero (unsigned) extensions, truncations + {name: "SignExt8to16", argLength: 1, typ: "Int16"}, + {name: "SignExt8to32", argLength: 1}, + {name: "SignExt8to64", argLength: 1}, + {name: "SignExt16to32", argLength: 1}, + {name: "SignExt16to64", argLength: 1}, + {name: "SignExt32to64", argLength: 1}, + {name: "ZeroExt8to16", argLength: 1, typ: "UInt16"}, + {name: "ZeroExt8to32", argLength: 1}, + {name: "ZeroExt8to64", argLength: 1}, + {name: "ZeroExt16to32", argLength: 1}, + {name: "ZeroExt16to64", argLength: 1}, + {name: "ZeroExt32to64", argLength: 1}, + {name: "Trunc16to8", argLength: 1}, + {name: "Trunc32to8", argLength: 1}, + {name: "Trunc32to16", argLength: 1}, + {name: "Trunc64to8", argLength: 1}, + {name: "Trunc64to16", argLength: 1}, + {name: "Trunc64to32", argLength: 1}, + + {name: "Cvt32to32F", argLength: 1}, + {name: "Cvt32to64F", argLength: 1}, + {name: "Cvt64to32F", argLength: 1}, + {name: "Cvt64to64F", argLength: 1}, + {name: "Cvt32Fto32", argLength: 1}, + {name: "Cvt32Fto64", argLength: 1}, + {name: "Cvt64Fto32", argLength: 1}, + {name: "Cvt64Fto64", argLength: 1}, + {name: "Cvt32Fto64F", argLength: 1}, + {name: "Cvt64Fto32F", argLength: 1}, + + // Automatically inserted safety checks + {name: "IsNonNil", argLength: 1, typ: "Bool"}, // arg0 != nil + {name: "IsInBounds", argLength: 2, typ: "Bool"}, // 0 <= arg0 < arg1 + {name: "IsSliceInBounds", argLength: 2, typ: "Bool"}, // 0 <= arg0 <= arg1 + {name: "NilCheck", argLength: 2, typ: "Void"}, // arg0=ptr, arg1=mem. Panics if arg0 is nil, returns void. + + // Pseudo-ops + {name: "GetG", argLength: 1}, // runtime.getg() (read g pointer). arg0=mem + {name: "GetClosurePtr"}, // get closure pointer from dedicated register + + // Indexing operations + {name: "ArrayIndex", argLength: 2}, // arg0=array, arg1=index. Returns a[i] + {name: "PtrIndex", argLength: 2}, // arg0=ptr, arg1=index. Computes ptr+sizeof(*v.type)*index, where index is extended to ptrwidth type + {name: "OffPtr", argLength: 1, aux: "Int64"}, // arg0 + auxint (arg0 and result are pointers) + + // Slices + {name: "SliceMake", argLength: 3}, // arg0=ptr, arg1=len, arg2=cap + {name: "SlicePtr", argLength: 1, typ: "BytePtr"}, // ptr(arg0) + {name: "SliceLen", argLength: 1}, // len(arg0) + {name: "SliceCap", argLength: 1}, // cap(arg0) + + // Complex (part/whole) + {name: "ComplexMake", argLength: 2}, // arg0=real, arg1=imag + {name: "ComplexReal", argLength: 1}, // real(arg0) + {name: "ComplexImag", argLength: 1}, // imag(arg0) + + // Strings + {name: "StringMake", argLength: 2}, // arg0=ptr, arg1=len + {name: "StringPtr", argLength: 1}, // ptr(arg0) + {name: "StringLen", argLength: 1}, // len(arg0) + + // Interfaces + {name: "IMake", argLength: 2}, // arg0=itab, arg1=data + {name: "ITab", argLength: 1, typ: "BytePtr"}, // arg0=interface, returns itable field + {name: "IData", argLength: 1}, // arg0=interface, returns data field + + // Structs + {name: "StructMake0"}, // Returns struct with 0 fields. + {name: "StructMake1", argLength: 1}, // arg0=field0. Returns struct. + {name: "StructMake2", argLength: 2}, // arg0,arg1=field0,field1. Returns struct. + {name: "StructMake3", argLength: 3}, // arg0..2=field0..2. Returns struct. + {name: "StructMake4", argLength: 4}, // arg0..3=field0..3. Returns struct. + {name: "StructSelect", argLength: 1, aux: "Int64"}, // arg0=struct, auxint=field index. Returns the auxint'th field. + + // Spill&restore ops for the register allocator. These are + // semantically identical to OpCopy; they do not take/return + // stores like regular memory ops do. We can get away without memory + // args because we know there is no aliasing of spill slots on the stack. + {name: "StoreReg", argLength: 1}, + {name: "LoadReg", argLength: 1}, + + // Used during ssa construction. Like Copy, but the arg has not been specified yet. + {name: "FwdRef"}, + + // Unknown value. Used for Values whose values don't matter because they are dead code. + {name: "Unknown"}, + + {name: "VarDef", argLength: 1, aux: "Sym", typ: "Mem"}, // aux is a *gc.Node of a variable that is about to be initialized. arg0=mem, returns mem + {name: "VarKill", argLength: 1, aux: "Sym"}, // aux is a *gc.Node of a variable that is known to be dead. arg0=mem, returns mem + {name: "VarLive", argLength: 1, aux: "Sym"}, // aux is a *gc.Node of a variable that must be kept live. arg0=mem, returns mem +} + +// kind control successors implicit exit +// ---------------------------------------------------------- +// Exit return mem [] yes +// Ret return mem [] yes +// RetJmp return mem [] yes +// Plain nil [next] +// If a boolean Value [then, else] +// Call mem [next] yes (control opcode should be OpCall or OpStaticCall) +// Check void [next] yes (control opcode should be Op{Lowered}NilCheck) +// First nil [always,never] + +var genericBlocks = []blockData{ + {name: "Plain"}, // a single successor + {name: "If"}, // 2 successors, if control goto Succs[0] else goto Succs[1] + {name: "Call"}, // 1 successor, control is call op (of memory type) + {name: "Check"}, // 1 successor, control is nilcheck op (of void type) + {name: "Ret"}, // no successors, control value is memory result + {name: "RetJmp"}, // no successors, jumps to b.Aux.(*gc.Sym) + {name: "Exit"}, // no successors, control value generates a panic + + // transient block states used for dead code removal + {name: "First"}, // 2 successors, always takes the first one (second is dead) + {name: "Dead"}, // no successors; determined to be dead but not yet removed +} + +func init() { + archs = append(archs, arch{"generic", genericOps, genericBlocks, nil}) +} diff --git a/src/cmd/compile/internal/ssa/gen/main.go b/src/cmd/compile/internal/ssa/gen/main.go new file mode 100644 index 0000000000..660511e46c --- /dev/null +++ b/src/cmd/compile/internal/ssa/gen/main.go @@ -0,0 +1,262 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// The gen command generates Go code (in the parent directory) for all +// the architecture-specific opcodes, blocks, and rewrites. + +package main + +import ( + "bytes" + "flag" + "fmt" + "go/format" + "io/ioutil" + "log" + "regexp" + "sort" +) + +type arch struct { + name string + ops []opData + blocks []blockData + regnames []string +} + +type opData struct { + name string + reg regInfo + asm string + typ string // default result type + aux string + rematerializeable bool + argLength int32 // number of arguments, if -1, then this operation has a variable number of arguments + commutative bool // this operation is commutative (e.g. addition) +} + +type blockData struct { + name string +} + +type regInfo struct { + inputs []regMask + clobbers regMask + outputs []regMask +} + +type regMask uint64 + +func (a arch) regMaskComment(r regMask) string { + var buf bytes.Buffer + for i := uint64(0); r != 0; i++ { + if r&1 != 0 { + if buf.Len() == 0 { + buf.WriteString(" //") + } + buf.WriteString(" ") + buf.WriteString(a.regnames[i]) + } + r >>= 1 + } + return buf.String() +} + +var archs []arch + +func main() { + flag.Parse() + genOp() + genLower() +} + +func genOp() { + w := new(bytes.Buffer) + fmt.Fprintf(w, "// autogenerated: do not edit!\n") + fmt.Fprintf(w, "// generated from gen/*Ops.go\n") + fmt.Fprintln(w) + fmt.Fprintln(w, "package ssa") + + fmt.Fprintln(w, "import \"cmd/internal/obj/x86\"") + + // generate Block* declarations + fmt.Fprintln(w, "const (") + fmt.Fprintln(w, "BlockInvalid BlockKind = iota") + for _, a := range archs { + fmt.Fprintln(w) + for _, d := range a.blocks { + fmt.Fprintf(w, "Block%s%s\n", a.Name(), d.name) + } + } + fmt.Fprintln(w, ")") + + // generate block kind string method + fmt.Fprintln(w, "var blockString = [...]string{") + fmt.Fprintln(w, "BlockInvalid:\"BlockInvalid\",") + for _, a := range archs { + fmt.Fprintln(w) + for _, b := range a.blocks { + fmt.Fprintf(w, "Block%s%s:\"%s\",\n", a.Name(), b.name, b.name) + } + } + fmt.Fprintln(w, "}") + fmt.Fprintln(w, "func (k BlockKind) String() string {return blockString[k]}") + + // generate Op* declarations + fmt.Fprintln(w, "const (") + fmt.Fprintln(w, "OpInvalid Op = iota") + for _, a := range archs { + fmt.Fprintln(w) + for _, v := range a.ops { + fmt.Fprintf(w, "Op%s%s\n", a.Name(), v.name) + } + } + fmt.Fprintln(w, ")") + + // generate OpInfo table + fmt.Fprintln(w, "var opcodeTable = [...]opInfo{") + fmt.Fprintln(w, " { name: \"OpInvalid\" },") + for _, a := range archs { + fmt.Fprintln(w) + for _, v := range a.ops { + fmt.Fprintln(w, "{") + fmt.Fprintf(w, "name:\"%s\",\n", v.name) + + // flags + if v.aux != "" { + fmt.Fprintf(w, "auxType: aux%s,\n", v.aux) + } + fmt.Fprintf(w, "argLen: %d,\n", v.argLength) + + if v.rematerializeable { + if v.reg.clobbers != 0 { + log.Fatalf("%s is rematerializeable and clobbers registers", v.name) + } + fmt.Fprintln(w, "rematerializeable: true,") + } + if v.commutative { + fmt.Fprintln(w, "commutative: true,") + } + if a.name == "generic" { + fmt.Fprintln(w, "generic:true,") + fmt.Fprintln(w, "},") // close op + // generic ops have no reg info or asm + continue + } + if v.asm != "" { + fmt.Fprintf(w, "asm: x86.A%s,\n", v.asm) + } + fmt.Fprintln(w, "reg:regInfo{") + + // Compute input allocation order. We allocate from the + // most to the least constrained input. This order guarantees + // that we will always be able to find a register. + var s []intPair + for i, r := range v.reg.inputs { + if r != 0 { + s = append(s, intPair{countRegs(r), i}) + } + } + if len(s) > 0 { + sort.Sort(byKey(s)) + fmt.Fprintln(w, "inputs: []inputInfo{") + for _, p := range s { + r := v.reg.inputs[p.val] + fmt.Fprintf(w, "{%d,%d},%s\n", p.val, r, a.regMaskComment(r)) + } + fmt.Fprintln(w, "},") + } + if v.reg.clobbers > 0 { + fmt.Fprintf(w, "clobbers: %d,%s\n", v.reg.clobbers, a.regMaskComment(v.reg.clobbers)) + } + // reg outputs + if len(v.reg.outputs) > 0 { + fmt.Fprintln(w, "outputs: []regMask{") + for _, r := range v.reg.outputs { + fmt.Fprintf(w, "%d,%s\n", r, a.regMaskComment(r)) + } + fmt.Fprintln(w, "},") + } + fmt.Fprintln(w, "},") // close reg info + fmt.Fprintln(w, "},") // close op + } + } + fmt.Fprintln(w, "}") + + fmt.Fprintln(w, "func (o Op) Asm() int {return opcodeTable[o].asm}") + + // generate op string method + fmt.Fprintln(w, "func (o Op) String() string {return opcodeTable[o].name }") + + // gofmt result + b := w.Bytes() + var err error + b, err = format.Source(b) + if err != nil { + fmt.Printf("%s\n", w.Bytes()) + panic(err) + } + + err = ioutil.WriteFile("../opGen.go", b, 0666) + if err != nil { + log.Fatalf("can't write output: %v\n", err) + } + + // Check that ../gc/ssa.go handles all the arch-specific opcodes. + // This is very much a hack, but it is better than nothing. + ssa, err := ioutil.ReadFile("../../gc/ssa.go") + if err != nil { + log.Fatalf("can't read ../../gc/ssa.go: %v", err) + } + for _, a := range archs { + if a.name == "generic" { + continue + } + for _, v := range a.ops { + pattern := fmt.Sprintf("\\Wssa[.]Op%s%s\\W", a.name, v.name) + match, err := regexp.Match(pattern, ssa) + if err != nil { + log.Fatalf("bad opcode regexp %s: %v", pattern, err) + } + if !match { + log.Fatalf("Op%s%s has no code generation in ../../gc/ssa.go", a.name, v.name) + } + } + } +} + +// Name returns the name of the architecture for use in Op* and Block* enumerations. +func (a arch) Name() string { + s := a.name + if s == "generic" { + s = "" + } + return s +} + +func genLower() { + for _, a := range archs { + genRules(a) + } +} + +// countRegs returns the number of set bits in the register mask. +func countRegs(r regMask) int { + n := 0 + for r != 0 { + n += int(r & 1) + r >>= 1 + } + return n +} + +// for sorting a pair of integers by key +type intPair struct { + key, val int +} +type byKey []intPair + +func (a byKey) Len() int { return len(a) } +func (a byKey) Swap(i, j int) { a[i], a[j] = a[j], a[i] } +func (a byKey) Less(i, j int) bool { return a[i].key < a[j].key } diff --git a/src/cmd/compile/internal/ssa/gen/rulegen.go b/src/cmd/compile/internal/ssa/gen/rulegen.go new file mode 100644 index 0000000000..e3e3efac41 --- /dev/null +++ b/src/cmd/compile/internal/ssa/gen/rulegen.go @@ -0,0 +1,630 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// This program generates Go code that applies rewrite rules to a Value. +// The generated code implements a function of type func (v *Value) bool +// which returns true iff if did something. +// Ideas stolen from Swift: http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-2000-2.html + +package main + +import ( + "bufio" + "bytes" + "flag" + "fmt" + "go/format" + "io" + "io/ioutil" + "log" + "os" + "regexp" + "sort" + "strings" +) + +// rule syntax: +// sexpr [&& extra conditions] -> [@block] sexpr +// +// sexpr are s-expressions (lisp-like parenthesized groupings) +// sexpr ::= (opcode sexpr*) +// | variable +// | <type> +// | [auxint] +// | {aux} +// +// aux ::= variable | {code} +// type ::= variable | {code} +// variable ::= some token +// opcode ::= one of the opcodes from ../op.go (without the Op prefix) + +// extra conditions is just a chunk of Go that evaluates to a boolean. It may use +// variables declared in the matching sexpr. The variable "v" is predefined to be +// the value matched by the entire rule. + +// If multiple rules match, the first one in file order is selected. + +var ( + genLog = flag.Bool("log", false, "generate code that logs; for debugging only") +) + +type Rule struct { + rule string + lineno int +} + +func (r Rule) String() string { + return fmt.Sprintf("rule %q at line %d", r.rule, r.lineno) +} + +// parse returns the matching part of the rule, additional conditions, and the result. +func (r Rule) parse() (match, cond, result string) { + s := strings.Split(r.rule, "->") + if len(s) != 2 { + log.Fatalf("no arrow in %s", r) + } + match = strings.TrimSpace(s[0]) + result = strings.TrimSpace(s[1]) + cond = "" + if i := strings.Index(match, "&&"); i >= 0 { + cond = strings.TrimSpace(match[i+2:]) + match = strings.TrimSpace(match[:i]) + } + return match, cond, result +} + +func genRules(arch arch) { + // Open input file. + text, err := os.Open(arch.name + ".rules") + if err != nil { + log.Fatalf("can't read rule file: %v", err) + } + + // oprules contains a list of rules for each block and opcode + blockrules := map[string][]Rule{} + oprules := map[string][]Rule{} + + // read rule file + scanner := bufio.NewScanner(text) + rule := "" + var lineno int + for scanner.Scan() { + lineno++ + line := scanner.Text() + if i := strings.Index(line, "//"); i >= 0 { + // Remove comments. Note that this isn't string safe, so + // it will truncate lines with // inside strings. Oh well. + line = line[:i] + } + rule += " " + line + rule = strings.TrimSpace(rule) + if rule == "" { + continue + } + if !strings.Contains(rule, "->") { + continue + } + if strings.HasSuffix(rule, "->") { + continue + } + if unbalanced(rule) { + continue + } + op := strings.Split(rule, " ")[0][1:] + if op[len(op)-1] == ')' { + op = op[:len(op)-1] // rule has only opcode, e.g. (ConstNil) -> ... + } + if isBlock(op, arch) { + blockrules[op] = append(blockrules[op], Rule{rule: rule, lineno: lineno}) + } else { + oprules[op] = append(oprules[op], Rule{rule: rule, lineno: lineno}) + } + rule = "" + } + if err := scanner.Err(); err != nil { + log.Fatalf("scanner failed: %v\n", err) + } + if unbalanced(rule) { + log.Fatalf("unbalanced rule at line %d: %v\n", lineno, rule) + } + + // Order all the ops. + var ops []string + for op := range oprules { + ops = append(ops, op) + } + sort.Strings(ops) + + // Start output buffer, write header. + w := new(bytes.Buffer) + fmt.Fprintf(w, "// autogenerated from gen/%s.rules: do not edit!\n", arch.name) + fmt.Fprintln(w, "// generated with: cd gen; go run *.go") + fmt.Fprintln(w) + fmt.Fprintln(w, "package ssa") + if *genLog { + fmt.Fprintln(w, "import \"fmt\"") + } + fmt.Fprintln(w, "import \"math\"") + fmt.Fprintln(w, "var _ = math.MinInt8 // in case not otherwise used") + + // Main rewrite routine is a switch on v.Op. + fmt.Fprintf(w, "func rewriteValue%s(v *Value, config *Config) bool {\n", arch.name) + fmt.Fprintf(w, "switch v.Op {\n") + for _, op := range ops { + fmt.Fprintf(w, "case %s:\n", opName(op, arch)) + fmt.Fprintf(w, "return rewriteValue%s_%s(v, config)\n", arch.name, opName(op, arch)) + } + fmt.Fprintf(w, "}\n") + fmt.Fprintf(w, "return false\n") + fmt.Fprintf(w, "}\n") + + // Generate a routine per op. Note that we don't make one giant routine + // because it is too big for some compilers. + for _, op := range ops { + fmt.Fprintf(w, "func rewriteValue%s_%s(v *Value, config *Config) bool {\n", arch.name, opName(op, arch)) + fmt.Fprintln(w, "b := v.Block") + fmt.Fprintln(w, "_ = b") + for _, rule := range oprules[op] { + match, cond, result := rule.parse() + fmt.Fprintf(w, "// match: %s\n", match) + fmt.Fprintf(w, "// cond: %s\n", cond) + fmt.Fprintf(w, "// result: %s\n", result) + + fmt.Fprintf(w, "for {\n") + genMatch(w, arch, match) + + if cond != "" { + fmt.Fprintf(w, "if !(%s) {\nbreak\n}\n", cond) + } + + genResult(w, arch, result) + if *genLog { + fmt.Fprintf(w, "fmt.Println(\"rewrite %s.rules:%d\")\n", arch.name, rule.lineno) + } + fmt.Fprintf(w, "return true\n") + + fmt.Fprintf(w, "}\n") + } + fmt.Fprintf(w, "return false\n") + fmt.Fprintf(w, "}\n") + } + + // Generate block rewrite function. There are only a few block types + // so we can make this one function with a switch. + fmt.Fprintf(w, "func rewriteBlock%s(b *Block) bool {\n", arch.name) + fmt.Fprintf(w, "switch b.Kind {\n") + ops = nil + for op := range blockrules { + ops = append(ops, op) + } + sort.Strings(ops) + for _, op := range ops { + fmt.Fprintf(w, "case %s:\n", blockName(op, arch)) + for _, rule := range blockrules[op] { + match, cond, result := rule.parse() + fmt.Fprintf(w, "// match: %s\n", match) + fmt.Fprintf(w, "// cond: %s\n", cond) + fmt.Fprintf(w, "// result: %s\n", result) + + fmt.Fprintf(w, "for {\n") + + s := split(match[1 : len(match)-1]) // remove parens, then split + + // check match of control value + if s[1] != "nil" { + fmt.Fprintf(w, "v := b.Control\n") + genMatch0(w, arch, s[1], "v", map[string]string{}, false) + } + + // assign successor names + succs := s[2:] + for i, a := range succs { + if a != "_" { + fmt.Fprintf(w, "%s := b.Succs[%d]\n", a, i) + } + } + + if cond != "" { + fmt.Fprintf(w, "if !(%s) {\nbreak\n}\n", cond) + } + + // Rule matches. Generate result. + t := split(result[1 : len(result)-1]) // remove parens, then split + newsuccs := t[2:] + + // Check if newsuccs is the same set as succs. + m := map[string]bool{} + for _, succ := range succs { + if m[succ] { + log.Fatalf("can't have a repeat successor name %s in %s", succ, rule) + } + m[succ] = true + } + for _, succ := range newsuccs { + if !m[succ] { + log.Fatalf("unknown successor %s in %s", succ, rule) + } + delete(m, succ) + } + if len(m) != 0 { + log.Fatalf("unmatched successors %v in %s", m, rule) + } + + // Modify predecessor lists for no-longer-reachable blocks + for succ := range m { + fmt.Fprintf(w, "b.Func.removePredecessor(b, %s)\n", succ) + } + + fmt.Fprintf(w, "b.Kind = %s\n", blockName(t[0], arch)) + if t[1] == "nil" { + fmt.Fprintf(w, "b.Control = nil\n") + } else { + fmt.Fprintf(w, "b.Control = %s\n", genResult0(w, arch, t[1], new(int), false, false)) + } + if len(newsuccs) < len(succs) { + fmt.Fprintf(w, "b.Succs = b.Succs[:%d]\n", len(newsuccs)) + } + for i, a := range newsuccs { + fmt.Fprintf(w, "b.Succs[%d] = %s\n", i, a) + } + // Update branch prediction + switch { + case len(newsuccs) != 2: + fmt.Fprintln(w, "b.Likely = BranchUnknown") + case newsuccs[0] == succs[0] && newsuccs[1] == succs[1]: + // unchanged + case newsuccs[0] == succs[1] && newsuccs[1] == succs[0]: + // flipped + fmt.Fprintln(w, "b.Likely *= -1") + default: + // unknown + fmt.Fprintln(w, "b.Likely = BranchUnknown") + } + + if *genLog { + fmt.Fprintf(w, "fmt.Println(\"rewrite %s.rules:%d\")\n", arch.name, rule.lineno) + } + fmt.Fprintf(w, "return true\n") + + fmt.Fprintf(w, "}\n") + } + } + fmt.Fprintf(w, "}\n") + fmt.Fprintf(w, "return false\n") + fmt.Fprintf(w, "}\n") + + // gofmt result + b := w.Bytes() + src, err := format.Source(b) + if err != nil { + fmt.Printf("%s\n", b) + panic(err) + } + + // Write to file + err = ioutil.WriteFile("../rewrite"+arch.name+".go", src, 0666) + if err != nil { + log.Fatalf("can't write output: %v\n", err) + } +} + +func genMatch(w io.Writer, arch arch, match string) { + genMatch0(w, arch, match, "v", map[string]string{}, true) +} + +func genMatch0(w io.Writer, arch arch, match, v string, m map[string]string, top bool) { + if match[0] != '(' { + if _, ok := m[match]; ok { + // variable already has a definition. Check whether + // the old definition and the new definition match. + // For example, (add x x). Equality is just pointer equality + // on Values (so cse is important to do before lowering). + fmt.Fprintf(w, "if %s != %s {\nbreak\n}\n", v, match) + return + } + // remember that this variable references the given value + if match == "_" { + return + } + m[match] = v + fmt.Fprintf(w, "%s := %s\n", match, v) + return + } + + // split body up into regions. Split by spaces/tabs, except those + // contained in () or {}. + s := split(match[1 : len(match)-1]) // remove parens, then split + + // check op + if !top { + fmt.Fprintf(w, "if %s.Op != %s {\nbreak\n}\n", v, opName(s[0], arch)) + } + + // check type/aux/args + argnum := 0 + for _, a := range s[1:] { + if a[0] == '<' { + // type restriction + t := a[1 : len(a)-1] // remove <> + if !isVariable(t) { + // code. We must match the results of this code. + fmt.Fprintf(w, "if %s.Type != %s {\nbreak\n}\n", v, t) + } else { + // variable + if u, ok := m[t]; ok { + // must match previous variable + fmt.Fprintf(w, "if %s.Type != %s {\nbreak\n}\n", v, u) + } else { + m[t] = v + ".Type" + fmt.Fprintf(w, "%s := %s.Type\n", t, v) + } + } + } else if a[0] == '[' { + // auxint restriction + x := a[1 : len(a)-1] // remove [] + if !isVariable(x) { + // code + fmt.Fprintf(w, "if %s.AuxInt != %s {\nbreak\n}\n", v, x) + } else { + // variable + if y, ok := m[x]; ok { + fmt.Fprintf(w, "if %s.AuxInt != %s {\nbreak\n}\n", v, y) + } else { + m[x] = v + ".AuxInt" + fmt.Fprintf(w, "%s := %s.AuxInt\n", x, v) + } + } + } else if a[0] == '{' { + // auxint restriction + x := a[1 : len(a)-1] // remove {} + if !isVariable(x) { + // code + fmt.Fprintf(w, "if %s.Aux != %s {\nbreak\n}\n", v, x) + } else { + // variable + if y, ok := m[x]; ok { + fmt.Fprintf(w, "if %s.Aux != %s {\nbreak\n}\n", v, y) + } else { + m[x] = v + ".Aux" + fmt.Fprintf(w, "%s := %s.Aux\n", x, v) + } + } + } else { + // variable or sexpr + genMatch0(w, arch, a, fmt.Sprintf("%s.Args[%d]", v, argnum), m, false) + argnum++ + } + } + + variableLength := false + for _, op := range genericOps { + if op.name == s[0] && op.argLength == -1 { + variableLength = true + break + } + } + for _, op := range arch.ops { + if op.name == s[0] && op.argLength == -1 { + variableLength = true + break + } + } + if variableLength { + fmt.Fprintf(w, "if len(%s.Args) != %d {\nbreak\n}\n", v, argnum) + } +} + +func genResult(w io.Writer, arch arch, result string) { + move := false + if result[0] == '@' { + // parse @block directive + s := strings.SplitN(result[1:], " ", 2) + fmt.Fprintf(w, "b = %s\n", s[0]) + result = s[1] + move = true + } + genResult0(w, arch, result, new(int), true, move) +} +func genResult0(w io.Writer, arch arch, result string, alloc *int, top, move bool) string { + // TODO: when generating a constant result, use f.constVal to avoid + // introducing copies just to clean them up again. + if result[0] != '(' { + // variable + if top { + // It in not safe in general to move a variable between blocks + // (and particularly not a phi node). + // Introduce a copy. + fmt.Fprintf(w, "v.reset(OpCopy)\n") + fmt.Fprintf(w, "v.Type = %s.Type\n", result) + fmt.Fprintf(w, "v.AddArg(%s)\n", result) + } + return result + } + + s := split(result[1 : len(result)-1]) // remove parens, then split + + // Find the type of the variable. + var opType string + var typeOverride bool + for _, a := range s[1:] { + if a[0] == '<' { + // type restriction + opType = a[1 : len(a)-1] // remove <> + typeOverride = true + break + } + } + if opType == "" { + // find default type, if any + for _, op := range arch.ops { + if op.name == s[0] && op.typ != "" { + opType = typeName(op.typ) + break + } + } + } + if opType == "" { + for _, op := range genericOps { + if op.name == s[0] && op.typ != "" { + opType = typeName(op.typ) + break + } + } + } + var v string + if top && !move { + v = "v" + fmt.Fprintf(w, "v.reset(%s)\n", opName(s[0], arch)) + if typeOverride { + fmt.Fprintf(w, "v.Type = %s\n", opType) + } + } else { + if opType == "" { + log.Fatalf("sub-expression %s (op=%s) must have a type", result, s[0]) + } + v = fmt.Sprintf("v%d", *alloc) + *alloc++ + fmt.Fprintf(w, "%s := b.NewValue0(v.Line, %s, %s)\n", v, opName(s[0], arch), opType) + if move { + // Rewrite original into a copy + fmt.Fprintf(w, "v.reset(OpCopy)\n") + fmt.Fprintf(w, "v.AddArg(%s)\n", v) + } + } + for _, a := range s[1:] { + if a[0] == '<' { + // type restriction, handled above + } else if a[0] == '[' { + // auxint restriction + x := a[1 : len(a)-1] // remove [] + fmt.Fprintf(w, "%s.AuxInt = %s\n", v, x) + } else if a[0] == '{' { + // aux restriction + x := a[1 : len(a)-1] // remove {} + fmt.Fprintf(w, "%s.Aux = %s\n", v, x) + } else { + // regular argument (sexpr or variable) + x := genResult0(w, arch, a, alloc, false, move) + fmt.Fprintf(w, "%s.AddArg(%s)\n", v, x) + } + } + + return v +} + +func split(s string) []string { + var r []string + +outer: + for s != "" { + d := 0 // depth of ({[< + var open, close byte // opening and closing markers ({[< or )}]> + nonsp := false // found a non-space char so far + for i := 0; i < len(s); i++ { + switch { + case d == 0 && s[i] == '(': + open, close = '(', ')' + d++ + case d == 0 && s[i] == '<': + open, close = '<', '>' + d++ + case d == 0 && s[i] == '[': + open, close = '[', ']' + d++ + case d == 0 && s[i] == '{': + open, close = '{', '}' + d++ + case d == 0 && (s[i] == ' ' || s[i] == '\t'): + if nonsp { + r = append(r, strings.TrimSpace(s[:i])) + s = s[i:] + continue outer + } + case d > 0 && s[i] == open: + d++ + case d > 0 && s[i] == close: + d-- + default: + nonsp = true + } + } + if d != 0 { + panic("imbalanced expression: " + s) + } + if nonsp { + r = append(r, strings.TrimSpace(s)) + } + break + } + return r +} + +// isBlock returns true if this op is a block opcode. +func isBlock(name string, arch arch) bool { + for _, b := range genericBlocks { + if b.name == name { + return true + } + } + for _, b := range arch.blocks { + if b.name == name { + return true + } + } + return false +} + +// opName converts from an op name specified in a rule file to an Op enum. +// if the name matches a generic op, returns "Op" plus the specified name. +// Otherwise, returns "Op" plus arch name plus op name. +func opName(name string, arch arch) string { + for _, op := range genericOps { + if op.name == name { + return "Op" + name + } + } + return "Op" + arch.name + name +} + +func blockName(name string, arch arch) string { + for _, b := range genericBlocks { + if b.name == name { + return "Block" + name + } + } + return "Block" + arch.name + name +} + +// typeName returns the string to use to generate a type. +func typeName(typ string) string { + switch typ { + case "Flags", "Mem", "Void", "Int128": + return "Type" + typ + default: + return "config.fe.Type" + typ + "()" + } +} + +// unbalanced returns true if there aren't the same number of ( and ) in the string. +func unbalanced(s string) bool { + var left, right int + for _, c := range s { + if c == '(' { + left++ + } + if c == ')' { + right++ + } + } + return left != right +} + +// isVariable reports whether s is a single Go alphanumeric identifier. +func isVariable(s string) bool { + b, err := regexp.MatchString("^[A-Za-z_][A-Za-z_0-9]*$", s) + if err != nil { + panic("bad variable regexp") + } + return b +} diff --git a/src/cmd/compile/internal/ssa/html.go b/src/cmd/compile/internal/ssa/html.go new file mode 100644 index 0000000000..bb88a3ebde --- /dev/null +++ b/src/cmd/compile/internal/ssa/html.go @@ -0,0 +1,478 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import ( + "bytes" + "fmt" + "html" + "io" + "os" +) + +type HTMLWriter struct { + Logger + *os.File +} + +func NewHTMLWriter(path string, logger Logger, funcname string) *HTMLWriter { + out, err := os.OpenFile(path, os.O_WRONLY|os.O_CREATE|os.O_TRUNC, 0644) + if err != nil { + logger.Fatalf(0, "%v", err) + } + html := HTMLWriter{File: out, Logger: logger} + html.start(funcname) + return &html +} + +func (w *HTMLWriter) start(name string) { + if w == nil { + return + } + w.WriteString("<html>") + w.WriteString(`<head> +<style> + +#helplink { + margin-bottom: 15px; + display: block; + margin-top: -15px; +} + +#help { + display: none; +} + +.stats { + font-size: 60%; +} + +table { + border: 1px solid black; + table-layout: fixed; + width: 300px; +} + +th, td { + border: 1px solid black; + overflow: hidden; + width: 400px; + vertical-align: top; + padding: 5px; +} + +li { + list-style-type: none; +} + +li.ssa-long-value { + text-indent: -2em; /* indent wrapped lines */ +} + +li.ssa-value-list { + display: inline; +} + +li.ssa-start-block { + padding: 0; + margin: 0; +} + +li.ssa-end-block { + padding: 0; + margin: 0; +} + +ul.ssa-print-func { + padding-left: 0; +} + +dl.ssa-gen { + padding-left: 0; +} + +dt.ssa-prog-src { + padding: 0; + margin: 0; + float: left; + width: 4em; +} + +dd.ssa-prog { + padding: 0; + margin-right: 0; + margin-left: 4em; +} + +.dead-value { + color: gray; +} + +.dead-block { + opacity: 0.5; +} + +.depcycle { + font-style: italic; +} + +.highlight-yellow { background-color: yellow; } +.highlight-aquamarine { background-color: aquamarine; } +.highlight-coral { background-color: coral; } +.highlight-lightpink { background-color: lightpink; } +.highlight-lightsteelblue { background-color: lightsteelblue; } +.highlight-palegreen { background-color: palegreen; } +.highlight-powderblue { background-color: powderblue; } +.highlight-lightgray { background-color: lightgray; } + +.outline-blue { outline: blue solid 2px; } +.outline-red { outline: red solid 2px; } +.outline-blueviolet { outline: blueviolet solid 2px; } +.outline-darkolivegreen { outline: darkolivegreen solid 2px; } +.outline-fuchsia { outline: fuchsia solid 2px; } +.outline-sienna { outline: sienna solid 2px; } +.outline-gold { outline: gold solid 2px; } + +</style> + +<script type="text/javascript"> +// ordered list of all available highlight colors +var highlights = [ + "highlight-yellow", + "highlight-aquamarine", + "highlight-coral", + "highlight-lightpink", + "highlight-lightsteelblue", + "highlight-palegreen", + "highlight-lightgray" +]; + +// state: which value is highlighted this color? +var highlighted = {}; +for (var i = 0; i < highlights.length; i++) { + highlighted[highlights[i]] = ""; +} + +// ordered list of all available outline colors +var outlines = [ + "outline-blue", + "outline-red", + "outline-blueviolet", + "outline-darkolivegreen", + "outline-fuchsia", + "outline-sienna", + "outline-gold" +]; + +// state: which value is outlined this color? +var outlined = {}; +for (var i = 0; i < outlines.length; i++) { + outlined[outlines[i]] = ""; +} + +window.onload = function() { + var ssaElemClicked = function(elem, event, selections, selected) { + event.stopPropagation() + + // TODO: pushState with updated state and read it on page load, + // so that state can survive across reloads + + // find all values with the same name + var c = elem.classList.item(0); + var x = document.getElementsByClassName(c); + + // if selected, remove selections from all of them + // otherwise, attempt to add + + var remove = ""; + for (var i = 0; i < selections.length; i++) { + var color = selections[i]; + if (selected[color] == c) { + remove = color; + break; + } + } + + if (remove != "") { + for (var i = 0; i < x.length; i++) { + x[i].classList.remove(remove); + } + selected[remove] = ""; + return; + } + + // we're adding a selection + // find first available color + var avail = ""; + for (var i = 0; i < selections.length; i++) { + var color = selections[i]; + if (selected[color] == "") { + avail = color; + break; + } + } + if (avail == "") { + alert("out of selection colors; go add more"); + return; + } + + // set that as the selection + for (var i = 0; i < x.length; i++) { + x[i].classList.add(avail); + } + selected[avail] = c; + }; + + var ssaValueClicked = function(event) { + ssaElemClicked(this, event, highlights, highlighted); + } + + var ssaBlockClicked = function(event) { + ssaElemClicked(this, event, outlines, outlined); + } + + var ssavalues = document.getElementsByClassName("ssa-value"); + for (var i = 0; i < ssavalues.length; i++) { + ssavalues[i].addEventListener('click', ssaValueClicked); + } + + var ssalongvalues = document.getElementsByClassName("ssa-long-value"); + for (var i = 0; i < ssalongvalues.length; i++) { + // don't attach listeners to li nodes, just the spans they contain + if (ssalongvalues[i].nodeName == "SPAN") { + ssalongvalues[i].addEventListener('click', ssaValueClicked); + } + } + + var ssablocks = document.getElementsByClassName("ssa-block"); + for (var i = 0; i < ssablocks.length; i++) { + ssablocks[i].addEventListener('click', ssaBlockClicked); + } +}; + +function toggle_visibility(id) { + var e = document.getElementById(id); + if(e.style.display == 'block') + e.style.display = 'none'; + else + e.style.display = 'block'; +} +</script> + +</head>`) + // TODO: Add javascript click handlers for blocks + // to outline that block across all phases + w.WriteString("<body>") + w.WriteString("<h1>") + w.WriteString(html.EscapeString(name)) + w.WriteString("</h1>") + w.WriteString(` +<a href="#" onclick="toggle_visibility('help');" id="helplink">help</a> +<div id="help"> + +<p> +Click on a value or block to toggle highlighting of that value/block and its uses. +Values and blocks are highlighted by ID, which may vary across passes. +(TODO: Fix this.) +</p> + +<p> +Faded out values and blocks are dead code that has not been eliminated. +</p> + +<p> +Values printed in italics have a dependency cycle. +</p> + +</div> +`) + w.WriteString("<table>") + w.WriteString("<tr>") +} + +func (w *HTMLWriter) Close() { + if w == nil { + return + } + w.WriteString("</tr>") + w.WriteString("</table>") + w.WriteString("</body>") + w.WriteString("</html>") + w.File.Close() +} + +// WriteFunc writes f in a column headed by title. +func (w *HTMLWriter) WriteFunc(title string, f *Func) { + if w == nil { + return // avoid generating HTML just to discard it + } + w.WriteColumn(title, f.HTML()) + // TODO: Add visual representation of f's CFG. +} + +// WriteColumn writes raw HTML in a column headed by title. +// It is intended for pre- and post-compilation log output. +func (w *HTMLWriter) WriteColumn(title string, html string) { + if w == nil { + return + } + w.WriteString("<td>") + w.WriteString("<h2>" + title + "</h2>") + w.WriteString(html) + w.WriteString("</td>") +} + +func (w *HTMLWriter) Printf(msg string, v ...interface{}) { + if _, err := fmt.Fprintf(w.File, msg, v...); err != nil { + w.Fatalf(0, "%v", err) + } +} + +func (w *HTMLWriter) WriteString(s string) { + if _, err := w.File.WriteString(s); err != nil { + w.Fatalf(0, "%v", err) + } +} + +func (v *Value) HTML() string { + // TODO: Using the value ID as the class ignores the fact + // that value IDs get recycled and that some values + // are transmuted into other values. + return fmt.Sprintf("<span class=\"%[1]s ssa-value\">%[1]s</span>", v.String()) +} + +func (v *Value) LongHTML() string { + // TODO: Any intra-value formatting? + // I'm wary of adding too much visual noise, + // but a little bit might be valuable. + // We already have visual noise in the form of punctuation + // maybe we could replace some of that with formatting. + s := fmt.Sprintf("<span class=\"%s ssa-long-value\">", v.String()) + s += fmt.Sprintf("%s = %s", v.HTML(), v.Op.String()) + s += " <" + html.EscapeString(v.Type.String()) + ">" + if v.AuxInt != 0 { + s += fmt.Sprintf(" [%d]", v.AuxInt) + } + if v.Aux != nil { + if _, ok := v.Aux.(string); ok { + s += html.EscapeString(fmt.Sprintf(" {%q}", v.Aux)) + } else { + s += html.EscapeString(fmt.Sprintf(" {%v}", v.Aux)) + } + } + for _, a := range v.Args { + s += fmt.Sprintf(" %s", a.HTML()) + } + r := v.Block.Func.RegAlloc + if int(v.ID) < len(r) && r[v.ID] != nil { + s += " : " + r[v.ID].Name() + } + + s += "</span>" + return s +} + +func (b *Block) HTML() string { + // TODO: Using the value ID as the class ignores the fact + // that value IDs get recycled and that some values + // are transmuted into other values. + return fmt.Sprintf("<span class=\"%[1]s ssa-block\">%[1]s</span>", html.EscapeString(b.String())) +} + +func (b *Block) LongHTML() string { + // TODO: improve this for HTML? + s := fmt.Sprintf("<span class=\"%s ssa-block\">%s</span>", html.EscapeString(b.String()), html.EscapeString(b.Kind.String())) + if b.Aux != nil { + s += html.EscapeString(fmt.Sprintf(" {%v}", b.Aux)) + } + if b.Control != nil { + s += fmt.Sprintf(" %s", b.Control.HTML()) + } + if len(b.Succs) > 0 { + s += " →" // right arrow + for _, c := range b.Succs { + s += " " + c.HTML() + } + } + switch b.Likely { + case BranchUnlikely: + s += " (unlikely)" + case BranchLikely: + s += " (likely)" + } + return s +} + +func (f *Func) HTML() string { + var buf bytes.Buffer + fmt.Fprint(&buf, "<code>") + p := htmlFuncPrinter{w: &buf} + fprintFunc(p, f) + + // fprintFunc(&buf, f) // TODO: HTML, not text, <br /> for line breaks, etc. + fmt.Fprint(&buf, "</code>") + return buf.String() +} + +type htmlFuncPrinter struct { + w io.Writer +} + +func (p htmlFuncPrinter) header(f *Func) {} + +func (p htmlFuncPrinter) startBlock(b *Block, reachable bool) { + // TODO: Make blocks collapsable? + var dead string + if !reachable { + dead = "dead-block" + } + fmt.Fprintf(p.w, "<ul class=\"%s ssa-print-func %s\">", b, dead) + fmt.Fprintf(p.w, "<li class=\"ssa-start-block\">%s:", b.HTML()) + if len(b.Preds) > 0 { + io.WriteString(p.w, " ←") // left arrow + for _, pred := range b.Preds { + fmt.Fprintf(p.w, " %s", pred.HTML()) + } + } + io.WriteString(p.w, "</li>") + if len(b.Values) > 0 { // start list of values + io.WriteString(p.w, "<li class=\"ssa-value-list\">") + io.WriteString(p.w, "<ul>") + } +} + +func (p htmlFuncPrinter) endBlock(b *Block) { + if len(b.Values) > 0 { // end list of values + io.WriteString(p.w, "</ul>") + io.WriteString(p.w, "</li>") + } + io.WriteString(p.w, "<li class=\"ssa-end-block\">") + fmt.Fprint(p.w, b.LongHTML()) + io.WriteString(p.w, "</li>") + io.WriteString(p.w, "</ul>") + // io.WriteString(p.w, "</span>") +} + +func (p htmlFuncPrinter) value(v *Value, live bool) { + var dead string + if !live { + dead = "dead-value" + } + fmt.Fprintf(p.w, "<li class=\"ssa-long-value %s\">", dead) + fmt.Fprint(p.w, v.LongHTML()) + io.WriteString(p.w, "</li>") +} + +func (p htmlFuncPrinter) startDepCycle() { + fmt.Fprintln(p.w, "<span class=\"depcycle\">") +} + +func (p htmlFuncPrinter) endDepCycle() { + fmt.Fprintln(p.w, "</span>") +} + +func (p htmlFuncPrinter) named(n LocalSlot, vals []*Value) { + // TODO +} diff --git a/src/cmd/compile/internal/ssa/id.go b/src/cmd/compile/internal/ssa/id.go new file mode 100644 index 0000000000..367e687abf --- /dev/null +++ b/src/cmd/compile/internal/ssa/id.go @@ -0,0 +1,28 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +type ID int32 + +// idAlloc provides an allocator for unique integers. +type idAlloc struct { + last ID +} + +// get allocates an ID and returns it. +func (a *idAlloc) get() ID { + x := a.last + x++ + if x == 1<<31-1 { + panic("too many ids for this function") + } + a.last = x + return x +} + +// num returns the maximum ID ever returned + 1. +func (a *idAlloc) num() int { + return int(a.last + 1) +} diff --git a/src/cmd/compile/internal/ssa/layout.go b/src/cmd/compile/internal/ssa/layout.go new file mode 100644 index 0000000000..8dd4b65979 --- /dev/null +++ b/src/cmd/compile/internal/ssa/layout.go @@ -0,0 +1,102 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +// layout orders basic blocks in f with the goal of minimizing control flow instructions. +// After this phase returns, the order of f.Blocks matters and is the order +// in which those blocks will appear in the assembly output. +func layout(f *Func) { + order := make([]*Block, 0, f.NumBlocks()) + scheduled := make([]bool, f.NumBlocks()) + idToBlock := make([]*Block, f.NumBlocks()) + indegree := make([]int, f.NumBlocks()) + posdegree := f.newSparseSet(f.NumBlocks()) // blocks with positive remaining degree + defer f.retSparseSet(posdegree) + zerodegree := f.newSparseSet(f.NumBlocks()) // blocks with zero remaining degree + defer f.retSparseSet(zerodegree) + + // Initialize indegree of each block + for _, b := range f.Blocks { + idToBlock[b.ID] = b + indegree[b.ID] = len(b.Preds) + if len(b.Preds) == 0 { + zerodegree.add(b.ID) + } else { + posdegree.add(b.ID) + } + } + + bid := f.Entry.ID +blockloop: + for { + // add block to schedule + b := idToBlock[bid] + order = append(order, b) + scheduled[bid] = true + if len(order) == len(f.Blocks) { + break + } + + for _, c := range b.Succs { + indegree[c.ID]-- + if indegree[c.ID] == 0 { + posdegree.remove(c.ID) + zerodegree.add(c.ID) + } + } + + // Pick the next block to schedule + // Pick among the successor blocks that have not been scheduled yet. + + // Use likely direction if we have it. + var likely *Block + switch b.Likely { + case BranchLikely: + likely = b.Succs[0] + case BranchUnlikely: + likely = b.Succs[1] + } + if likely != nil && !scheduled[likely.ID] { + bid = likely.ID + continue + } + + // Use degree for now. + bid = 0 + mindegree := f.NumBlocks() + for _, c := range order[len(order)-1].Succs { + if scheduled[c.ID] { + continue + } + if indegree[c.ID] < mindegree { + mindegree = indegree[c.ID] + bid = c.ID + } + } + if bid != 0 { + continue + } + // TODO: improve this part + // No successor of the previously scheduled block works. + // Pick a zero-degree block if we can. + for zerodegree.size() > 0 { + cid := zerodegree.pop() + if !scheduled[cid] { + bid = cid + continue blockloop + } + } + // Still nothing, pick any block. + for { + cid := posdegree.pop() + if !scheduled[cid] { + bid = cid + continue blockloop + } + } + b.Fatalf("no block available for layout") + } + f.Blocks = order +} diff --git a/src/cmd/compile/internal/ssa/likelyadjust.go b/src/cmd/compile/internal/ssa/likelyadjust.go new file mode 100755 index 0000000000..6ce8705272 --- /dev/null +++ b/src/cmd/compile/internal/ssa/likelyadjust.go @@ -0,0 +1,300 @@ +// Copyright 2016 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import ( + "fmt" +) + +type loop struct { + header *Block // The header node of this (reducible) loop + outer *loop // loop containing this loop + // Next two fields not currently used, but cheap to maintain, + // and aid in computation of inner-ness and list of blocks. + nBlocks int32 // Number of blocks in this loop but not within inner loops + isInner bool // True if never discovered to contain a loop +} + +// outerinner records that outer contains inner +func (sdom sparseTree) outerinner(outer, inner *loop) { + oldouter := inner.outer + if oldouter == nil || sdom.isAncestorEq(oldouter.header, outer.header) { + inner.outer = outer + outer.isInner = false + } +} + +type loopnest struct { + f *Func + b2l []*loop + po []*Block + sdom sparseTree + loops []*loop +} + +func min8(a, b int8) int8 { + if a < b { + return a + } + return b +} + +func max8(a, b int8) int8 { + if a > b { + return a + } + return b +} + +const ( + blDEFAULT = 0 + blMin = blDEFAULT + blCALL = 1 + blRET = 2 + blEXIT = 3 +) + +var bllikelies [4]string = [4]string{"default", "call", "ret", "exit"} + +func describePredictionAgrees(b *Block, prediction BranchPrediction) string { + s := "" + if prediction == b.Likely { + s = " (agrees with previous)" + } else if b.Likely != BranchUnknown { + s = " (disagrees with previous, ignored)" + } + return s +} + +func describeBranchPrediction(f *Func, b *Block, likely, not int8, prediction BranchPrediction) { + f.Config.Warnl(int(b.Line), "Branch prediction rule %s < %s%s", + bllikelies[likely-blMin], bllikelies[not-blMin], describePredictionAgrees(b, prediction)) +} + +func likelyadjust(f *Func) { + // The values assigned to certain and local only matter + // in their rank order. 0 is default, more positive + // is less likely. It's possible to assign a negative + // unlikeliness (though not currently the case). + certain := make([]int8, f.NumBlocks()) // In the long run, all outcomes are at least this bad. Mainly for Exit + local := make([]int8, f.NumBlocks()) // for our immediate predecessors. + + nest := loopnestfor(f) + po := nest.po + b2l := nest.b2l + + for _, b := range po { + switch b.Kind { + case BlockExit: + // Very unlikely. + local[b.ID] = blEXIT + certain[b.ID] = blEXIT + + // Ret, it depends. + case BlockRet, BlockRetJmp: + local[b.ID] = blRET + certain[b.ID] = blRET + + // Calls. TODO not all calls are equal, names give useful clues. + // Any name-based heuristics are only relative to other calls, + // and less influential than inferences from loop structure. + case BlockCall: + local[b.ID] = blCALL + certain[b.ID] = max8(blCALL, certain[b.Succs[0].ID]) + + default: + if len(b.Succs) == 1 { + certain[b.ID] = certain[b.Succs[0].ID] + } else if len(b.Succs) == 2 { + // If successor is an unvisited backedge, it's in loop and we don't care. + // Its default unlikely is also zero which is consistent with favoring loop edges. + // Notice that this can act like a "reset" on unlikeliness at loops; the + // default "everything returns" unlikeliness is erased by min with the + // backedge likeliness; however a loop with calls on every path will be + // tagged with call cost. Net effect is that loop entry is favored. + b0 := b.Succs[0].ID + b1 := b.Succs[1].ID + certain[b.ID] = min8(certain[b0], certain[b1]) + + l := b2l[b.ID] + l0 := b2l[b0] + l1 := b2l[b1] + + prediction := b.Likely + // Weak loop heuristic -- both source and at least one dest are in loops, + // and there is a difference in the destinations. + // TODO what is best arrangement for nested loops? + if l != nil && l0 != l1 { + noprediction := false + switch { + // prefer not to exit loops + case l1 == nil: + prediction = BranchLikely + case l0 == nil: + prediction = BranchUnlikely + + // prefer to stay in loop, not exit to outer. + case l == l0: + prediction = BranchLikely + case l == l1: + prediction = BranchUnlikely + default: + noprediction = true + } + if f.pass.debug > 0 && !noprediction { + f.Config.Warnl(int(b.Line), "Branch prediction rule stay in loop%s", + describePredictionAgrees(b, prediction)) + } + + } else { + // Lacking loop structure, fall back on heuristics. + if certain[b1] > certain[b0] { + prediction = BranchLikely + if f.pass.debug > 0 { + describeBranchPrediction(f, b, certain[b0], certain[b1], prediction) + } + } else if certain[b0] > certain[b1] { + prediction = BranchUnlikely + if f.pass.debug > 0 { + describeBranchPrediction(f, b, certain[b1], certain[b0], prediction) + } + } else if local[b1] > local[b0] { + prediction = BranchLikely + if f.pass.debug > 0 { + describeBranchPrediction(f, b, local[b0], local[b1], prediction) + } + } else if local[b0] > local[b1] { + prediction = BranchUnlikely + if f.pass.debug > 0 { + describeBranchPrediction(f, b, local[b1], local[b0], prediction) + } + } + } + if b.Likely != prediction { + if b.Likely == BranchUnknown { + b.Likely = prediction + } + } + } + } + if f.pass.debug > 2 { + f.Config.Warnl(int(b.Line), "BP: Block %s, local=%s, certain=%s", b, bllikelies[local[b.ID]-blMin], bllikelies[certain[b.ID]-blMin]) + } + + } +} + +func (l *loop) String() string { + return fmt.Sprintf("hdr:%s", l.header) +} + +func (l *loop) LongString() string { + i := "" + o := "" + if l.isInner { + i = ", INNER" + } + if l.outer != nil { + o = ", o=" + l.outer.header.String() + } + return fmt.Sprintf("hdr:%s%s%s", l.header, i, o) +} + +// nearestOuterLoop returns the outer loop of loop most nearly +// containing block b; the header must dominate b. loop itself +// is assumed to not be that loop. For acceptable performance, +// we're relying on loop nests to not be terribly deep. +func (l *loop) nearestOuterLoop(sdom sparseTree, b *Block) *loop { + var o *loop + for o = l.outer; o != nil && !sdom.isAncestorEq(o.header, b); o = o.outer { + } + return o +} + +func loopnestfor(f *Func) *loopnest { + po := postorder(f) + dom := dominators(f) + sdom := newSparseTree(f, dom) + b2l := make([]*loop, f.NumBlocks()) + loops := make([]*loop, 0) + + // Reducible-loop-nest-finding. + for _, b := range po { + if f.pass.debug > 3 { + fmt.Printf("loop finding (0) at %s\n", b) + } + + var innermost *loop // innermost header reachable from this block + + // IF any successor s of b is in a loop headed by h + // AND h dominates b + // THEN b is in the loop headed by h. + // + // Choose the first/innermost such h. + // + // IF s itself dominates b, the s is a loop header; + // and there may be more than one such s. + // Since there's at most 2 successors, the inner/outer ordering + // between them can be established with simple comparisons. + for _, bb := range b.Succs { + l := b2l[bb.ID] + + if sdom.isAncestorEq(bb, b) { // Found a loop header + if l == nil { + l = &loop{header: bb, isInner: true} + loops = append(loops, l) + b2l[bb.ID] = l + } + } else { // Perhaps a loop header is inherited. + // is there any loop containing our successor whose + // header dominates b? + if l != nil && !sdom.isAncestorEq(l.header, b) { + l = l.nearestOuterLoop(sdom, b) + } + } + + if l == nil || innermost == l { + continue + } + + if innermost == nil { + innermost = l + continue + } + + if sdom.isAncestor(innermost.header, l.header) { + sdom.outerinner(innermost, l) + innermost = l + } else if sdom.isAncestor(l.header, innermost.header) { + sdom.outerinner(l, innermost) + } + } + + if innermost != nil { + b2l[b.ID] = innermost + innermost.nBlocks++ + } + } + if f.pass.debug > 1 && len(loops) > 0 { + fmt.Printf("Loops in %s:\n", f.Name) + for _, l := range loops { + fmt.Printf("%s, b=", l.LongString()) + for _, b := range f.Blocks { + if b2l[b.ID] == l { + fmt.Printf(" %s", b) + } + } + fmt.Print("\n") + } + fmt.Printf("Nonloop blocks in %s:", f.Name) + for _, b := range f.Blocks { + if b2l[b.ID] == nil { + fmt.Printf(" %s", b) + } + } + fmt.Print("\n") + } + return &loopnest{f, b2l, po, sdom, loops} +} diff --git a/src/cmd/compile/internal/ssa/location.go b/src/cmd/compile/internal/ssa/location.go new file mode 100644 index 0000000000..85f525565b --- /dev/null +++ b/src/cmd/compile/internal/ssa/location.go @@ -0,0 +1,38 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import "fmt" + +// A place that an ssa variable can reside. +type Location interface { + Name() string // name to use in assembly templates: %rax, 16(%rsp), ... +} + +// A Register is a machine register, like %rax. +// They are numbered densely from 0 (for each architecture). +type Register struct { + Num int32 + name string +} + +func (r *Register) Name() string { + return r.name +} + +// A LocalSlot is a location in the stack frame. +// It is (possibly a subpiece of) a PPARAM, PPARAMOUT, or PAUTO ONAME node. +type LocalSlot struct { + N GCNode // an ONAME *gc.Node representing a variable on the stack + Type Type // type of slot + Off int64 // offset of slot in N +} + +func (s LocalSlot) Name() string { + if s.Off == 0 { + return fmt.Sprintf("%s[%s]", s.N, s.Type) + } + return fmt.Sprintf("%s+%d[%s]", s.N, s.Off, s.Type) +} diff --git a/src/cmd/compile/internal/ssa/lower.go b/src/cmd/compile/internal/ssa/lower.go new file mode 100644 index 0000000000..af0ee4cccf --- /dev/null +++ b/src/cmd/compile/internal/ssa/lower.go @@ -0,0 +1,34 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +// convert to machine-dependent ops +func lower(f *Func) { + // repeat rewrites until we find no more rewrites + applyRewrite(f, f.Config.lowerBlock, f.Config.lowerValue) +} + +// checkLower checks for unlowered opcodes and fails if we find one. +func checkLower(f *Func) { + // Needs to be a separate phase because it must run after both + // lowering and a subsequent dead code elimination (because lowering + // rules may leave dead generic ops behind). + for _, b := range f.Blocks { + for _, v := range b.Values { + if !opcodeTable[v.Op].generic { + continue // lowered + } + switch v.Op { + case OpSP, OpSB, OpInitMem, OpArg, OpPhi, OpVarDef, OpVarKill, OpVarLive: + continue // ok not to lower + } + s := "not lowered: " + v.Op.String() + " " + v.Type.SimpleString() + for _, a := range v.Args { + s += " " + a.Type.SimpleString() + } + f.Unimplementedf("%s", s) + } + } +} diff --git a/src/cmd/compile/internal/ssa/magic.go b/src/cmd/compile/internal/ssa/magic.go new file mode 100644 index 0000000000..a8e84d5c93 --- /dev/null +++ b/src/cmd/compile/internal/ssa/magic.go @@ -0,0 +1,260 @@ +// Copyright 2016 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +// A copy of the code in ../gc/subr.go. +// We can't use it directly because it would generate +// an import cycle. TODO: move to a common support package. + +// argument passing to/from +// smagic and umagic +type magic struct { + W int // input for both - width + S int // output for both - shift + Bad int // output for both - unexpected failure + + // magic multiplier for signed literal divisors + Sd int64 // input - literal divisor + Sm int64 // output - multiplier + + // magic multiplier for unsigned literal divisors + Ud uint64 // input - literal divisor + Um uint64 // output - multiplier + Ua int // output - adder +} + +// magic number for signed division +// see hacker's delight chapter 10 +func smagic(m *magic) { + var mask uint64 + + m.Bad = 0 + switch m.W { + default: + m.Bad = 1 + return + + case 8: + mask = 0xff + + case 16: + mask = 0xffff + + case 32: + mask = 0xffffffff + + case 64: + mask = 0xffffffffffffffff + } + + two31 := mask ^ (mask >> 1) + + p := m.W - 1 + ad := uint64(m.Sd) + if m.Sd < 0 { + ad = -uint64(m.Sd) + } + + // bad denominators + if ad == 0 || ad == 1 || ad == two31 { + m.Bad = 1 + return + } + + t := two31 + ad &= mask + + anc := t - 1 - t%ad + anc &= mask + + q1 := two31 / anc + r1 := two31 - q1*anc + q1 &= mask + r1 &= mask + + q2 := two31 / ad + r2 := two31 - q2*ad + q2 &= mask + r2 &= mask + + var delta uint64 + for { + p++ + q1 <<= 1 + r1 <<= 1 + q1 &= mask + r1 &= mask + if r1 >= anc { + q1++ + r1 -= anc + q1 &= mask + r1 &= mask + } + + q2 <<= 1 + r2 <<= 1 + q2 &= mask + r2 &= mask + if r2 >= ad { + q2++ + r2 -= ad + q2 &= mask + r2 &= mask + } + + delta = ad - r2 + delta &= mask + if q1 < delta || (q1 == delta && r1 == 0) { + continue + } + + break + } + + m.Sm = int64(q2 + 1) + if uint64(m.Sm)&two31 != 0 { + m.Sm |= ^int64(mask) + } + m.S = p - m.W +} + +// magic number for unsigned division +// see hacker's delight chapter 10 +func umagic(m *magic) { + var mask uint64 + + m.Bad = 0 + m.Ua = 0 + + switch m.W { + default: + m.Bad = 1 + return + + case 8: + mask = 0xff + + case 16: + mask = 0xffff + + case 32: + mask = 0xffffffff + + case 64: + mask = 0xffffffffffffffff + } + + two31 := mask ^ (mask >> 1) + + m.Ud &= mask + if m.Ud == 0 || m.Ud == two31 { + m.Bad = 1 + return + } + + nc := mask - (-m.Ud&mask)%m.Ud + p := m.W - 1 + + q1 := two31 / nc + r1 := two31 - q1*nc + q1 &= mask + r1 &= mask + + q2 := (two31 - 1) / m.Ud + r2 := (two31 - 1) - q2*m.Ud + q2 &= mask + r2 &= mask + + var delta uint64 + for { + p++ + if r1 >= nc-r1 { + q1 <<= 1 + q1++ + r1 <<= 1 + r1 -= nc + } else { + q1 <<= 1 + r1 <<= 1 + } + + q1 &= mask + r1 &= mask + if r2+1 >= m.Ud-r2 { + if q2 >= two31-1 { + m.Ua = 1 + } + + q2 <<= 1 + q2++ + r2 <<= 1 + r2++ + r2 -= m.Ud + } else { + if q2 >= two31 { + m.Ua = 1 + } + + q2 <<= 1 + r2 <<= 1 + r2++ + } + + q2 &= mask + r2 &= mask + + delta = m.Ud - 1 - r2 + delta &= mask + + if p < m.W+m.W { + if q1 < delta || (q1 == delta && r1 == 0) { + continue + } + } + + break + } + + m.Um = q2 + 1 + m.S = p - m.W +} + +// adaptors for use by rewrite rules +func smagic64ok(d int64) bool { + m := magic{W: 64, Sd: d} + smagic(&m) + return m.Bad == 0 +} +func smagic64m(d int64) int64 { + m := magic{W: 64, Sd: d} + smagic(&m) + return m.Sm +} +func smagic64s(d int64) int64 { + m := magic{W: 64, Sd: d} + smagic(&m) + return int64(m.S) +} + +func umagic64ok(d int64) bool { + m := magic{W: 64, Ud: uint64(d)} + umagic(&m) + return m.Bad == 0 +} +func umagic64m(d int64) int64 { + m := magic{W: 64, Ud: uint64(d)} + umagic(&m) + return int64(m.Um) +} +func umagic64s(d int64) int64 { + m := magic{W: 64, Ud: uint64(d)} + umagic(&m) + return int64(m.S) +} +func umagic64a(d int64) bool { + m := magic{W: 64, Ud: uint64(d)} + umagic(&m) + return m.Ua != 0 +} diff --git a/src/cmd/compile/internal/ssa/nilcheck.go b/src/cmd/compile/internal/ssa/nilcheck.go new file mode 100644 index 0000000000..f8caa7b042 --- /dev/null +++ b/src/cmd/compile/internal/ssa/nilcheck.go @@ -0,0 +1,163 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +// TODO: return value from newobject/newarray is non-nil. + +// nilcheckelim eliminates unnecessary nil checks. +func nilcheckelim(f *Func) { + // A nil check is redundant if the same nil check was successful in a + // dominating block. The efficacy of this pass depends heavily on the + // efficacy of the cse pass. + idom := dominators(f) + domTree := make([][]*Block, f.NumBlocks()) + + // Create a block ID -> [dominees] mapping + for _, b := range f.Blocks { + if dom := idom[b.ID]; dom != nil { + domTree[dom.ID] = append(domTree[dom.ID], b) + } + } + + // TODO: Eliminate more nil checks. + // We can recursively remove any chain of fixed offset calculations, + // i.e. struct fields and array elements, even with non-constant + // indices: x is non-nil iff x.a.b[i].c is. + + type walkState int + const ( + Work walkState = iota // clear nil check if we should and traverse to dominees regardless + RecPtr // record the pointer as being nil checked + ClearPtr + ) + + type bp struct { + block *Block // block, or nil in RecPtr/ClearPtr state + ptr *Value // if non-nil, ptr that is to be set/cleared in RecPtr/ClearPtr state + op walkState + } + + work := make([]bp, 0, 256) + work = append(work, bp{block: f.Entry}) + + // map from value ID to bool indicating if value is known to be non-nil + // in the current dominator path being walked. This slice is updated by + // walkStates to maintain the known non-nil values. + nonNilValues := make([]bool, f.NumValues()) + + // make an initial pass identifying any non-nil values + for _, b := range f.Blocks { + // a value resulting from taking the address of a + // value, or a value constructed from an offset of a + // non-nil ptr (OpAddPtr) implies it is non-nil + for _, v := range b.Values { + if v.Op == OpAddr || v.Op == OpAddPtr { + nonNilValues[v.ID] = true + } else if v.Op == OpPhi { + // phis whose arguments are all non-nil + // are non-nil + argsNonNil := true + for _, a := range v.Args { + if !nonNilValues[a.ID] { + argsNonNil = false + } + } + if argsNonNil { + nonNilValues[v.ID] = true + } + } + } + } + + // perform a depth first walk of the dominee tree + for len(work) > 0 { + node := work[len(work)-1] + work = work[:len(work)-1] + + switch node.op { + case Work: + checked := checkedptr(node.block) // ptr being checked for nil/non-nil + nonnil := nonnilptr(node.block) // ptr that is non-nil due to this blocks pred + + if checked != nil { + // already have a nilcheck in the dominator path, or this block is a success + // block for the same value it is checking + if nonNilValues[checked.ID] || checked == nonnil { + // Eliminate the nil check. + // The deadcode pass will remove vestigial values, + // and the fuse pass will join this block with its successor. + + // Logging in the style of the former compiler -- and omit line 1, + // which is usually in generated code. + if f.Config.Debug_checknil() && int(node.block.Control.Line) > 1 { + f.Config.Warnl(int(node.block.Control.Line), "removed nil check") + } + + switch node.block.Kind { + case BlockIf: + node.block.Kind = BlockFirst + node.block.Control = nil + case BlockCheck: + node.block.Kind = BlockPlain + node.block.Control = nil + default: + f.Fatalf("bad block kind in nilcheck %s", node.block.Kind) + } + } + } + + if nonnil != nil && !nonNilValues[nonnil.ID] { + // this is a new nilcheck so add a ClearPtr node to clear the + // ptr from the map of nil checks once we traverse + // back up the tree + work = append(work, bp{op: ClearPtr, ptr: nonnil}) + } + + // add all dominated blocks to the work list + for _, w := range domTree[node.block.ID] { + work = append(work, bp{block: w}) + } + + if nonnil != nil && !nonNilValues[nonnil.ID] { + work = append(work, bp{op: RecPtr, ptr: nonnil}) + } + case RecPtr: + nonNilValues[node.ptr.ID] = true + continue + case ClearPtr: + nonNilValues[node.ptr.ID] = false + continue + } + } +} + +// checkedptr returns the Value, if any, +// that is used in a nil check in b's Control op. +func checkedptr(b *Block) *Value { + if b.Kind == BlockCheck { + return b.Control.Args[0] + } + if b.Kind == BlockIf && b.Control.Op == OpIsNonNil { + return b.Control.Args[0] + } + return nil +} + +// nonnilptr returns the Value, if any, +// that is non-nil due to b being the successor block +// of an OpIsNonNil or OpNilCheck block for the value and having a single +// predecessor. +func nonnilptr(b *Block) *Value { + if len(b.Preds) == 1 { + bp := b.Preds[0] + if bp.Kind == BlockCheck { + return bp.Control.Args[0] + } + if bp.Kind == BlockIf && bp.Control.Op == OpIsNonNil && bp.Succs[0] == b { + return bp.Control.Args[0] + } + } + return nil +} diff --git a/src/cmd/compile/internal/ssa/nilcheck_test.go b/src/cmd/compile/internal/ssa/nilcheck_test.go new file mode 100644 index 0000000000..2d1dbc6f3e --- /dev/null +++ b/src/cmd/compile/internal/ssa/nilcheck_test.go @@ -0,0 +1,433 @@ +package ssa + +import ( + "strconv" + "testing" +) + +func BenchmarkNilCheckDeep1(b *testing.B) { benchmarkNilCheckDeep(b, 1) } +func BenchmarkNilCheckDeep10(b *testing.B) { benchmarkNilCheckDeep(b, 10) } +func BenchmarkNilCheckDeep100(b *testing.B) { benchmarkNilCheckDeep(b, 100) } +func BenchmarkNilCheckDeep1000(b *testing.B) { benchmarkNilCheckDeep(b, 1000) } +func BenchmarkNilCheckDeep10000(b *testing.B) { benchmarkNilCheckDeep(b, 10000) } + +// benchmarkNilCheckDeep is a stress test of nilcheckelim. +// It uses the worst possible input: A linear string of +// nil checks, none of which can be eliminated. +// Run with multiple depths to observe big-O behavior. +func benchmarkNilCheckDeep(b *testing.B, depth int) { + ptrType := &TypeImpl{Size_: 8, Ptr: true, Name: "testptr"} // dummy for testing + + var blocs []bloc + blocs = append(blocs, + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("sb", OpSB, TypeInvalid, 0, nil), + Goto(blockn(0)), + ), + ) + for i := 0; i < depth; i++ { + blocs = append(blocs, + Bloc(blockn(i), + Valu(ptrn(i), OpAddr, ptrType, 0, nil, "sb"), + Valu(booln(i), OpIsNonNil, TypeBool, 0, nil, ptrn(i)), + If(booln(i), blockn(i+1), "exit"), + ), + ) + } + blocs = append(blocs, + Bloc(blockn(depth), Goto("exit")), + Bloc("exit", Exit("mem")), + ) + + c := NewConfig("amd64", DummyFrontend{b}, nil, true) + fun := Fun(c, "entry", blocs...) + + CheckFunc(fun.f) + b.SetBytes(int64(depth)) // helps for eyeballing linearity + b.ResetTimer() + b.ReportAllocs() + + for i := 0; i < b.N; i++ { + nilcheckelim(fun.f) + } +} + +func blockn(n int) string { return "b" + strconv.Itoa(n) } +func ptrn(n int) string { return "p" + strconv.Itoa(n) } +func booln(n int) string { return "c" + strconv.Itoa(n) } + +func isNilCheck(b *Block) bool { + return b.Kind == BlockIf && b.Control.Op == OpIsNonNil +} + +// TestNilcheckSimple verifies that a second repeated nilcheck is removed. +func TestNilcheckSimple(t *testing.T) { + ptrType := &TypeImpl{Size_: 8, Ptr: true, Name: "testptr"} // dummy for testing + c := NewConfig("amd64", DummyFrontend{t}, nil, true) + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("sb", OpSB, TypeInvalid, 0, nil), + Goto("checkPtr")), + Bloc("checkPtr", + Valu("ptr1", OpLoad, ptrType, 0, nil, "sb", "mem"), + Valu("bool1", OpIsNonNil, TypeBool, 0, nil, "ptr1"), + If("bool1", "secondCheck", "exit")), + Bloc("secondCheck", + Valu("bool2", OpIsNonNil, TypeBool, 0, nil, "ptr1"), + If("bool2", "extra", "exit")), + Bloc("extra", + Goto("exit")), + Bloc("exit", + Exit("mem"))) + + CheckFunc(fun.f) + nilcheckelim(fun.f) + + // clean up the removed nil check + fuse(fun.f) + deadcode(fun.f) + + CheckFunc(fun.f) + for _, b := range fun.f.Blocks { + if b == fun.blocks["secondCheck"] && isNilCheck(b) { + t.Errorf("secondCheck was not eliminated") + } + } +} + +// TestNilcheckDomOrder ensures that the nil check elimination isn't dependant +// on the order of the dominees. +func TestNilcheckDomOrder(t *testing.T) { + ptrType := &TypeImpl{Size_: 8, Ptr: true, Name: "testptr"} // dummy for testing + c := NewConfig("amd64", DummyFrontend{t}, nil, true) + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("sb", OpSB, TypeInvalid, 0, nil), + Goto("checkPtr")), + Bloc("checkPtr", + Valu("ptr1", OpLoad, ptrType, 0, nil, "sb", "mem"), + Valu("bool1", OpIsNonNil, TypeBool, 0, nil, "ptr1"), + If("bool1", "secondCheck", "exit")), + Bloc("exit", + Exit("mem")), + Bloc("secondCheck", + Valu("bool2", OpIsNonNil, TypeBool, 0, nil, "ptr1"), + If("bool2", "extra", "exit")), + Bloc("extra", + Goto("exit"))) + + CheckFunc(fun.f) + nilcheckelim(fun.f) + + // clean up the removed nil check + fuse(fun.f) + deadcode(fun.f) + + CheckFunc(fun.f) + for _, b := range fun.f.Blocks { + if b == fun.blocks["secondCheck"] && isNilCheck(b) { + t.Errorf("secondCheck was not eliminated") + } + } +} + +// TestNilcheckAddr verifies that nilchecks of OpAddr constructed values are removed. +func TestNilcheckAddr(t *testing.T) { + ptrType := &TypeImpl{Size_: 8, Ptr: true, Name: "testptr"} // dummy for testing + c := NewConfig("amd64", DummyFrontend{t}, nil, true) + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("sb", OpSB, TypeInvalid, 0, nil), + Goto("checkPtr")), + Bloc("checkPtr", + Valu("ptr1", OpAddr, ptrType, 0, nil, "sb"), + Valu("bool1", OpIsNonNil, TypeBool, 0, nil, "ptr1"), + If("bool1", "extra", "exit")), + Bloc("extra", + Goto("exit")), + Bloc("exit", + Exit("mem"))) + + CheckFunc(fun.f) + nilcheckelim(fun.f) + + // clean up the removed nil check + fuse(fun.f) + deadcode(fun.f) + + CheckFunc(fun.f) + for _, b := range fun.f.Blocks { + if b == fun.blocks["checkPtr"] && isNilCheck(b) { + t.Errorf("checkPtr was not eliminated") + } + } +} + +// TestNilcheckAddPtr verifies that nilchecks of OpAddPtr constructed values are removed. +func TestNilcheckAddPtr(t *testing.T) { + ptrType := &TypeImpl{Size_: 8, Ptr: true, Name: "testptr"} // dummy for testing + c := NewConfig("amd64", DummyFrontend{t}, nil, true) + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("sb", OpSB, TypeInvalid, 0, nil), + Goto("checkPtr")), + Bloc("checkPtr", + Valu("off", OpConst64, TypeInt64, 20, nil), + Valu("ptr1", OpAddPtr, ptrType, 0, nil, "sb", "off"), + Valu("bool1", OpIsNonNil, TypeBool, 0, nil, "ptr1"), + If("bool1", "extra", "exit")), + Bloc("extra", + Goto("exit")), + Bloc("exit", + Exit("mem"))) + + CheckFunc(fun.f) + nilcheckelim(fun.f) + + // clean up the removed nil check + fuse(fun.f) + deadcode(fun.f) + + CheckFunc(fun.f) + for _, b := range fun.f.Blocks { + if b == fun.blocks["checkPtr"] && isNilCheck(b) { + t.Errorf("checkPtr was not eliminated") + } + } +} + +// TestNilcheckPhi tests that nil checks of phis, for which all values are known to be +// non-nil are removed. +func TestNilcheckPhi(t *testing.T) { + ptrType := &TypeImpl{Size_: 8, Ptr: true, Name: "testptr"} // dummy for testing + c := NewConfig("amd64", DummyFrontend{t}, nil, true) + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("sb", OpSB, TypeInvalid, 0, nil), + Valu("sp", OpSP, TypeInvalid, 0, nil), + Valu("baddr", OpAddr, TypeBool, 0, "b", "sp"), + Valu("bool1", OpLoad, TypeBool, 0, nil, "baddr", "mem"), + If("bool1", "b1", "b2")), + Bloc("b1", + Valu("ptr1", OpAddr, ptrType, 0, nil, "sb"), + Goto("checkPtr")), + Bloc("b2", + Valu("ptr2", OpAddr, ptrType, 0, nil, "sb"), + Goto("checkPtr")), + // both ptr1 and ptr2 are guaranteed non-nil here + Bloc("checkPtr", + Valu("phi", OpPhi, ptrType, 0, nil, "ptr1", "ptr2"), + Valu("bool2", OpIsNonNil, TypeBool, 0, nil, "phi"), + If("bool2", "extra", "exit")), + Bloc("extra", + Goto("exit")), + Bloc("exit", + Exit("mem"))) + + CheckFunc(fun.f) + nilcheckelim(fun.f) + + // clean up the removed nil check + fuse(fun.f) + deadcode(fun.f) + + CheckFunc(fun.f) + for _, b := range fun.f.Blocks { + if b == fun.blocks["checkPtr"] && isNilCheck(b) { + t.Errorf("checkPtr was not eliminated") + } + } +} + +// TestNilcheckKeepRemove verifies that duplicate checks of the same pointer +// are removed, but checks of different pointers are not. +func TestNilcheckKeepRemove(t *testing.T) { + ptrType := &TypeImpl{Size_: 8, Ptr: true, Name: "testptr"} // dummy for testing + c := NewConfig("amd64", DummyFrontend{t}, nil, true) + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("sb", OpSB, TypeInvalid, 0, nil), + Goto("checkPtr")), + Bloc("checkPtr", + Valu("ptr1", OpLoad, ptrType, 0, nil, "sb", "mem"), + Valu("bool1", OpIsNonNil, TypeBool, 0, nil, "ptr1"), + If("bool1", "differentCheck", "exit")), + Bloc("differentCheck", + Valu("ptr2", OpLoad, ptrType, 0, nil, "sb", "mem"), + Valu("bool2", OpIsNonNil, TypeBool, 0, nil, "ptr2"), + If("bool2", "secondCheck", "exit")), + Bloc("secondCheck", + Valu("bool3", OpIsNonNil, TypeBool, 0, nil, "ptr1"), + If("bool3", "extra", "exit")), + Bloc("extra", + Goto("exit")), + Bloc("exit", + Exit("mem"))) + + CheckFunc(fun.f) + nilcheckelim(fun.f) + + // clean up the removed nil check + fuse(fun.f) + deadcode(fun.f) + + CheckFunc(fun.f) + foundDifferentCheck := false + for _, b := range fun.f.Blocks { + if b == fun.blocks["secondCheck"] && isNilCheck(b) { + t.Errorf("secondCheck was not eliminated") + } + if b == fun.blocks["differentCheck"] && isNilCheck(b) { + foundDifferentCheck = true + } + } + if !foundDifferentCheck { + t.Errorf("removed differentCheck, but shouldn't have") + } +} + +// TestNilcheckInFalseBranch tests that nil checks in the false branch of an nilcheck +// block are *not* removed. +func TestNilcheckInFalseBranch(t *testing.T) { + ptrType := &TypeImpl{Size_: 8, Ptr: true, Name: "testptr"} // dummy for testing + c := NewConfig("amd64", DummyFrontend{t}, nil, true) + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("sb", OpSB, TypeInvalid, 0, nil), + Goto("checkPtr")), + Bloc("checkPtr", + Valu("ptr1", OpLoad, ptrType, 0, nil, "sb", "mem"), + Valu("bool1", OpIsNonNil, TypeBool, 0, nil, "ptr1"), + If("bool1", "extra", "secondCheck")), + Bloc("secondCheck", + Valu("bool2", OpIsNonNil, TypeBool, 0, nil, "ptr1"), + If("bool2", "extra", "thirdCheck")), + Bloc("thirdCheck", + Valu("bool3", OpIsNonNil, TypeBool, 0, nil, "ptr1"), + If("bool3", "extra", "exit")), + Bloc("extra", + Goto("exit")), + Bloc("exit", + Exit("mem"))) + + CheckFunc(fun.f) + nilcheckelim(fun.f) + + // clean up the removed nil check + fuse(fun.f) + deadcode(fun.f) + + CheckFunc(fun.f) + foundSecondCheck := false + foundThirdCheck := false + for _, b := range fun.f.Blocks { + if b == fun.blocks["secondCheck"] && isNilCheck(b) { + foundSecondCheck = true + } + if b == fun.blocks["thirdCheck"] && isNilCheck(b) { + foundThirdCheck = true + } + } + if !foundSecondCheck { + t.Errorf("removed secondCheck, but shouldn't have [false branch]") + } + if !foundThirdCheck { + t.Errorf("removed thirdCheck, but shouldn't have [false branch]") + } +} + +// TestNilcheckUser verifies that a user nil check that dominates a generated nil check +// wil remove the generated nil check. +func TestNilcheckUser(t *testing.T) { + ptrType := &TypeImpl{Size_: 8, Ptr: true, Name: "testptr"} // dummy for testing + c := NewConfig("amd64", DummyFrontend{t}, nil, true) + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("sb", OpSB, TypeInvalid, 0, nil), + Goto("checkPtr")), + Bloc("checkPtr", + Valu("ptr1", OpLoad, ptrType, 0, nil, "sb", "mem"), + Valu("nilptr", OpConstNil, ptrType, 0, nil), + Valu("bool1", OpNeqPtr, TypeBool, 0, nil, "ptr1", "nilptr"), + If("bool1", "secondCheck", "exit")), + Bloc("secondCheck", + Valu("bool2", OpIsNonNil, TypeBool, 0, nil, "ptr1"), + If("bool2", "extra", "exit")), + Bloc("extra", + Goto("exit")), + Bloc("exit", + Exit("mem"))) + + CheckFunc(fun.f) + // we need the opt here to rewrite the user nilcheck + opt(fun.f) + nilcheckelim(fun.f) + + // clean up the removed nil check + fuse(fun.f) + deadcode(fun.f) + + CheckFunc(fun.f) + for _, b := range fun.f.Blocks { + if b == fun.blocks["secondCheck"] && isNilCheck(b) { + t.Errorf("secondCheck was not eliminated") + } + } +} + +// TestNilcheckBug reproduces a bug in nilcheckelim found by compiling math/big +func TestNilcheckBug(t *testing.T) { + ptrType := &TypeImpl{Size_: 8, Ptr: true, Name: "testptr"} // dummy for testing + c := NewConfig("amd64", DummyFrontend{t}, nil, true) + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("sb", OpSB, TypeInvalid, 0, nil), + Goto("checkPtr")), + Bloc("checkPtr", + Valu("ptr1", OpLoad, ptrType, 0, nil, "sb", "mem"), + Valu("nilptr", OpConstNil, ptrType, 0, nil), + Valu("bool1", OpNeqPtr, TypeBool, 0, nil, "ptr1", "nilptr"), + If("bool1", "secondCheck", "couldBeNil")), + Bloc("couldBeNil", + Goto("secondCheck")), + Bloc("secondCheck", + Valu("bool2", OpIsNonNil, TypeBool, 0, nil, "ptr1"), + If("bool2", "extra", "exit")), + Bloc("extra", + // prevent fuse from eliminating this block + Valu("store", OpStore, TypeMem, 8, nil, "ptr1", "nilptr", "mem"), + Goto("exit")), + Bloc("exit", + Valu("phi", OpPhi, TypeMem, 0, nil, "mem", "store"), + Exit("mem"))) + + CheckFunc(fun.f) + // we need the opt here to rewrite the user nilcheck + opt(fun.f) + nilcheckelim(fun.f) + + // clean up the removed nil check + fuse(fun.f) + deadcode(fun.f) + + CheckFunc(fun.f) + foundSecondCheck := false + for _, b := range fun.f.Blocks { + if b == fun.blocks["secondCheck"] && isNilCheck(b) { + foundSecondCheck = true + } + } + if !foundSecondCheck { + t.Errorf("secondCheck was eliminated, but shouldn't have") + } +} diff --git a/src/cmd/compile/internal/ssa/op.go b/src/cmd/compile/internal/ssa/op.go new file mode 100644 index 0000000000..7b2a8f8f04 --- /dev/null +++ b/src/cmd/compile/internal/ssa/op.go @@ -0,0 +1,118 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import "fmt" + +// An Op encodes the specific operation that a Value performs. +// Opcodes' semantics can be modified by the type and aux fields of the Value. +// For instance, OpAdd can be 32 or 64 bit, signed or unsigned, float or complex, depending on Value.Type. +// Semantics of each op are described in the opcode files in gen/*Ops.go. +// There is one file for generic (architecture-independent) ops and one file +// for each architecture. +type Op int32 + +type opInfo struct { + name string + asm int + reg regInfo + auxType auxType + argLen int32 // the number of arugments, -1 if variable length + generic bool // this is a generic (arch-independent) opcode + rematerializeable bool // this op is rematerializeable + commutative bool // this operation is commutative (e.g. addition) +} + +type inputInfo struct { + idx int // index in Args array + regs regMask // allowed input registers +} + +type regInfo struct { + inputs []inputInfo // ordered in register allocation order + clobbers regMask + outputs []regMask // NOTE: values can only have 1 output for now. +} + +type auxType int8 + +const ( + auxNone auxType = iota + auxBool // auxInt is 0/1 for false/true + auxInt8 // auxInt is an 8-bit integer + auxInt16 // auxInt is a 16-bit integer + auxInt32 // auxInt is a 32-bit integer + auxInt64 // auxInt is a 64-bit integer + auxFloat // auxInt is a float64 (encoded with math.Float64bits) + auxString // auxInt is a string + auxSym // aux is a symbol + auxSymOff // aux is a symbol, auxInt is an offset + auxSymValAndOff // aux is a symbol, auxInt is a ValAndOff +) + +// A ValAndOff is used by the several opcodes. It holds +// both a value and a pointer offset. +// A ValAndOff is intended to be encoded into an AuxInt field. +// The zero ValAndOff encodes a value of 0 and an offset of 0. +// The high 32 bits hold a value. +// The low 32 bits hold a pointer offset. +type ValAndOff int64 + +func (x ValAndOff) Val() int64 { + return int64(x) >> 32 +} +func (x ValAndOff) Off() int64 { + return int64(int32(x)) +} +func (x ValAndOff) Int64() int64 { + return int64(x) +} +func (x ValAndOff) String() string { + return fmt.Sprintf("val=%d,off=%d", x.Val(), x.Off()) +} + +// validVal reports whether the value can be used +// as an argument to makeValAndOff. +func validVal(val int64) bool { + return val == int64(int32(val)) +} + +// validOff reports whether the offset can be used +// as an argument to makeValAndOff. +func validOff(off int64) bool { + return off == int64(int32(off)) +} + +// validValAndOff reports whether we can fit the value and offset into +// a ValAndOff value. +func validValAndOff(val, off int64) bool { + if !validVal(val) { + return false + } + if !validOff(off) { + return false + } + return true +} + +// makeValAndOff encodes a ValAndOff into an int64 suitable for storing in an AuxInt field. +func makeValAndOff(val, off int64) int64 { + if !validValAndOff(val, off) { + panic("invalid makeValAndOff") + } + return ValAndOff(val<<32 + int64(uint32(off))).Int64() +} + +func (x ValAndOff) canAdd(off int64) bool { + newoff := x.Off() + off + return newoff == int64(int32(newoff)) +} + +func (x ValAndOff) add(off int64) int64 { + if !x.canAdd(off) { + panic("invalid ValAndOff.add") + } + return makeValAndOff(x.Val(), x.Off()+off) +} diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go new file mode 100644 index 0000000000..a48766ffc0 --- /dev/null +++ b/src/cmd/compile/internal/ssa/opGen.go @@ -0,0 +1,5264 @@ +// autogenerated: do not edit! +// generated from gen/*Ops.go + +package ssa + +import "cmd/internal/obj/x86" + +const ( + BlockInvalid BlockKind = iota + + BlockAMD64EQ + BlockAMD64NE + BlockAMD64LT + BlockAMD64LE + BlockAMD64GT + BlockAMD64GE + BlockAMD64ULT + BlockAMD64ULE + BlockAMD64UGT + BlockAMD64UGE + BlockAMD64EQF + BlockAMD64NEF + BlockAMD64ORD + BlockAMD64NAN + + BlockPlain + BlockIf + BlockCall + BlockCheck + BlockRet + BlockRetJmp + BlockExit + BlockFirst + BlockDead +) + +var blockString = [...]string{ + BlockInvalid: "BlockInvalid", + + BlockAMD64EQ: "EQ", + BlockAMD64NE: "NE", + BlockAMD64LT: "LT", + BlockAMD64LE: "LE", + BlockAMD64GT: "GT", + BlockAMD64GE: "GE", + BlockAMD64ULT: "ULT", + BlockAMD64ULE: "ULE", + BlockAMD64UGT: "UGT", + BlockAMD64UGE: "UGE", + BlockAMD64EQF: "EQF", + BlockAMD64NEF: "NEF", + BlockAMD64ORD: "ORD", + BlockAMD64NAN: "NAN", + + BlockPlain: "Plain", + BlockIf: "If", + BlockCall: "Call", + BlockCheck: "Check", + BlockRet: "Ret", + BlockRetJmp: "RetJmp", + BlockExit: "Exit", + BlockFirst: "First", + BlockDead: "Dead", +} + +func (k BlockKind) String() string { return blockString[k] } + +const ( + OpInvalid Op = iota + + OpAMD64ADDSS + OpAMD64ADDSD + OpAMD64SUBSS + OpAMD64SUBSD + OpAMD64MULSS + OpAMD64MULSD + OpAMD64DIVSS + OpAMD64DIVSD + OpAMD64MOVSSload + OpAMD64MOVSDload + OpAMD64MOVSSconst + OpAMD64MOVSDconst + OpAMD64MOVSSloadidx4 + OpAMD64MOVSDloadidx8 + OpAMD64MOVSSstore + OpAMD64MOVSDstore + OpAMD64MOVSSstoreidx4 + OpAMD64MOVSDstoreidx8 + OpAMD64ADDQ + OpAMD64ADDL + OpAMD64ADDW + OpAMD64ADDB + OpAMD64ADDQconst + OpAMD64ADDLconst + OpAMD64ADDWconst + OpAMD64ADDBconst + OpAMD64SUBQ + OpAMD64SUBL + OpAMD64SUBW + OpAMD64SUBB + OpAMD64SUBQconst + OpAMD64SUBLconst + OpAMD64SUBWconst + OpAMD64SUBBconst + OpAMD64MULQ + OpAMD64MULL + OpAMD64MULW + OpAMD64MULB + OpAMD64MULQconst + OpAMD64MULLconst + OpAMD64MULWconst + OpAMD64MULBconst + OpAMD64HMULQ + OpAMD64HMULL + OpAMD64HMULW + OpAMD64HMULB + OpAMD64HMULQU + OpAMD64HMULLU + OpAMD64HMULWU + OpAMD64HMULBU + OpAMD64AVGQU + OpAMD64DIVQ + OpAMD64DIVL + OpAMD64DIVW + OpAMD64DIVQU + OpAMD64DIVLU + OpAMD64DIVWU + OpAMD64MODQ + OpAMD64MODL + OpAMD64MODW + OpAMD64MODQU + OpAMD64MODLU + OpAMD64MODWU + OpAMD64ANDQ + OpAMD64ANDL + OpAMD64ANDW + OpAMD64ANDB + OpAMD64ANDQconst + OpAMD64ANDLconst + OpAMD64ANDWconst + OpAMD64ANDBconst + OpAMD64ORQ + OpAMD64ORL + OpAMD64ORW + OpAMD64ORB + OpAMD64ORQconst + OpAMD64ORLconst + OpAMD64ORWconst + OpAMD64ORBconst + OpAMD64XORQ + OpAMD64XORL + OpAMD64XORW + OpAMD64XORB + OpAMD64XORQconst + OpAMD64XORLconst + OpAMD64XORWconst + OpAMD64XORBconst + OpAMD64CMPQ + OpAMD64CMPL + OpAMD64CMPW + OpAMD64CMPB + OpAMD64CMPQconst + OpAMD64CMPLconst + OpAMD64CMPWconst + OpAMD64CMPBconst + OpAMD64UCOMISS + OpAMD64UCOMISD + OpAMD64TESTQ + OpAMD64TESTL + OpAMD64TESTW + OpAMD64TESTB + OpAMD64TESTQconst + OpAMD64TESTLconst + OpAMD64TESTWconst + OpAMD64TESTBconst + OpAMD64SHLQ + OpAMD64SHLL + OpAMD64SHLW + OpAMD64SHLB + OpAMD64SHLQconst + OpAMD64SHLLconst + OpAMD64SHLWconst + OpAMD64SHLBconst + OpAMD64SHRQ + OpAMD64SHRL + OpAMD64SHRW + OpAMD64SHRB + OpAMD64SHRQconst + OpAMD64SHRLconst + OpAMD64SHRWconst + OpAMD64SHRBconst + OpAMD64SARQ + OpAMD64SARL + OpAMD64SARW + OpAMD64SARB + OpAMD64SARQconst + OpAMD64SARLconst + OpAMD64SARWconst + OpAMD64SARBconst + OpAMD64ROLQconst + OpAMD64ROLLconst + OpAMD64ROLWconst + OpAMD64ROLBconst + OpAMD64NEGQ + OpAMD64NEGL + OpAMD64NEGW + OpAMD64NEGB + OpAMD64NOTQ + OpAMD64NOTL + OpAMD64NOTW + OpAMD64NOTB + OpAMD64SQRTSD + OpAMD64SBBQcarrymask + OpAMD64SBBLcarrymask + OpAMD64SETEQ + OpAMD64SETNE + OpAMD64SETL + OpAMD64SETLE + OpAMD64SETG + OpAMD64SETGE + OpAMD64SETB + OpAMD64SETBE + OpAMD64SETA + OpAMD64SETAE + OpAMD64SETEQF + OpAMD64SETNEF + OpAMD64SETORD + OpAMD64SETNAN + OpAMD64SETGF + OpAMD64SETGEF + OpAMD64MOVBQSX + OpAMD64MOVBQZX + OpAMD64MOVWQSX + OpAMD64MOVWQZX + OpAMD64MOVLQSX + OpAMD64MOVLQZX + OpAMD64MOVBconst + OpAMD64MOVWconst + OpAMD64MOVLconst + OpAMD64MOVQconst + OpAMD64CVTTSD2SL + OpAMD64CVTTSD2SQ + OpAMD64CVTTSS2SL + OpAMD64CVTTSS2SQ + OpAMD64CVTSL2SS + OpAMD64CVTSL2SD + OpAMD64CVTSQ2SS + OpAMD64CVTSQ2SD + OpAMD64CVTSD2SS + OpAMD64CVTSS2SD + OpAMD64PXOR + OpAMD64LEAQ + OpAMD64LEAQ1 + OpAMD64LEAQ2 + OpAMD64LEAQ4 + OpAMD64LEAQ8 + OpAMD64MOVBload + OpAMD64MOVBQSXload + OpAMD64MOVBQZXload + OpAMD64MOVWload + OpAMD64MOVWQSXload + OpAMD64MOVWQZXload + OpAMD64MOVLload + OpAMD64MOVLQSXload + OpAMD64MOVLQZXload + OpAMD64MOVQload + OpAMD64MOVBstore + OpAMD64MOVWstore + OpAMD64MOVLstore + OpAMD64MOVQstore + OpAMD64MOVOload + OpAMD64MOVOstore + OpAMD64MOVBloadidx1 + OpAMD64MOVWloadidx2 + OpAMD64MOVLloadidx4 + OpAMD64MOVQloadidx8 + OpAMD64MOVBstoreidx1 + OpAMD64MOVWstoreidx2 + OpAMD64MOVLstoreidx4 + OpAMD64MOVQstoreidx8 + OpAMD64MOVBstoreconst + OpAMD64MOVWstoreconst + OpAMD64MOVLstoreconst + OpAMD64MOVQstoreconst + OpAMD64MOVBstoreconstidx1 + OpAMD64MOVWstoreconstidx2 + OpAMD64MOVLstoreconstidx4 + OpAMD64MOVQstoreconstidx8 + OpAMD64DUFFZERO + OpAMD64MOVOconst + OpAMD64REPSTOSQ + OpAMD64CALLstatic + OpAMD64CALLclosure + OpAMD64CALLdefer + OpAMD64CALLgo + OpAMD64CALLinter + OpAMD64DUFFCOPY + OpAMD64REPMOVSQ + OpAMD64InvertFlags + OpAMD64LoweredGetG + OpAMD64LoweredGetClosurePtr + OpAMD64LoweredNilCheck + OpAMD64MOVQconvert + OpAMD64FlagEQ + OpAMD64FlagLT_ULT + OpAMD64FlagLT_UGT + OpAMD64FlagGT_UGT + OpAMD64FlagGT_ULT + + OpAdd8 + OpAdd16 + OpAdd32 + OpAdd64 + OpAddPtr + OpAdd32F + OpAdd64F + OpSub8 + OpSub16 + OpSub32 + OpSub64 + OpSubPtr + OpSub32F + OpSub64F + OpMul8 + OpMul16 + OpMul32 + OpMul64 + OpMul32F + OpMul64F + OpDiv32F + OpDiv64F + OpHmul8 + OpHmul8u + OpHmul16 + OpHmul16u + OpHmul32 + OpHmul32u + OpHmul64 + OpHmul64u + OpAvg64u + OpDiv8 + OpDiv8u + OpDiv16 + OpDiv16u + OpDiv32 + OpDiv32u + OpDiv64 + OpDiv64u + OpMod8 + OpMod8u + OpMod16 + OpMod16u + OpMod32 + OpMod32u + OpMod64 + OpMod64u + OpAnd8 + OpAnd16 + OpAnd32 + OpAnd64 + OpOr8 + OpOr16 + OpOr32 + OpOr64 + OpXor8 + OpXor16 + OpXor32 + OpXor64 + OpLsh8x8 + OpLsh8x16 + OpLsh8x32 + OpLsh8x64 + OpLsh16x8 + OpLsh16x16 + OpLsh16x32 + OpLsh16x64 + OpLsh32x8 + OpLsh32x16 + OpLsh32x32 + OpLsh32x64 + OpLsh64x8 + OpLsh64x16 + OpLsh64x32 + OpLsh64x64 + OpRsh8x8 + OpRsh8x16 + OpRsh8x32 + OpRsh8x64 + OpRsh16x8 + OpRsh16x16 + OpRsh16x32 + OpRsh16x64 + OpRsh32x8 + OpRsh32x16 + OpRsh32x32 + OpRsh32x64 + OpRsh64x8 + OpRsh64x16 + OpRsh64x32 + OpRsh64x64 + OpRsh8Ux8 + OpRsh8Ux16 + OpRsh8Ux32 + OpRsh8Ux64 + OpRsh16Ux8 + OpRsh16Ux16 + OpRsh16Ux32 + OpRsh16Ux64 + OpRsh32Ux8 + OpRsh32Ux16 + OpRsh32Ux32 + OpRsh32Ux64 + OpRsh64Ux8 + OpRsh64Ux16 + OpRsh64Ux32 + OpRsh64Ux64 + OpLrot8 + OpLrot16 + OpLrot32 + OpLrot64 + OpEq8 + OpEq16 + OpEq32 + OpEq64 + OpEqPtr + OpEqInter + OpEqSlice + OpEq32F + OpEq64F + OpNeq8 + OpNeq16 + OpNeq32 + OpNeq64 + OpNeqPtr + OpNeqInter + OpNeqSlice + OpNeq32F + OpNeq64F + OpLess8 + OpLess8U + OpLess16 + OpLess16U + OpLess32 + OpLess32U + OpLess64 + OpLess64U + OpLess32F + OpLess64F + OpLeq8 + OpLeq8U + OpLeq16 + OpLeq16U + OpLeq32 + OpLeq32U + OpLeq64 + OpLeq64U + OpLeq32F + OpLeq64F + OpGreater8 + OpGreater8U + OpGreater16 + OpGreater16U + OpGreater32 + OpGreater32U + OpGreater64 + OpGreater64U + OpGreater32F + OpGreater64F + OpGeq8 + OpGeq8U + OpGeq16 + OpGeq16U + OpGeq32 + OpGeq32U + OpGeq64 + OpGeq64U + OpGeq32F + OpGeq64F + OpNot + OpNeg8 + OpNeg16 + OpNeg32 + OpNeg64 + OpNeg32F + OpNeg64F + OpCom8 + OpCom16 + OpCom32 + OpCom64 + OpSqrt + OpPhi + OpCopy + OpConvert + OpConstBool + OpConstString + OpConstNil + OpConst8 + OpConst16 + OpConst32 + OpConst64 + OpConst32F + OpConst64F + OpConstInterface + OpConstSlice + OpInitMem + OpArg + OpAddr + OpSP + OpSB + OpFunc + OpLoad + OpStore + OpMove + OpZero + OpClosureCall + OpStaticCall + OpDeferCall + OpGoCall + OpInterCall + OpSignExt8to16 + OpSignExt8to32 + OpSignExt8to64 + OpSignExt16to32 + OpSignExt16to64 + OpSignExt32to64 + OpZeroExt8to16 + OpZeroExt8to32 + OpZeroExt8to64 + OpZeroExt16to32 + OpZeroExt16to64 + OpZeroExt32to64 + OpTrunc16to8 + OpTrunc32to8 + OpTrunc32to16 + OpTrunc64to8 + OpTrunc64to16 + OpTrunc64to32 + OpCvt32to32F + OpCvt32to64F + OpCvt64to32F + OpCvt64to64F + OpCvt32Fto32 + OpCvt32Fto64 + OpCvt64Fto32 + OpCvt64Fto64 + OpCvt32Fto64F + OpCvt64Fto32F + OpIsNonNil + OpIsInBounds + OpIsSliceInBounds + OpNilCheck + OpGetG + OpGetClosurePtr + OpArrayIndex + OpPtrIndex + OpOffPtr + OpSliceMake + OpSlicePtr + OpSliceLen + OpSliceCap + OpComplexMake + OpComplexReal + OpComplexImag + OpStringMake + OpStringPtr + OpStringLen + OpIMake + OpITab + OpIData + OpStructMake0 + OpStructMake1 + OpStructMake2 + OpStructMake3 + OpStructMake4 + OpStructSelect + OpStoreReg + OpLoadReg + OpFwdRef + OpUnknown + OpVarDef + OpVarKill + OpVarLive +) + +var opcodeTable = [...]opInfo{ + {name: "OpInvalid"}, + + { + name: "ADDSS", + argLen: 2, + asm: x86.AADDSS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + outputs: []regMask{ + 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + }, + }, + { + name: "ADDSD", + argLen: 2, + asm: x86.AADDSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + outputs: []regMask{ + 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + }, + }, + { + name: "SUBSS", + argLen: 2, + asm: x86.ASUBSS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 + {1, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 + }, + clobbers: 2147483648, // .X15 + outputs: []regMask{ + 2147418112, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 + }, + }, + }, + { + name: "SUBSD", + argLen: 2, + asm: x86.ASUBSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 + {1, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 + }, + clobbers: 2147483648, // .X15 + outputs: []regMask{ + 2147418112, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 + }, + }, + }, + { + name: "MULSS", + argLen: 2, + asm: x86.AMULSS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + outputs: []regMask{ + 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + }, + }, + { + name: "MULSD", + argLen: 2, + asm: x86.AMULSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + outputs: []regMask{ + 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + }, + }, + { + name: "DIVSS", + argLen: 2, + asm: x86.ADIVSS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 + {1, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 + }, + clobbers: 2147483648, // .X15 + outputs: []regMask{ + 2147418112, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 + }, + }, + }, + { + name: "DIVSD", + argLen: 2, + asm: x86.ADIVSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 + {1, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 + }, + clobbers: 2147483648, // .X15 + outputs: []regMask{ + 2147418112, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 + }, + }, + }, + { + name: "MOVSSload", + auxType: auxSymOff, + argLen: 2, + asm: x86.AMOVSS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + outputs: []regMask{ + 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + }, + }, + { + name: "MOVSDload", + auxType: auxSymOff, + argLen: 2, + asm: x86.AMOVSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + outputs: []regMask{ + 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + }, + }, + { + name: "MOVSSconst", + auxType: auxFloat, + argLen: 0, + rematerializeable: true, + asm: x86.AMOVSS, + reg: regInfo{ + outputs: []regMask{ + 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + }, + }, + { + name: "MOVSDconst", + auxType: auxFloat, + argLen: 0, + rematerializeable: true, + asm: x86.AMOVSD, + reg: regInfo{ + outputs: []regMask{ + 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + }, + }, + { + name: "MOVSSloadidx4", + auxType: auxSymOff, + argLen: 3, + asm: x86.AMOVSS, + reg: regInfo{ + inputs: []inputInfo{ + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + outputs: []regMask{ + 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + }, + }, + { + name: "MOVSDloadidx8", + auxType: auxSymOff, + argLen: 3, + asm: x86.AMOVSD, + reg: regInfo{ + inputs: []inputInfo{ + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + outputs: []regMask{ + 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + }, + }, + { + name: "MOVSSstore", + auxType: auxSymOff, + argLen: 3, + asm: x86.AMOVSS, + reg: regInfo{ + inputs: []inputInfo{ + {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + }, + }, + { + name: "MOVSDstore", + auxType: auxSymOff, + argLen: 3, + asm: x86.AMOVSD, + reg: regInfo{ + inputs: []inputInfo{ + {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + }, + }, + { + name: "MOVSSstoreidx4", + auxType: auxSymOff, + argLen: 4, + asm: x86.AMOVSS, + reg: regInfo{ + inputs: []inputInfo{ + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {2, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + }, + }, + { + name: "MOVSDstoreidx8", + auxType: auxSymOff, + argLen: 4, + asm: x86.AMOVSD, + reg: regInfo{ + inputs: []inputInfo{ + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {2, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + }, + }, + { + name: "ADDQ", + argLen: 2, + asm: x86.AADDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ADDL", + argLen: 2, + asm: x86.AADDL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ADDW", + argLen: 2, + asm: x86.AADDL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ADDB", + argLen: 2, + asm: x86.AADDL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ADDQconst", + auxType: auxInt64, + argLen: 1, + asm: x86.AADDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ADDLconst", + auxType: auxInt32, + argLen: 1, + asm: x86.AADDL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ADDWconst", + auxType: auxInt16, + argLen: 1, + asm: x86.AADDL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ADDBconst", + auxType: auxInt8, + argLen: 1, + asm: x86.AADDL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SUBQ", + argLen: 2, + asm: x86.ASUBQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SUBL", + argLen: 2, + asm: x86.ASUBL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SUBW", + argLen: 2, + asm: x86.ASUBL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SUBB", + argLen: 2, + asm: x86.ASUBL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SUBQconst", + auxType: auxInt64, + argLen: 1, + asm: x86.ASUBQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SUBLconst", + auxType: auxInt32, + argLen: 1, + asm: x86.ASUBL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SUBWconst", + auxType: auxInt16, + argLen: 1, + asm: x86.ASUBL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SUBBconst", + auxType: auxInt8, + argLen: 1, + asm: x86.ASUBL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MULQ", + argLen: 2, + asm: x86.AIMULQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MULL", + argLen: 2, + asm: x86.AIMULL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MULW", + argLen: 2, + asm: x86.AIMULW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MULB", + argLen: 2, + asm: x86.AIMULW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MULQconst", + auxType: auxInt64, + argLen: 1, + asm: x86.AIMULQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MULLconst", + auxType: auxInt32, + argLen: 1, + asm: x86.AIMULL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MULWconst", + auxType: auxInt16, + argLen: 1, + asm: x86.AIMULW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MULBconst", + auxType: auxInt8, + argLen: 1, + asm: x86.AIMULW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "HMULQ", + argLen: 2, + asm: x86.AIMULQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1}, // .AX + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934593, // .AX .FLAGS + outputs: []regMask{ + 4, // .DX + }, + }, + }, + { + name: "HMULL", + argLen: 2, + asm: x86.AIMULL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1}, // .AX + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934593, // .AX .FLAGS + outputs: []regMask{ + 4, // .DX + }, + }, + }, + { + name: "HMULW", + argLen: 2, + asm: x86.AIMULW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1}, // .AX + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934593, // .AX .FLAGS + outputs: []regMask{ + 4, // .DX + }, + }, + }, + { + name: "HMULB", + argLen: 2, + asm: x86.AIMULB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1}, // .AX + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934593, // .AX .FLAGS + outputs: []regMask{ + 4, // .DX + }, + }, + }, + { + name: "HMULQU", + argLen: 2, + asm: x86.AMULQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1}, // .AX + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934593, // .AX .FLAGS + outputs: []regMask{ + 4, // .DX + }, + }, + }, + { + name: "HMULLU", + argLen: 2, + asm: x86.AMULL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1}, // .AX + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934593, // .AX .FLAGS + outputs: []regMask{ + 4, // .DX + }, + }, + }, + { + name: "HMULWU", + argLen: 2, + asm: x86.AMULW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1}, // .AX + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934593, // .AX .FLAGS + outputs: []regMask{ + 4, // .DX + }, + }, + }, + { + name: "HMULBU", + argLen: 2, + asm: x86.AMULB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1}, // .AX + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934593, // .AX .FLAGS + outputs: []regMask{ + 4, // .DX + }, + }, + }, + { + name: "AVGQU", + argLen: 2, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "DIVQ", + argLen: 2, + asm: x86.AIDIVQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1}, // .AX + {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934596, // .DX .FLAGS + outputs: []regMask{ + 1, // .AX + }, + }, + }, + { + name: "DIVL", + argLen: 2, + asm: x86.AIDIVL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1}, // .AX + {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934596, // .DX .FLAGS + outputs: []regMask{ + 1, // .AX + }, + }, + }, + { + name: "DIVW", + argLen: 2, + asm: x86.AIDIVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1}, // .AX + {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934596, // .DX .FLAGS + outputs: []regMask{ + 1, // .AX + }, + }, + }, + { + name: "DIVQU", + argLen: 2, + asm: x86.ADIVQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1}, // .AX + {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934596, // .DX .FLAGS + outputs: []regMask{ + 1, // .AX + }, + }, + }, + { + name: "DIVLU", + argLen: 2, + asm: x86.ADIVL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1}, // .AX + {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934596, // .DX .FLAGS + outputs: []regMask{ + 1, // .AX + }, + }, + }, + { + name: "DIVWU", + argLen: 2, + asm: x86.ADIVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1}, // .AX + {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934596, // .DX .FLAGS + outputs: []regMask{ + 1, // .AX + }, + }, + }, + { + name: "MODQ", + argLen: 2, + asm: x86.AIDIVQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1}, // .AX + {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934593, // .AX .FLAGS + outputs: []regMask{ + 4, // .DX + }, + }, + }, + { + name: "MODL", + argLen: 2, + asm: x86.AIDIVL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1}, // .AX + {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934593, // .AX .FLAGS + outputs: []regMask{ + 4, // .DX + }, + }, + }, + { + name: "MODW", + argLen: 2, + asm: x86.AIDIVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1}, // .AX + {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934593, // .AX .FLAGS + outputs: []regMask{ + 4, // .DX + }, + }, + }, + { + name: "MODQU", + argLen: 2, + asm: x86.ADIVQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1}, // .AX + {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934593, // .AX .FLAGS + outputs: []regMask{ + 4, // .DX + }, + }, + }, + { + name: "MODLU", + argLen: 2, + asm: x86.ADIVL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1}, // .AX + {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934593, // .AX .FLAGS + outputs: []regMask{ + 4, // .DX + }, + }, + }, + { + name: "MODWU", + argLen: 2, + asm: x86.ADIVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1}, // .AX + {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934593, // .AX .FLAGS + outputs: []regMask{ + 4, // .DX + }, + }, + }, + { + name: "ANDQ", + argLen: 2, + asm: x86.AANDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ANDL", + argLen: 2, + asm: x86.AANDL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ANDW", + argLen: 2, + asm: x86.AANDL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ANDB", + argLen: 2, + asm: x86.AANDL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ANDQconst", + auxType: auxInt64, + argLen: 1, + asm: x86.AANDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ANDLconst", + auxType: auxInt32, + argLen: 1, + asm: x86.AANDL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ANDWconst", + auxType: auxInt16, + argLen: 1, + asm: x86.AANDL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ANDBconst", + auxType: auxInt8, + argLen: 1, + asm: x86.AANDL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ORQ", + argLen: 2, + asm: x86.AORQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ORL", + argLen: 2, + asm: x86.AORL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ORW", + argLen: 2, + asm: x86.AORL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ORB", + argLen: 2, + asm: x86.AORL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ORQconst", + auxType: auxInt64, + argLen: 1, + asm: x86.AORQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ORLconst", + auxType: auxInt32, + argLen: 1, + asm: x86.AORL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ORWconst", + auxType: auxInt16, + argLen: 1, + asm: x86.AORL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ORBconst", + auxType: auxInt8, + argLen: 1, + asm: x86.AORL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "XORQ", + argLen: 2, + asm: x86.AXORQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "XORL", + argLen: 2, + asm: x86.AXORL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "XORW", + argLen: 2, + asm: x86.AXORL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "XORB", + argLen: 2, + asm: x86.AXORL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "XORQconst", + auxType: auxInt64, + argLen: 1, + asm: x86.AXORQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "XORLconst", + auxType: auxInt32, + argLen: 1, + asm: x86.AXORL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "XORWconst", + auxType: auxInt16, + argLen: 1, + asm: x86.AXORL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "XORBconst", + auxType: auxInt8, + argLen: 1, + asm: x86.AXORL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "CMPQ", + argLen: 2, + asm: x86.ACMPQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 8589934592, // .FLAGS + }, + }, + }, + { + name: "CMPL", + argLen: 2, + asm: x86.ACMPL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 8589934592, // .FLAGS + }, + }, + }, + { + name: "CMPW", + argLen: 2, + asm: x86.ACMPW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 8589934592, // .FLAGS + }, + }, + }, + { + name: "CMPB", + argLen: 2, + asm: x86.ACMPB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 8589934592, // .FLAGS + }, + }, + }, + { + name: "CMPQconst", + auxType: auxInt64, + argLen: 1, + asm: x86.ACMPQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 8589934592, // .FLAGS + }, + }, + }, + { + name: "CMPLconst", + auxType: auxInt32, + argLen: 1, + asm: x86.ACMPL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 8589934592, // .FLAGS + }, + }, + }, + { + name: "CMPWconst", + auxType: auxInt16, + argLen: 1, + asm: x86.ACMPW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 8589934592, // .FLAGS + }, + }, + }, + { + name: "CMPBconst", + auxType: auxInt8, + argLen: 1, + asm: x86.ACMPB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 8589934592, // .FLAGS + }, + }, + }, + { + name: "UCOMISS", + argLen: 2, + asm: x86.AUCOMISS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + outputs: []regMask{ + 8589934592, // .FLAGS + }, + }, + }, + { + name: "UCOMISD", + argLen: 2, + asm: x86.AUCOMISD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + outputs: []regMask{ + 8589934592, // .FLAGS + }, + }, + }, + { + name: "TESTQ", + argLen: 2, + asm: x86.ATESTQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 8589934592, // .FLAGS + }, + }, + }, + { + name: "TESTL", + argLen: 2, + asm: x86.ATESTL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 8589934592, // .FLAGS + }, + }, + }, + { + name: "TESTW", + argLen: 2, + asm: x86.ATESTW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 8589934592, // .FLAGS + }, + }, + }, + { + name: "TESTB", + argLen: 2, + asm: x86.ATESTB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 8589934592, // .FLAGS + }, + }, + }, + { + name: "TESTQconst", + auxType: auxInt64, + argLen: 1, + asm: x86.ATESTQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 8589934592, // .FLAGS + }, + }, + }, + { + name: "TESTLconst", + auxType: auxInt32, + argLen: 1, + asm: x86.ATESTL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 8589934592, // .FLAGS + }, + }, + }, + { + name: "TESTWconst", + auxType: auxInt16, + argLen: 1, + asm: x86.ATESTW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 8589934592, // .FLAGS + }, + }, + }, + { + name: "TESTBconst", + auxType: auxInt8, + argLen: 1, + asm: x86.ATESTB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 8589934592, // .FLAGS + }, + }, + }, + { + name: "SHLQ", + argLen: 2, + asm: x86.ASHLQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 2}, // .CX + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SHLL", + argLen: 2, + asm: x86.ASHLL, + reg: regInfo{ + inputs: []inputInfo{ + {1, 2}, // .CX + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SHLW", + argLen: 2, + asm: x86.ASHLL, + reg: regInfo{ + inputs: []inputInfo{ + {1, 2}, // .CX + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SHLB", + argLen: 2, + asm: x86.ASHLL, + reg: regInfo{ + inputs: []inputInfo{ + {1, 2}, // .CX + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SHLQconst", + auxType: auxInt64, + argLen: 1, + asm: x86.ASHLQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SHLLconst", + auxType: auxInt32, + argLen: 1, + asm: x86.ASHLL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SHLWconst", + auxType: auxInt16, + argLen: 1, + asm: x86.ASHLL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SHLBconst", + auxType: auxInt8, + argLen: 1, + asm: x86.ASHLL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SHRQ", + argLen: 2, + asm: x86.ASHRQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 2}, // .CX + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SHRL", + argLen: 2, + asm: x86.ASHRL, + reg: regInfo{ + inputs: []inputInfo{ + {1, 2}, // .CX + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SHRW", + argLen: 2, + asm: x86.ASHRW, + reg: regInfo{ + inputs: []inputInfo{ + {1, 2}, // .CX + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SHRB", + argLen: 2, + asm: x86.ASHRB, + reg: regInfo{ + inputs: []inputInfo{ + {1, 2}, // .CX + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SHRQconst", + auxType: auxInt64, + argLen: 1, + asm: x86.ASHRQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SHRLconst", + auxType: auxInt32, + argLen: 1, + asm: x86.ASHRL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SHRWconst", + auxType: auxInt16, + argLen: 1, + asm: x86.ASHRW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SHRBconst", + auxType: auxInt8, + argLen: 1, + asm: x86.ASHRB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SARQ", + argLen: 2, + asm: x86.ASARQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 2}, // .CX + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SARL", + argLen: 2, + asm: x86.ASARL, + reg: regInfo{ + inputs: []inputInfo{ + {1, 2}, // .CX + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SARW", + argLen: 2, + asm: x86.ASARW, + reg: regInfo{ + inputs: []inputInfo{ + {1, 2}, // .CX + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SARB", + argLen: 2, + asm: x86.ASARB, + reg: regInfo{ + inputs: []inputInfo{ + {1, 2}, // .CX + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SARQconst", + auxType: auxInt64, + argLen: 1, + asm: x86.ASARQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SARLconst", + auxType: auxInt32, + argLen: 1, + asm: x86.ASARL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SARWconst", + auxType: auxInt16, + argLen: 1, + asm: x86.ASARW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SARBconst", + auxType: auxInt8, + argLen: 1, + asm: x86.ASARB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ROLQconst", + auxType: auxInt64, + argLen: 1, + asm: x86.AROLQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ROLLconst", + auxType: auxInt32, + argLen: 1, + asm: x86.AROLL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ROLWconst", + auxType: auxInt16, + argLen: 1, + asm: x86.AROLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "ROLBconst", + auxType: auxInt8, + argLen: 1, + asm: x86.AROLB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "NEGQ", + argLen: 1, + asm: x86.ANEGQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "NEGL", + argLen: 1, + asm: x86.ANEGL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "NEGW", + argLen: 1, + asm: x86.ANEGL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "NEGB", + argLen: 1, + asm: x86.ANEGL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "NOTQ", + argLen: 1, + asm: x86.ANOTQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "NOTL", + argLen: 1, + asm: x86.ANOTL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "NOTW", + argLen: 1, + asm: x86.ANOTL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "NOTB", + argLen: 1, + asm: x86.ANOTL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SQRTSD", + argLen: 1, + asm: x86.ASQRTSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + outputs: []regMask{ + 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + }, + }, + { + name: "SBBQcarrymask", + argLen: 1, + asm: x86.ASBBQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 8589934592}, // .FLAGS + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SBBLcarrymask", + argLen: 1, + asm: x86.ASBBL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 8589934592}, // .FLAGS + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SETEQ", + argLen: 1, + asm: x86.ASETEQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 8589934592}, // .FLAGS + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SETNE", + argLen: 1, + asm: x86.ASETNE, + reg: regInfo{ + inputs: []inputInfo{ + {0, 8589934592}, // .FLAGS + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SETL", + argLen: 1, + asm: x86.ASETLT, + reg: regInfo{ + inputs: []inputInfo{ + {0, 8589934592}, // .FLAGS + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SETLE", + argLen: 1, + asm: x86.ASETLE, + reg: regInfo{ + inputs: []inputInfo{ + {0, 8589934592}, // .FLAGS + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SETG", + argLen: 1, + asm: x86.ASETGT, + reg: regInfo{ + inputs: []inputInfo{ + {0, 8589934592}, // .FLAGS + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SETGE", + argLen: 1, + asm: x86.ASETGE, + reg: regInfo{ + inputs: []inputInfo{ + {0, 8589934592}, // .FLAGS + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SETB", + argLen: 1, + asm: x86.ASETCS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 8589934592}, // .FLAGS + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SETBE", + argLen: 1, + asm: x86.ASETLS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 8589934592}, // .FLAGS + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SETA", + argLen: 1, + asm: x86.ASETHI, + reg: regInfo{ + inputs: []inputInfo{ + {0, 8589934592}, // .FLAGS + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SETAE", + argLen: 1, + asm: x86.ASETCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 8589934592}, // .FLAGS + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SETEQF", + argLen: 1, + asm: x86.ASETEQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 8589934592}, // .FLAGS + }, + clobbers: 8589934593, // .AX .FLAGS + outputs: []regMask{ + 65518, // .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SETNEF", + argLen: 1, + asm: x86.ASETNE, + reg: regInfo{ + inputs: []inputInfo{ + {0, 8589934592}, // .FLAGS + }, + clobbers: 8589934593, // .AX .FLAGS + outputs: []regMask{ + 65518, // .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SETORD", + argLen: 1, + asm: x86.ASETPC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 8589934592}, // .FLAGS + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SETNAN", + argLen: 1, + asm: x86.ASETPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 8589934592}, // .FLAGS + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SETGF", + argLen: 1, + asm: x86.ASETHI, + reg: regInfo{ + inputs: []inputInfo{ + {0, 8589934592}, // .FLAGS + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "SETGEF", + argLen: 1, + asm: x86.ASETCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 8589934592}, // .FLAGS + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVBQSX", + argLen: 1, + asm: x86.AMOVBQSX, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVBQZX", + argLen: 1, + asm: x86.AMOVBQZX, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVWQSX", + argLen: 1, + asm: x86.AMOVWQSX, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVWQZX", + argLen: 1, + asm: x86.AMOVWQZX, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVLQSX", + argLen: 1, + asm: x86.AMOVLQSX, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVLQZX", + argLen: 1, + asm: x86.AMOVLQZX, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVBconst", + auxType: auxInt8, + argLen: 0, + rematerializeable: true, + asm: x86.AMOVB, + reg: regInfo{ + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVWconst", + auxType: auxInt16, + argLen: 0, + rematerializeable: true, + asm: x86.AMOVW, + reg: regInfo{ + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVLconst", + auxType: auxInt32, + argLen: 0, + rematerializeable: true, + asm: x86.AMOVL, + reg: regInfo{ + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVQconst", + auxType: auxInt64, + argLen: 0, + rematerializeable: true, + asm: x86.AMOVQ, + reg: regInfo{ + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "CVTTSD2SL", + argLen: 1, + asm: x86.ACVTTSD2SL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "CVTTSD2SQ", + argLen: 1, + asm: x86.ACVTTSD2SQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "CVTTSS2SL", + argLen: 1, + asm: x86.ACVTTSS2SL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "CVTTSS2SQ", + argLen: 1, + asm: x86.ACVTTSS2SQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "CVTSL2SS", + argLen: 1, + asm: x86.ACVTSL2SS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + }, + }, + { + name: "CVTSL2SD", + argLen: 1, + asm: x86.ACVTSL2SD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + }, + }, + { + name: "CVTSQ2SS", + argLen: 1, + asm: x86.ACVTSQ2SS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + }, + }, + { + name: "CVTSQ2SD", + argLen: 1, + asm: x86.ACVTSQ2SD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + }, + }, + { + name: "CVTSD2SS", + argLen: 1, + asm: x86.ACVTSD2SS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + outputs: []regMask{ + 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + }, + }, + { + name: "CVTSS2SD", + argLen: 1, + asm: x86.ACVTSS2SD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + outputs: []regMask{ + 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + }, + }, + { + name: "PXOR", + argLen: 2, + asm: x86.APXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + outputs: []regMask{ + 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + }, + }, + { + name: "LEAQ", + auxType: auxSymOff, + argLen: 1, + rematerializeable: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "LEAQ1", + auxType: auxSymOff, + argLen: 2, + reg: regInfo{ + inputs: []inputInfo{ + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "LEAQ2", + auxType: auxSymOff, + argLen: 2, + reg: regInfo{ + inputs: []inputInfo{ + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "LEAQ4", + auxType: auxSymOff, + argLen: 2, + reg: regInfo{ + inputs: []inputInfo{ + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "LEAQ8", + auxType: auxSymOff, + argLen: 2, + reg: regInfo{ + inputs: []inputInfo{ + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVBload", + auxType: auxSymOff, + argLen: 2, + asm: x86.AMOVBLZX, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVBQSXload", + auxType: auxSymOff, + argLen: 2, + asm: x86.AMOVBQSX, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVBQZXload", + auxType: auxSymOff, + argLen: 2, + asm: x86.AMOVBQZX, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVWload", + auxType: auxSymOff, + argLen: 2, + asm: x86.AMOVWLZX, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVWQSXload", + auxType: auxSymOff, + argLen: 2, + asm: x86.AMOVWQSX, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVWQZXload", + auxType: auxSymOff, + argLen: 2, + asm: x86.AMOVWQZX, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVLload", + auxType: auxSymOff, + argLen: 2, + asm: x86.AMOVL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVLQSXload", + auxType: auxSymOff, + argLen: 2, + asm: x86.AMOVLQSX, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVLQZXload", + auxType: auxSymOff, + argLen: 2, + asm: x86.AMOVLQZX, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVQload", + auxType: auxSymOff, + argLen: 2, + asm: x86.AMOVQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVBstore", + auxType: auxSymOff, + argLen: 3, + asm: x86.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + }, + }, + { + name: "MOVWstore", + auxType: auxSymOff, + argLen: 3, + asm: x86.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + }, + }, + { + name: "MOVLstore", + auxType: auxSymOff, + argLen: 3, + asm: x86.AMOVL, + reg: regInfo{ + inputs: []inputInfo{ + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + }, + }, + { + name: "MOVQstore", + auxType: auxSymOff, + argLen: 3, + asm: x86.AMOVQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + }, + }, + { + name: "MOVOload", + auxType: auxSymOff, + argLen: 2, + asm: x86.AMOVUPS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + outputs: []regMask{ + 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + }, + }, + { + name: "MOVOstore", + auxType: auxSymOff, + argLen: 3, + asm: x86.AMOVUPS, + reg: regInfo{ + inputs: []inputInfo{ + {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + }, + }, + { + name: "MOVBloadidx1", + auxType: auxSymOff, + argLen: 3, + asm: x86.AMOVBLZX, + reg: regInfo{ + inputs: []inputInfo{ + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVWloadidx2", + auxType: auxSymOff, + argLen: 3, + asm: x86.AMOVWLZX, + reg: regInfo{ + inputs: []inputInfo{ + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVLloadidx4", + auxType: auxSymOff, + argLen: 3, + asm: x86.AMOVL, + reg: regInfo{ + inputs: []inputInfo{ + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVQloadidx8", + auxType: auxSymOff, + argLen: 3, + asm: x86.AMOVQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "MOVBstoreidx1", + auxType: auxSymOff, + argLen: 4, + asm: x86.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {2, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + }, + }, + { + name: "MOVWstoreidx2", + auxType: auxSymOff, + argLen: 4, + asm: x86.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {2, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + }, + }, + { + name: "MOVLstoreidx4", + auxType: auxSymOff, + argLen: 4, + asm: x86.AMOVL, + reg: regInfo{ + inputs: []inputInfo{ + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {2, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + }, + }, + { + name: "MOVQstoreidx8", + auxType: auxSymOff, + argLen: 4, + asm: x86.AMOVQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {2, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + }, + }, + { + name: "MOVBstoreconst", + auxType: auxSymValAndOff, + argLen: 2, + asm: x86.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + }, + }, + { + name: "MOVWstoreconst", + auxType: auxSymValAndOff, + argLen: 2, + asm: x86.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + }, + }, + { + name: "MOVLstoreconst", + auxType: auxSymValAndOff, + argLen: 2, + asm: x86.AMOVL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + }, + }, + { + name: "MOVQstoreconst", + auxType: auxSymValAndOff, + argLen: 2, + asm: x86.AMOVQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + }, + }, + { + name: "MOVBstoreconstidx1", + auxType: auxSymValAndOff, + argLen: 3, + asm: x86.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + }, + }, + { + name: "MOVWstoreconstidx2", + auxType: auxSymValAndOff, + argLen: 3, + asm: x86.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + }, + }, + { + name: "MOVLstoreconstidx4", + auxType: auxSymValAndOff, + argLen: 3, + asm: x86.AMOVL, + reg: regInfo{ + inputs: []inputInfo{ + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + }, + }, + { + name: "MOVQstoreconstidx8", + auxType: auxSymValAndOff, + argLen: 3, + asm: x86.AMOVQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB + }, + }, + }, + { + name: "DUFFZERO", + auxType: auxInt64, + argLen: 3, + reg: regInfo{ + inputs: []inputInfo{ + {0, 128}, // .DI + {1, 65536}, // .X0 + }, + clobbers: 8589934720, // .DI .FLAGS + }, + }, + { + name: "MOVOconst", + argLen: 0, + rematerializeable: true, + reg: regInfo{ + outputs: []regMask{ + 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 + }, + }, + }, + { + name: "REPSTOSQ", + argLen: 4, + reg: regInfo{ + inputs: []inputInfo{ + {0, 128}, // .DI + {1, 2}, // .CX + {2, 1}, // .AX + }, + clobbers: 8589934722, // .CX .DI .FLAGS + }, + }, + { + name: "CALLstatic", + auxType: auxSymOff, + argLen: 1, + reg: regInfo{ + clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS + }, + }, + { + name: "CALLclosure", + auxType: auxInt64, + argLen: 3, + reg: regInfo{ + inputs: []inputInfo{ + {1, 4}, // .DX + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS + }, + }, + { + name: "CALLdefer", + auxType: auxInt64, + argLen: 1, + reg: regInfo{ + clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS + }, + }, + { + name: "CALLgo", + auxType: auxInt64, + argLen: 1, + reg: regInfo{ + clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS + }, + }, + { + name: "CALLinter", + auxType: auxInt64, + argLen: 2, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS + }, + }, + { + name: "DUFFCOPY", + auxType: auxInt64, + argLen: 3, + reg: regInfo{ + inputs: []inputInfo{ + {0, 128}, // .DI + {1, 64}, // .SI + }, + clobbers: 8590000320, // .SI .DI .X0 .FLAGS + }, + }, + { + name: "REPMOVSQ", + argLen: 4, + reg: regInfo{ + inputs: []inputInfo{ + {0, 128}, // .DI + {1, 64}, // .SI + {2, 2}, // .CX + }, + clobbers: 194, // .CX .SI .DI + }, + }, + { + name: "InvertFlags", + argLen: 1, + reg: regInfo{}, + }, + { + name: "LoweredGetG", + argLen: 1, + reg: regInfo{ + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "LoweredGetClosurePtr", + argLen: 0, + reg: regInfo{ + outputs: []regMask{ + 4, // .DX + }, + }, + }, + { + name: "LoweredNilCheck", + argLen: 2, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + clobbers: 8589934592, // .FLAGS + }, + }, + { + name: "MOVQconvert", + argLen: 2, + asm: x86.AMOVQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + outputs: []regMask{ + 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 + }, + }, + }, + { + name: "FlagEQ", + argLen: 0, + reg: regInfo{}, + }, + { + name: "FlagLT_ULT", + argLen: 0, + reg: regInfo{}, + }, + { + name: "FlagLT_UGT", + argLen: 0, + reg: regInfo{}, + }, + { + name: "FlagGT_UGT", + argLen: 0, + reg: regInfo{}, + }, + { + name: "FlagGT_ULT", + argLen: 0, + reg: regInfo{}, + }, + + { + name: "Add8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Add16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Add32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Add64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddPtr", + argLen: 2, + generic: true, + }, + { + name: "Add32F", + argLen: 2, + generic: true, + }, + { + name: "Add64F", + argLen: 2, + generic: true, + }, + { + name: "Sub8", + argLen: 2, + generic: true, + }, + { + name: "Sub16", + argLen: 2, + generic: true, + }, + { + name: "Sub32", + argLen: 2, + generic: true, + }, + { + name: "Sub64", + argLen: 2, + generic: true, + }, + { + name: "SubPtr", + argLen: 2, + generic: true, + }, + { + name: "Sub32F", + argLen: 2, + generic: true, + }, + { + name: "Sub64F", + argLen: 2, + generic: true, + }, + { + name: "Mul8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Mul16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Mul32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Mul64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Mul32F", + argLen: 2, + generic: true, + }, + { + name: "Mul64F", + argLen: 2, + generic: true, + }, + { + name: "Div32F", + argLen: 2, + generic: true, + }, + { + name: "Div64F", + argLen: 2, + generic: true, + }, + { + name: "Hmul8", + argLen: 2, + generic: true, + }, + { + name: "Hmul8u", + argLen: 2, + generic: true, + }, + { + name: "Hmul16", + argLen: 2, + generic: true, + }, + { + name: "Hmul16u", + argLen: 2, + generic: true, + }, + { + name: "Hmul32", + argLen: 2, + generic: true, + }, + { + name: "Hmul32u", + argLen: 2, + generic: true, + }, + { + name: "Hmul64", + argLen: 2, + generic: true, + }, + { + name: "Hmul64u", + argLen: 2, + generic: true, + }, + { + name: "Avg64u", + argLen: 2, + generic: true, + }, + { + name: "Div8", + argLen: 2, + generic: true, + }, + { + name: "Div8u", + argLen: 2, + generic: true, + }, + { + name: "Div16", + argLen: 2, + generic: true, + }, + { + name: "Div16u", + argLen: 2, + generic: true, + }, + { + name: "Div32", + argLen: 2, + generic: true, + }, + { + name: "Div32u", + argLen: 2, + generic: true, + }, + { + name: "Div64", + argLen: 2, + generic: true, + }, + { + name: "Div64u", + argLen: 2, + generic: true, + }, + { + name: "Mod8", + argLen: 2, + generic: true, + }, + { + name: "Mod8u", + argLen: 2, + generic: true, + }, + { + name: "Mod16", + argLen: 2, + generic: true, + }, + { + name: "Mod16u", + argLen: 2, + generic: true, + }, + { + name: "Mod32", + argLen: 2, + generic: true, + }, + { + name: "Mod32u", + argLen: 2, + generic: true, + }, + { + name: "Mod64", + argLen: 2, + generic: true, + }, + { + name: "Mod64u", + argLen: 2, + generic: true, + }, + { + name: "And8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "And16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "And32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "And64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Or8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Or16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Or32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Or64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Xor8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Xor16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Xor32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Xor64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Lsh8x8", + argLen: 2, + generic: true, + }, + { + name: "Lsh8x16", + argLen: 2, + generic: true, + }, + { + name: "Lsh8x32", + argLen: 2, + generic: true, + }, + { + name: "Lsh8x64", + argLen: 2, + generic: true, + }, + { + name: "Lsh16x8", + argLen: 2, + generic: true, + }, + { + name: "Lsh16x16", + argLen: 2, + generic: true, + }, + { + name: "Lsh16x32", + argLen: 2, + generic: true, + }, + { + name: "Lsh16x64", + argLen: 2, + generic: true, + }, + { + name: "Lsh32x8", + argLen: 2, + generic: true, + }, + { + name: "Lsh32x16", + argLen: 2, + generic: true, + }, + { + name: "Lsh32x32", + argLen: 2, + generic: true, + }, + { + name: "Lsh32x64", + argLen: 2, + generic: true, + }, + { + name: "Lsh64x8", + argLen: 2, + generic: true, + }, + { + name: "Lsh64x16", + argLen: 2, + generic: true, + }, + { + name: "Lsh64x32", + argLen: 2, + generic: true, + }, + { + name: "Lsh64x64", + argLen: 2, + generic: true, + }, + { + name: "Rsh8x8", + argLen: 2, + generic: true, + }, + { + name: "Rsh8x16", + argLen: 2, + generic: true, + }, + { + name: "Rsh8x32", + argLen: 2, + generic: true, + }, + { + name: "Rsh8x64", + argLen: 2, + generic: true, + }, + { + name: "Rsh16x8", + argLen: 2, + generic: true, + }, + { + name: "Rsh16x16", + argLen: 2, + generic: true, + }, + { + name: "Rsh16x32", + argLen: 2, + generic: true, + }, + { + name: "Rsh16x64", + argLen: 2, + generic: true, + }, + { + name: "Rsh32x8", + argLen: 2, + generic: true, + }, + { + name: "Rsh32x16", + argLen: 2, + generic: true, + }, + { + name: "Rsh32x32", + argLen: 2, + generic: true, + }, + { + name: "Rsh32x64", + argLen: 2, + generic: true, + }, + { + name: "Rsh64x8", + argLen: 2, + generic: true, + }, + { + name: "Rsh64x16", + argLen: 2, + generic: true, + }, + { + name: "Rsh64x32", + argLen: 2, + generic: true, + }, + { + name: "Rsh64x64", + argLen: 2, + generic: true, + }, + { + name: "Rsh8Ux8", + argLen: 2, + generic: true, + }, + { + name: "Rsh8Ux16", + argLen: 2, + generic: true, + }, + { + name: "Rsh8Ux32", + argLen: 2, + generic: true, + }, + { + name: "Rsh8Ux64", + argLen: 2, + generic: true, + }, + { + name: "Rsh16Ux8", + argLen: 2, + generic: true, + }, + { + name: "Rsh16Ux16", + argLen: 2, + generic: true, + }, + { + name: "Rsh16Ux32", + argLen: 2, + generic: true, + }, + { + name: "Rsh16Ux64", + argLen: 2, + generic: true, + }, + { + name: "Rsh32Ux8", + argLen: 2, + generic: true, + }, + { + name: "Rsh32Ux16", + argLen: 2, + generic: true, + }, + { + name: "Rsh32Ux32", + argLen: 2, + generic: true, + }, + { + name: "Rsh32Ux64", + argLen: 2, + generic: true, + }, + { + name: "Rsh64Ux8", + argLen: 2, + generic: true, + }, + { + name: "Rsh64Ux16", + argLen: 2, + generic: true, + }, + { + name: "Rsh64Ux32", + argLen: 2, + generic: true, + }, + { + name: "Rsh64Ux64", + argLen: 2, + generic: true, + }, + { + name: "Lrot8", + auxType: auxInt64, + argLen: 1, + generic: true, + }, + { + name: "Lrot16", + auxType: auxInt64, + argLen: 1, + generic: true, + }, + { + name: "Lrot32", + auxType: auxInt64, + argLen: 1, + generic: true, + }, + { + name: "Lrot64", + auxType: auxInt64, + argLen: 1, + generic: true, + }, + { + name: "Eq8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Eq16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Eq32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Eq64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqPtr", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqInter", + argLen: 2, + generic: true, + }, + { + name: "EqSlice", + argLen: 2, + generic: true, + }, + { + name: "Eq32F", + argLen: 2, + generic: true, + }, + { + name: "Eq64F", + argLen: 2, + generic: true, + }, + { + name: "Neq8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Neq16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Neq32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Neq64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NeqPtr", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NeqInter", + argLen: 2, + generic: true, + }, + { + name: "NeqSlice", + argLen: 2, + generic: true, + }, + { + name: "Neq32F", + argLen: 2, + generic: true, + }, + { + name: "Neq64F", + argLen: 2, + generic: true, + }, + { + name: "Less8", + argLen: 2, + generic: true, + }, + { + name: "Less8U", + argLen: 2, + generic: true, + }, + { + name: "Less16", + argLen: 2, + generic: true, + }, + { + name: "Less16U", + argLen: 2, + generic: true, + }, + { + name: "Less32", + argLen: 2, + generic: true, + }, + { + name: "Less32U", + argLen: 2, + generic: true, + }, + { + name: "Less64", + argLen: 2, + generic: true, + }, + { + name: "Less64U", + argLen: 2, + generic: true, + }, + { + name: "Less32F", + argLen: 2, + generic: true, + }, + { + name: "Less64F", + argLen: 2, + generic: true, + }, + { + name: "Leq8", + argLen: 2, + generic: true, + }, + { + name: "Leq8U", + argLen: 2, + generic: true, + }, + { + name: "Leq16", + argLen: 2, + generic: true, + }, + { + name: "Leq16U", + argLen: 2, + generic: true, + }, + { + name: "Leq32", + argLen: 2, + generic: true, + }, + { + name: "Leq32U", + argLen: 2, + generic: true, + }, + { + name: "Leq64", + argLen: 2, + generic: true, + }, + { + name: "Leq64U", + argLen: 2, + generic: true, + }, + { + name: "Leq32F", + argLen: 2, + generic: true, + }, + { + name: "Leq64F", + argLen: 2, + generic: true, + }, + { + name: "Greater8", + argLen: 2, + generic: true, + }, + { + name: "Greater8U", + argLen: 2, + generic: true, + }, + { + name: "Greater16", + argLen: 2, + generic: true, + }, + { + name: "Greater16U", + argLen: 2, + generic: true, + }, + { + name: "Greater32", + argLen: 2, + generic: true, + }, + { + name: "Greater32U", + argLen: 2, + generic: true, + }, + { + name: "Greater64", + argLen: 2, + generic: true, + }, + { + name: "Greater64U", + argLen: 2, + generic: true, + }, + { + name: "Greater32F", + argLen: 2, + generic: true, + }, + { + name: "Greater64F", + argLen: 2, + generic: true, + }, + { + name: "Geq8", + argLen: 2, + generic: true, + }, + { + name: "Geq8U", + argLen: 2, + generic: true, + }, + { + name: "Geq16", + argLen: 2, + generic: true, + }, + { + name: "Geq16U", + argLen: 2, + generic: true, + }, + { + name: "Geq32", + argLen: 2, + generic: true, + }, + { + name: "Geq32U", + argLen: 2, + generic: true, + }, + { + name: "Geq64", + argLen: 2, + generic: true, + }, + { + name: "Geq64U", + argLen: 2, + generic: true, + }, + { + name: "Geq32F", + argLen: 2, + generic: true, + }, + { + name: "Geq64F", + argLen: 2, + generic: true, + }, + { + name: "Not", + argLen: 1, + generic: true, + }, + { + name: "Neg8", + argLen: 1, + generic: true, + }, + { + name: "Neg16", + argLen: 1, + generic: true, + }, + { + name: "Neg32", + argLen: 1, + generic: true, + }, + { + name: "Neg64", + argLen: 1, + generic: true, + }, + { + name: "Neg32F", + argLen: 1, + generic: true, + }, + { + name: "Neg64F", + argLen: 1, + generic: true, + }, + { + name: "Com8", + argLen: 1, + generic: true, + }, + { + name: "Com16", + argLen: 1, + generic: true, + }, + { + name: "Com32", + argLen: 1, + generic: true, + }, + { + name: "Com64", + argLen: 1, + generic: true, + }, + { + name: "Sqrt", + argLen: 1, + generic: true, + }, + { + name: "Phi", + argLen: -1, + generic: true, + }, + { + name: "Copy", + argLen: 1, + generic: true, + }, + { + name: "Convert", + argLen: 2, + generic: true, + }, + { + name: "ConstBool", + auxType: auxBool, + argLen: 0, + generic: true, + }, + { + name: "ConstString", + auxType: auxString, + argLen: 0, + generic: true, + }, + { + name: "ConstNil", + argLen: 0, + generic: true, + }, + { + name: "Const8", + auxType: auxInt8, + argLen: 0, + generic: true, + }, + { + name: "Const16", + auxType: auxInt16, + argLen: 0, + generic: true, + }, + { + name: "Const32", + auxType: auxInt32, + argLen: 0, + generic: true, + }, + { + name: "Const64", + auxType: auxInt64, + argLen: 0, + generic: true, + }, + { + name: "Const32F", + auxType: auxFloat, + argLen: 0, + generic: true, + }, + { + name: "Const64F", + auxType: auxFloat, + argLen: 0, + generic: true, + }, + { + name: "ConstInterface", + argLen: 0, + generic: true, + }, + { + name: "ConstSlice", + argLen: 0, + generic: true, + }, + { + name: "InitMem", + argLen: 0, + generic: true, + }, + { + name: "Arg", + auxType: auxSymOff, + argLen: 0, + generic: true, + }, + { + name: "Addr", + auxType: auxSym, + argLen: 1, + generic: true, + }, + { + name: "SP", + argLen: 0, + generic: true, + }, + { + name: "SB", + argLen: 0, + generic: true, + }, + { + name: "Func", + auxType: auxSym, + argLen: 0, + generic: true, + }, + { + name: "Load", + argLen: 2, + generic: true, + }, + { + name: "Store", + auxType: auxInt64, + argLen: 3, + generic: true, + }, + { + name: "Move", + auxType: auxInt64, + argLen: 3, + generic: true, + }, + { + name: "Zero", + auxType: auxInt64, + argLen: 2, + generic: true, + }, + { + name: "ClosureCall", + auxType: auxInt64, + argLen: 3, + generic: true, + }, + { + name: "StaticCall", + auxType: auxSymOff, + argLen: 1, + generic: true, + }, + { + name: "DeferCall", + auxType: auxInt64, + argLen: 1, + generic: true, + }, + { + name: "GoCall", + auxType: auxInt64, + argLen: 1, + generic: true, + }, + { + name: "InterCall", + auxType: auxInt64, + argLen: 2, + generic: true, + }, + { + name: "SignExt8to16", + argLen: 1, + generic: true, + }, + { + name: "SignExt8to32", + argLen: 1, + generic: true, + }, + { + name: "SignExt8to64", + argLen: 1, + generic: true, + }, + { + name: "SignExt16to32", + argLen: 1, + generic: true, + }, + { + name: "SignExt16to64", + argLen: 1, + generic: true, + }, + { + name: "SignExt32to64", + argLen: 1, + generic: true, + }, + { + name: "ZeroExt8to16", + argLen: 1, + generic: true, + }, + { + name: "ZeroExt8to32", + argLen: 1, + generic: true, + }, + { + name: "ZeroExt8to64", + argLen: 1, + generic: true, + }, + { + name: "ZeroExt16to32", + argLen: 1, + generic: true, + }, + { + name: "ZeroExt16to64", + argLen: 1, + generic: true, + }, + { + name: "ZeroExt32to64", + argLen: 1, + generic: true, + }, + { + name: "Trunc16to8", + argLen: 1, + generic: true, + }, + { + name: "Trunc32to8", + argLen: 1, + generic: true, + }, + { + name: "Trunc32to16", + argLen: 1, + generic: true, + }, + { + name: "Trunc64to8", + argLen: 1, + generic: true, + }, + { + name: "Trunc64to16", + argLen: 1, + generic: true, + }, + { + name: "Trunc64to32", + argLen: 1, + generic: true, + }, + { + name: "Cvt32to32F", + argLen: 1, + generic: true, + }, + { + name: "Cvt32to64F", + argLen: 1, + generic: true, + }, + { + name: "Cvt64to32F", + argLen: 1, + generic: true, + }, + { + name: "Cvt64to64F", + argLen: 1, + generic: true, + }, + { + name: "Cvt32Fto32", + argLen: 1, + generic: true, + }, + { + name: "Cvt32Fto64", + argLen: 1, + generic: true, + }, + { + name: "Cvt64Fto32", + argLen: 1, + generic: true, + }, + { + name: "Cvt64Fto64", + argLen: 1, + generic: true, + }, + { + name: "Cvt32Fto64F", + argLen: 1, + generic: true, + }, + { + name: "Cvt64Fto32F", + argLen: 1, + generic: true, + }, + { + name: "IsNonNil", + argLen: 1, + generic: true, + }, + { + name: "IsInBounds", + argLen: 2, + generic: true, + }, + { + name: "IsSliceInBounds", + argLen: 2, + generic: true, + }, + { + name: "NilCheck", + argLen: 2, + generic: true, + }, + { + name: "GetG", + argLen: 1, + generic: true, + }, + { + name: "GetClosurePtr", + argLen: 0, + generic: true, + }, + { + name: "ArrayIndex", + argLen: 2, + generic: true, + }, + { + name: "PtrIndex", + argLen: 2, + generic: true, + }, + { + name: "OffPtr", + auxType: auxInt64, + argLen: 1, + generic: true, + }, + { + name: "SliceMake", + argLen: 3, + generic: true, + }, + { + name: "SlicePtr", + argLen: 1, + generic: true, + }, + { + name: "SliceLen", + argLen: 1, + generic: true, + }, + { + name: "SliceCap", + argLen: 1, + generic: true, + }, + { + name: "ComplexMake", + argLen: 2, + generic: true, + }, + { + name: "ComplexReal", + argLen: 1, + generic: true, + }, + { + name: "ComplexImag", + argLen: 1, + generic: true, + }, + { + name: "StringMake", + argLen: 2, + generic: true, + }, + { + name: "StringPtr", + argLen: 1, + generic: true, + }, + { + name: "StringLen", + argLen: 1, + generic: true, + }, + { + name: "IMake", + argLen: 2, + generic: true, + }, + { + name: "ITab", + argLen: 1, + generic: true, + }, + { + name: "IData", + argLen: 1, + generic: true, + }, + { + name: "StructMake0", + argLen: 0, + generic: true, + }, + { + name: "StructMake1", + argLen: 1, + generic: true, + }, + { + name: "StructMake2", + argLen: 2, + generic: true, + }, + { + name: "StructMake3", + argLen: 3, + generic: true, + }, + { + name: "StructMake4", + argLen: 4, + generic: true, + }, + { + name: "StructSelect", + auxType: auxInt64, + argLen: 1, + generic: true, + }, + { + name: "StoreReg", + argLen: 1, + generic: true, + }, + { + name: "LoadReg", + argLen: 1, + generic: true, + }, + { + name: "FwdRef", + argLen: 0, + generic: true, + }, + { + name: "Unknown", + argLen: 0, + generic: true, + }, + { + name: "VarDef", + auxType: auxSym, + argLen: 1, + generic: true, + }, + { + name: "VarKill", + auxType: auxSym, + argLen: 1, + generic: true, + }, + { + name: "VarLive", + auxType: auxSym, + argLen: 1, + generic: true, + }, +} + +func (o Op) Asm() int { return opcodeTable[o].asm } +func (o Op) String() string { return opcodeTable[o].name } diff --git a/src/cmd/compile/internal/ssa/opt.go b/src/cmd/compile/internal/ssa/opt.go new file mode 100644 index 0000000000..6e91fd7da3 --- /dev/null +++ b/src/cmd/compile/internal/ssa/opt.go @@ -0,0 +1,10 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +// machine-independent optimization +func opt(f *Func) { + applyRewrite(f, rewriteBlockgeneric, rewriteValuegeneric) +} diff --git a/src/cmd/compile/internal/ssa/passbm_test.go b/src/cmd/compile/internal/ssa/passbm_test.go new file mode 100644 index 0000000000..8dff17a5b4 --- /dev/null +++ b/src/cmd/compile/internal/ssa/passbm_test.go @@ -0,0 +1,101 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. +package ssa + +import ( + "fmt" + "testing" +) + +const ( + blockCount = 1000 + passCount = 15000 +) + +type passFunc func(*Func) + +func BenchmarkDSEPass(b *testing.B) { benchFnPass(b, dse, blockCount, genFunction) } +func BenchmarkDSEPassBlock(b *testing.B) { benchFnBlock(b, dse, genFunction) } +func BenchmarkCSEPass(b *testing.B) { benchFnPass(b, cse, blockCount, genFunction) } +func BenchmarkCSEPassBlock(b *testing.B) { benchFnBlock(b, cse, genFunction) } +func BenchmarkDeadcodePass(b *testing.B) { benchFnPass(b, deadcode, blockCount, genFunction) } +func BenchmarkDeadcodePassBlock(b *testing.B) { benchFnBlock(b, deadcode, genFunction) } + +func multi(f *Func) { + cse(f) + dse(f) + deadcode(f) +} +func BenchmarkMultiPass(b *testing.B) { benchFnPass(b, multi, blockCount, genFunction) } +func BenchmarkMultiPassBlock(b *testing.B) { benchFnBlock(b, multi, genFunction) } + +// benchFnPass runs passFunc b.N times across a single function. +func benchFnPass(b *testing.B, fn passFunc, size int, bg blockGen) { + b.ReportAllocs() + c := NewConfig("amd64", DummyFrontend{b}, nil, true) + fun := Fun(c, "entry", bg(size)...) + + CheckFunc(fun.f) + b.ResetTimer() + for i := 0; i < b.N; i++ { + fn(fun.f) + b.StopTimer() + CheckFunc(fun.f) + b.StartTimer() + } +} + +// benchFnPass runs passFunc across a function with b.N blocks. +func benchFnBlock(b *testing.B, fn passFunc, bg blockGen) { + b.ReportAllocs() + c := NewConfig("amd64", DummyFrontend{b}, nil, true) + fun := Fun(c, "entry", bg(b.N)...) + + CheckFunc(fun.f) + b.ResetTimer() + for i := 0; i < passCount; i++ { + fn(fun.f) + } + b.StopTimer() +} + +func genFunction(size int) []bloc { + var blocs []bloc + elemType := &TypeImpl{Size_: 8, Name: "testtype"} + ptrType := &TypeImpl{Size_: 8, Ptr: true, Name: "testptr", Elem_: elemType} // dummy for testing + + valn := func(s string, m, n int) string { return fmt.Sprintf("%s%d-%d", s, m, n) } + blocs = append(blocs, + Bloc("entry", + Valu(valn("store", 0, 4), OpInitMem, TypeMem, 0, nil), + Valu("sb", OpSB, TypeInvalid, 0, nil), + Goto(blockn(1)), + ), + ) + for i := 1; i < size+1; i++ { + blocs = append(blocs, Bloc(blockn(i), + Valu(valn("v", i, 0), OpConstBool, TypeBool, 1, nil), + Valu(valn("addr", i, 1), OpAddr, ptrType, 0, nil, "sb"), + Valu(valn("addr", i, 2), OpAddr, ptrType, 0, nil, "sb"), + Valu(valn("addr", i, 3), OpAddr, ptrType, 0, nil, "sb"), + Valu(valn("zero", i, 1), OpZero, TypeMem, 8, nil, valn("addr", i, 3), + valn("store", i-1, 4)), + Valu(valn("store", i, 1), OpStore, TypeMem, 0, nil, valn("addr", i, 1), + valn("v", i, 0), valn("zero", i, 1)), + Valu(valn("store", i, 2), OpStore, TypeMem, 0, nil, valn("addr", i, 2), + valn("v", i, 0), valn("store", i, 1)), + Valu(valn("store", i, 3), OpStore, TypeMem, 0, nil, valn("addr", i, 1), + valn("v", i, 0), valn("store", i, 2)), + Valu(valn("store", i, 4), OpStore, TypeMem, 0, nil, valn("addr", i, 3), + valn("v", i, 0), valn("store", i, 3)), + Goto(blockn(i+1)))) + } + + blocs = append(blocs, + Bloc(blockn(size+1), Goto("exit")), + Bloc("exit", Exit("store0-4")), + ) + + return blocs +} diff --git a/src/cmd/compile/internal/ssa/phielim.go b/src/cmd/compile/internal/ssa/phielim.go new file mode 100644 index 0000000000..d69449ee21 --- /dev/null +++ b/src/cmd/compile/internal/ssa/phielim.go @@ -0,0 +1,68 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +// phielim eliminates redundant phi values from f. +// A phi is redundant if its arguments are all equal. For +// purposes of counting, ignore the phi itself. Both of +// these phis are redundant: +// v = phi(x,x,x) +// v = phi(x,v,x,v) +// We repeat this process to also catch situations like: +// v = phi(x, phi(x, x), phi(x, v)) +// TODO: Can we also simplify cases like: +// v = phi(v, w, x) +// w = phi(v, w, x) +// and would that be useful? +func phielim(f *Func) { + for { + change := false + for _, b := range f.Blocks { + for _, v := range b.Values { + copyelimValue(v) + change = phielimValue(v) || change + } + } + if !change { + break + } + } +} + +func phielimValue(v *Value) bool { + if v.Op != OpPhi { + return false + } + + // If there are two distinct args of v which + // are not v itself, then the phi must remain. + // Otherwise, we can replace it with a copy. + var w *Value + for i, x := range v.Args { + if b := v.Block.Preds[i]; b.Kind == BlockFirst && b.Succs[1] == v.Block { + // This branch is never taken so we can just eliminate it. + continue + } + if x == v { + continue + } + if x == w { + continue + } + if w != nil { + return false + } + w = x + } + + if w == nil { + // v references only itself. It must be in + // a dead code loop. Don't bother modifying it. + return false + } + v.Op = OpCopy + v.SetArgs1(w) + return true +} diff --git a/src/cmd/compile/internal/ssa/phiopt.go b/src/cmd/compile/internal/ssa/phiopt.go new file mode 100644 index 0000000000..fb17727242 --- /dev/null +++ b/src/cmd/compile/internal/ssa/phiopt.go @@ -0,0 +1,86 @@ +package ssa + +// phiopt eliminates boolean Phis based on the previous if. +// +// Main use case is to transform: +// x := false +// if b { +// x = true +// } +// into x = b. +// +// In SSA code this appears as +// +// b0 +// If b -> b1 b2 +// b1 +// Plain -> b2 +// b2 +// x = (OpPhi (ConstBool [true]) (ConstBool [false])) +// +// In this case we can replace x with a copy of b. +func phiopt(f *Func) { + for _, b := range f.Blocks { + if len(b.Preds) != 2 || len(b.Values) == 0 { + continue + } + + pb0, b0 := b, b.Preds[0] + for b0.Kind != BlockIf && len(b0.Preds) == 1 { + pb0, b0 = b0, b0.Preds[0] + } + if b0.Kind != BlockIf { + continue + } + pb1, b1 := b, b.Preds[1] + for b1.Kind != BlockIf && len(b1.Preds) == 1 { + pb1, b1 = b1, b1.Preds[0] + } + if b1 != b0 { + continue + } + // b0 is the if block giving the boolean value. + + var reverse bool + if b0.Succs[0] == pb0 && b0.Succs[1] == pb1 { + reverse = false + } else if b0.Succs[0] == pb1 && b0.Succs[1] == pb0 { + reverse = true + } else { + b.Fatalf("invalid predecessors\n") + } + + for _, v := range b.Values { + if v.Op != OpPhi || !v.Type.IsBoolean() || v.Args[0].Op != OpConstBool || v.Args[1].Op != OpConstBool { + continue + } + + ok, isCopy := false, false + if v.Args[0].AuxInt == 1 && v.Args[1].AuxInt == 0 { + ok, isCopy = true, !reverse + } else if v.Args[0].AuxInt == 0 && v.Args[1].AuxInt == 1 { + ok, isCopy = true, reverse + } + + // (Phi (ConstBool [x]) (ConstBool [x])) is already handled by opt / phielim. + + if ok && isCopy { + if f.pass.debug > 0 { + f.Config.Warnl(int(b.Line), "converted OpPhi to OpCopy") + } + v.reset(OpCopy) + v.AddArg(b0.Control) + continue + } + if ok && !isCopy { + if f.pass.debug > 0 { + f.Config.Warnl(int(b.Line), "converted OpPhi to OpNot") + } + v.reset(OpNot) + v.AddArg(b0.Control) + continue + } + } + } + +} diff --git a/src/cmd/compile/internal/ssa/print.go b/src/cmd/compile/internal/ssa/print.go new file mode 100644 index 0000000000..c6f84ab6cb --- /dev/null +++ b/src/cmd/compile/internal/ssa/print.go @@ -0,0 +1,149 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import ( + "bytes" + "fmt" + "io" +) + +func printFunc(f *Func) { + f.Logf("%s", f) +} + +func (f *Func) String() string { + var buf bytes.Buffer + p := stringFuncPrinter{w: &buf} + fprintFunc(p, f) + return buf.String() +} + +type funcPrinter interface { + header(f *Func) + startBlock(b *Block, reachable bool) + endBlock(b *Block) + value(v *Value, live bool) + startDepCycle() + endDepCycle() + named(n LocalSlot, vals []*Value) +} + +type stringFuncPrinter struct { + w io.Writer +} + +func (p stringFuncPrinter) header(f *Func) { + fmt.Fprint(p.w, f.Name) + fmt.Fprint(p.w, " ") + fmt.Fprintln(p.w, f.Type) +} + +func (p stringFuncPrinter) startBlock(b *Block, reachable bool) { + fmt.Fprintf(p.w, " b%d:", b.ID) + if len(b.Preds) > 0 { + io.WriteString(p.w, " <-") + for _, pred := range b.Preds { + fmt.Fprintf(p.w, " b%d", pred.ID) + } + } + if !reachable { + fmt.Fprint(p.w, " DEAD") + } + io.WriteString(p.w, "\n") +} + +func (p stringFuncPrinter) endBlock(b *Block) { + fmt.Fprintln(p.w, " "+b.LongString()) +} + +func (p stringFuncPrinter) value(v *Value, live bool) { + fmt.Fprint(p.w, " ") + //fmt.Fprint(p.w, v.Block.Func.Config.fe.Line(v.Line)) + //fmt.Fprint(p.w, ": ") + fmt.Fprint(p.w, v.LongString()) + if !live { + fmt.Fprint(p.w, " DEAD") + } + fmt.Fprintln(p.w) +} + +func (p stringFuncPrinter) startDepCycle() { + fmt.Fprintln(p.w, "dependency cycle!") +} + +func (p stringFuncPrinter) endDepCycle() {} + +func (p stringFuncPrinter) named(n LocalSlot, vals []*Value) { + fmt.Fprintf(p.w, "name %s: %v\n", n.Name(), vals) +} + +func fprintFunc(p funcPrinter, f *Func) { + reachable, live := findlive(f) + p.header(f) + printed := make([]bool, f.NumValues()) + for _, b := range f.Blocks { + p.startBlock(b, reachable[b.ID]) + + if f.scheduled { + // Order of Values has been decided - print in that order. + for _, v := range b.Values { + p.value(v, live[v.ID]) + printed[v.ID] = true + } + p.endBlock(b) + continue + } + + // print phis first since all value cycles contain a phi + n := 0 + for _, v := range b.Values { + if v.Op != OpPhi { + continue + } + p.value(v, live[v.ID]) + printed[v.ID] = true + n++ + } + + // print rest of values in dependency order + for n < len(b.Values) { + m := n + outer: + for _, v := range b.Values { + if printed[v.ID] { + continue + } + for _, w := range v.Args { + // w == nil shouldn't happen, but if it does, + // don't panic; we'll get a better diagnosis later. + if w != nil && w.Block == b && !printed[w.ID] { + continue outer + } + } + p.value(v, live[v.ID]) + printed[v.ID] = true + n++ + } + if m == n { + p.startDepCycle() + for _, v := range b.Values { + if printed[v.ID] { + continue + } + p.value(v, live[v.ID]) + printed[v.ID] = true + n++ + } + p.endDepCycle() + } + } + + p.endBlock(b) + } + for name, vals := range f.NamedValues { + p.named(name, vals) + } +} diff --git a/src/cmd/compile/internal/ssa/prove.go b/src/cmd/compile/internal/ssa/prove.go new file mode 100644 index 0000000000..a915e0b5a7 --- /dev/null +++ b/src/cmd/compile/internal/ssa/prove.go @@ -0,0 +1,351 @@ +// Copyright 2016 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +// rangeMask represents the possible relations between a pair of variables. +type rangeMask uint + +const ( + lt rangeMask = 1 << iota + eq + gt +) + +// typeMask represents the universe of a variable pair in which +// a set of relations is known. +// For example, information learned for unsigned pairs cannot +// be transfered to signed pairs because the same bit representation +// can mean something else. +type typeMask uint + +const ( + signed typeMask = 1 << iota + unsigned + pointer +) + +type typeRange struct { + t typeMask + r rangeMask +} + +type control struct { + tm typeMask + a0, a1 ID +} + +var ( + reverseBits = [...]rangeMask{0, 4, 2, 6, 1, 5, 3, 7} + + // maps what we learn when the positive branch is taken. + // For example: + // OpLess8: {signed, lt}, + // v1 = (OpLess8 v2 v3). + // If v1 branch is taken than we learn that the rangeMaks + // can be at most lt. + typeRangeTable = map[Op]typeRange{ + OpEq8: {signed | unsigned, eq}, + OpEq16: {signed | unsigned, eq}, + OpEq32: {signed | unsigned, eq}, + OpEq64: {signed | unsigned, eq}, + OpEqPtr: {pointer, eq}, + + OpNeq8: {signed | unsigned, lt | gt}, + OpNeq16: {signed | unsigned, lt | gt}, + OpNeq32: {signed | unsigned, lt | gt}, + OpNeq64: {signed | unsigned, lt | gt}, + OpNeqPtr: {pointer, lt | gt}, + + OpLess8: {signed, lt}, + OpLess8U: {unsigned, lt}, + OpLess16: {signed, lt}, + OpLess16U: {unsigned, lt}, + OpLess32: {signed, lt}, + OpLess32U: {unsigned, lt}, + OpLess64: {signed, lt}, + OpLess64U: {unsigned, lt}, + + OpLeq8: {signed, lt | eq}, + OpLeq8U: {unsigned, lt | eq}, + OpLeq16: {signed, lt | eq}, + OpLeq16U: {unsigned, lt | eq}, + OpLeq32: {signed, lt | eq}, + OpLeq32U: {unsigned, lt | eq}, + OpLeq64: {signed, lt | eq}, + OpLeq64U: {unsigned, lt | eq}, + + OpGeq8: {signed, eq | gt}, + OpGeq8U: {unsigned, eq | gt}, + OpGeq16: {signed, eq | gt}, + OpGeq16U: {unsigned, eq | gt}, + OpGeq32: {signed, eq | gt}, + OpGeq32U: {unsigned, eq | gt}, + OpGeq64: {signed, eq | gt}, + OpGeq64U: {unsigned, eq | gt}, + + OpGreater8: {signed, gt}, + OpGreater8U: {unsigned, gt}, + OpGreater16: {signed, gt}, + OpGreater16U: {unsigned, gt}, + OpGreater32: {signed, gt}, + OpGreater32U: {unsigned, gt}, + OpGreater64: {signed, gt}, + OpGreater64U: {unsigned, gt}, + + // TODO: OpIsInBounds actually test 0 <= a < b. This means + // that the positive branch learns signed/LT and unsigned/LT + // but the negative branch only learns unsigned/GE. + OpIsInBounds: {unsigned, lt}, + OpIsSliceInBounds: {unsigned, lt | eq}, + } +) + +// prove removes redundant BlockIf controls that can be inferred in a straight line. +// +// By far, the most common redundant control are generated by bounds checking. +// For example for the code: +// +// a[i] = 4 +// foo(a[i]) +// +// The compiler will generate the following code: +// +// if i >= len(a) { +// panic("not in bounds") +// } +// a[i] = 4 +// if i >= len(a) { +// panic("not in bounds") +// } +// foo(a[i]) +// +// The second comparison i >= len(a) is clearly redundant because if the +// else branch of the first comparison is executed, we already know that i < len(a). +// The code for the second panic can be removed. +func prove(f *Func) { + idom := dominators(f) + sdom := newSparseTree(f, idom) + + // current node state + type walkState int + const ( + descend walkState = iota + simplify + ) + // work maintains the DFS stack. + type bp struct { + block *Block // current handled block + state walkState // what's to do + saved []typeRange // save previous map entries modified by node + } + work := make([]bp, 0, 256) + work = append(work, bp{ + block: f.Entry, + state: descend, + }) + + // mask keep tracks of restrictions for each pair of values in + // the dominators for the current node. + // Invariant: a0.ID <= a1.ID + // For example {unsigned, a0, a1} -> eq|gt means that from + // predecessors we know that a0 must be greater or equal to + // a1. + mask := make(map[control]rangeMask) + + // DFS on the dominator tree. + for len(work) > 0 { + node := work[len(work)-1] + work = work[:len(work)-1] + + switch node.state { + case descend: + parent := idom[node.block.ID] + tr := getRestrict(sdom, parent, node.block) + saved := updateRestrictions(mask, parent, tr) + + work = append(work, bp{ + block: node.block, + state: simplify, + saved: saved, + }) + + for s := sdom.Child(node.block); s != nil; s = sdom.Sibling(s) { + work = append(work, bp{ + block: s, + state: descend, + }) + } + + case simplify: + simplifyBlock(mask, node.block) + restoreRestrictions(mask, idom[node.block.ID], node.saved) + } + } +} + +// getRestrict returns the range restrictions added by p +// when reaching b. p is the immediate dominator or b. +func getRestrict(sdom sparseTree, p *Block, b *Block) typeRange { + if p == nil || p.Kind != BlockIf { + return typeRange{} + } + tr, has := typeRangeTable[p.Control.Op] + if !has { + return typeRange{} + } + // If p and p.Succs[0] are dominators it means that every path + // from entry to b passes through p and p.Succs[0]. We care that + // no path from entry to b passes through p.Succs[1]. If p.Succs[0] + // has one predecessor then (apart from the degenerate case), + // there is no path from entry that can reach b through p.Succs[1]. + // TODO: how about p->yes->b->yes, i.e. a loop in yes. + if sdom.isAncestorEq(p.Succs[0], b) && len(p.Succs[0].Preds) == 1 { + return tr + } else if sdom.isAncestorEq(p.Succs[1], b) && len(p.Succs[1].Preds) == 1 { + tr.r = (lt | eq | gt) ^ tr.r + return tr + } + return typeRange{} +} + +// updateRestrictions updates restrictions from the previous block (p) based on tr. +// normally tr was calculated with getRestrict. +func updateRestrictions(mask map[control]rangeMask, p *Block, tr typeRange) []typeRange { + if tr.t == 0 { + return nil + } + + // p modifies the restrictions for (a0, a1). + // save and return the previous state. + a0 := p.Control.Args[0] + a1 := p.Control.Args[1] + if a0.ID > a1.ID { + tr.r = reverseBits[tr.r] + a0, a1 = a1, a0 + } + + saved := make([]typeRange, 0, 2) + for t := typeMask(1); t <= tr.t; t <<= 1 { + if t&tr.t == 0 { + continue + } + + i := control{t, a0.ID, a1.ID} + oldRange, ok := mask[i] + if !ok { + if a1 != a0 { + oldRange = lt | eq | gt + } else { // sometimes happens after cse + oldRange = eq + } + } + // if i was not already in the map we save the full range + // so that when we restore it we properly keep track of it. + saved = append(saved, typeRange{t, oldRange}) + // mask[i] contains the possible relations between a0 and a1. + // When we branched from parent we learned that the possible + // relations cannot be more than tr.r. We compute the new set of + // relations as the intersection betwee the old and the new set. + mask[i] = oldRange & tr.r + } + return saved +} + +func restoreRestrictions(mask map[control]rangeMask, p *Block, saved []typeRange) { + if p == nil || p.Kind != BlockIf || len(saved) == 0 { + return + } + + a0 := p.Control.Args[0].ID + a1 := p.Control.Args[1].ID + if a0 > a1 { + a0, a1 = a1, a0 + } + + for _, tr := range saved { + i := control{tr.t, a0, a1} + if tr.r != lt|eq|gt { + mask[i] = tr.r + } else { + delete(mask, i) + } + } +} + +// simplifyBlock simplifies block known the restrictions in mask. +func simplifyBlock(mask map[control]rangeMask, b *Block) { + if b.Kind != BlockIf { + return + } + + tr, has := typeRangeTable[b.Control.Op] + if !has { + return + } + + succ := -1 + a0 := b.Control.Args[0].ID + a1 := b.Control.Args[1].ID + if a0 > a1 { + tr.r = reverseBits[tr.r] + a0, a1 = a1, a0 + } + + for t := typeMask(1); t <= tr.t; t <<= 1 { + if t&tr.t == 0 { + continue + } + + // tr.r represents in which case the positive branch is taken. + // m.r represents which cases are possible because of previous relations. + // If the set of possible relations m.r is included in the set of relations + // need to take the positive branch (or negative) then that branch will + // always be taken. + // For shortcut, if m.r == 0 then this block is dead code. + i := control{t, a0, a1} + m := mask[i] + if m != 0 && tr.r&m == m { + if b.Func.pass.debug > 0 { + b.Func.Config.Warnl(int(b.Line), "Proved %s", b.Control.Op) + } + b.Logf("proved positive branch of %s, block %s in %s\n", b.Control, b, b.Func.Name) + succ = 0 + break + } + if m != 0 && ((lt|eq|gt)^tr.r)&m == m { + if b.Func.pass.debug > 0 { + b.Func.Config.Warnl(int(b.Line), "Disproved %s", b.Control.Op) + } + b.Logf("proved negative branch of %s, block %s in %s\n", b.Control, b, b.Func.Name) + succ = 1 + break + } + } + + if succ == -1 { + // HACK: If the first argument of IsInBounds or IsSliceInBounds + // is a constant and we already know that constant is smaller (or equal) + // to the upper bound than this is proven. Most useful in cases such as: + // if len(a) <= 1 { return } + // do something with a[1] + c := b.Control + if (c.Op == OpIsInBounds || c.Op == OpIsSliceInBounds) && + c.Args[0].Op == OpConst64 && c.Args[0].AuxInt >= 0 { + m := mask[control{signed, a0, a1}] + if m != 0 && tr.r&m == m { + if b.Func.pass.debug > 0 { + b.Func.Config.Warnl(int(b.Line), "Proved constant %s", c.Op) + } + succ = 0 + } + } + } + + if succ != -1 { + b.Kind = BlockFirst + b.Control = nil + b.Succs[0], b.Succs[1] = b.Succs[succ], b.Succs[1-succ] + } +} diff --git a/src/cmd/compile/internal/ssa/regalloc.go b/src/cmd/compile/internal/ssa/regalloc.go new file mode 100644 index 0000000000..e900a3cfb8 --- /dev/null +++ b/src/cmd/compile/internal/ssa/regalloc.go @@ -0,0 +1,1658 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// Register allocation. +// +// We use a version of a linear scan register allocator. We treat the +// whole function as a single long basic block and run through +// it using a greedy register allocator. Then all merge edges +// (those targeting a block with len(Preds)>1) are processed to +// shuffle data into the place that the target of the edge expects. +// +// The greedy allocator moves values into registers just before they +// are used, spills registers only when necessary, and spills the +// value whose next use is farthest in the future. +// +// The register allocator requires that a block is not scheduled until +// at least one of its predecessors have been scheduled. The most recent +// such predecessor provides the starting register state for a block. +// +// It also requires that there are no critical edges (critical = +// comes from a block with >1 successor and goes to a block with >1 +// predecessor). This makes it easy to add fixup code on merge edges - +// the source of a merge edge has only one successor, so we can add +// fixup code to the end of that block. + +// Spilling +// +// For every value, we generate a spill immediately after the value itself. +// x = Op y z : AX +// x2 = StoreReg x +// While AX still holds x, any uses of x will use that value. When AX is needed +// for another value, we simply reuse AX. Spill code has already been generated +// so there is no code generated at "spill" time. When x is referenced +// subsequently, we issue a load to restore x to a register using x2 as +// its argument: +// x3 = Restore x2 : CX +// x3 can then be used wherever x is referenced again. +// If the spill (x2) is never used, it will be removed at the end of regalloc. +// +// Phi values are special, as always. We define two kinds of phis, those +// where the merge happens in a register (a "register" phi) and those where +// the merge happens in a stack location (a "stack" phi). +// +// A register phi must have the phi and all of its inputs allocated to the +// same register. Register phis are spilled similarly to regular ops: +// b1: y = ... : AX b2: z = ... : AX +// goto b3 goto b3 +// b3: x = phi(y, z) : AX +// x2 = StoreReg x +// +// A stack phi must have the phi and all of its inputs allocated to the same +// stack location. Stack phis start out life already spilled - each phi +// input must be a store (using StoreReg) at the end of the corresponding +// predecessor block. +// b1: y = ... : AX b2: z = ... : BX +// y2 = StoreReg y z2 = StoreReg z +// goto b3 goto b3 +// b3: x = phi(y2, z2) +// The stack allocator knows that StoreReg args of stack-allocated phis +// must be allocated to the same stack slot as the phi that uses them. +// x is now a spilled value and a restore must appear before its first use. + +// TODO + +// Use an affinity graph to mark two values which should use the +// same register. This affinity graph will be used to prefer certain +// registers for allocation. This affinity helps eliminate moves that +// are required for phi implementations and helps generate allocations +// for 2-register architectures. + +// Note: regalloc generates a not-quite-SSA output. If we have: +// +// b1: x = ... : AX +// x2 = StoreReg x +// ... AX gets reused for something else ... +// if ... goto b3 else b4 +// +// b3: x3 = LoadReg x2 : BX b4: x4 = LoadReg x2 : CX +// ... use x3 ... ... use x4 ... +// +// b2: ... use x3 ... +// +// If b3 is the primary predecessor of b2, then we use x3 in b2 and +// add a x4:CX->BX copy at the end of b4. +// But the definition of x3 doesn't dominate b2. We should really +// insert a dummy phi at the start of b2 (x5=phi(x3,x4):BX) to keep +// SSA form. For now, we ignore this problem as remaining in strict +// SSA form isn't needed after regalloc. We'll just leave the use +// of x3 not dominated by the definition of x3, and the CX->BX copy +// will have no use (so don't run deadcode after regalloc!). +// TODO: maybe we should introduce these extra phis? + +package ssa + +import ( + "cmd/internal/obj" + "fmt" + "unsafe" +) + +const regDebug = false // TODO: compiler flag +const logSpills = false + +// regalloc performs register allocation on f. It sets f.RegAlloc +// to the resulting allocation. +func regalloc(f *Func) { + var s regAllocState + s.init(f) + s.regalloc(f) +} + +type register uint8 + +const noRegister register = 255 + +type regMask uint64 + +func (m regMask) String() string { + s := "" + for r := register(0); r < numRegs; r++ { + if m>>r&1 == 0 { + continue + } + if s != "" { + s += " " + } + s += fmt.Sprintf("r%d", r) + } + return s +} + +// TODO: make arch-dependent +var numRegs register = 64 + +var registers = [...]Register{ + Register{0, "AX"}, + Register{1, "CX"}, + Register{2, "DX"}, + Register{3, "BX"}, + Register{4, "SP"}, + Register{5, "BP"}, + Register{6, "SI"}, + Register{7, "DI"}, + Register{8, "R8"}, + Register{9, "R9"}, + Register{10, "R10"}, + Register{11, "R11"}, + Register{12, "R12"}, + Register{13, "R13"}, + Register{14, "R14"}, + Register{15, "R15"}, + Register{16, "X0"}, + Register{17, "X1"}, + Register{18, "X2"}, + Register{19, "X3"}, + Register{20, "X4"}, + Register{21, "X5"}, + Register{22, "X6"}, + Register{23, "X7"}, + Register{24, "X8"}, + Register{25, "X9"}, + Register{26, "X10"}, + Register{27, "X11"}, + Register{28, "X12"}, + Register{29, "X13"}, + Register{30, "X14"}, + Register{31, "X15"}, + Register{32, "SB"}, // pseudo-register for global base pointer (aka %rip) + + // TODO: make arch-dependent +} + +// countRegs returns the number of set bits in the register mask. +func countRegs(r regMask) int { + n := 0 + for r != 0 { + n += int(r & 1) + r >>= 1 + } + return n +} + +// pickReg picks an arbitrary register from the register mask. +func pickReg(r regMask) register { + // pick the lowest one + if r == 0 { + panic("can't pick a register from an empty set") + } + for i := register(0); ; i++ { + if r&1 != 0 { + return i + } + r >>= 1 + } +} + +type use struct { + dist int32 // distance from start of the block to a use of a value + next *use // linked list of uses of a value in nondecreasing dist order +} + +type valState struct { + regs regMask // the set of registers holding a Value (usually just one) + uses *use // list of uses in this block + spill *Value // spilled copy of the Value + spillUsed bool + needReg bool // cached value of !v.Type.IsMemory() && !v.Type.IsVoid() && !.v.Type.IsFlags() + rematerializeable bool // cached value of v.rematerializeable() + desired register // register we want value to be in, if any + avoid regMask // registers to avoid if we can +} + +type regState struct { + v *Value // Original (preregalloc) Value stored in this register. + c *Value // A Value equal to v which is currently in a register. Might be v or a copy of it. + // If a register is unused, v==c==nil +} + +type regAllocState struct { + f *Func + + // for each block, its primary predecessor. + // A predecessor of b is primary if it is the closest + // predecessor that appears before b in the layout order. + // We record the index in the Preds list where the primary predecessor sits. + primary []int32 + + // live values at the end of each block. live[b.ID] is a list of value IDs + // which are live at the end of b, together with a count of how many instructions + // forward to the next use. + live [][]liveInfo + + // current state of each (preregalloc) Value + values []valState + + // For each Value, map from its value ID back to the + // preregalloc Value it was derived from. + orig []*Value + + // current state of each register + regs []regState + + // registers that contain values which can't be kicked out + nospill regMask + + // mask of registers currently in use + used regMask + + // current block we're working on + curBlock *Block + + // cache of use records + freeUseRecords *use + + // endRegs[blockid] is the register state at the end of each block. + // encoded as a set of endReg records. + endRegs [][]endReg + + // startRegs[blockid] is the register state at the start of merge blocks. + // saved state does not include the state of phi ops in the block. + startRegs [][]startReg + + // spillLive[blockid] is the set of live spills at the end of each block + spillLive [][]ID +} + +type endReg struct { + r register + v *Value // pre-regalloc value held in this register (TODO: can we use ID here?) + c *Value // cached version of the value +} + +type startReg struct { + r register + vid ID // pre-regalloc value needed in this register +} + +// freeReg frees up register r. Any current user of r is kicked out. +func (s *regAllocState) freeReg(r register) { + v := s.regs[r].v + if v == nil { + s.f.Fatalf("tried to free an already free register %d\n", r) + } + + // Mark r as unused. + if regDebug { + fmt.Printf("freeReg %s (dump %s/%s)\n", registers[r].Name(), v, s.regs[r].c) + } + s.regs[r] = regState{} + s.values[v.ID].regs &^= regMask(1) << r + s.used &^= regMask(1) << r +} + +// freeRegs frees up all registers listed in m. +func (s *regAllocState) freeRegs(m regMask) { + for m&s.used != 0 { + s.freeReg(pickReg(m & s.used)) + } +} + +// setOrig records that c's original value is the same as +// v's original value. +func (s *regAllocState) setOrig(c *Value, v *Value) { + for int(c.ID) >= len(s.orig) { + s.orig = append(s.orig, nil) + } + if s.orig[c.ID] != nil { + s.f.Fatalf("orig value set twice %s %s", c, v) + } + s.orig[c.ID] = s.orig[v.ID] +} + +// assignReg assigns register r to hold c, a copy of v. +// r must be unused. +func (s *regAllocState) assignReg(r register, v *Value, c *Value) { + if regDebug { + fmt.Printf("assignReg %s %s/%s\n", registers[r].Name(), v, c) + } + if s.regs[r].v != nil { + s.f.Fatalf("tried to assign register %d to %s/%s but it is already used by %s", r, v, c, s.regs[r].v) + } + + // Update state. + s.regs[r] = regState{v, c} + s.values[v.ID].regs |= regMask(1) << r + s.used |= regMask(1) << r + s.f.setHome(c, ®isters[r]) +} + +// allocReg chooses a register for v from the set of registers in mask. +// If there is no unused register, a Value will be kicked out of +// a register to make room. +func (s *regAllocState) allocReg(v *Value, mask regMask) register { + mask &^= s.nospill + if mask == 0 { + s.f.Fatalf("no register available") + } + + // Pick an unused register if one is available. + if mask&^s.used != 0 { + mask &^= s.used + + // Use desired register if we can. + d := s.values[v.ID].desired + if d != noRegister && mask>>d&1 != 0 { + mask = regMask(1) << d + } + + // Avoid avoidable registers if we can. + if mask&^s.values[v.ID].avoid != 0 { + mask &^= s.values[v.ID].avoid + } + + return pickReg(mask) + } + + // Pick a value to spill. Spill the value with the + // farthest-in-the-future use. + // TODO: Prefer registers with already spilled Values? + // TODO: Modify preference using affinity graph. + // TODO: if a single value is in multiple registers, spill one of them + // before spilling a value in just a single register. + + // SP and SB are allocated specially. No regular value should + // be allocated to them. + mask &^= 1<<4 | 1<<32 + + // Find a register to spill. We spill the register containing the value + // whose next use is as far in the future as possible. + // https://en.wikipedia.org/wiki/Page_replacement_algorithm#The_theoretically_optimal_page_replacement_algorithm + var r register + maxuse := int32(-1) + for t := register(0); t < numRegs; t++ { + if mask>>t&1 == 0 { + continue + } + v := s.regs[t].v + if n := s.values[v.ID].uses.dist; n > maxuse { + // v's next use is farther in the future than any value + // we've seen so far. A new best spill candidate. + r = t + maxuse = n + } + } + if maxuse == -1 { + s.f.Unimplementedf("couldn't find register to spill") + } + s.freeReg(r) + return r +} + +// allocValToReg allocates v to a register selected from regMask and +// returns the register copy of v. Any previous user is kicked out and spilled +// (if necessary). Load code is added at the current pc. If nospill is set the +// allocated register is marked nospill so the assignment cannot be +// undone until the caller allows it by clearing nospill. Returns a +// *Value which is either v or a copy of v allocated to the chosen register. +func (s *regAllocState) allocValToReg(v *Value, mask regMask, nospill bool, line int32) *Value { + vi := &s.values[v.ID] + + // Check if v is already in a requested register. + if mask&vi.regs != 0 { + r := pickReg(mask & vi.regs) + if s.regs[r].v != v || s.regs[r].c == nil { + panic("bad register state") + } + if nospill { + s.nospill |= regMask(1) << r + } + return s.regs[r].c + } + + if v.Op != OpSP { + mask &^= 1 << 4 // dont' spill SP + } + if v.Op != OpSB { + mask &^= 1 << 32 // don't spill SB + } + mask &^= s.reserved() + + // Allocate a register. + r := s.allocReg(v, mask) + + // Allocate v to the new register. + var c *Value + if vi.regs != 0 { + // Copy from a register that v is already in. + r2 := pickReg(vi.regs) + if s.regs[r2].v != v { + panic("bad register state") + } + c = s.curBlock.NewValue1(line, OpCopy, v.Type, s.regs[r2].c) + } else if v.rematerializeable() { + // Rematerialize instead of loading from the spill location. + c = v.copyInto(s.curBlock) + } else { + switch { + // Load v from its spill location. + case vi.spill != nil: + if logSpills { + fmt.Println("regalloc: load spill") + } + c = s.curBlock.NewValue1(line, OpLoadReg, v.Type, vi.spill) + vi.spillUsed = true + default: + s.f.Fatalf("attempt to load unspilled value %v", v.LongString()) + } + } + s.setOrig(c, v) + s.assignReg(r, v, c) + if nospill { + s.nospill |= regMask(1) << r + } + return c +} + +func (s *regAllocState) init(f *Func) { + if numRegs > noRegister || numRegs > register(unsafe.Sizeof(regMask(0))*8) { + panic("too many registers") + } + + s.f = f + s.regs = make([]regState, numRegs) + s.values = make([]valState, f.NumValues()) + s.orig = make([]*Value, f.NumValues()) + for _, b := range f.Blocks { + for _, v := range b.Values { + if !v.Type.IsMemory() && !v.Type.IsVoid() && !v.Type.IsFlags() { + s.values[v.ID].needReg = true + s.values[v.ID].rematerializeable = v.rematerializeable() + s.values[v.ID].desired = noRegister + s.orig[v.ID] = v + } + } + } + s.computeLive() + + // Compute block order. This array allows us to distinguish forward edges + // from backward edges and compute how far they go. + blockOrder := make([]int32, f.NumBlocks()) + for i, b := range f.Blocks { + blockOrder[b.ID] = int32(i) + } + + // Compute primary predecessors. + s.primary = make([]int32, f.NumBlocks()) + for _, b := range f.Blocks { + best := -1 + for i, p := range b.Preds { + if blockOrder[p.ID] >= blockOrder[b.ID] { + continue // backward edge + } + if best == -1 || blockOrder[p.ID] > blockOrder[b.Preds[best].ID] { + best = i + } + } + s.primary[b.ID] = int32(best) + } + + s.endRegs = make([][]endReg, f.NumBlocks()) + s.startRegs = make([][]startReg, f.NumBlocks()) + s.spillLive = make([][]ID, f.NumBlocks()) +} + +// Adds a use record for id at distance dist from the start of the block. +// All calls to addUse must happen with nonincreasing dist. +func (s *regAllocState) addUse(id ID, dist int32) { + r := s.freeUseRecords + if r != nil { + s.freeUseRecords = r.next + } else { + r = &use{} + } + r.dist = dist + r.next = s.values[id].uses + s.values[id].uses = r + if r.next != nil && dist > r.next.dist { + s.f.Fatalf("uses added in wrong order") + } +} + +// advanceUses advances the uses of v's args from the state before v to the state after v. +// Any values which have no more uses are deallocated from registers. +func (s *regAllocState) advanceUses(v *Value) { + for _, a := range v.Args { + if !s.values[a.ID].needReg { + continue + } + ai := &s.values[a.ID] + r := ai.uses + ai.uses = r.next + if r.next == nil { + // Value is dead, free all registers that hold it. + s.freeRegs(ai.regs) + } + r.next = s.freeUseRecords + s.freeUseRecords = r + } +} + +// Sets the state of the registers to that encoded in regs. +func (s *regAllocState) setState(regs []endReg) { + s.freeRegs(s.used) + for _, x := range regs { + s.assignReg(x.r, x.v, x.c) + } +} + +// compatRegs returns the set of registers which can store a type t. +func (s *regAllocState) compatRegs(t Type) regMask { + var m regMask + if t.IsFloat() { + m = 0xffff << 16 // X0-X15 + } else { + m = 0xffef << 0 // AX-R15, except SP + } + return m &^ s.reserved() +} + +func (s *regAllocState) regalloc(f *Func) { + liveSet := f.newSparseSet(f.NumValues()) + defer f.retSparseSet(liveSet) + var oldSched []*Value + var phis []*Value + var phiRegs []register + var args []*Value + + if f.Entry != f.Blocks[0] { + f.Fatalf("entry block must be first") + } + + for _, b := range f.Blocks { + s.curBlock = b + + // Initialize liveSet and uses fields for this block. + // Walk backwards through the block doing liveness analysis. + liveSet.clear() + for _, e := range s.live[b.ID] { + s.addUse(e.ID, int32(len(b.Values))+e.dist) // pseudo-uses from beyond end of block + liveSet.add(e.ID) + } + if v := b.Control; v != nil && s.values[v.ID].needReg { + s.addUse(v.ID, int32(len(b.Values))) // psuedo-use by control value + liveSet.add(v.ID) + } + for i := len(b.Values) - 1; i >= 0; i-- { + v := b.Values[i] + liveSet.remove(v.ID) + if v.Op == OpPhi { + // Remove v from the live set, but don't add + // any inputs. This is the state the len(b.Preds)>1 + // case below desires; it wants to process phis specially. + continue + } + for _, a := range v.Args { + if !s.values[a.ID].needReg { + continue + } + s.addUse(a.ID, int32(i)) + liveSet.add(a.ID) + } + } + if regDebug { + fmt.Printf("uses for %s:%s\n", s.f.Name, b) + for i := range s.values { + vi := &s.values[i] + u := vi.uses + if u == nil { + continue + } + fmt.Printf(" v%d:", i) + for u != nil { + fmt.Printf(" %d", u.dist) + u = u.next + } + fmt.Println() + } + } + + // Make a copy of the block schedule so we can generate a new one in place. + // We make a separate copy for phis and regular values. + nphi := 0 + for _, v := range b.Values { + if v.Op != OpPhi { + break + } + nphi++ + } + phis = append(phis[:0], b.Values[:nphi]...) + oldSched = append(oldSched[:0], b.Values[nphi:]...) + b.Values = b.Values[:0] + + // Initialize start state of block. + if b == f.Entry { + // Regalloc state is empty to start. + if nphi > 0 { + f.Fatalf("phis in entry block") + } + } else if len(b.Preds) == 1 { + // Start regalloc state with the end state of the previous block. + s.setState(s.endRegs[b.Preds[0].ID]) + if nphi > 0 { + f.Fatalf("phis in single-predecessor block") + } + // Drop any values which are no longer live. + // This may happen because at the end of p, a value may be + // live but only used by some other successor of p. + for r := register(0); r < numRegs; r++ { + v := s.regs[r].v + if v != nil && !liveSet.contains(v.ID) { + s.freeReg(r) + } + } + } else { + // This is the complicated case. We have more than one predecessor, + // which means we may have Phi ops. + + // Copy phi ops into new schedule. + b.Values = append(b.Values, phis...) + + // Start with the final register state of the primary predecessor + idx := s.primary[b.ID] + if idx < 0 { + f.Fatalf("block with no primary predecessor %s", b) + } + p := b.Preds[idx] + s.setState(s.endRegs[p.ID]) + + if regDebug { + fmt.Printf("starting merge block %s with end state of %s:\n", b, p) + for _, x := range s.endRegs[p.ID] { + fmt.Printf(" %s: orig:%s cache:%s\n", registers[x.r].Name(), x.v, x.c) + } + } + + // Decide on registers for phi ops. Use the registers determined + // by the primary predecessor if we can. + // TODO: pick best of (already processed) predecessors? + // Majority vote? Deepest nesting level? + phiRegs = phiRegs[:0] + var phiUsed regMask + for _, v := range phis { + if !s.values[v.ID].needReg { + phiRegs = append(phiRegs, noRegister) + continue + } + a := v.Args[idx] + m := s.values[a.ID].regs &^ phiUsed + var r register + if m != 0 { + r = pickReg(m) + s.freeReg(r) + phiUsed |= regMask(1) << r + phiRegs = append(phiRegs, r) + } else { + phiRegs = append(phiRegs, noRegister) + } + } + + // Second pass - deallocate any phi inputs which are now dead. + for _, v := range phis { + if !s.values[v.ID].needReg { + continue + } + a := v.Args[idx] + if !liveSet.contains(a.ID) { + // Input is dead beyond the phi, deallocate + // anywhere else it might live. + s.freeRegs(s.values[a.ID].regs) + } + } + + // Third pass - pick registers for phis whose inputs + // were not in a register. + for i, v := range phis { + if !s.values[v.ID].needReg { + continue + } + if phiRegs[i] != noRegister { + continue + } + m := s.compatRegs(v.Type) &^ phiUsed &^ s.used + if m != 0 { + r := pickReg(m) + phiRegs[i] = r + phiUsed |= regMask(1) << r + } + } + + // Set registers for phis. Add phi spill code. + for i, v := range phis { + if !s.values[v.ID].needReg { + continue + } + r := phiRegs[i] + if r == noRegister { + // stack-based phi + // Spills will be inserted in all the predecessors below. + s.values[v.ID].spill = v // v starts life spilled + s.values[v.ID].spillUsed = true // use is guaranteed + continue + } + // register-based phi + s.assignReg(r, v, v) + // Spill the phi in case we need to restore it later. + spill := b.NewValue1(v.Line, OpStoreReg, v.Type, v) + s.setOrig(spill, v) + s.values[v.ID].spill = spill + s.values[v.ID].spillUsed = false + } + + // Save the starting state for use by merge edges. + var regList []startReg + for r := register(0); r < numRegs; r++ { + v := s.regs[r].v + if v == nil { + continue + } + if phiUsed>>r&1 != 0 { + // Skip registers that phis used, we'll handle those + // specially during merge edge processing. + continue + } + regList = append(regList, startReg{r, v.ID}) + } + s.startRegs[b.ID] = regList + + if regDebug { + fmt.Printf("after phis\n") + for _, x := range s.startRegs[b.ID] { + fmt.Printf(" %s: v%d\n", registers[x.r].Name(), x.vid) + } + } + } + + // Compute preferred registers for each value using a backwards pass. + // Note that we do this phase after startRegs is set above, so that + // we get the right behavior for a block which branches to itself. + for _, succ := range b.Succs { + // TODO: prioritize likely successor. + for _, x := range s.startRegs[succ.ID] { + v := s.orig[x.vid] + s.values[v.ID].desired = x.r + } + // Process phi ops in succ + i := -1 + for j, p := range succ.Preds { + if p == b { + i = j + break + } + } + if i == -1 { + s.f.Fatalf("can't find predecssor %s of %s\n", b, succ) + } + for _, v := range succ.Values { + if v.Op != OpPhi { + break + } + if !s.values[v.ID].needReg { + continue + } + r, ok := s.f.getHome(v.ID).(*Register) + if !ok { + continue + } + a := s.orig[v.Args[i].ID] + s.values[a.ID].desired = register(r.Num) + } + } + + // Set avoid fields to help desired register availability. + liveSet.clear() + for _, e := range s.live[b.ID] { + liveSet.add(e.ID) + } + if v := b.Control; v != nil && s.values[v.ID].needReg { + liveSet.add(v.ID) + } + for i := len(oldSched) - 1; i >= 0; i-- { + v := oldSched[i] + liveSet.remove(v.ID) + + r := s.values[v.ID].desired + if r != noRegister { + m := regMask(1) << r + // All live values should avoid this register so + // it will be available at this point. + for _, w := range liveSet.contents() { + s.values[w].avoid |= m + } + } + + for _, a := range v.Args { + if !s.values[a.ID].needReg { + continue + } + liveSet.add(a.ID) + } + } + + // Process all the non-phi values. + for _, v := range oldSched { + if regDebug { + fmt.Printf(" processing %s\n", v.LongString()) + } + if v.Op == OpPhi { + f.Fatalf("phi %s not at start of block", v) + } + if v.Op == OpSP { + s.assignReg(4, v, v) // TODO: arch-dependent + b.Values = append(b.Values, v) + s.advanceUses(v) + continue + } + if v.Op == OpSB { + s.assignReg(32, v, v) // TODO: arch-dependent + b.Values = append(b.Values, v) + s.advanceUses(v) + continue + } + if v.Op == OpArg { + // Args are "pre-spilled" values. We don't allocate + // any register here. We just set up the spill pointer to + // point at itself and any later user will restore it to use it. + s.values[v.ID].spill = v + s.values[v.ID].spillUsed = true // use is guaranteed + b.Values = append(b.Values, v) + s.advanceUses(v) + continue + } + regspec := opcodeTable[v.Op].reg + if len(regspec.inputs) == 0 && len(regspec.outputs) == 0 { + // No register allocation required (or none specified yet) + s.freeRegs(regspec.clobbers) + b.Values = append(b.Values, v) + continue + } + + if s.values[v.ID].rematerializeable { + // Value is rematerializeable, don't issue it here. + // It will get issued just before each use (see + // allocValueToReg). + s.advanceUses(v) + continue + } + + // Move arguments to registers. Process in an ordering defined + // by the register specification (most constrained first). + args = append(args[:0], v.Args...) + for _, i := range regspec.inputs { + if i.regs == flagRegMask { + // TODO: remove flag input from regspec.inputs. + continue + } + args[i.idx] = s.allocValToReg(v.Args[i.idx], i.regs, true, v.Line) + } + + // Now that all args are in regs, we're ready to issue the value itself. + // Before we pick a register for the output value, allow input registers + // to be deallocated. We do this here so that the output can use the + // same register as a dying input. + s.nospill = 0 + s.advanceUses(v) // frees any registers holding args that are no longer live + + // Dump any registers which will be clobbered + s.freeRegs(regspec.clobbers) + + // Pick register for output. + var mask regMask + if s.values[v.ID].needReg { + mask = regspec.outputs[0] &^ s.reserved() + if mask>>33&1 != 0 { + s.f.Fatalf("bad mask %s\n", v.LongString()) + } + } + if mask != 0 { + r := s.allocReg(v, mask) + s.assignReg(r, v, v) + } + + // Issue the Value itself. + for i, a := range args { + v.Args[i] = a // use register version of arguments + } + b.Values = append(b.Values, v) + + // Issue a spill for this value. We issue spills unconditionally, + // then at the end of regalloc delete the ones we never use. + // TODO: schedule the spill at a point that dominates all restores. + // The restore may be off in an unlikely branch somewhere and it + // would be better to have the spill in that unlikely branch as well. + // v := ... + // if unlikely { + // f() + // } + // It would be good to have both spill and restore inside the IF. + if s.values[v.ID].needReg { + spill := b.NewValue1(v.Line, OpStoreReg, v.Type, v) + s.setOrig(spill, v) + s.values[v.ID].spill = spill + s.values[v.ID].spillUsed = false + } + } + + if v := b.Control; v != nil && s.values[v.ID].needReg { + if regDebug { + fmt.Printf(" processing control %s\n", v.LongString()) + } + // Load control value into reg. + // TODO: regspec for block control values, instead of using + // register set from the control op's output. + s.allocValToReg(v, opcodeTable[v.Op].reg.outputs[0], false, b.Line) + // Remove this use from the uses list. + vi := &s.values[v.ID] + u := vi.uses + vi.uses = u.next + if u.next == nil { + s.freeRegs(vi.regs) // value is dead + } + u.next = s.freeUseRecords + s.freeUseRecords = u + } + + // Save end-of-block register state. + // First count how many, this cuts allocations in half. + k := 0 + for r := register(0); r < numRegs; r++ { + v := s.regs[r].v + if v == nil { + continue + } + k++ + } + regList := make([]endReg, 0, k) + for r := register(0); r < numRegs; r++ { + v := s.regs[r].v + if v == nil { + continue + } + regList = append(regList, endReg{r, v, s.regs[r].c}) + } + s.endRegs[b.ID] = regList + + // Check. TODO: remove + { + liveSet.clear() + for _, x := range s.live[b.ID] { + liveSet.add(x.ID) + } + for r := register(0); r < numRegs; r++ { + v := s.regs[r].v + if v == nil { + continue + } + if !liveSet.contains(v.ID) { + s.f.Fatalf("val %s is in reg but not live at end of %s", v, b) + } + } + } + + // If a value is live at the end of the block and + // isn't in a register, remember that its spill location + // is live. We need to remember this information so that + // the liveness analysis in stackalloc is correct. + for _, e := range s.live[b.ID] { + if s.values[e.ID].regs != 0 { + // in a register, we'll use that source for the merge. + continue + } + spill := s.values[e.ID].spill + if spill == nil { + // rematerializeable values will have spill==nil. + continue + } + s.spillLive[b.ID] = append(s.spillLive[b.ID], spill.ID) + s.values[e.ID].spillUsed = true + } + + // Clear any final uses. + // All that is left should be the pseudo-uses added for values which + // are live at the end of b. + for _, e := range s.live[b.ID] { + u := s.values[e.ID].uses + if u == nil { + f.Fatalf("live at end, no uses v%d", e.ID) + } + if u.next != nil { + f.Fatalf("live at end, too many uses v%d", e.ID) + } + s.values[e.ID].uses = nil + u.next = s.freeUseRecords + s.freeUseRecords = u + } + } + + // Erase any spills we never used + for i := range s.values { + vi := s.values[i] + if vi.spillUsed { + if logSpills { + fmt.Println("regalloc: spilled value") + } + continue + } + spill := vi.spill + if spill == nil { + // Constants, SP, SB, ... + continue + } + f.freeValue(spill) + } + for _, b := range f.Blocks { + i := 0 + for _, v := range b.Values { + if v.Op == OpInvalid { + continue + } + b.Values[i] = v + i++ + } + b.Values = b.Values[:i] + // TODO: zero b.Values[i:], recycle Values + // Not important now because this is the last phase that manipulates Values + } + + // Anything that didn't get a register gets a stack location here. + // (StoreReg, stack-based phis, inputs, ...) + stacklive := stackalloc(s.f, s.spillLive) + + // Fix up all merge edges. + s.shuffle(stacklive) +} + +// shuffle fixes up all the merge edges (those going into blocks of indegree > 1). +func (s *regAllocState) shuffle(stacklive [][]ID) { + var e edgeState + e.s = s + e.cache = map[ID][]*Value{} + e.contents = map[Location]contentRecord{} + if regDebug { + fmt.Printf("shuffle %s\n", s.f.Name) + fmt.Println(s.f.String()) + } + + for _, b := range s.f.Blocks { + if len(b.Preds) <= 1 { + continue + } + e.b = b + for i, p := range b.Preds { + e.p = p + e.setup(i, s.endRegs[p.ID], s.startRegs[b.ID], stacklive[p.ID]) + e.process() + } + } +} + +type edgeState struct { + s *regAllocState + p, b *Block // edge goes from p->b. + + // for each pre-regalloc value, a list of equivalent cached values + cache map[ID][]*Value + + // map from location to the value it contains + contents map[Location]contentRecord + + // desired destination locations + destinations []dstRecord + extra []dstRecord + + usedRegs regMask // registers currently holding something + uniqueRegs regMask // registers holding the only copy of a value + finalRegs regMask // registers holding final target +} + +type contentRecord struct { + vid ID // pre-regalloc value + c *Value // cached value + final bool // this is a satisfied destination +} + +type dstRecord struct { + loc Location // register or stack slot + vid ID // pre-regalloc value it should contain + splice **Value // place to store reference to the generating instruction +} + +// setup initializes the edge state for shuffling. +func (e *edgeState) setup(idx int, srcReg []endReg, dstReg []startReg, stacklive []ID) { + if regDebug { + fmt.Printf("edge %s->%s\n", e.p, e.b) + } + + // Clear state. + for k := range e.cache { + delete(e.cache, k) + } + for k := range e.contents { + delete(e.contents, k) + } + e.usedRegs = 0 + e.uniqueRegs = 0 + e.finalRegs = 0 + + // Live registers can be sources. + for _, x := range srcReg { + e.set(®isters[x.r], x.v.ID, x.c, false) + } + // So can all of the spill locations. + for _, spillID := range stacklive { + v := e.s.orig[spillID] + spill := e.s.values[v.ID].spill + e.set(e.s.f.getHome(spillID), v.ID, spill, false) + } + + // Figure out all the destinations we need. + dsts := e.destinations[:0] + for _, x := range dstReg { + dsts = append(dsts, dstRecord{®isters[x.r], x.vid, nil}) + } + // Phis need their args to end up in a specific location. + for _, v := range e.b.Values { + if v.Op != OpPhi { + break + } + loc := e.s.f.getHome(v.ID) + if loc == nil { + continue + } + dsts = append(dsts, dstRecord{loc, v.Args[idx].ID, &v.Args[idx]}) + } + e.destinations = dsts + + if regDebug { + for vid, a := range e.cache { + for _, c := range a { + fmt.Printf("src %s: v%d cache=%s\n", e.s.f.getHome(c.ID).Name(), vid, c) + } + } + for _, d := range e.destinations { + fmt.Printf("dst %s: v%d\n", d.loc.Name(), d.vid) + } + } +} + +// process generates code to move all the values to the right destination locations. +func (e *edgeState) process() { + dsts := e.destinations + + // Process the destinations until they are all satisfied. + for len(dsts) > 0 { + i := 0 + for _, d := range dsts { + if !e.processDest(d.loc, d.vid, d.splice) { + // Failed - save for next iteration. + dsts[i] = d + i++ + } + } + if i < len(dsts) { + // Made some progress. Go around again. + dsts = dsts[:i] + + // Append any extras destinations we generated. + dsts = append(dsts, e.extra...) + e.extra = e.extra[:0] + continue + } + + // We made no progress. That means that any + // remaining unsatisfied moves are in simple cycles. + // For example, A -> B -> C -> D -> A. + // A ----> B + // ^ | + // | | + // | v + // D <---- C + + // To break the cycle, we pick an unused register, say R, + // and put a copy of B there. + // A ----> B + // ^ | + // | | + // | v + // D <---- C <---- R=copyofB + // When we resume the outer loop, the A->B move can now proceed, + // and eventually the whole cycle completes. + + // Copy any cycle location to a temp register. This duplicates + // one of the cycle entries, allowing the just duplicated value + // to be overwritten and the cycle to proceed. + loc := dsts[0].loc + vid := e.contents[loc].vid + c := e.contents[loc].c + r := e.findRegFor(c.Type) + if regDebug { + fmt.Printf("breaking cycle with v%d in %s:%s\n", vid, loc.Name(), c) + } + if _, isReg := loc.(*Register); isReg { + c = e.p.NewValue1(c.Line, OpCopy, c.Type, c) + } else { + c = e.p.NewValue1(c.Line, OpLoadReg, c.Type, c) + } + e.set(r, vid, c, false) + } +} + +// processDest generates code to put value vid into location loc. Returns true +// if progress was made. +func (e *edgeState) processDest(loc Location, vid ID, splice **Value) bool { + occupant := e.contents[loc] + if occupant.vid == vid { + // Value is already in the correct place. + e.contents[loc] = contentRecord{vid, occupant.c, true} + if splice != nil { + *splice = occupant.c + } + // Note: if splice==nil then c will appear dead. This is + // non-SSA formed code, so be careful after this pass not to run + // deadcode elimination. + return true + } + + // Check if we're allowed to clobber the destination location. + if len(e.cache[occupant.vid]) == 1 && !e.s.values[occupant.vid].rematerializeable { + // We can't overwrite the last copy + // of a value that needs to survive. + return false + } + + // Copy from a source of v, register preferred. + v := e.s.orig[vid] + var c *Value + var src Location + if regDebug { + fmt.Printf("moving v%d to %s\n", vid, loc.Name()) + fmt.Printf("sources of v%d:", vid) + } + for _, w := range e.cache[vid] { + h := e.s.f.getHome(w.ID) + if regDebug { + fmt.Printf(" %s:%s", h.Name(), w) + } + _, isreg := h.(*Register) + if src == nil || isreg { + c = w + src = h + } + } + if regDebug { + if src != nil { + fmt.Printf(" [use %s]\n", src.Name()) + } else { + fmt.Printf(" [no source]\n") + } + } + _, dstReg := loc.(*Register) + var x *Value + if c == nil { + if !e.s.values[vid].rematerializeable { + e.s.f.Fatalf("can't find source for %s->%s: v%d\n", e.p, e.b, vid) + } + if dstReg { + x = v.copyInto(e.p) + } else { + // Rematerialize into stack slot. Need a free + // register to accomplish this. + e.erase(loc) // see pre-clobber comment below + r := e.findRegFor(v.Type) + x = v.copyInto(e.p) + e.set(r, vid, x, false) + // Make sure we spill with the size of the slot, not the + // size of x (which might be wider due to our dropping + // of narrowing conversions). + x = e.p.NewValue1(x.Line, OpStoreReg, loc.(LocalSlot).Type, x) + } + } else { + // Emit move from src to dst. + _, srcReg := src.(*Register) + if srcReg { + if dstReg { + x = e.p.NewValue1(c.Line, OpCopy, c.Type, c) + } else { + x = e.p.NewValue1(c.Line, OpStoreReg, loc.(LocalSlot).Type, c) + } + } else { + if dstReg { + x = e.p.NewValue1(c.Line, OpLoadReg, c.Type, c) + } else { + // mem->mem. Use temp register. + + // Pre-clobber destination. This avoids the + // following situation: + // - v is currently held in R0 and stacktmp0. + // - We want to copy stacktmp1 to stacktmp0. + // - We choose R0 as the temporary register. + // During the copy, both R0 and stacktmp0 are + // clobbered, losing both copies of v. Oops! + // Erasing the destination early means R0 will not + // be chosen as the temp register, as it will then + // be the last copy of v. + e.erase(loc) + + r := e.findRegFor(c.Type) + t := e.p.NewValue1(c.Line, OpLoadReg, c.Type, c) + e.set(r, vid, t, false) + x = e.p.NewValue1(c.Line, OpStoreReg, loc.(LocalSlot).Type, t) + } + } + } + e.set(loc, vid, x, true) + if splice != nil { + *splice = x + } + return true +} + +// set changes the contents of location loc to hold the given value and its cached representative. +func (e *edgeState) set(loc Location, vid ID, c *Value, final bool) { + e.s.f.setHome(c, loc) + e.erase(loc) + e.contents[loc] = contentRecord{vid, c, final} + a := e.cache[vid] + a = append(a, c) + e.cache[vid] = a + if r, ok := loc.(*Register); ok { + e.usedRegs |= regMask(1) << uint(r.Num) + if final { + e.finalRegs |= regMask(1) << uint(r.Num) + } + if len(a) == 1 { + e.uniqueRegs |= regMask(1) << uint(r.Num) + } + if len(a) == 2 { + if t, ok := e.s.f.getHome(a[0].ID).(*Register); ok { + e.uniqueRegs &^= regMask(1) << uint(t.Num) + } + } + } + if regDebug { + fmt.Printf("%s\n", c.LongString()) + fmt.Printf("v%d now available in %s:%s\n", vid, loc.Name(), c) + } +} + +// erase removes any user of loc. +func (e *edgeState) erase(loc Location) { + cr := e.contents[loc] + if cr.c == nil { + return + } + vid := cr.vid + + if cr.final { + // Add a destination to move this value back into place. + // Make sure it gets added to the tail of the destination queue + // so we make progress on other moves first. + e.extra = append(e.extra, dstRecord{loc, cr.vid, nil}) + } + + // Remove c from the list of cached values. + a := e.cache[vid] + for i, c := range a { + if e.s.f.getHome(c.ID) == loc { + if regDebug { + fmt.Printf("v%d no longer available in %s:%s\n", vid, loc.Name(), c) + } + a[i], a = a[len(a)-1], a[:len(a)-1] + break + } + } + e.cache[vid] = a + + // Update register masks. + if r, ok := loc.(*Register); ok { + e.usedRegs &^= regMask(1) << uint(r.Num) + if cr.final { + e.finalRegs &^= regMask(1) << uint(r.Num) + } + } + if len(a) == 1 { + if r, ok := e.s.f.getHome(a[0].ID).(*Register); ok { + e.uniqueRegs |= regMask(1) << uint(r.Num) + } + } +} + +// findRegFor finds a register we can use to make a temp copy of type typ. +func (e *edgeState) findRegFor(typ Type) Location { + // Which registers are possibilities. + var m regMask + if typ.IsFloat() { + m = e.s.compatRegs(e.s.f.Config.fe.TypeFloat64()) + } else { + m = e.s.compatRegs(e.s.f.Config.fe.TypeInt64()) + } + + // Pick a register. In priority order: + // 1) an unused register + // 2) a non-unique register not holding a final value + // 3) a non-unique register + x := m &^ e.usedRegs + if x != 0 { + return ®isters[pickReg(x)] + } + x = m &^ e.uniqueRegs &^ e.finalRegs + if x != 0 { + return ®isters[pickReg(x)] + } + x = m &^ e.uniqueRegs + if x != 0 { + return ®isters[pickReg(x)] + } + + // No register is available. Allocate a temp location to spill a register to. + // The type of the slot is immaterial - it will not be live across + // any safepoint. Just use a type big enough to hold any register. + typ = e.s.f.Config.fe.TypeInt64() + t := LocalSlot{e.s.f.Config.fe.Auto(typ), typ, 0} + // TODO: reuse these slots. + + // Pick a register to spill. + for vid, a := range e.cache { + for _, c := range a { + if r, ok := e.s.f.getHome(c.ID).(*Register); ok && m>>uint(r.Num)&1 != 0 { + x := e.p.NewValue1(c.Line, OpStoreReg, c.Type, c) + e.set(t, vid, x, false) + if regDebug { + fmt.Printf(" SPILL %s->%s %s\n", r.Name(), t.Name(), x.LongString()) + } + // r will now be overwritten by the caller. At some point + // later, the newly saved value will be moved back to its + // final destination in processDest. + return r + } + } + } + + fmt.Printf("m:%d unique:%d final:%d\n", m, e.uniqueRegs, e.finalRegs) + for vid, a := range e.cache { + for _, c := range a { + fmt.Printf("v%d: %s %s\n", vid, c, e.s.f.getHome(c.ID).Name()) + } + } + e.s.f.Fatalf("can't find empty register on edge %s->%s", e.p, e.b) + return nil +} + +func (v *Value) rematerializeable() bool { + if !opcodeTable[v.Op].rematerializeable { + return false + } + for _, a := range v.Args { + // SP and SB (generated by OpSP and OpSB) are always available. + if a.Op != OpSP && a.Op != OpSB { + return false + } + } + return true +} + +type liveInfo struct { + ID ID // ID of variable + dist int32 // # of instructions before next use +} + +// computeLive computes a map from block ID to a list of value IDs live at the end +// of that block. Together with the value ID is a count of how many instructions +// to the next use of that value. The resulting map is stored at s.live. +// TODO: this could be quadratic if lots of variables are live across lots of +// basic blocks. Figure out a way to make this function (or, more precisely, the user +// of this function) require only linear size & time. +func (s *regAllocState) computeLive() { + f := s.f + s.live = make([][]liveInfo, f.NumBlocks()) + var phis []*Value + + live := newSparseMap(f.NumValues()) + t := newSparseMap(f.NumValues()) + + // Instead of iterating over f.Blocks, iterate over their postordering. + // Liveness information flows backward, so starting at the end + // increases the probability that we will stabilize quickly. + // TODO: Do a better job yet. Here's one possibility: + // Calculate the dominator tree and locate all strongly connected components. + // If a value is live in one block of an SCC, it is live in all. + // Walk the dominator tree from end to beginning, just once, treating SCC + // components as single blocks, duplicated calculated liveness information + // out to all of them. + po := postorder(f) + for { + changed := false + + for _, b := range po { + // Start with known live values at the end of the block. + // Add len(b.Values) to adjust from end-of-block distance + // to beginning-of-block distance. + live.clear() + for _, e := range s.live[b.ID] { + live.set(e.ID, e.dist+int32(len(b.Values))) + } + + // Mark control value as live + if b.Control != nil && s.values[b.Control.ID].needReg { + live.set(b.Control.ID, int32(len(b.Values))) + } + + // Propagate backwards to the start of the block + // Assumes Values have been scheduled. + phis := phis[:0] + for i := len(b.Values) - 1; i >= 0; i-- { + v := b.Values[i] + live.remove(v.ID) + if v.Op == OpPhi { + // save phi ops for later + phis = append(phis, v) + continue + } + for _, a := range v.Args { + if s.values[a.ID].needReg { + live.set(a.ID, int32(i)) + } + } + } + + // For each predecessor of b, expand its list of live-at-end values. + // invariant: live contains the values live at the start of b (excluding phi inputs) + for i, p := range b.Preds { + // Compute additional distance for the edge. + const normalEdge = 10 + const likelyEdge = 1 + const unlikelyEdge = 100 + // Note: delta must be at least 1 to distinguish the control + // value use from the first user in a successor block. + delta := int32(normalEdge) + if len(p.Succs) == 2 { + if p.Succs[0] == b && p.Likely == BranchLikely || + p.Succs[1] == b && p.Likely == BranchUnlikely { + delta = likelyEdge + } + if p.Succs[0] == b && p.Likely == BranchUnlikely || + p.Succs[1] == b && p.Likely == BranchLikely { + delta = unlikelyEdge + } + } + + // Start t off with the previously known live values at the end of p. + t.clear() + for _, e := range s.live[p.ID] { + t.set(e.ID, e.dist) + } + update := false + + // Add new live values from scanning this block. + for _, e := range live.contents() { + d := e.val + delta + if !t.contains(e.key) || d < t.get(e.key) { + update = true + t.set(e.key, d) + } + } + // Also add the correct arg from the saved phi values. + // All phis are at distance delta (we consider them + // simultaneously happening at the start of the block). + for _, v := range phis { + id := v.Args[i].ID + if s.values[id].needReg && !t.contains(id) || delta < t.get(id) { + update = true + t.set(id, delta) + } + } + + if !update { + continue + } + // The live set has changed, update it. + l := s.live[p.ID][:0] + if cap(l) < t.size() { + l = make([]liveInfo, 0, t.size()) + } + for _, e := range t.contents() { + l = append(l, liveInfo{e.key, e.val}) + } + s.live[p.ID] = l + changed = true + } + } + + if !changed { + break + } + } + if regDebug { + fmt.Println("live values at end of each block") + for _, b := range f.Blocks { + fmt.Printf(" %s:", b) + for _, x := range s.live[b.ID] { + fmt.Printf(" v%d", x.ID) + } + fmt.Println() + } + } +} + +// reserved returns a mask of reserved registers. +func (s *regAllocState) reserved() regMask { + var m regMask + if obj.Framepointer_enabled != 0 { + m |= 1 << 5 // BP + } + if s.f.Config.ctxt.Flag_dynlink { + m |= 1 << 15 // R15 + } + return m +} diff --git a/src/cmd/compile/internal/ssa/regalloc_test.go b/src/cmd/compile/internal/ssa/regalloc_test.go new file mode 100644 index 0000000000..6f3f690f1e --- /dev/null +++ b/src/cmd/compile/internal/ssa/regalloc_test.go @@ -0,0 +1,33 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import "testing" + +func TestLiveControlOps(t *testing.T) { + c := testConfig(t) + f := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("x", OpAMD64MOVBconst, TypeInt8, 1, nil), + Valu("y", OpAMD64MOVBconst, TypeInt8, 2, nil), + Valu("a", OpAMD64TESTB, TypeFlags, 0, nil, "x", "y"), + Valu("b", OpAMD64TESTB, TypeFlags, 0, nil, "y", "x"), + Eq("a", "if", "exit"), + ), + Bloc("if", + Eq("b", "plain", "exit"), + ), + Bloc("plain", + Goto("exit"), + ), + Bloc("exit", + Exit("mem"), + ), + ) + flagalloc(f.f) + regalloc(f.f) + checkFunc(f.f) +} diff --git a/src/cmd/compile/internal/ssa/rewrite.go b/src/cmd/compile/internal/ssa/rewrite.go new file mode 100644 index 0000000000..60509d214e --- /dev/null +++ b/src/cmd/compile/internal/ssa/rewrite.go @@ -0,0 +1,261 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import ( + "fmt" + "math" +) + +func applyRewrite(f *Func, rb func(*Block) bool, rv func(*Value, *Config) bool) { + // repeat rewrites until we find no more rewrites + var curb *Block + var curv *Value + defer func() { + if curb != nil { + curb.Fatalf("panic during rewrite of block %s\n", curb.LongString()) + } + if curv != nil { + curv.Fatalf("panic during rewrite of value %s\n", curv.LongString()) + // TODO(khr): print source location also + } + }() + config := f.Config + for { + change := false + for _, b := range f.Blocks { + if b.Kind == BlockDead { + continue + } + if b.Control != nil && b.Control.Op == OpCopy { + for b.Control.Op == OpCopy { + b.Control = b.Control.Args[0] + } + } + curb = b + if rb(b) { + change = true + } + curb = nil + for _, v := range b.Values { + copyelimValue(v) + change = phielimValue(v) || change + + // apply rewrite function + curv = v + if rv(v, config) { + change = true + } + curv = nil + } + } + if !change { + return + } + } +} + +// Common functions called from rewriting rules + +func is64BitFloat(t Type) bool { + return t.Size() == 8 && t.IsFloat() +} + +func is32BitFloat(t Type) bool { + return t.Size() == 4 && t.IsFloat() +} + +func is64BitInt(t Type) bool { + return t.Size() == 8 && t.IsInteger() +} + +func is32BitInt(t Type) bool { + return t.Size() == 4 && t.IsInteger() +} + +func is16BitInt(t Type) bool { + return t.Size() == 2 && t.IsInteger() +} + +func is8BitInt(t Type) bool { + return t.Size() == 1 && t.IsInteger() +} + +func isPtr(t Type) bool { + return t.IsPtr() +} + +func isSigned(t Type) bool { + return t.IsSigned() +} + +func typeSize(t Type) int64 { + return t.Size() +} + +// addOff adds two int64 offsets. Fails if wraparound happens. +func addOff(x, y int64) int64 { + z := x + y + // x and y have same sign and z has a different sign => overflow + if x^y >= 0 && x^z < 0 { + panic(fmt.Sprintf("offset overflow %d %d", x, y)) + } + return z +} + +// mergeSym merges two symbolic offsets. There is no real merging of +// offsets, we just pick the non-nil one. +func mergeSym(x, y interface{}) interface{} { + if x == nil { + return y + } + if y == nil { + return x + } + panic(fmt.Sprintf("mergeSym with two non-nil syms %s %s", x, y)) + return nil +} +func canMergeSym(x, y interface{}) bool { + return x == nil || y == nil +} + +func inBounds8(idx, len int64) bool { return int8(idx) >= 0 && int8(idx) < int8(len) } +func inBounds16(idx, len int64) bool { return int16(idx) >= 0 && int16(idx) < int16(len) } +func inBounds32(idx, len int64) bool { return int32(idx) >= 0 && int32(idx) < int32(len) } +func inBounds64(idx, len int64) bool { return idx >= 0 && idx < len } +func sliceInBounds32(idx, len int64) bool { return int32(idx) >= 0 && int32(idx) <= int32(len) } +func sliceInBounds64(idx, len int64) bool { return idx >= 0 && idx <= len } + +// nlz returns the number of leading zeros. +func nlz(x int64) int64 { + // log2(0) == 1, so nlz(0) == 64 + return 63 - log2(x) +} + +// ntz returns the number of trailing zeros. +func ntz(x int64) int64 { + return 64 - nlz(^x&(x-1)) +} + +// nlo returns the number of leading ones. +func nlo(x int64) int64 { + return nlz(^x) +} + +// nto returns the number of trailing ones. +func nto(x int64) int64 { + return ntz(^x) +} + +// log2 returns logarithm in base of uint64(n), with log2(0) = -1. +func log2(n int64) (l int64) { + l = -1 + x := uint64(n) + for ; x >= 0x8000; x >>= 16 { + l += 16 + } + if x >= 0x80 { + x >>= 8 + l += 8 + } + if x >= 0x8 { + x >>= 4 + l += 4 + } + if x >= 0x2 { + x >>= 2 + l += 2 + } + if x >= 0x1 { + l++ + } + return +} + +// isPowerOfTwo reports whether n is a power of 2. +func isPowerOfTwo(n int64) bool { + return n > 0 && n&(n-1) == 0 +} + +// is32Bit reports whether n can be represented as a signed 32 bit integer. +func is32Bit(n int64) bool { + return n == int64(int32(n)) +} + +// b2i translates a boolean value to 0 or 1 for assigning to auxInt. +func b2i(b bool) int64 { + if b { + return 1 + } + return 0 +} + +// f2i is used in the rules for storing a float in AuxInt. +func f2i(f float64) int64 { + return int64(math.Float64bits(f)) +} + +// uaddOvf returns true if unsigned a+b would overflow. +func uaddOvf(a, b int64) bool { + return uint64(a)+uint64(b) < uint64(a) +} + +// isSamePtr reports whether p1 and p2 point to the same address. +func isSamePtr(p1, p2 *Value) bool { + if p1 == p2 { + return true + } + // Aux isn't used in OffPtr, and AuxInt isn't currently used in + // Addr, but this still works as the values will be null/0 + return (p1.Op == OpOffPtr || p1.Op == OpAddr) && p1.Op == p2.Op && + p1.Aux == p2.Aux && p1.AuxInt == p2.AuxInt && + p1.Args[0] == p2.Args[0] +} + +// DUFFZERO consists of repeated blocks of 4 MOVUPSs + ADD, +// See runtime/mkduff.go. +const ( + dzBlocks = 16 // number of MOV/ADD blocks + dzBlockLen = 4 // number of clears per block + dzBlockSize = 19 // size of instructions in a single block + dzMovSize = 4 // size of single MOV instruction w/ offset + dzAddSize = 4 // size of single ADD instruction + dzClearStep = 16 // number of bytes cleared by each MOV instruction + + dzTailLen = 4 // number of final STOSQ instructions + dzTailSize = 2 // size of single STOSQ instruction + + dzClearLen = dzClearStep * dzBlockLen // bytes cleared by one block + dzSize = dzBlocks * dzBlockSize +) + +func duffStart(size int64) int64 { + x, _ := duff(size) + return x +} +func duffAdj(size int64) int64 { + _, x := duff(size) + return x +} + +// duff returns the offset (from duffzero, in bytes) and pointer adjust (in bytes) +// required to use the duffzero mechanism for a block of the given size. +func duff(size int64) (int64, int64) { + if size < 32 || size > 1024 || size%dzClearStep != 0 { + panic("bad duffzero size") + } + // TODO: arch-dependent + steps := size / dzClearStep + blocks := steps / dzBlockLen + steps %= dzBlockLen + off := dzBlockSize * (dzBlocks - blocks) + var adj int64 + if steps != 0 { + off -= dzAddSize + off -= dzMovSize * steps + adj -= dzClearStep * (dzBlockLen - steps) + } + return off, adj +} diff --git a/src/cmd/compile/internal/ssa/rewriteAMD64.go b/src/cmd/compile/internal/ssa/rewriteAMD64.go new file mode 100644 index 0000000000..83fc437747 --- /dev/null +++ b/src/cmd/compile/internal/ssa/rewriteAMD64.go @@ -0,0 +1,15394 @@ +// autogenerated from gen/AMD64.rules: do not edit! +// generated with: cd gen; go run *.go + +package ssa + +import "math" + +var _ = math.MinInt8 // in case not otherwise used +func rewriteValueAMD64(v *Value, config *Config) bool { + switch v.Op { + case OpAMD64ADDB: + return rewriteValueAMD64_OpAMD64ADDB(v, config) + case OpAMD64ADDBconst: + return rewriteValueAMD64_OpAMD64ADDBconst(v, config) + case OpAMD64ADDL: + return rewriteValueAMD64_OpAMD64ADDL(v, config) + case OpAMD64ADDLconst: + return rewriteValueAMD64_OpAMD64ADDLconst(v, config) + case OpAMD64ADDQ: + return rewriteValueAMD64_OpAMD64ADDQ(v, config) + case OpAMD64ADDQconst: + return rewriteValueAMD64_OpAMD64ADDQconst(v, config) + case OpAMD64ADDW: + return rewriteValueAMD64_OpAMD64ADDW(v, config) + case OpAMD64ADDWconst: + return rewriteValueAMD64_OpAMD64ADDWconst(v, config) + case OpAMD64ANDB: + return rewriteValueAMD64_OpAMD64ANDB(v, config) + case OpAMD64ANDBconst: + return rewriteValueAMD64_OpAMD64ANDBconst(v, config) + case OpAMD64ANDL: + return rewriteValueAMD64_OpAMD64ANDL(v, config) + case OpAMD64ANDLconst: + return rewriteValueAMD64_OpAMD64ANDLconst(v, config) + case OpAMD64ANDQ: + return rewriteValueAMD64_OpAMD64ANDQ(v, config) + case OpAMD64ANDQconst: + return rewriteValueAMD64_OpAMD64ANDQconst(v, config) + case OpAMD64ANDW: + return rewriteValueAMD64_OpAMD64ANDW(v, config) + case OpAMD64ANDWconst: + return rewriteValueAMD64_OpAMD64ANDWconst(v, config) + case OpAdd16: + return rewriteValueAMD64_OpAdd16(v, config) + case OpAdd32: + return rewriteValueAMD64_OpAdd32(v, config) + case OpAdd32F: + return rewriteValueAMD64_OpAdd32F(v, config) + case OpAdd64: + return rewriteValueAMD64_OpAdd64(v, config) + case OpAdd64F: + return rewriteValueAMD64_OpAdd64F(v, config) + case OpAdd8: + return rewriteValueAMD64_OpAdd8(v, config) + case OpAddPtr: + return rewriteValueAMD64_OpAddPtr(v, config) + case OpAddr: + return rewriteValueAMD64_OpAddr(v, config) + case OpAnd16: + return rewriteValueAMD64_OpAnd16(v, config) + case OpAnd32: + return rewriteValueAMD64_OpAnd32(v, config) + case OpAnd64: + return rewriteValueAMD64_OpAnd64(v, config) + case OpAnd8: + return rewriteValueAMD64_OpAnd8(v, config) + case OpAvg64u: + return rewriteValueAMD64_OpAvg64u(v, config) + case OpAMD64CMPB: + return rewriteValueAMD64_OpAMD64CMPB(v, config) + case OpAMD64CMPBconst: + return rewriteValueAMD64_OpAMD64CMPBconst(v, config) + case OpAMD64CMPL: + return rewriteValueAMD64_OpAMD64CMPL(v, config) + case OpAMD64CMPLconst: + return rewriteValueAMD64_OpAMD64CMPLconst(v, config) + case OpAMD64CMPQ: + return rewriteValueAMD64_OpAMD64CMPQ(v, config) + case OpAMD64CMPQconst: + return rewriteValueAMD64_OpAMD64CMPQconst(v, config) + case OpAMD64CMPW: + return rewriteValueAMD64_OpAMD64CMPW(v, config) + case OpAMD64CMPWconst: + return rewriteValueAMD64_OpAMD64CMPWconst(v, config) + case OpClosureCall: + return rewriteValueAMD64_OpClosureCall(v, config) + case OpCom16: + return rewriteValueAMD64_OpCom16(v, config) + case OpCom32: + return rewriteValueAMD64_OpCom32(v, config) + case OpCom64: + return rewriteValueAMD64_OpCom64(v, config) + case OpCom8: + return rewriteValueAMD64_OpCom8(v, config) + case OpConst16: + return rewriteValueAMD64_OpConst16(v, config) + case OpConst32: + return rewriteValueAMD64_OpConst32(v, config) + case OpConst32F: + return rewriteValueAMD64_OpConst32F(v, config) + case OpConst64: + return rewriteValueAMD64_OpConst64(v, config) + case OpConst64F: + return rewriteValueAMD64_OpConst64F(v, config) + case OpConst8: + return rewriteValueAMD64_OpConst8(v, config) + case OpConstBool: + return rewriteValueAMD64_OpConstBool(v, config) + case OpConstNil: + return rewriteValueAMD64_OpConstNil(v, config) + case OpConvert: + return rewriteValueAMD64_OpConvert(v, config) + case OpCvt32Fto32: + return rewriteValueAMD64_OpCvt32Fto32(v, config) + case OpCvt32Fto64: + return rewriteValueAMD64_OpCvt32Fto64(v, config) + case OpCvt32Fto64F: + return rewriteValueAMD64_OpCvt32Fto64F(v, config) + case OpCvt32to32F: + return rewriteValueAMD64_OpCvt32to32F(v, config) + case OpCvt32to64F: + return rewriteValueAMD64_OpCvt32to64F(v, config) + case OpCvt64Fto32: + return rewriteValueAMD64_OpCvt64Fto32(v, config) + case OpCvt64Fto32F: + return rewriteValueAMD64_OpCvt64Fto32F(v, config) + case OpCvt64Fto64: + return rewriteValueAMD64_OpCvt64Fto64(v, config) + case OpCvt64to32F: + return rewriteValueAMD64_OpCvt64to32F(v, config) + case OpCvt64to64F: + return rewriteValueAMD64_OpCvt64to64F(v, config) + case OpDeferCall: + return rewriteValueAMD64_OpDeferCall(v, config) + case OpDiv16: + return rewriteValueAMD64_OpDiv16(v, config) + case OpDiv16u: + return rewriteValueAMD64_OpDiv16u(v, config) + case OpDiv32: + return rewriteValueAMD64_OpDiv32(v, config) + case OpDiv32F: + return rewriteValueAMD64_OpDiv32F(v, config) + case OpDiv32u: + return rewriteValueAMD64_OpDiv32u(v, config) + case OpDiv64: + return rewriteValueAMD64_OpDiv64(v, config) + case OpDiv64F: + return rewriteValueAMD64_OpDiv64F(v, config) + case OpDiv64u: + return rewriteValueAMD64_OpDiv64u(v, config) + case OpDiv8: + return rewriteValueAMD64_OpDiv8(v, config) + case OpDiv8u: + return rewriteValueAMD64_OpDiv8u(v, config) + case OpEq16: + return rewriteValueAMD64_OpEq16(v, config) + case OpEq32: + return rewriteValueAMD64_OpEq32(v, config) + case OpEq32F: + return rewriteValueAMD64_OpEq32F(v, config) + case OpEq64: + return rewriteValueAMD64_OpEq64(v, config) + case OpEq64F: + return rewriteValueAMD64_OpEq64F(v, config) + case OpEq8: + return rewriteValueAMD64_OpEq8(v, config) + case OpEqPtr: + return rewriteValueAMD64_OpEqPtr(v, config) + case OpGeq16: + return rewriteValueAMD64_OpGeq16(v, config) + case OpGeq16U: + return rewriteValueAMD64_OpGeq16U(v, config) + case OpGeq32: + return rewriteValueAMD64_OpGeq32(v, config) + case OpGeq32F: + return rewriteValueAMD64_OpGeq32F(v, config) + case OpGeq32U: + return rewriteValueAMD64_OpGeq32U(v, config) + case OpGeq64: + return rewriteValueAMD64_OpGeq64(v, config) + case OpGeq64F: + return rewriteValueAMD64_OpGeq64F(v, config) + case OpGeq64U: + return rewriteValueAMD64_OpGeq64U(v, config) + case OpGeq8: + return rewriteValueAMD64_OpGeq8(v, config) + case OpGeq8U: + return rewriteValueAMD64_OpGeq8U(v, config) + case OpGetClosurePtr: + return rewriteValueAMD64_OpGetClosurePtr(v, config) + case OpGetG: + return rewriteValueAMD64_OpGetG(v, config) + case OpGoCall: + return rewriteValueAMD64_OpGoCall(v, config) + case OpGreater16: + return rewriteValueAMD64_OpGreater16(v, config) + case OpGreater16U: + return rewriteValueAMD64_OpGreater16U(v, config) + case OpGreater32: + return rewriteValueAMD64_OpGreater32(v, config) + case OpGreater32F: + return rewriteValueAMD64_OpGreater32F(v, config) + case OpGreater32U: + return rewriteValueAMD64_OpGreater32U(v, config) + case OpGreater64: + return rewriteValueAMD64_OpGreater64(v, config) + case OpGreater64F: + return rewriteValueAMD64_OpGreater64F(v, config) + case OpGreater64U: + return rewriteValueAMD64_OpGreater64U(v, config) + case OpGreater8: + return rewriteValueAMD64_OpGreater8(v, config) + case OpGreater8U: + return rewriteValueAMD64_OpGreater8U(v, config) + case OpHmul16: + return rewriteValueAMD64_OpHmul16(v, config) + case OpHmul16u: + return rewriteValueAMD64_OpHmul16u(v, config) + case OpHmul32: + return rewriteValueAMD64_OpHmul32(v, config) + case OpHmul32u: + return rewriteValueAMD64_OpHmul32u(v, config) + case OpHmul64: + return rewriteValueAMD64_OpHmul64(v, config) + case OpHmul64u: + return rewriteValueAMD64_OpHmul64u(v, config) + case OpHmul8: + return rewriteValueAMD64_OpHmul8(v, config) + case OpHmul8u: + return rewriteValueAMD64_OpHmul8u(v, config) + case OpITab: + return rewriteValueAMD64_OpITab(v, config) + case OpInterCall: + return rewriteValueAMD64_OpInterCall(v, config) + case OpIsInBounds: + return rewriteValueAMD64_OpIsInBounds(v, config) + case OpIsNonNil: + return rewriteValueAMD64_OpIsNonNil(v, config) + case OpIsSliceInBounds: + return rewriteValueAMD64_OpIsSliceInBounds(v, config) + case OpAMD64LEAQ: + return rewriteValueAMD64_OpAMD64LEAQ(v, config) + case OpAMD64LEAQ1: + return rewriteValueAMD64_OpAMD64LEAQ1(v, config) + case OpAMD64LEAQ2: + return rewriteValueAMD64_OpAMD64LEAQ2(v, config) + case OpAMD64LEAQ4: + return rewriteValueAMD64_OpAMD64LEAQ4(v, config) + case OpAMD64LEAQ8: + return rewriteValueAMD64_OpAMD64LEAQ8(v, config) + case OpLeq16: + return rewriteValueAMD64_OpLeq16(v, config) + case OpLeq16U: + return rewriteValueAMD64_OpLeq16U(v, config) + case OpLeq32: + return rewriteValueAMD64_OpLeq32(v, config) + case OpLeq32F: + return rewriteValueAMD64_OpLeq32F(v, config) + case OpLeq32U: + return rewriteValueAMD64_OpLeq32U(v, config) + case OpLeq64: + return rewriteValueAMD64_OpLeq64(v, config) + case OpLeq64F: + return rewriteValueAMD64_OpLeq64F(v, config) + case OpLeq64U: + return rewriteValueAMD64_OpLeq64U(v, config) + case OpLeq8: + return rewriteValueAMD64_OpLeq8(v, config) + case OpLeq8U: + return rewriteValueAMD64_OpLeq8U(v, config) + case OpLess16: + return rewriteValueAMD64_OpLess16(v, config) + case OpLess16U: + return rewriteValueAMD64_OpLess16U(v, config) + case OpLess32: + return rewriteValueAMD64_OpLess32(v, config) + case OpLess32F: + return rewriteValueAMD64_OpLess32F(v, config) + case OpLess32U: + return rewriteValueAMD64_OpLess32U(v, config) + case OpLess64: + return rewriteValueAMD64_OpLess64(v, config) + case OpLess64F: + return rewriteValueAMD64_OpLess64F(v, config) + case OpLess64U: + return rewriteValueAMD64_OpLess64U(v, config) + case OpLess8: + return rewriteValueAMD64_OpLess8(v, config) + case OpLess8U: + return rewriteValueAMD64_OpLess8U(v, config) + case OpLoad: + return rewriteValueAMD64_OpLoad(v, config) + case OpLrot16: + return rewriteValueAMD64_OpLrot16(v, config) + case OpLrot32: + return rewriteValueAMD64_OpLrot32(v, config) + case OpLrot64: + return rewriteValueAMD64_OpLrot64(v, config) + case OpLrot8: + return rewriteValueAMD64_OpLrot8(v, config) + case OpLsh16x16: + return rewriteValueAMD64_OpLsh16x16(v, config) + case OpLsh16x32: + return rewriteValueAMD64_OpLsh16x32(v, config) + case OpLsh16x64: + return rewriteValueAMD64_OpLsh16x64(v, config) + case OpLsh16x8: + return rewriteValueAMD64_OpLsh16x8(v, config) + case OpLsh32x16: + return rewriteValueAMD64_OpLsh32x16(v, config) + case OpLsh32x32: + return rewriteValueAMD64_OpLsh32x32(v, config) + case OpLsh32x64: + return rewriteValueAMD64_OpLsh32x64(v, config) + case OpLsh32x8: + return rewriteValueAMD64_OpLsh32x8(v, config) + case OpLsh64x16: + return rewriteValueAMD64_OpLsh64x16(v, config) + case OpLsh64x32: + return rewriteValueAMD64_OpLsh64x32(v, config) + case OpLsh64x64: + return rewriteValueAMD64_OpLsh64x64(v, config) + case OpLsh64x8: + return rewriteValueAMD64_OpLsh64x8(v, config) + case OpLsh8x16: + return rewriteValueAMD64_OpLsh8x16(v, config) + case OpLsh8x32: + return rewriteValueAMD64_OpLsh8x32(v, config) + case OpLsh8x64: + return rewriteValueAMD64_OpLsh8x64(v, config) + case OpLsh8x8: + return rewriteValueAMD64_OpLsh8x8(v, config) + case OpAMD64MOVBQSX: + return rewriteValueAMD64_OpAMD64MOVBQSX(v, config) + case OpAMD64MOVBQZX: + return rewriteValueAMD64_OpAMD64MOVBQZX(v, config) + case OpAMD64MOVBload: + return rewriteValueAMD64_OpAMD64MOVBload(v, config) + case OpAMD64MOVBloadidx1: + return rewriteValueAMD64_OpAMD64MOVBloadidx1(v, config) + case OpAMD64MOVBstore: + return rewriteValueAMD64_OpAMD64MOVBstore(v, config) + case OpAMD64MOVBstoreconst: + return rewriteValueAMD64_OpAMD64MOVBstoreconst(v, config) + case OpAMD64MOVBstoreconstidx1: + return rewriteValueAMD64_OpAMD64MOVBstoreconstidx1(v, config) + case OpAMD64MOVBstoreidx1: + return rewriteValueAMD64_OpAMD64MOVBstoreidx1(v, config) + case OpAMD64MOVLQSX: + return rewriteValueAMD64_OpAMD64MOVLQSX(v, config) + case OpAMD64MOVLQZX: + return rewriteValueAMD64_OpAMD64MOVLQZX(v, config) + case OpAMD64MOVLload: + return rewriteValueAMD64_OpAMD64MOVLload(v, config) + case OpAMD64MOVLloadidx4: + return rewriteValueAMD64_OpAMD64MOVLloadidx4(v, config) + case OpAMD64MOVLstore: + return rewriteValueAMD64_OpAMD64MOVLstore(v, config) + case OpAMD64MOVLstoreconst: + return rewriteValueAMD64_OpAMD64MOVLstoreconst(v, config) + case OpAMD64MOVLstoreconstidx4: + return rewriteValueAMD64_OpAMD64MOVLstoreconstidx4(v, config) + case OpAMD64MOVLstoreidx4: + return rewriteValueAMD64_OpAMD64MOVLstoreidx4(v, config) + case OpAMD64MOVOload: + return rewriteValueAMD64_OpAMD64MOVOload(v, config) + case OpAMD64MOVOstore: + return rewriteValueAMD64_OpAMD64MOVOstore(v, config) + case OpAMD64MOVQload: + return rewriteValueAMD64_OpAMD64MOVQload(v, config) + case OpAMD64MOVQloadidx8: + return rewriteValueAMD64_OpAMD64MOVQloadidx8(v, config) + case OpAMD64MOVQstore: + return rewriteValueAMD64_OpAMD64MOVQstore(v, config) + case OpAMD64MOVQstoreconst: + return rewriteValueAMD64_OpAMD64MOVQstoreconst(v, config) + case OpAMD64MOVQstoreconstidx8: + return rewriteValueAMD64_OpAMD64MOVQstoreconstidx8(v, config) + case OpAMD64MOVQstoreidx8: + return rewriteValueAMD64_OpAMD64MOVQstoreidx8(v, config) + case OpAMD64MOVSDload: + return rewriteValueAMD64_OpAMD64MOVSDload(v, config) + case OpAMD64MOVSDloadidx8: + return rewriteValueAMD64_OpAMD64MOVSDloadidx8(v, config) + case OpAMD64MOVSDstore: + return rewriteValueAMD64_OpAMD64MOVSDstore(v, config) + case OpAMD64MOVSDstoreidx8: + return rewriteValueAMD64_OpAMD64MOVSDstoreidx8(v, config) + case OpAMD64MOVSSload: + return rewriteValueAMD64_OpAMD64MOVSSload(v, config) + case OpAMD64MOVSSloadidx4: + return rewriteValueAMD64_OpAMD64MOVSSloadidx4(v, config) + case OpAMD64MOVSSstore: + return rewriteValueAMD64_OpAMD64MOVSSstore(v, config) + case OpAMD64MOVSSstoreidx4: + return rewriteValueAMD64_OpAMD64MOVSSstoreidx4(v, config) + case OpAMD64MOVWQSX: + return rewriteValueAMD64_OpAMD64MOVWQSX(v, config) + case OpAMD64MOVWQZX: + return rewriteValueAMD64_OpAMD64MOVWQZX(v, config) + case OpAMD64MOVWload: + return rewriteValueAMD64_OpAMD64MOVWload(v, config) + case OpAMD64MOVWloadidx2: + return rewriteValueAMD64_OpAMD64MOVWloadidx2(v, config) + case OpAMD64MOVWstore: + return rewriteValueAMD64_OpAMD64MOVWstore(v, config) + case OpAMD64MOVWstoreconst: + return rewriteValueAMD64_OpAMD64MOVWstoreconst(v, config) + case OpAMD64MOVWstoreconstidx2: + return rewriteValueAMD64_OpAMD64MOVWstoreconstidx2(v, config) + case OpAMD64MOVWstoreidx2: + return rewriteValueAMD64_OpAMD64MOVWstoreidx2(v, config) + case OpAMD64MULB: + return rewriteValueAMD64_OpAMD64MULB(v, config) + case OpAMD64MULBconst: + return rewriteValueAMD64_OpAMD64MULBconst(v, config) + case OpAMD64MULL: + return rewriteValueAMD64_OpAMD64MULL(v, config) + case OpAMD64MULLconst: + return rewriteValueAMD64_OpAMD64MULLconst(v, config) + case OpAMD64MULQ: + return rewriteValueAMD64_OpAMD64MULQ(v, config) + case OpAMD64MULQconst: + return rewriteValueAMD64_OpAMD64MULQconst(v, config) + case OpAMD64MULW: + return rewriteValueAMD64_OpAMD64MULW(v, config) + case OpAMD64MULWconst: + return rewriteValueAMD64_OpAMD64MULWconst(v, config) + case OpMod16: + return rewriteValueAMD64_OpMod16(v, config) + case OpMod16u: + return rewriteValueAMD64_OpMod16u(v, config) + case OpMod32: + return rewriteValueAMD64_OpMod32(v, config) + case OpMod32u: + return rewriteValueAMD64_OpMod32u(v, config) + case OpMod64: + return rewriteValueAMD64_OpMod64(v, config) + case OpMod64u: + return rewriteValueAMD64_OpMod64u(v, config) + case OpMod8: + return rewriteValueAMD64_OpMod8(v, config) + case OpMod8u: + return rewriteValueAMD64_OpMod8u(v, config) + case OpMove: + return rewriteValueAMD64_OpMove(v, config) + case OpMul16: + return rewriteValueAMD64_OpMul16(v, config) + case OpMul32: + return rewriteValueAMD64_OpMul32(v, config) + case OpMul32F: + return rewriteValueAMD64_OpMul32F(v, config) + case OpMul64: + return rewriteValueAMD64_OpMul64(v, config) + case OpMul64F: + return rewriteValueAMD64_OpMul64F(v, config) + case OpMul8: + return rewriteValueAMD64_OpMul8(v, config) + case OpAMD64NEGB: + return rewriteValueAMD64_OpAMD64NEGB(v, config) + case OpAMD64NEGL: + return rewriteValueAMD64_OpAMD64NEGL(v, config) + case OpAMD64NEGQ: + return rewriteValueAMD64_OpAMD64NEGQ(v, config) + case OpAMD64NEGW: + return rewriteValueAMD64_OpAMD64NEGW(v, config) + case OpAMD64NOTB: + return rewriteValueAMD64_OpAMD64NOTB(v, config) + case OpAMD64NOTL: + return rewriteValueAMD64_OpAMD64NOTL(v, config) + case OpAMD64NOTQ: + return rewriteValueAMD64_OpAMD64NOTQ(v, config) + case OpAMD64NOTW: + return rewriteValueAMD64_OpAMD64NOTW(v, config) + case OpNeg16: + return rewriteValueAMD64_OpNeg16(v, config) + case OpNeg32: + return rewriteValueAMD64_OpNeg32(v, config) + case OpNeg32F: + return rewriteValueAMD64_OpNeg32F(v, config) + case OpNeg64: + return rewriteValueAMD64_OpNeg64(v, config) + case OpNeg64F: + return rewriteValueAMD64_OpNeg64F(v, config) + case OpNeg8: + return rewriteValueAMD64_OpNeg8(v, config) + case OpNeq16: + return rewriteValueAMD64_OpNeq16(v, config) + case OpNeq32: + return rewriteValueAMD64_OpNeq32(v, config) + case OpNeq32F: + return rewriteValueAMD64_OpNeq32F(v, config) + case OpNeq64: + return rewriteValueAMD64_OpNeq64(v, config) + case OpNeq64F: + return rewriteValueAMD64_OpNeq64F(v, config) + case OpNeq8: + return rewriteValueAMD64_OpNeq8(v, config) + case OpNeqPtr: + return rewriteValueAMD64_OpNeqPtr(v, config) + case OpNilCheck: + return rewriteValueAMD64_OpNilCheck(v, config) + case OpNot: + return rewriteValueAMD64_OpNot(v, config) + case OpAMD64ORB: + return rewriteValueAMD64_OpAMD64ORB(v, config) + case OpAMD64ORBconst: + return rewriteValueAMD64_OpAMD64ORBconst(v, config) + case OpAMD64ORL: + return rewriteValueAMD64_OpAMD64ORL(v, config) + case OpAMD64ORLconst: + return rewriteValueAMD64_OpAMD64ORLconst(v, config) + case OpAMD64ORQ: + return rewriteValueAMD64_OpAMD64ORQ(v, config) + case OpAMD64ORQconst: + return rewriteValueAMD64_OpAMD64ORQconst(v, config) + case OpAMD64ORW: + return rewriteValueAMD64_OpAMD64ORW(v, config) + case OpAMD64ORWconst: + return rewriteValueAMD64_OpAMD64ORWconst(v, config) + case OpOffPtr: + return rewriteValueAMD64_OpOffPtr(v, config) + case OpOr16: + return rewriteValueAMD64_OpOr16(v, config) + case OpOr32: + return rewriteValueAMD64_OpOr32(v, config) + case OpOr64: + return rewriteValueAMD64_OpOr64(v, config) + case OpOr8: + return rewriteValueAMD64_OpOr8(v, config) + case OpRsh16Ux16: + return rewriteValueAMD64_OpRsh16Ux16(v, config) + case OpRsh16Ux32: + return rewriteValueAMD64_OpRsh16Ux32(v, config) + case OpRsh16Ux64: + return rewriteValueAMD64_OpRsh16Ux64(v, config) + case OpRsh16Ux8: + return rewriteValueAMD64_OpRsh16Ux8(v, config) + case OpRsh16x16: + return rewriteValueAMD64_OpRsh16x16(v, config) + case OpRsh16x32: + return rewriteValueAMD64_OpRsh16x32(v, config) + case OpRsh16x64: + return rewriteValueAMD64_OpRsh16x64(v, config) + case OpRsh16x8: + return rewriteValueAMD64_OpRsh16x8(v, config) + case OpRsh32Ux16: + return rewriteValueAMD64_OpRsh32Ux16(v, config) + case OpRsh32Ux32: + return rewriteValueAMD64_OpRsh32Ux32(v, config) + case OpRsh32Ux64: + return rewriteValueAMD64_OpRsh32Ux64(v, config) + case OpRsh32Ux8: + return rewriteValueAMD64_OpRsh32Ux8(v, config) + case OpRsh32x16: + return rewriteValueAMD64_OpRsh32x16(v, config) + case OpRsh32x32: + return rewriteValueAMD64_OpRsh32x32(v, config) + case OpRsh32x64: + return rewriteValueAMD64_OpRsh32x64(v, config) + case OpRsh32x8: + return rewriteValueAMD64_OpRsh32x8(v, config) + case OpRsh64Ux16: + return rewriteValueAMD64_OpRsh64Ux16(v, config) + case OpRsh64Ux32: + return rewriteValueAMD64_OpRsh64Ux32(v, config) + case OpRsh64Ux64: + return rewriteValueAMD64_OpRsh64Ux64(v, config) + case OpRsh64Ux8: + return rewriteValueAMD64_OpRsh64Ux8(v, config) + case OpRsh64x16: + return rewriteValueAMD64_OpRsh64x16(v, config) + case OpRsh64x32: + return rewriteValueAMD64_OpRsh64x32(v, config) + case OpRsh64x64: + return rewriteValueAMD64_OpRsh64x64(v, config) + case OpRsh64x8: + return rewriteValueAMD64_OpRsh64x8(v, config) + case OpRsh8Ux16: + return rewriteValueAMD64_OpRsh8Ux16(v, config) + case OpRsh8Ux32: + return rewriteValueAMD64_OpRsh8Ux32(v, config) + case OpRsh8Ux64: + return rewriteValueAMD64_OpRsh8Ux64(v, config) + case OpRsh8Ux8: + return rewriteValueAMD64_OpRsh8Ux8(v, config) + case OpRsh8x16: + return rewriteValueAMD64_OpRsh8x16(v, config) + case OpRsh8x32: + return rewriteValueAMD64_OpRsh8x32(v, config) + case OpRsh8x64: + return rewriteValueAMD64_OpRsh8x64(v, config) + case OpRsh8x8: + return rewriteValueAMD64_OpRsh8x8(v, config) + case OpAMD64SARB: + return rewriteValueAMD64_OpAMD64SARB(v, config) + case OpAMD64SARBconst: + return rewriteValueAMD64_OpAMD64SARBconst(v, config) + case OpAMD64SARL: + return rewriteValueAMD64_OpAMD64SARL(v, config) + case OpAMD64SARLconst: + return rewriteValueAMD64_OpAMD64SARLconst(v, config) + case OpAMD64SARQ: + return rewriteValueAMD64_OpAMD64SARQ(v, config) + case OpAMD64SARQconst: + return rewriteValueAMD64_OpAMD64SARQconst(v, config) + case OpAMD64SARW: + return rewriteValueAMD64_OpAMD64SARW(v, config) + case OpAMD64SARWconst: + return rewriteValueAMD64_OpAMD64SARWconst(v, config) + case OpAMD64SBBLcarrymask: + return rewriteValueAMD64_OpAMD64SBBLcarrymask(v, config) + case OpAMD64SBBQcarrymask: + return rewriteValueAMD64_OpAMD64SBBQcarrymask(v, config) + case OpAMD64SETA: + return rewriteValueAMD64_OpAMD64SETA(v, config) + case OpAMD64SETAE: + return rewriteValueAMD64_OpAMD64SETAE(v, config) + case OpAMD64SETB: + return rewriteValueAMD64_OpAMD64SETB(v, config) + case OpAMD64SETBE: + return rewriteValueAMD64_OpAMD64SETBE(v, config) + case OpAMD64SETEQ: + return rewriteValueAMD64_OpAMD64SETEQ(v, config) + case OpAMD64SETG: + return rewriteValueAMD64_OpAMD64SETG(v, config) + case OpAMD64SETGE: + return rewriteValueAMD64_OpAMD64SETGE(v, config) + case OpAMD64SETL: + return rewriteValueAMD64_OpAMD64SETL(v, config) + case OpAMD64SETLE: + return rewriteValueAMD64_OpAMD64SETLE(v, config) + case OpAMD64SETNE: + return rewriteValueAMD64_OpAMD64SETNE(v, config) + case OpAMD64SHLB: + return rewriteValueAMD64_OpAMD64SHLB(v, config) + case OpAMD64SHLL: + return rewriteValueAMD64_OpAMD64SHLL(v, config) + case OpAMD64SHLQ: + return rewriteValueAMD64_OpAMD64SHLQ(v, config) + case OpAMD64SHLW: + return rewriteValueAMD64_OpAMD64SHLW(v, config) + case OpAMD64SHRB: + return rewriteValueAMD64_OpAMD64SHRB(v, config) + case OpAMD64SHRL: + return rewriteValueAMD64_OpAMD64SHRL(v, config) + case OpAMD64SHRQ: + return rewriteValueAMD64_OpAMD64SHRQ(v, config) + case OpAMD64SHRW: + return rewriteValueAMD64_OpAMD64SHRW(v, config) + case OpAMD64SUBB: + return rewriteValueAMD64_OpAMD64SUBB(v, config) + case OpAMD64SUBBconst: + return rewriteValueAMD64_OpAMD64SUBBconst(v, config) + case OpAMD64SUBL: + return rewriteValueAMD64_OpAMD64SUBL(v, config) + case OpAMD64SUBLconst: + return rewriteValueAMD64_OpAMD64SUBLconst(v, config) + case OpAMD64SUBQ: + return rewriteValueAMD64_OpAMD64SUBQ(v, config) + case OpAMD64SUBQconst: + return rewriteValueAMD64_OpAMD64SUBQconst(v, config) + case OpAMD64SUBW: + return rewriteValueAMD64_OpAMD64SUBW(v, config) + case OpAMD64SUBWconst: + return rewriteValueAMD64_OpAMD64SUBWconst(v, config) + case OpSignExt16to32: + return rewriteValueAMD64_OpSignExt16to32(v, config) + case OpSignExt16to64: + return rewriteValueAMD64_OpSignExt16to64(v, config) + case OpSignExt32to64: + return rewriteValueAMD64_OpSignExt32to64(v, config) + case OpSignExt8to16: + return rewriteValueAMD64_OpSignExt8to16(v, config) + case OpSignExt8to32: + return rewriteValueAMD64_OpSignExt8to32(v, config) + case OpSignExt8to64: + return rewriteValueAMD64_OpSignExt8to64(v, config) + case OpSqrt: + return rewriteValueAMD64_OpSqrt(v, config) + case OpStaticCall: + return rewriteValueAMD64_OpStaticCall(v, config) + case OpStore: + return rewriteValueAMD64_OpStore(v, config) + case OpSub16: + return rewriteValueAMD64_OpSub16(v, config) + case OpSub32: + return rewriteValueAMD64_OpSub32(v, config) + case OpSub32F: + return rewriteValueAMD64_OpSub32F(v, config) + case OpSub64: + return rewriteValueAMD64_OpSub64(v, config) + case OpSub64F: + return rewriteValueAMD64_OpSub64F(v, config) + case OpSub8: + return rewriteValueAMD64_OpSub8(v, config) + case OpSubPtr: + return rewriteValueAMD64_OpSubPtr(v, config) + case OpTrunc16to8: + return rewriteValueAMD64_OpTrunc16to8(v, config) + case OpTrunc32to16: + return rewriteValueAMD64_OpTrunc32to16(v, config) + case OpTrunc32to8: + return rewriteValueAMD64_OpTrunc32to8(v, config) + case OpTrunc64to16: + return rewriteValueAMD64_OpTrunc64to16(v, config) + case OpTrunc64to32: + return rewriteValueAMD64_OpTrunc64to32(v, config) + case OpTrunc64to8: + return rewriteValueAMD64_OpTrunc64to8(v, config) + case OpAMD64XORB: + return rewriteValueAMD64_OpAMD64XORB(v, config) + case OpAMD64XORBconst: + return rewriteValueAMD64_OpAMD64XORBconst(v, config) + case OpAMD64XORL: + return rewriteValueAMD64_OpAMD64XORL(v, config) + case OpAMD64XORLconst: + return rewriteValueAMD64_OpAMD64XORLconst(v, config) + case OpAMD64XORQ: + return rewriteValueAMD64_OpAMD64XORQ(v, config) + case OpAMD64XORQconst: + return rewriteValueAMD64_OpAMD64XORQconst(v, config) + case OpAMD64XORW: + return rewriteValueAMD64_OpAMD64XORW(v, config) + case OpAMD64XORWconst: + return rewriteValueAMD64_OpAMD64XORWconst(v, config) + case OpXor16: + return rewriteValueAMD64_OpXor16(v, config) + case OpXor32: + return rewriteValueAMD64_OpXor32(v, config) + case OpXor64: + return rewriteValueAMD64_OpXor64(v, config) + case OpXor8: + return rewriteValueAMD64_OpXor8(v, config) + case OpZero: + return rewriteValueAMD64_OpZero(v, config) + case OpZeroExt16to32: + return rewriteValueAMD64_OpZeroExt16to32(v, config) + case OpZeroExt16to64: + return rewriteValueAMD64_OpZeroExt16to64(v, config) + case OpZeroExt32to64: + return rewriteValueAMD64_OpZeroExt32to64(v, config) + case OpZeroExt8to16: + return rewriteValueAMD64_OpZeroExt8to16(v, config) + case OpZeroExt8to32: + return rewriteValueAMD64_OpZeroExt8to32(v, config) + case OpZeroExt8to64: + return rewriteValueAMD64_OpZeroExt8to64(v, config) + } + return false +} +func rewriteValueAMD64_OpAMD64ADDB(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ADDB x (MOVBconst [c])) + // cond: + // result: (ADDBconst [c] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVBconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64ADDBconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ADDB (MOVBconst [c]) x) + // cond: + // result: (ADDBconst [c] x) + for { + if v.Args[0].Op != OpAMD64MOVBconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + v.reset(OpAMD64ADDBconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ADDB x (NEGB y)) + // cond: + // result: (SUBB x y) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64NEGB { + break + } + y := v.Args[1].Args[0] + v.reset(OpAMD64SUBB) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ADDBconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ADDBconst [c] x) + // cond: int8(c)==0 + // result: x + for { + c := v.AuxInt + x := v.Args[0] + if !(int8(c) == 0) { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (ADDBconst [c] (MOVBconst [d])) + // cond: + // result: (MOVBconst [c+d]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVBconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVBconst) + v.AuxInt = c + d + return true + } + // match: (ADDBconst [c] (ADDBconst [d] x)) + // cond: + // result: (ADDBconst [c+d] x) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64ADDBconst { + break + } + d := v.Args[0].AuxInt + x := v.Args[0].Args[0] + v.reset(OpAMD64ADDBconst) + v.AuxInt = c + d + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ADDL(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ADDL x (MOVLconst [c])) + // cond: + // result: (ADDLconst [c] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64ADDLconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ADDL (MOVLconst [c]) x) + // cond: + // result: (ADDLconst [c] x) + for { + if v.Args[0].Op != OpAMD64MOVLconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + v.reset(OpAMD64ADDLconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ADDL x (NEGL y)) + // cond: + // result: (SUBL x y) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64NEGL { + break + } + y := v.Args[1].Args[0] + v.reset(OpAMD64SUBL) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ADDLconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ADDLconst [c] x) + // cond: int32(c)==0 + // result: x + for { + c := v.AuxInt + x := v.Args[0] + if !(int32(c) == 0) { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (ADDLconst [c] (MOVLconst [d])) + // cond: + // result: (MOVLconst [c+d]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVLconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVLconst) + v.AuxInt = c + d + return true + } + // match: (ADDLconst [c] (ADDLconst [d] x)) + // cond: + // result: (ADDLconst [c+d] x) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64ADDLconst { + break + } + d := v.Args[0].AuxInt + x := v.Args[0].Args[0] + v.reset(OpAMD64ADDLconst) + v.AuxInt = c + d + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ADDQ(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ADDQ x (MOVQconst [c])) + // cond: is32Bit(c) + // result: (ADDQconst [c] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVQconst { + break + } + c := v.Args[1].AuxInt + if !(is32Bit(c)) { + break + } + v.reset(OpAMD64ADDQconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ADDQ (MOVQconst [c]) x) + // cond: is32Bit(c) + // result: (ADDQconst [c] x) + for { + if v.Args[0].Op != OpAMD64MOVQconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + if !(is32Bit(c)) { + break + } + v.reset(OpAMD64ADDQconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ADDQ x (SHLQconst [3] y)) + // cond: + // result: (LEAQ8 x y) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64SHLQconst { + break + } + if v.Args[1].AuxInt != 3 { + break + } + y := v.Args[1].Args[0] + v.reset(OpAMD64LEAQ8) + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (ADDQ x (SHLQconst [2] y)) + // cond: + // result: (LEAQ4 x y) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64SHLQconst { + break + } + if v.Args[1].AuxInt != 2 { + break + } + y := v.Args[1].Args[0] + v.reset(OpAMD64LEAQ4) + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (ADDQ x (SHLQconst [1] y)) + // cond: + // result: (LEAQ2 x y) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64SHLQconst { + break + } + if v.Args[1].AuxInt != 1 { + break + } + y := v.Args[1].Args[0] + v.reset(OpAMD64LEAQ2) + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (ADDQ x (ADDQ y y)) + // cond: + // result: (LEAQ2 x y) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64ADDQ { + break + } + y := v.Args[1].Args[0] + if v.Args[1].Args[1] != y { + break + } + v.reset(OpAMD64LEAQ2) + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (ADDQ x (ADDQ x y)) + // cond: + // result: (LEAQ2 y x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64ADDQ { + break + } + if v.Args[1].Args[0] != x { + break + } + y := v.Args[1].Args[1] + v.reset(OpAMD64LEAQ2) + v.AddArg(y) + v.AddArg(x) + return true + } + // match: (ADDQ x (ADDQ y x)) + // cond: + // result: (LEAQ2 y x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64ADDQ { + break + } + y := v.Args[1].Args[0] + if v.Args[1].Args[1] != x { + break + } + v.reset(OpAMD64LEAQ2) + v.AddArg(y) + v.AddArg(x) + return true + } + // match: (ADDQ (ADDQconst [c] x) y) + // cond: + // result: (LEAQ1 [c] x y) + for { + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[0].Args[0] + y := v.Args[1] + v.reset(OpAMD64LEAQ1) + v.AuxInt = c + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (ADDQ x (ADDQconst [c] y)) + // cond: + // result: (LEAQ1 [c] x y) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64ADDQconst { + break + } + c := v.Args[1].AuxInt + y := v.Args[1].Args[0] + v.reset(OpAMD64LEAQ1) + v.AuxInt = c + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (ADDQ x (LEAQ [c] {s} y)) + // cond: x.Op != OpSB && y.Op != OpSB + // result: (LEAQ1 [c] {s} x y) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64LEAQ { + break + } + c := v.Args[1].AuxInt + s := v.Args[1].Aux + y := v.Args[1].Args[0] + if !(x.Op != OpSB && y.Op != OpSB) { + break + } + v.reset(OpAMD64LEAQ1) + v.AuxInt = c + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (ADDQ (LEAQ [c] {s} x) y) + // cond: x.Op != OpSB && y.Op != OpSB + // result: (LEAQ1 [c] {s} x y) + for { + if v.Args[0].Op != OpAMD64LEAQ { + break + } + c := v.Args[0].AuxInt + s := v.Args[0].Aux + x := v.Args[0].Args[0] + y := v.Args[1] + if !(x.Op != OpSB && y.Op != OpSB) { + break + } + v.reset(OpAMD64LEAQ1) + v.AuxInt = c + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (ADDQ x (NEGQ y)) + // cond: + // result: (SUBQ x y) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64NEGQ { + break + } + y := v.Args[1].Args[0] + v.reset(OpAMD64SUBQ) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ADDQconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ADDQconst [c] (ADDQ x y)) + // cond: + // result: (LEAQ1 [c] x y) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64ADDQ { + break + } + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + v.reset(OpAMD64LEAQ1) + v.AuxInt = c + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (ADDQconst [c] (LEAQ [d] {s} x)) + // cond: + // result: (LEAQ [c+d] {s} x) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64LEAQ { + break + } + d := v.Args[0].AuxInt + s := v.Args[0].Aux + x := v.Args[0].Args[0] + v.reset(OpAMD64LEAQ) + v.AuxInt = c + d + v.Aux = s + v.AddArg(x) + return true + } + // match: (ADDQconst [c] (LEAQ1 [d] {s} x y)) + // cond: + // result: (LEAQ1 [c+d] {s} x y) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64LEAQ1 { + break + } + d := v.Args[0].AuxInt + s := v.Args[0].Aux + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + v.reset(OpAMD64LEAQ1) + v.AuxInt = c + d + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (ADDQconst [c] (LEAQ2 [d] {s} x y)) + // cond: + // result: (LEAQ2 [c+d] {s} x y) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64LEAQ2 { + break + } + d := v.Args[0].AuxInt + s := v.Args[0].Aux + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + v.reset(OpAMD64LEAQ2) + v.AuxInt = c + d + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (ADDQconst [c] (LEAQ4 [d] {s} x y)) + // cond: + // result: (LEAQ4 [c+d] {s} x y) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64LEAQ4 { + break + } + d := v.Args[0].AuxInt + s := v.Args[0].Aux + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + v.reset(OpAMD64LEAQ4) + v.AuxInt = c + d + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (ADDQconst [c] (LEAQ8 [d] {s} x y)) + // cond: + // result: (LEAQ8 [c+d] {s} x y) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64LEAQ8 { + break + } + d := v.Args[0].AuxInt + s := v.Args[0].Aux + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + v.reset(OpAMD64LEAQ8) + v.AuxInt = c + d + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (ADDQconst [0] x) + // cond: + // result: x + for { + if v.AuxInt != 0 { + break + } + x := v.Args[0] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (ADDQconst [c] (MOVQconst [d])) + // cond: + // result: (MOVQconst [c+d]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVQconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVQconst) + v.AuxInt = c + d + return true + } + // match: (ADDQconst [c] (ADDQconst [d] x)) + // cond: + // result: (ADDQconst [c+d] x) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + d := v.Args[0].AuxInt + x := v.Args[0].Args[0] + v.reset(OpAMD64ADDQconst) + v.AuxInt = c + d + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ADDW(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ADDW x (MOVWconst [c])) + // cond: + // result: (ADDWconst [c] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVWconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64ADDWconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ADDW (MOVWconst [c]) x) + // cond: + // result: (ADDWconst [c] x) + for { + if v.Args[0].Op != OpAMD64MOVWconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + v.reset(OpAMD64ADDWconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ADDW x (NEGW y)) + // cond: + // result: (SUBW x y) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64NEGW { + break + } + y := v.Args[1].Args[0] + v.reset(OpAMD64SUBW) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ADDWconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ADDWconst [c] x) + // cond: int16(c)==0 + // result: x + for { + c := v.AuxInt + x := v.Args[0] + if !(int16(c) == 0) { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (ADDWconst [c] (MOVWconst [d])) + // cond: + // result: (MOVWconst [c+d]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVWconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVWconst) + v.AuxInt = c + d + return true + } + // match: (ADDWconst [c] (ADDWconst [d] x)) + // cond: + // result: (ADDWconst [c+d] x) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64ADDWconst { + break + } + d := v.Args[0].AuxInt + x := v.Args[0].Args[0] + v.reset(OpAMD64ADDWconst) + v.AuxInt = c + d + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ANDB(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ANDB x (MOVLconst [c])) + // cond: + // result: (ANDBconst [c] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64ANDBconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ANDB (MOVLconst [c]) x) + // cond: + // result: (ANDBconst [c] x) + for { + if v.Args[0].Op != OpAMD64MOVLconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + v.reset(OpAMD64ANDBconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ANDB x (MOVBconst [c])) + // cond: + // result: (ANDBconst [c] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVBconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64ANDBconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ANDB (MOVBconst [c]) x) + // cond: + // result: (ANDBconst [c] x) + for { + if v.Args[0].Op != OpAMD64MOVBconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + v.reset(OpAMD64ANDBconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ANDB x x) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ANDBconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ANDBconst [c] _) + // cond: int8(c)==0 + // result: (MOVBconst [0]) + for { + c := v.AuxInt + if !(int8(c) == 0) { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + // match: (ANDBconst [c] x) + // cond: int8(c)==-1 + // result: x + for { + c := v.AuxInt + x := v.Args[0] + if !(int8(c) == -1) { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (ANDBconst [c] (MOVBconst [d])) + // cond: + // result: (MOVBconst [c&d]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVBconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVBconst) + v.AuxInt = c & d + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ANDL(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ANDL x (MOVLconst [c])) + // cond: + // result: (ANDLconst [c] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64ANDLconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ANDL (MOVLconst [c]) x) + // cond: + // result: (ANDLconst [c] x) + for { + if v.Args[0].Op != OpAMD64MOVLconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + v.reset(OpAMD64ANDLconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ANDL x x) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ANDLconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ANDLconst [c] _) + // cond: int32(c)==0 + // result: (MOVLconst [0]) + for { + c := v.AuxInt + if !(int32(c) == 0) { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = 0 + return true + } + // match: (ANDLconst [c] x) + // cond: int32(c)==-1 + // result: x + for { + c := v.AuxInt + x := v.Args[0] + if !(int32(c) == -1) { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (ANDLconst [c] (MOVLconst [d])) + // cond: + // result: (MOVLconst [c&d]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVLconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVLconst) + v.AuxInt = c & d + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ANDQ(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ANDQ x (MOVQconst [c])) + // cond: is32Bit(c) + // result: (ANDQconst [c] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVQconst { + break + } + c := v.Args[1].AuxInt + if !(is32Bit(c)) { + break + } + v.reset(OpAMD64ANDQconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ANDQ (MOVQconst [c]) x) + // cond: is32Bit(c) + // result: (ANDQconst [c] x) + for { + if v.Args[0].Op != OpAMD64MOVQconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + if !(is32Bit(c)) { + break + } + v.reset(OpAMD64ANDQconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ANDQ x x) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ANDQconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ANDQconst [0] _) + // cond: + // result: (MOVQconst [0]) + for { + if v.AuxInt != 0 { + break + } + v.reset(OpAMD64MOVQconst) + v.AuxInt = 0 + return true + } + // match: (ANDQconst [-1] x) + // cond: + // result: x + for { + if v.AuxInt != -1 { + break + } + x := v.Args[0] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (ANDQconst [c] (MOVQconst [d])) + // cond: + // result: (MOVQconst [c&d]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVQconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVQconst) + v.AuxInt = c & d + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ANDW(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ANDW x (MOVLconst [c])) + // cond: + // result: (ANDWconst [c] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64ANDWconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ANDW (MOVLconst [c]) x) + // cond: + // result: (ANDWconst [c] x) + for { + if v.Args[0].Op != OpAMD64MOVLconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + v.reset(OpAMD64ANDWconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ANDW x (MOVWconst [c])) + // cond: + // result: (ANDWconst [c] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVWconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64ANDWconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ANDW (MOVWconst [c]) x) + // cond: + // result: (ANDWconst [c] x) + for { + if v.Args[0].Op != OpAMD64MOVWconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + v.reset(OpAMD64ANDWconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ANDW x x) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ANDWconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ANDWconst [c] _) + // cond: int16(c)==0 + // result: (MOVWconst [0]) + for { + c := v.AuxInt + if !(int16(c) == 0) { + break + } + v.reset(OpAMD64MOVWconst) + v.AuxInt = 0 + return true + } + // match: (ANDWconst [c] x) + // cond: int16(c)==-1 + // result: x + for { + c := v.AuxInt + x := v.Args[0] + if !(int16(c) == -1) { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (ANDWconst [c] (MOVWconst [d])) + // cond: + // result: (MOVWconst [c&d]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVWconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVWconst) + v.AuxInt = c & d + return true + } + return false +} +func rewriteValueAMD64_OpAdd16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Add16 x y) + // cond: + // result: (ADDW x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ADDW) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpAdd32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Add32 x y) + // cond: + // result: (ADDL x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ADDL) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpAdd32F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Add32F x y) + // cond: + // result: (ADDSS x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ADDSS) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpAdd64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Add64 x y) + // cond: + // result: (ADDQ x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ADDQ) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpAdd64F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Add64F x y) + // cond: + // result: (ADDSD x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ADDSD) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpAdd8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Add8 x y) + // cond: + // result: (ADDB x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ADDB) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpAddPtr(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (AddPtr x y) + // cond: + // result: (ADDQ x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ADDQ) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpAddr(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Addr {sym} base) + // cond: + // result: (LEAQ {sym} base) + for { + sym := v.Aux + base := v.Args[0] + v.reset(OpAMD64LEAQ) + v.Aux = sym + v.AddArg(base) + return true + } + return false +} +func rewriteValueAMD64_OpAnd16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (And16 x y) + // cond: + // result: (ANDW x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDW) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpAnd32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (And32 x y) + // cond: + // result: (ANDL x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDL) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpAnd64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (And64 x y) + // cond: + // result: (ANDQ x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDQ) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpAnd8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (And8 x y) + // cond: + // result: (ANDB x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDB) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpAvg64u(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Avg64u x y) + // cond: + // result: (AVGQU x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64AVGQU) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64CMPB(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (CMPB x (MOVBconst [c])) + // cond: + // result: (CMPBconst x [c]) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVBconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64CMPBconst) + v.AddArg(x) + v.AuxInt = c + return true + } + // match: (CMPB (MOVBconst [c]) x) + // cond: + // result: (InvertFlags (CMPBconst x [c])) + for { + if v.Args[0].Op != OpAMD64MOVBconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + v.reset(OpAMD64InvertFlags) + v0 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeFlags) + v0.AddArg(x) + v0.AuxInt = c + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64CMPBconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (CMPBconst (MOVBconst [x]) [y]) + // cond: int8(x)==int8(y) + // result: (FlagEQ) + for { + if v.Args[0].Op != OpAMD64MOVBconst { + break + } + x := v.Args[0].AuxInt + y := v.AuxInt + if !(int8(x) == int8(y)) { + break + } + v.reset(OpAMD64FlagEQ) + return true + } + // match: (CMPBconst (MOVBconst [x]) [y]) + // cond: int8(x)<int8(y) && uint8(x)<uint8(y) + // result: (FlagLT_ULT) + for { + if v.Args[0].Op != OpAMD64MOVBconst { + break + } + x := v.Args[0].AuxInt + y := v.AuxInt + if !(int8(x) < int8(y) && uint8(x) < uint8(y)) { + break + } + v.reset(OpAMD64FlagLT_ULT) + return true + } + // match: (CMPBconst (MOVBconst [x]) [y]) + // cond: int8(x)<int8(y) && uint8(x)>uint8(y) + // result: (FlagLT_UGT) + for { + if v.Args[0].Op != OpAMD64MOVBconst { + break + } + x := v.Args[0].AuxInt + y := v.AuxInt + if !(int8(x) < int8(y) && uint8(x) > uint8(y)) { + break + } + v.reset(OpAMD64FlagLT_UGT) + return true + } + // match: (CMPBconst (MOVBconst [x]) [y]) + // cond: int8(x)>int8(y) && uint8(x)<uint8(y) + // result: (FlagGT_ULT) + for { + if v.Args[0].Op != OpAMD64MOVBconst { + break + } + x := v.Args[0].AuxInt + y := v.AuxInt + if !(int8(x) > int8(y) && uint8(x) < uint8(y)) { + break + } + v.reset(OpAMD64FlagGT_ULT) + return true + } + // match: (CMPBconst (MOVBconst [x]) [y]) + // cond: int8(x)>int8(y) && uint8(x)>uint8(y) + // result: (FlagGT_UGT) + for { + if v.Args[0].Op != OpAMD64MOVBconst { + break + } + x := v.Args[0].AuxInt + y := v.AuxInt + if !(int8(x) > int8(y) && uint8(x) > uint8(y)) { + break + } + v.reset(OpAMD64FlagGT_UGT) + return true + } + // match: (CMPBconst (ANDBconst _ [m]) [n]) + // cond: int8(m)+1==int8(n) && isPowerOfTwo(int64(int8(n))) + // result: (FlagLT_ULT) + for { + if v.Args[0].Op != OpAMD64ANDBconst { + break + } + m := v.Args[0].AuxInt + n := v.AuxInt + if !(int8(m)+1 == int8(n) && isPowerOfTwo(int64(int8(n)))) { + break + } + v.reset(OpAMD64FlagLT_ULT) + return true + } + // match: (CMPBconst (ANDB x y) [0]) + // cond: + // result: (TESTB x y) + for { + if v.Args[0].Op != OpAMD64ANDB { + break + } + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + if v.AuxInt != 0 { + break + } + v.reset(OpAMD64TESTB) + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (CMPBconst (ANDBconst [c] x) [0]) + // cond: + // result: (TESTBconst [c] x) + for { + if v.Args[0].Op != OpAMD64ANDBconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[0].Args[0] + if v.AuxInt != 0 { + break + } + v.reset(OpAMD64TESTBconst) + v.AuxInt = c + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64CMPL(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (CMPL x (MOVLconst [c])) + // cond: + // result: (CMPLconst x [c]) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64CMPLconst) + v.AddArg(x) + v.AuxInt = c + return true + } + // match: (CMPL (MOVLconst [c]) x) + // cond: + // result: (InvertFlags (CMPLconst x [c])) + for { + if v.Args[0].Op != OpAMD64MOVLconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + v.reset(OpAMD64InvertFlags) + v0 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeFlags) + v0.AddArg(x) + v0.AuxInt = c + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64CMPLconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (CMPLconst (MOVLconst [x]) [y]) + // cond: int32(x)==int32(y) + // result: (FlagEQ) + for { + if v.Args[0].Op != OpAMD64MOVLconst { + break + } + x := v.Args[0].AuxInt + y := v.AuxInt + if !(int32(x) == int32(y)) { + break + } + v.reset(OpAMD64FlagEQ) + return true + } + // match: (CMPLconst (MOVLconst [x]) [y]) + // cond: int32(x)<int32(y) && uint32(x)<uint32(y) + // result: (FlagLT_ULT) + for { + if v.Args[0].Op != OpAMD64MOVLconst { + break + } + x := v.Args[0].AuxInt + y := v.AuxInt + if !(int32(x) < int32(y) && uint32(x) < uint32(y)) { + break + } + v.reset(OpAMD64FlagLT_ULT) + return true + } + // match: (CMPLconst (MOVLconst [x]) [y]) + // cond: int32(x)<int32(y) && uint32(x)>uint32(y) + // result: (FlagLT_UGT) + for { + if v.Args[0].Op != OpAMD64MOVLconst { + break + } + x := v.Args[0].AuxInt + y := v.AuxInt + if !(int32(x) < int32(y) && uint32(x) > uint32(y)) { + break + } + v.reset(OpAMD64FlagLT_UGT) + return true + } + // match: (CMPLconst (MOVLconst [x]) [y]) + // cond: int32(x)>int32(y) && uint32(x)<uint32(y) + // result: (FlagGT_ULT) + for { + if v.Args[0].Op != OpAMD64MOVLconst { + break + } + x := v.Args[0].AuxInt + y := v.AuxInt + if !(int32(x) > int32(y) && uint32(x) < uint32(y)) { + break + } + v.reset(OpAMD64FlagGT_ULT) + return true + } + // match: (CMPLconst (MOVLconst [x]) [y]) + // cond: int32(x)>int32(y) && uint32(x)>uint32(y) + // result: (FlagGT_UGT) + for { + if v.Args[0].Op != OpAMD64MOVLconst { + break + } + x := v.Args[0].AuxInt + y := v.AuxInt + if !(int32(x) > int32(y) && uint32(x) > uint32(y)) { + break + } + v.reset(OpAMD64FlagGT_UGT) + return true + } + // match: (CMPLconst (ANDLconst _ [m]) [n]) + // cond: int32(m)+1==int32(n) && isPowerOfTwo(int64(int32(n))) + // result: (FlagLT_ULT) + for { + if v.Args[0].Op != OpAMD64ANDLconst { + break + } + m := v.Args[0].AuxInt + n := v.AuxInt + if !(int32(m)+1 == int32(n) && isPowerOfTwo(int64(int32(n)))) { + break + } + v.reset(OpAMD64FlagLT_ULT) + return true + } + // match: (CMPLconst (ANDL x y) [0]) + // cond: + // result: (TESTL x y) + for { + if v.Args[0].Op != OpAMD64ANDL { + break + } + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + if v.AuxInt != 0 { + break + } + v.reset(OpAMD64TESTL) + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (CMPLconst (ANDLconst [c] x) [0]) + // cond: + // result: (TESTLconst [c] x) + for { + if v.Args[0].Op != OpAMD64ANDLconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[0].Args[0] + if v.AuxInt != 0 { + break + } + v.reset(OpAMD64TESTLconst) + v.AuxInt = c + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64CMPQ(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (CMPQ x (MOVQconst [c])) + // cond: is32Bit(c) + // result: (CMPQconst x [c]) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVQconst { + break + } + c := v.Args[1].AuxInt + if !(is32Bit(c)) { + break + } + v.reset(OpAMD64CMPQconst) + v.AddArg(x) + v.AuxInt = c + return true + } + // match: (CMPQ (MOVQconst [c]) x) + // cond: is32Bit(c) + // result: (InvertFlags (CMPQconst x [c])) + for { + if v.Args[0].Op != OpAMD64MOVQconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + if !(is32Bit(c)) { + break + } + v.reset(OpAMD64InvertFlags) + v0 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeFlags) + v0.AddArg(x) + v0.AuxInt = c + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64CMPQconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (CMPQconst (MOVQconst [x]) [y]) + // cond: x==y + // result: (FlagEQ) + for { + if v.Args[0].Op != OpAMD64MOVQconst { + break + } + x := v.Args[0].AuxInt + y := v.AuxInt + if !(x == y) { + break + } + v.reset(OpAMD64FlagEQ) + return true + } + // match: (CMPQconst (MOVQconst [x]) [y]) + // cond: x<y && uint64(x)<uint64(y) + // result: (FlagLT_ULT) + for { + if v.Args[0].Op != OpAMD64MOVQconst { + break + } + x := v.Args[0].AuxInt + y := v.AuxInt + if !(x < y && uint64(x) < uint64(y)) { + break + } + v.reset(OpAMD64FlagLT_ULT) + return true + } + // match: (CMPQconst (MOVQconst [x]) [y]) + // cond: x<y && uint64(x)>uint64(y) + // result: (FlagLT_UGT) + for { + if v.Args[0].Op != OpAMD64MOVQconst { + break + } + x := v.Args[0].AuxInt + y := v.AuxInt + if !(x < y && uint64(x) > uint64(y)) { + break + } + v.reset(OpAMD64FlagLT_UGT) + return true + } + // match: (CMPQconst (MOVQconst [x]) [y]) + // cond: x>y && uint64(x)<uint64(y) + // result: (FlagGT_ULT) + for { + if v.Args[0].Op != OpAMD64MOVQconst { + break + } + x := v.Args[0].AuxInt + y := v.AuxInt + if !(x > y && uint64(x) < uint64(y)) { + break + } + v.reset(OpAMD64FlagGT_ULT) + return true + } + // match: (CMPQconst (MOVQconst [x]) [y]) + // cond: x>y && uint64(x)>uint64(y) + // result: (FlagGT_UGT) + for { + if v.Args[0].Op != OpAMD64MOVQconst { + break + } + x := v.Args[0].AuxInt + y := v.AuxInt + if !(x > y && uint64(x) > uint64(y)) { + break + } + v.reset(OpAMD64FlagGT_UGT) + return true + } + // match: (CMPQconst (ANDQconst _ [m]) [n]) + // cond: m+1==n && isPowerOfTwo(n) + // result: (FlagLT_ULT) + for { + if v.Args[0].Op != OpAMD64ANDQconst { + break + } + m := v.Args[0].AuxInt + n := v.AuxInt + if !(m+1 == n && isPowerOfTwo(n)) { + break + } + v.reset(OpAMD64FlagLT_ULT) + return true + } + // match: (CMPQconst (ANDQ x y) [0]) + // cond: + // result: (TESTQ x y) + for { + if v.Args[0].Op != OpAMD64ANDQ { + break + } + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + if v.AuxInt != 0 { + break + } + v.reset(OpAMD64TESTQ) + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (CMPQconst (ANDQconst [c] x) [0]) + // cond: + // result: (TESTQconst [c] x) + for { + if v.Args[0].Op != OpAMD64ANDQconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[0].Args[0] + if v.AuxInt != 0 { + break + } + v.reset(OpAMD64TESTQconst) + v.AuxInt = c + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64CMPW(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (CMPW x (MOVWconst [c])) + // cond: + // result: (CMPWconst x [c]) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVWconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64CMPWconst) + v.AddArg(x) + v.AuxInt = c + return true + } + // match: (CMPW (MOVWconst [c]) x) + // cond: + // result: (InvertFlags (CMPWconst x [c])) + for { + if v.Args[0].Op != OpAMD64MOVWconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + v.reset(OpAMD64InvertFlags) + v0 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeFlags) + v0.AddArg(x) + v0.AuxInt = c + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64CMPWconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (CMPWconst (MOVWconst [x]) [y]) + // cond: int16(x)==int16(y) + // result: (FlagEQ) + for { + if v.Args[0].Op != OpAMD64MOVWconst { + break + } + x := v.Args[0].AuxInt + y := v.AuxInt + if !(int16(x) == int16(y)) { + break + } + v.reset(OpAMD64FlagEQ) + return true + } + // match: (CMPWconst (MOVWconst [x]) [y]) + // cond: int16(x)<int16(y) && uint16(x)<uint16(y) + // result: (FlagLT_ULT) + for { + if v.Args[0].Op != OpAMD64MOVWconst { + break + } + x := v.Args[0].AuxInt + y := v.AuxInt + if !(int16(x) < int16(y) && uint16(x) < uint16(y)) { + break + } + v.reset(OpAMD64FlagLT_ULT) + return true + } + // match: (CMPWconst (MOVWconst [x]) [y]) + // cond: int16(x)<int16(y) && uint16(x)>uint16(y) + // result: (FlagLT_UGT) + for { + if v.Args[0].Op != OpAMD64MOVWconst { + break + } + x := v.Args[0].AuxInt + y := v.AuxInt + if !(int16(x) < int16(y) && uint16(x) > uint16(y)) { + break + } + v.reset(OpAMD64FlagLT_UGT) + return true + } + // match: (CMPWconst (MOVWconst [x]) [y]) + // cond: int16(x)>int16(y) && uint16(x)<uint16(y) + // result: (FlagGT_ULT) + for { + if v.Args[0].Op != OpAMD64MOVWconst { + break + } + x := v.Args[0].AuxInt + y := v.AuxInt + if !(int16(x) > int16(y) && uint16(x) < uint16(y)) { + break + } + v.reset(OpAMD64FlagGT_ULT) + return true + } + // match: (CMPWconst (MOVWconst [x]) [y]) + // cond: int16(x)>int16(y) && uint16(x)>uint16(y) + // result: (FlagGT_UGT) + for { + if v.Args[0].Op != OpAMD64MOVWconst { + break + } + x := v.Args[0].AuxInt + y := v.AuxInt + if !(int16(x) > int16(y) && uint16(x) > uint16(y)) { + break + } + v.reset(OpAMD64FlagGT_UGT) + return true + } + // match: (CMPWconst (ANDWconst _ [m]) [n]) + // cond: int16(m)+1==int16(n) && isPowerOfTwo(int64(int16(n))) + // result: (FlagLT_ULT) + for { + if v.Args[0].Op != OpAMD64ANDWconst { + break + } + m := v.Args[0].AuxInt + n := v.AuxInt + if !(int16(m)+1 == int16(n) && isPowerOfTwo(int64(int16(n)))) { + break + } + v.reset(OpAMD64FlagLT_ULT) + return true + } + // match: (CMPWconst (ANDW x y) [0]) + // cond: + // result: (TESTW x y) + for { + if v.Args[0].Op != OpAMD64ANDW { + break + } + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + if v.AuxInt != 0 { + break + } + v.reset(OpAMD64TESTW) + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (CMPWconst (ANDWconst [c] x) [0]) + // cond: + // result: (TESTWconst [c] x) + for { + if v.Args[0].Op != OpAMD64ANDWconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[0].Args[0] + if v.AuxInt != 0 { + break + } + v.reset(OpAMD64TESTWconst) + v.AuxInt = c + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpClosureCall(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ClosureCall [argwid] entry closure mem) + // cond: + // result: (CALLclosure [argwid] entry closure mem) + for { + argwid := v.AuxInt + entry := v.Args[0] + closure := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64CALLclosure) + v.AuxInt = argwid + v.AddArg(entry) + v.AddArg(closure) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpCom16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Com16 x) + // cond: + // result: (NOTW x) + for { + x := v.Args[0] + v.reset(OpAMD64NOTW) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpCom32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Com32 x) + // cond: + // result: (NOTL x) + for { + x := v.Args[0] + v.reset(OpAMD64NOTL) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpCom64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Com64 x) + // cond: + // result: (NOTQ x) + for { + x := v.Args[0] + v.reset(OpAMD64NOTQ) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpCom8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Com8 x) + // cond: + // result: (NOTB x) + for { + x := v.Args[0] + v.reset(OpAMD64NOTB) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpConst16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Const16 [val]) + // cond: + // result: (MOVWconst [val]) + for { + val := v.AuxInt + v.reset(OpAMD64MOVWconst) + v.AuxInt = val + return true + } + return false +} +func rewriteValueAMD64_OpConst32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Const32 [val]) + // cond: + // result: (MOVLconst [val]) + for { + val := v.AuxInt + v.reset(OpAMD64MOVLconst) + v.AuxInt = val + return true + } + return false +} +func rewriteValueAMD64_OpConst32F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Const32F [val]) + // cond: + // result: (MOVSSconst [val]) + for { + val := v.AuxInt + v.reset(OpAMD64MOVSSconst) + v.AuxInt = val + return true + } + return false +} +func rewriteValueAMD64_OpConst64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Const64 [val]) + // cond: + // result: (MOVQconst [val]) + for { + val := v.AuxInt + v.reset(OpAMD64MOVQconst) + v.AuxInt = val + return true + } + return false +} +func rewriteValueAMD64_OpConst64F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Const64F [val]) + // cond: + // result: (MOVSDconst [val]) + for { + val := v.AuxInt + v.reset(OpAMD64MOVSDconst) + v.AuxInt = val + return true + } + return false +} +func rewriteValueAMD64_OpConst8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Const8 [val]) + // cond: + // result: (MOVBconst [val]) + for { + val := v.AuxInt + v.reset(OpAMD64MOVBconst) + v.AuxInt = val + return true + } + return false +} +func rewriteValueAMD64_OpConstBool(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ConstBool [b]) + // cond: + // result: (MOVBconst [b]) + for { + b := v.AuxInt + v.reset(OpAMD64MOVBconst) + v.AuxInt = b + return true + } + return false +} +func rewriteValueAMD64_OpConstNil(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ConstNil) + // cond: + // result: (MOVQconst [0]) + for { + v.reset(OpAMD64MOVQconst) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValueAMD64_OpConvert(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Convert <t> x mem) + // cond: + // result: (MOVQconvert <t> x mem) + for { + t := v.Type + x := v.Args[0] + mem := v.Args[1] + v.reset(OpAMD64MOVQconvert) + v.Type = t + v.AddArg(x) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpCvt32Fto32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Cvt32Fto32 x) + // cond: + // result: (CVTTSS2SL x) + for { + x := v.Args[0] + v.reset(OpAMD64CVTTSS2SL) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpCvt32Fto64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Cvt32Fto64 x) + // cond: + // result: (CVTTSS2SQ x) + for { + x := v.Args[0] + v.reset(OpAMD64CVTTSS2SQ) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpCvt32Fto64F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Cvt32Fto64F x) + // cond: + // result: (CVTSS2SD x) + for { + x := v.Args[0] + v.reset(OpAMD64CVTSS2SD) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpCvt32to32F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Cvt32to32F x) + // cond: + // result: (CVTSL2SS x) + for { + x := v.Args[0] + v.reset(OpAMD64CVTSL2SS) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpCvt32to64F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Cvt32to64F x) + // cond: + // result: (CVTSL2SD x) + for { + x := v.Args[0] + v.reset(OpAMD64CVTSL2SD) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpCvt64Fto32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Cvt64Fto32 x) + // cond: + // result: (CVTTSD2SL x) + for { + x := v.Args[0] + v.reset(OpAMD64CVTTSD2SL) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpCvt64Fto32F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Cvt64Fto32F x) + // cond: + // result: (CVTSD2SS x) + for { + x := v.Args[0] + v.reset(OpAMD64CVTSD2SS) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpCvt64Fto64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Cvt64Fto64 x) + // cond: + // result: (CVTTSD2SQ x) + for { + x := v.Args[0] + v.reset(OpAMD64CVTTSD2SQ) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpCvt64to32F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Cvt64to32F x) + // cond: + // result: (CVTSQ2SS x) + for { + x := v.Args[0] + v.reset(OpAMD64CVTSQ2SS) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpCvt64to64F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Cvt64to64F x) + // cond: + // result: (CVTSQ2SD x) + for { + x := v.Args[0] + v.reset(OpAMD64CVTSQ2SD) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpDeferCall(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (DeferCall [argwid] mem) + // cond: + // result: (CALLdefer [argwid] mem) + for { + argwid := v.AuxInt + mem := v.Args[0] + v.reset(OpAMD64CALLdefer) + v.AuxInt = argwid + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpDiv16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Div16 x y) + // cond: + // result: (DIVW x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64DIVW) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpDiv16u(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Div16u x y) + // cond: + // result: (DIVWU x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64DIVWU) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpDiv32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Div32 x y) + // cond: + // result: (DIVL x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64DIVL) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpDiv32F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Div32F x y) + // cond: + // result: (DIVSS x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64DIVSS) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpDiv32u(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Div32u x y) + // cond: + // result: (DIVLU x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64DIVLU) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpDiv64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Div64 x y) + // cond: + // result: (DIVQ x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64DIVQ) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpDiv64F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Div64F x y) + // cond: + // result: (DIVSD x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64DIVSD) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpDiv64u(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Div64u x y) + // cond: + // result: (DIVQU x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64DIVQU) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpDiv8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Div8 x y) + // cond: + // result: (DIVW (SignExt8to16 x) (SignExt8to16 y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64DIVW) + v0 := b.NewValue0(v.Line, OpSignExt8to16, config.fe.TypeInt16()) + v0.AddArg(x) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpSignExt8to16, config.fe.TypeInt16()) + v1.AddArg(y) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpDiv8u(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Div8u x y) + // cond: + // result: (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64DIVWU) + v0 := b.NewValue0(v.Line, OpZeroExt8to16, config.fe.TypeUInt16()) + v0.AddArg(x) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpZeroExt8to16, config.fe.TypeUInt16()) + v1.AddArg(y) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpEq16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Eq16 x y) + // cond: + // result: (SETEQ (CMPW x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETEQ) + v0 := b.NewValue0(v.Line, OpAMD64CMPW, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpEq32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Eq32 x y) + // cond: + // result: (SETEQ (CMPL x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETEQ) + v0 := b.NewValue0(v.Line, OpAMD64CMPL, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpEq32F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Eq32F x y) + // cond: + // result: (SETEQF (UCOMISS x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETEQF) + v0 := b.NewValue0(v.Line, OpAMD64UCOMISS, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpEq64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Eq64 x y) + // cond: + // result: (SETEQ (CMPQ x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETEQ) + v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpEq64F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Eq64F x y) + // cond: + // result: (SETEQF (UCOMISD x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETEQF) + v0 := b.NewValue0(v.Line, OpAMD64UCOMISD, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpEq8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Eq8 x y) + // cond: + // result: (SETEQ (CMPB x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETEQ) + v0 := b.NewValue0(v.Line, OpAMD64CMPB, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpEqPtr(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (EqPtr x y) + // cond: + // result: (SETEQ (CMPQ x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETEQ) + v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpGeq16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Geq16 x y) + // cond: + // result: (SETGE (CMPW x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETGE) + v0 := b.NewValue0(v.Line, OpAMD64CMPW, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpGeq16U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Geq16U x y) + // cond: + // result: (SETAE (CMPW x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Line, OpAMD64CMPW, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpGeq32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Geq32 x y) + // cond: + // result: (SETGE (CMPL x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETGE) + v0 := b.NewValue0(v.Line, OpAMD64CMPL, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpGeq32F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Geq32F x y) + // cond: + // result: (SETGEF (UCOMISS x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETGEF) + v0 := b.NewValue0(v.Line, OpAMD64UCOMISS, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpGeq32U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Geq32U x y) + // cond: + // result: (SETAE (CMPL x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Line, OpAMD64CMPL, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpGeq64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Geq64 x y) + // cond: + // result: (SETGE (CMPQ x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETGE) + v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpGeq64F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Geq64F x y) + // cond: + // result: (SETGEF (UCOMISD x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETGEF) + v0 := b.NewValue0(v.Line, OpAMD64UCOMISD, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpGeq64U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Geq64U x y) + // cond: + // result: (SETAE (CMPQ x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpGeq8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Geq8 x y) + // cond: + // result: (SETGE (CMPB x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETGE) + v0 := b.NewValue0(v.Line, OpAMD64CMPB, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpGeq8U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Geq8U x y) + // cond: + // result: (SETAE (CMPB x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Line, OpAMD64CMPB, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpGetClosurePtr(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (GetClosurePtr) + // cond: + // result: (LoweredGetClosurePtr) + for { + v.reset(OpAMD64LoweredGetClosurePtr) + return true + } + return false +} +func rewriteValueAMD64_OpGetG(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (GetG mem) + // cond: + // result: (LoweredGetG mem) + for { + mem := v.Args[0] + v.reset(OpAMD64LoweredGetG) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpGoCall(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (GoCall [argwid] mem) + // cond: + // result: (CALLgo [argwid] mem) + for { + argwid := v.AuxInt + mem := v.Args[0] + v.reset(OpAMD64CALLgo) + v.AuxInt = argwid + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpGreater16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Greater16 x y) + // cond: + // result: (SETG (CMPW x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETG) + v0 := b.NewValue0(v.Line, OpAMD64CMPW, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpGreater16U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Greater16U x y) + // cond: + // result: (SETA (CMPW x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETA) + v0 := b.NewValue0(v.Line, OpAMD64CMPW, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpGreater32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Greater32 x y) + // cond: + // result: (SETG (CMPL x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETG) + v0 := b.NewValue0(v.Line, OpAMD64CMPL, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpGreater32F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Greater32F x y) + // cond: + // result: (SETGF (UCOMISS x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETGF) + v0 := b.NewValue0(v.Line, OpAMD64UCOMISS, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpGreater32U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Greater32U x y) + // cond: + // result: (SETA (CMPL x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETA) + v0 := b.NewValue0(v.Line, OpAMD64CMPL, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpGreater64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Greater64 x y) + // cond: + // result: (SETG (CMPQ x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETG) + v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpGreater64F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Greater64F x y) + // cond: + // result: (SETGF (UCOMISD x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETGF) + v0 := b.NewValue0(v.Line, OpAMD64UCOMISD, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpGreater64U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Greater64U x y) + // cond: + // result: (SETA (CMPQ x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETA) + v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpGreater8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Greater8 x y) + // cond: + // result: (SETG (CMPB x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETG) + v0 := b.NewValue0(v.Line, OpAMD64CMPB, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpGreater8U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Greater8U x y) + // cond: + // result: (SETA (CMPB x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETA) + v0 := b.NewValue0(v.Line, OpAMD64CMPB, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpHmul16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Hmul16 x y) + // cond: + // result: (HMULW x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64HMULW) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpHmul16u(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Hmul16u x y) + // cond: + // result: (HMULWU x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64HMULWU) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpHmul32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Hmul32 x y) + // cond: + // result: (HMULL x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64HMULL) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpHmul32u(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Hmul32u x y) + // cond: + // result: (HMULLU x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64HMULLU) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpHmul64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Hmul64 x y) + // cond: + // result: (HMULQ x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64HMULQ) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpHmul64u(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Hmul64u x y) + // cond: + // result: (HMULQU x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64HMULQU) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpHmul8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Hmul8 x y) + // cond: + // result: (HMULB x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64HMULB) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpHmul8u(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Hmul8u x y) + // cond: + // result: (HMULBU x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64HMULBU) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpITab(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ITab (Load ptr mem)) + // cond: + // result: (MOVQload ptr mem) + for { + if v.Args[0].Op != OpLoad { + break + } + ptr := v.Args[0].Args[0] + mem := v.Args[0].Args[1] + v.reset(OpAMD64MOVQload) + v.AddArg(ptr) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpInterCall(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (InterCall [argwid] entry mem) + // cond: + // result: (CALLinter [argwid] entry mem) + for { + argwid := v.AuxInt + entry := v.Args[0] + mem := v.Args[1] + v.reset(OpAMD64CALLinter) + v.AuxInt = argwid + v.AddArg(entry) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpIsInBounds(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (IsInBounds idx len) + // cond: + // result: (SETB (CMPQ idx len)) + for { + idx := v.Args[0] + len := v.Args[1] + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeFlags) + v0.AddArg(idx) + v0.AddArg(len) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpIsNonNil(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (IsNonNil p) + // cond: + // result: (SETNE (TESTQ p p)) + for { + p := v.Args[0] + v.reset(OpAMD64SETNE) + v0 := b.NewValue0(v.Line, OpAMD64TESTQ, TypeFlags) + v0.AddArg(p) + v0.AddArg(p) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpIsSliceInBounds(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (IsSliceInBounds idx len) + // cond: + // result: (SETBE (CMPQ idx len)) + for { + idx := v.Args[0] + len := v.Args[1] + v.reset(OpAMD64SETBE) + v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeFlags) + v0.AddArg(idx) + v0.AddArg(len) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64LEAQ(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (LEAQ [c] {s} (ADDQconst [d] x)) + // cond: + // result: (LEAQ [c+d] {s} x) + for { + c := v.AuxInt + s := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + d := v.Args[0].AuxInt + x := v.Args[0].Args[0] + v.reset(OpAMD64LEAQ) + v.AuxInt = c + d + v.Aux = s + v.AddArg(x) + return true + } + // match: (LEAQ [c] {s} (ADDQ x y)) + // cond: x.Op != OpSB && y.Op != OpSB + // result: (LEAQ1 [c] {s} x y) + for { + c := v.AuxInt + s := v.Aux + if v.Args[0].Op != OpAMD64ADDQ { + break + } + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + if !(x.Op != OpSB && y.Op != OpSB) { + break + } + v.reset(OpAMD64LEAQ1) + v.AuxInt = c + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) + // cond: canMergeSym(sym1, sym2) + // result: (LEAQ [addOff(off1,off2)] {mergeSym(sym1,sym2)} x) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + x := v.Args[0].Args[0] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64LEAQ) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(x) + return true + } + // match: (LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y)) + // cond: canMergeSym(sym1, sym2) + // result: (LEAQ1 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ1 { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64LEAQ1) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y)) + // cond: canMergeSym(sym1, sym2) + // result: (LEAQ2 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ2 { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64LEAQ2) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y)) + // cond: canMergeSym(sym1, sym2) + // result: (LEAQ4 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ4 { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64LEAQ4) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y)) + // cond: canMergeSym(sym1, sym2) + // result: (LEAQ8 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ8 { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64LEAQ8) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64LEAQ1(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (LEAQ1 [c] {s} (ADDQconst [d] x) y) + // cond: x.Op != OpSB + // result: (LEAQ1 [c+d] {s} x y) + for { + c := v.AuxInt + s := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + d := v.Args[0].AuxInt + x := v.Args[0].Args[0] + y := v.Args[1] + if !(x.Op != OpSB) { + break + } + v.reset(OpAMD64LEAQ1) + v.AuxInt = c + d + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (LEAQ1 [c] {s} x (ADDQconst [d] y)) + // cond: y.Op != OpSB + // result: (LEAQ1 [c+d] {s} x y) + for { + c := v.AuxInt + s := v.Aux + x := v.Args[0] + if v.Args[1].Op != OpAMD64ADDQconst { + break + } + d := v.Args[1].AuxInt + y := v.Args[1].Args[0] + if !(y.Op != OpSB) { + break + } + v.reset(OpAMD64LEAQ1) + v.AuxInt = c + d + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) + // cond: canMergeSym(sym1, sym2) && x.Op != OpSB + // result: (LEAQ1 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + x := v.Args[0].Args[0] + y := v.Args[1] + if !(canMergeSym(sym1, sym2) && x.Op != OpSB) { + break + } + v.reset(OpAMD64LEAQ1) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (LEAQ1 [off1] {sym1} x (LEAQ [off2] {sym2} y)) + // cond: canMergeSym(sym1, sym2) && y.Op != OpSB + // result: (LEAQ1 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y) + for { + off1 := v.AuxInt + sym1 := v.Aux + x := v.Args[0] + if v.Args[1].Op != OpAMD64LEAQ { + break + } + off2 := v.Args[1].AuxInt + sym2 := v.Args[1].Aux + y := v.Args[1].Args[0] + if !(canMergeSym(sym1, sym2) && y.Op != OpSB) { + break + } + v.reset(OpAMD64LEAQ1) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64LEAQ2(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (LEAQ2 [c] {s} (ADDQconst [d] x) y) + // cond: x.Op != OpSB + // result: (LEAQ2 [c+d] {s} x y) + for { + c := v.AuxInt + s := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + d := v.Args[0].AuxInt + x := v.Args[0].Args[0] + y := v.Args[1] + if !(x.Op != OpSB) { + break + } + v.reset(OpAMD64LEAQ2) + v.AuxInt = c + d + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (LEAQ2 [c] {s} x (ADDQconst [d] y)) + // cond: y.Op != OpSB + // result: (LEAQ2 [c+2*d] {s} x y) + for { + c := v.AuxInt + s := v.Aux + x := v.Args[0] + if v.Args[1].Op != OpAMD64ADDQconst { + break + } + d := v.Args[1].AuxInt + y := v.Args[1].Args[0] + if !(y.Op != OpSB) { + break + } + v.reset(OpAMD64LEAQ2) + v.AuxInt = c + 2*d + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y) + // cond: canMergeSym(sym1, sym2) && x.Op != OpSB + // result: (LEAQ2 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + x := v.Args[0].Args[0] + y := v.Args[1] + if !(canMergeSym(sym1, sym2) && x.Op != OpSB) { + break + } + v.reset(OpAMD64LEAQ2) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64LEAQ4(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (LEAQ4 [c] {s} (ADDQconst [d] x) y) + // cond: x.Op != OpSB + // result: (LEAQ4 [c+d] {s} x y) + for { + c := v.AuxInt + s := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + d := v.Args[0].AuxInt + x := v.Args[0].Args[0] + y := v.Args[1] + if !(x.Op != OpSB) { + break + } + v.reset(OpAMD64LEAQ4) + v.AuxInt = c + d + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (LEAQ4 [c] {s} x (ADDQconst [d] y)) + // cond: y.Op != OpSB + // result: (LEAQ4 [c+4*d] {s} x y) + for { + c := v.AuxInt + s := v.Aux + x := v.Args[0] + if v.Args[1].Op != OpAMD64ADDQconst { + break + } + d := v.Args[1].AuxInt + y := v.Args[1].Args[0] + if !(y.Op != OpSB) { + break + } + v.reset(OpAMD64LEAQ4) + v.AuxInt = c + 4*d + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y) + // cond: canMergeSym(sym1, sym2) && x.Op != OpSB + // result: (LEAQ4 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + x := v.Args[0].Args[0] + y := v.Args[1] + if !(canMergeSym(sym1, sym2) && x.Op != OpSB) { + break + } + v.reset(OpAMD64LEAQ4) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64LEAQ8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (LEAQ8 [c] {s} (ADDQconst [d] x) y) + // cond: x.Op != OpSB + // result: (LEAQ8 [c+d] {s} x y) + for { + c := v.AuxInt + s := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + d := v.Args[0].AuxInt + x := v.Args[0].Args[0] + y := v.Args[1] + if !(x.Op != OpSB) { + break + } + v.reset(OpAMD64LEAQ8) + v.AuxInt = c + d + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (LEAQ8 [c] {s} x (ADDQconst [d] y)) + // cond: y.Op != OpSB + // result: (LEAQ8 [c+8*d] {s} x y) + for { + c := v.AuxInt + s := v.Aux + x := v.Args[0] + if v.Args[1].Op != OpAMD64ADDQconst { + break + } + d := v.Args[1].AuxInt + y := v.Args[1].Args[0] + if !(y.Op != OpSB) { + break + } + v.reset(OpAMD64LEAQ8) + v.AuxInt = c + 8*d + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true + } + // match: (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y) + // cond: canMergeSym(sym1, sym2) && x.Op != OpSB + // result: (LEAQ8 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + x := v.Args[0].Args[0] + y := v.Args[1] + if !(canMergeSym(sym1, sym2) && x.Op != OpSB) { + break + } + v.reset(OpAMD64LEAQ8) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpLeq16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Leq16 x y) + // cond: + // result: (SETLE (CMPW x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETLE) + v0 := b.NewValue0(v.Line, OpAMD64CMPW, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpLeq16U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Leq16U x y) + // cond: + // result: (SETBE (CMPW x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETBE) + v0 := b.NewValue0(v.Line, OpAMD64CMPW, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpLeq32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Leq32 x y) + // cond: + // result: (SETLE (CMPL x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETLE) + v0 := b.NewValue0(v.Line, OpAMD64CMPL, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpLeq32F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Leq32F x y) + // cond: + // result: (SETGEF (UCOMISS y x)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETGEF) + v0 := b.NewValue0(v.Line, OpAMD64UCOMISS, TypeFlags) + v0.AddArg(y) + v0.AddArg(x) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpLeq32U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Leq32U x y) + // cond: + // result: (SETBE (CMPL x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETBE) + v0 := b.NewValue0(v.Line, OpAMD64CMPL, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpLeq64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Leq64 x y) + // cond: + // result: (SETLE (CMPQ x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETLE) + v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpLeq64F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Leq64F x y) + // cond: + // result: (SETGEF (UCOMISD y x)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETGEF) + v0 := b.NewValue0(v.Line, OpAMD64UCOMISD, TypeFlags) + v0.AddArg(y) + v0.AddArg(x) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpLeq64U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Leq64U x y) + // cond: + // result: (SETBE (CMPQ x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETBE) + v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpLeq8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Leq8 x y) + // cond: + // result: (SETLE (CMPB x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETLE) + v0 := b.NewValue0(v.Line, OpAMD64CMPB, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpLeq8U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Leq8U x y) + // cond: + // result: (SETBE (CMPB x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETBE) + v0 := b.NewValue0(v.Line, OpAMD64CMPB, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpLess16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Less16 x y) + // cond: + // result: (SETL (CMPW x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETL) + v0 := b.NewValue0(v.Line, OpAMD64CMPW, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpLess16U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Less16U x y) + // cond: + // result: (SETB (CMPW x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Line, OpAMD64CMPW, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpLess32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Less32 x y) + // cond: + // result: (SETL (CMPL x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETL) + v0 := b.NewValue0(v.Line, OpAMD64CMPL, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpLess32F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Less32F x y) + // cond: + // result: (SETGF (UCOMISS y x)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETGF) + v0 := b.NewValue0(v.Line, OpAMD64UCOMISS, TypeFlags) + v0.AddArg(y) + v0.AddArg(x) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpLess32U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Less32U x y) + // cond: + // result: (SETB (CMPL x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Line, OpAMD64CMPL, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpLess64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Less64 x y) + // cond: + // result: (SETL (CMPQ x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETL) + v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpLess64F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Less64F x y) + // cond: + // result: (SETGF (UCOMISD y x)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETGF) + v0 := b.NewValue0(v.Line, OpAMD64UCOMISD, TypeFlags) + v0.AddArg(y) + v0.AddArg(x) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpLess64U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Less64U x y) + // cond: + // result: (SETB (CMPQ x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpLess8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Less8 x y) + // cond: + // result: (SETL (CMPB x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETL) + v0 := b.NewValue0(v.Line, OpAMD64CMPB, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpLess8U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Less8U x y) + // cond: + // result: (SETB (CMPB x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Line, OpAMD64CMPB, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpLoad(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Load <t> ptr mem) + // cond: (is64BitInt(t) || isPtr(t)) + // result: (MOVQload ptr mem) + for { + t := v.Type + ptr := v.Args[0] + mem := v.Args[1] + if !(is64BitInt(t) || isPtr(t)) { + break + } + v.reset(OpAMD64MOVQload) + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (Load <t> ptr mem) + // cond: is32BitInt(t) + // result: (MOVLload ptr mem) + for { + t := v.Type + ptr := v.Args[0] + mem := v.Args[1] + if !(is32BitInt(t)) { + break + } + v.reset(OpAMD64MOVLload) + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (Load <t> ptr mem) + // cond: is16BitInt(t) + // result: (MOVWload ptr mem) + for { + t := v.Type + ptr := v.Args[0] + mem := v.Args[1] + if !(is16BitInt(t)) { + break + } + v.reset(OpAMD64MOVWload) + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (Load <t> ptr mem) + // cond: (t.IsBoolean() || is8BitInt(t)) + // result: (MOVBload ptr mem) + for { + t := v.Type + ptr := v.Args[0] + mem := v.Args[1] + if !(t.IsBoolean() || is8BitInt(t)) { + break + } + v.reset(OpAMD64MOVBload) + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (Load <t> ptr mem) + // cond: is32BitFloat(t) + // result: (MOVSSload ptr mem) + for { + t := v.Type + ptr := v.Args[0] + mem := v.Args[1] + if !(is32BitFloat(t)) { + break + } + v.reset(OpAMD64MOVSSload) + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (Load <t> ptr mem) + // cond: is64BitFloat(t) + // result: (MOVSDload ptr mem) + for { + t := v.Type + ptr := v.Args[0] + mem := v.Args[1] + if !(is64BitFloat(t)) { + break + } + v.reset(OpAMD64MOVSDload) + v.AddArg(ptr) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpLrot16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lrot16 <t> x [c]) + // cond: + // result: (ROLWconst <t> [c&15] x) + for { + t := v.Type + x := v.Args[0] + c := v.AuxInt + v.reset(OpAMD64ROLWconst) + v.Type = t + v.AuxInt = c & 15 + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpLrot32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lrot32 <t> x [c]) + // cond: + // result: (ROLLconst <t> [c&31] x) + for { + t := v.Type + x := v.Args[0] + c := v.AuxInt + v.reset(OpAMD64ROLLconst) + v.Type = t + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpLrot64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lrot64 <t> x [c]) + // cond: + // result: (ROLQconst <t> [c&63] x) + for { + t := v.Type + x := v.Args[0] + c := v.AuxInt + v.reset(OpAMD64ROLQconst) + v.Type = t + v.AuxInt = c & 63 + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpLrot8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lrot8 <t> x [c]) + // cond: + // result: (ROLBconst <t> [c&7] x) + for { + t := v.Type + x := v.Args[0] + c := v.AuxInt + v.reset(OpAMD64ROLBconst) + v.Type = t + v.AuxInt = c & 7 + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpLsh16x16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh16x16 <t> x y) + // cond: + // result: (ANDW (SHLW <t> x y) (SBBLcarrymask <t> (CMPWconst y [16]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDW) + v0 := b.NewValue0(v.Line, OpAMD64SHLW, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 16 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpLsh16x32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh16x32 <t> x y) + // cond: + // result: (ANDW (SHLW <t> x y) (SBBLcarrymask <t> (CMPLconst y [16]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDW) + v0 := b.NewValue0(v.Line, OpAMD64SHLW, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 16 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpLsh16x64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh16x64 <t> x y) + // cond: + // result: (ANDW (SHLW <t> x y) (SBBLcarrymask <t> (CMPQconst y [16]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDW) + v0 := b.NewValue0(v.Line, OpAMD64SHLW, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 16 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpLsh16x8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh16x8 <t> x y) + // cond: + // result: (ANDW (SHLW <t> x y) (SBBLcarrymask <t> (CMPBconst y [16]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDW) + v0 := b.NewValue0(v.Line, OpAMD64SHLW, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 16 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpLsh32x16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh32x16 <t> x y) + // cond: + // result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Line, OpAMD64SHLL, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 32 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpLsh32x32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh32x32 <t> x y) + // cond: + // result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Line, OpAMD64SHLL, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 32 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpLsh32x64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh32x64 <t> x y) + // cond: + // result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPQconst y [32]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Line, OpAMD64SHLL, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 32 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpLsh32x8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh32x8 <t> x y) + // cond: + // result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Line, OpAMD64SHLL, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 32 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpLsh64x16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh64x16 <t> x y) + // cond: + // result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPWconst y [64]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDQ) + v0 := b.NewValue0(v.Line, OpAMD64SHLQ, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBQcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 64 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpLsh64x32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh64x32 <t> x y) + // cond: + // result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPLconst y [64]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDQ) + v0 := b.NewValue0(v.Line, OpAMD64SHLQ, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBQcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 64 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpLsh64x64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh64x64 <t> x y) + // cond: + // result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPQconst y [64]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDQ) + v0 := b.NewValue0(v.Line, OpAMD64SHLQ, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBQcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 64 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpLsh64x8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh64x8 <t> x y) + // cond: + // result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPBconst y [64]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDQ) + v0 := b.NewValue0(v.Line, OpAMD64SHLQ, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBQcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 64 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpLsh8x16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh8x16 <t> x y) + // cond: + // result: (ANDB (SHLB <t> x y) (SBBLcarrymask <t> (CMPWconst y [8]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDB) + v0 := b.NewValue0(v.Line, OpAMD64SHLB, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 8 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpLsh8x32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh8x32 <t> x y) + // cond: + // result: (ANDB (SHLB <t> x y) (SBBLcarrymask <t> (CMPLconst y [8]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDB) + v0 := b.NewValue0(v.Line, OpAMD64SHLB, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 8 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpLsh8x64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh8x64 <t> x y) + // cond: + // result: (ANDB (SHLB <t> x y) (SBBLcarrymask <t> (CMPQconst y [8]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDB) + v0 := b.NewValue0(v.Line, OpAMD64SHLB, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 8 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpLsh8x8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh8x8 <t> x y) + // cond: + // result: (ANDB (SHLB <t> x y) (SBBLcarrymask <t> (CMPBconst y [8]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDB) + v0 := b.NewValue0(v.Line, OpAMD64SHLB, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 8 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVBQSX(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVBQSX (MOVBload [off] {sym} ptr mem)) + // cond: + // result: @v.Args[0].Block (MOVBQSXload <v.Type> [off] {sym} ptr mem) + for { + if v.Args[0].Op != OpAMD64MOVBload { + break + } + off := v.Args[0].AuxInt + sym := v.Args[0].Aux + ptr := v.Args[0].Args[0] + mem := v.Args[0].Args[1] + b = v.Args[0].Block + v0 := b.NewValue0(v.Line, OpAMD64MOVBQSXload, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = off + v0.Aux = sym + v0.AddArg(ptr) + v0.AddArg(mem) + return true + } + // match: (MOVBQSX (ANDBconst [c] x)) + // cond: c & 0x80 == 0 + // result: (ANDQconst [c & 0x7f] x) + for { + if v.Args[0].Op != OpAMD64ANDBconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[0].Args[0] + if !(c&0x80 == 0) { + break + } + v.reset(OpAMD64ANDQconst) + v.AuxInt = c & 0x7f + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVBQZX(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVBQZX (MOVBload [off] {sym} ptr mem)) + // cond: + // result: @v.Args[0].Block (MOVBQZXload <v.Type> [off] {sym} ptr mem) + for { + if v.Args[0].Op != OpAMD64MOVBload { + break + } + off := v.Args[0].AuxInt + sym := v.Args[0].Aux + ptr := v.Args[0].Args[0] + mem := v.Args[0].Args[1] + b = v.Args[0].Block + v0 := b.NewValue0(v.Line, OpAMD64MOVBQZXload, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = off + v0.Aux = sym + v0.AddArg(ptr) + v0.AddArg(mem) + return true + } + // match: (MOVBQZX (ANDBconst [c] x)) + // cond: + // result: (ANDQconst [c & 0xff] x) + for { + if v.Args[0].Op != OpAMD64ANDBconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[0].Args[0] + v.reset(OpAMD64ANDQconst) + v.AuxInt = c & 0xff + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVBload(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) + // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) + // result: x + for { + off := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64MOVBstore { + break + } + off2 := v.Args[1].AuxInt + sym2 := v.Args[1].Aux + ptr2 := v.Args[1].Args[0] + x := v.Args[1].Args[1] + if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (MOVBload [off1] {sym} (ADDQconst [off2] ptr) mem) + // cond: + // result: (MOVBload [addOff(off1, off2)] {sym} ptr mem) + for { + off1 := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + off2 := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + mem := v.Args[1] + v.reset(OpAMD64MOVBload) + v.AuxInt = addOff(off1, off2) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (MOVBload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVBload [addOff(off1,off2)] {mergeSym(sym1,sym2)} base mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + base := v.Args[0].Args[0] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVBload) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(base) + v.AddArg(mem) + return true + } + // match: (MOVBload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVBloadidx1 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ1 { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + ptr := v.Args[0].Args[0] + idx := v.Args[0].Args[1] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVBloadidx1) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + // match: (MOVBload [off] {sym} (ADDQ ptr idx) mem) + // cond: ptr.Op != OpSB + // result: (MOVBloadidx1 [off] {sym} ptr idx mem) + for { + off := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQ { + break + } + ptr := v.Args[0].Args[0] + idx := v.Args[0].Args[1] + mem := v.Args[1] + if !(ptr.Op != OpSB) { + break + } + v.reset(OpAMD64MOVBloadidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVBloadidx1(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVBloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) + // cond: + // result: (MOVBloadidx1 [c+d] {sym} ptr idx mem) + for { + c := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + d := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + idx := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVBloadidx1) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + // match: (MOVBloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) + // cond: + // result: (MOVBloadidx1 [c+d] {sym} ptr idx mem) + for { + c := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64ADDQconst { + break + } + d := v.Args[1].AuxInt + idx := v.Args[1].Args[0] + mem := v.Args[2] + v.reset(OpAMD64MOVBloadidx1) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVBstore(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVBstore [off] {sym} ptr (MOVBQSX x) mem) + // cond: + // result: (MOVBstore [off] {sym} ptr x mem) + for { + off := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64MOVBQSX { + break + } + x := v.Args[1].Args[0] + mem := v.Args[2] + v.reset(OpAMD64MOVBstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(x) + v.AddArg(mem) + return true + } + // match: (MOVBstore [off] {sym} ptr (MOVBQZX x) mem) + // cond: + // result: (MOVBstore [off] {sym} ptr x mem) + for { + off := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64MOVBQZX { + break + } + x := v.Args[1].Args[0] + mem := v.Args[2] + v.reset(OpAMD64MOVBstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(x) + v.AddArg(mem) + return true + } + // match: (MOVBstore [off1] {sym} (ADDQconst [off2] ptr) val mem) + // cond: + // result: (MOVBstore [addOff(off1, off2)] {sym} ptr val mem) + for { + off1 := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + off2 := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + val := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVBstore) + v.AuxInt = addOff(off1, off2) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (MOVBstore [off] {sym} ptr (MOVBconst [c]) mem) + // cond: validOff(off) + // result: (MOVBstoreconst [makeValAndOff(int64(int8(c)),off)] {sym} ptr mem) + for { + off := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64MOVBconst { + break + } + c := v.Args[1].AuxInt + mem := v.Args[2] + if !(validOff(off)) { + break + } + v.reset(OpAMD64MOVBstoreconst) + v.AuxInt = makeValAndOff(int64(int8(c)), off) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (MOVBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVBstore [addOff(off1,off2)] {mergeSym(sym1,sym2)} base val mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + base := v.Args[0].Args[0] + val := v.Args[1] + mem := v.Args[2] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVBstore) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(base) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (MOVBstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVBstoreidx1 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx val mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ1 { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + ptr := v.Args[0].Args[0] + idx := v.Args[0].Args[1] + val := v.Args[1] + mem := v.Args[2] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVBstoreidx1) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (MOVBstore [off] {sym} (ADDQ ptr idx) val mem) + // cond: ptr.Op != OpSB + // result: (MOVBstoreidx1 [off] {sym} ptr idx val mem) + for { + off := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQ { + break + } + ptr := v.Args[0].Args[0] + idx := v.Args[0].Args[1] + val := v.Args[1] + mem := v.Args[2] + if !(ptr.Op != OpSB) { + break + } + v.reset(OpAMD64MOVBstoreidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVBstoreconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVBstoreconst [sc] {s} (ADDQconst [off] ptr) mem) + // cond: ValAndOff(sc).canAdd(off) + // result: (MOVBstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) + for { + sc := v.AuxInt + s := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + off := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + mem := v.Args[1] + if !(ValAndOff(sc).canAdd(off)) { + break + } + v.reset(OpAMD64MOVBstoreconst) + v.AuxInt = ValAndOff(sc).add(off) + v.Aux = s + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (MOVBstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) + // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) + // result: (MOVBstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) + for { + sc := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ { + break + } + off := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + ptr := v.Args[0].Args[0] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { + break + } + v.reset(OpAMD64MOVBstoreconst) + v.AuxInt = ValAndOff(sc).add(off) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (MOVBstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVBstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) + for { + x := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ1 { + break + } + off := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + ptr := v.Args[0].Args[0] + idx := v.Args[0].Args[1] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVBstoreconstidx1) + v.AuxInt = ValAndOff(x).add(off) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + // match: (MOVBstoreconst [x] {sym} (ADDQ ptr idx) mem) + // cond: + // result: (MOVBstoreconstidx1 [x] {sym} ptr idx mem) + for { + x := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQ { + break + } + ptr := v.Args[0].Args[0] + idx := v.Args[0].Args[1] + mem := v.Args[1] + v.reset(OpAMD64MOVBstoreconstidx1) + v.AuxInt = x + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVBstoreconstidx1(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVBstoreconstidx1 [x] {sym} (ADDQconst [c] ptr) idx mem) + // cond: + // result: (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) + for { + x := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + c := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + idx := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVBstoreconstidx1) + v.AuxInt = ValAndOff(x).add(c) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + // match: (MOVBstoreconstidx1 [x] {sym} ptr (ADDQconst [c] idx) mem) + // cond: + // result: (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) + for { + x := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64ADDQconst { + break + } + c := v.Args[1].AuxInt + idx := v.Args[1].Args[0] + mem := v.Args[2] + v.reset(OpAMD64MOVBstoreconstidx1) + v.AuxInt = ValAndOff(x).add(c) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVBstoreidx1(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVBstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) + // cond: + // result: (MOVBstoreidx1 [c+d] {sym} ptr idx val mem) + for { + c := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + d := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + idx := v.Args[1] + val := v.Args[2] + mem := v.Args[3] + v.reset(OpAMD64MOVBstoreidx1) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (MOVBstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) + // cond: + // result: (MOVBstoreidx1 [c+d] {sym} ptr idx val mem) + for { + c := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64ADDQconst { + break + } + d := v.Args[1].AuxInt + idx := v.Args[1].Args[0] + val := v.Args[2] + mem := v.Args[3] + v.reset(OpAMD64MOVBstoreidx1) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVLQSX(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVLQSX (MOVLload [off] {sym} ptr mem)) + // cond: + // result: @v.Args[0].Block (MOVLQSXload <v.Type> [off] {sym} ptr mem) + for { + if v.Args[0].Op != OpAMD64MOVLload { + break + } + off := v.Args[0].AuxInt + sym := v.Args[0].Aux + ptr := v.Args[0].Args[0] + mem := v.Args[0].Args[1] + b = v.Args[0].Block + v0 := b.NewValue0(v.Line, OpAMD64MOVLQSXload, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = off + v0.Aux = sym + v0.AddArg(ptr) + v0.AddArg(mem) + return true + } + // match: (MOVLQSX (ANDLconst [c] x)) + // cond: c & 0x80000000 == 0 + // result: (ANDQconst [c & 0x7fffffff] x) + for { + if v.Args[0].Op != OpAMD64ANDLconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[0].Args[0] + if !(c&0x80000000 == 0) { + break + } + v.reset(OpAMD64ANDQconst) + v.AuxInt = c & 0x7fffffff + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVLQZX(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVLQZX (MOVLload [off] {sym} ptr mem)) + // cond: + // result: @v.Args[0].Block (MOVLQZXload <v.Type> [off] {sym} ptr mem) + for { + if v.Args[0].Op != OpAMD64MOVLload { + break + } + off := v.Args[0].AuxInt + sym := v.Args[0].Aux + ptr := v.Args[0].Args[0] + mem := v.Args[0].Args[1] + b = v.Args[0].Block + v0 := b.NewValue0(v.Line, OpAMD64MOVLQZXload, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = off + v0.Aux = sym + v0.AddArg(ptr) + v0.AddArg(mem) + return true + } + // match: (MOVLQZX (ANDLconst [c] x)) + // cond: + // result: (ANDQconst [c & 0xffffffff] x) + for { + if v.Args[0].Op != OpAMD64ANDLconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[0].Args[0] + v.reset(OpAMD64ANDQconst) + v.AuxInt = c & 0xffffffff + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVLload(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) + // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) + // result: x + for { + off := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLstore { + break + } + off2 := v.Args[1].AuxInt + sym2 := v.Args[1].Aux + ptr2 := v.Args[1].Args[0] + x := v.Args[1].Args[1] + if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (MOVLload [off1] {sym} (ADDQconst [off2] ptr) mem) + // cond: + // result: (MOVLload [addOff(off1, off2)] {sym} ptr mem) + for { + off1 := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + off2 := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + mem := v.Args[1] + v.reset(OpAMD64MOVLload) + v.AuxInt = addOff(off1, off2) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (MOVLload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVLload [addOff(off1,off2)] {mergeSym(sym1,sym2)} base mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + base := v.Args[0].Args[0] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVLload) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(base) + v.AddArg(mem) + return true + } + // match: (MOVLload [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVLloadidx4 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ4 { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + ptr := v.Args[0].Args[0] + idx := v.Args[0].Args[1] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVLloadidx4) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVLloadidx4(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVLloadidx4 [c] {sym} (ADDQconst [d] ptr) idx mem) + // cond: + // result: (MOVLloadidx4 [c+d] {sym} ptr idx mem) + for { + c := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + d := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + idx := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVLloadidx4) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + // match: (MOVLloadidx4 [c] {sym} ptr (ADDQconst [d] idx) mem) + // cond: + // result: (MOVLloadidx4 [c+4*d] {sym} ptr idx mem) + for { + c := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64ADDQconst { + break + } + d := v.Args[1].AuxInt + idx := v.Args[1].Args[0] + mem := v.Args[2] + v.reset(OpAMD64MOVLloadidx4) + v.AuxInt = c + 4*d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVLstore(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVLstore [off] {sym} ptr (MOVLQSX x) mem) + // cond: + // result: (MOVLstore [off] {sym} ptr x mem) + for { + off := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLQSX { + break + } + x := v.Args[1].Args[0] + mem := v.Args[2] + v.reset(OpAMD64MOVLstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(x) + v.AddArg(mem) + return true + } + // match: (MOVLstore [off] {sym} ptr (MOVLQZX x) mem) + // cond: + // result: (MOVLstore [off] {sym} ptr x mem) + for { + off := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLQZX { + break + } + x := v.Args[1].Args[0] + mem := v.Args[2] + v.reset(OpAMD64MOVLstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(x) + v.AddArg(mem) + return true + } + // match: (MOVLstore [off1] {sym} (ADDQconst [off2] ptr) val mem) + // cond: + // result: (MOVLstore [addOff(off1, off2)] {sym} ptr val mem) + for { + off1 := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + off2 := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + val := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVLstore) + v.AuxInt = addOff(off1, off2) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem) + // cond: validOff(off) + // result: (MOVLstoreconst [makeValAndOff(int64(int32(c)),off)] {sym} ptr mem) + for { + off := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLconst { + break + } + c := v.Args[1].AuxInt + mem := v.Args[2] + if !(validOff(off)) { + break + } + v.reset(OpAMD64MOVLstoreconst) + v.AuxInt = makeValAndOff(int64(int32(c)), off) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (MOVLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVLstore [addOff(off1,off2)] {mergeSym(sym1,sym2)} base val mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + base := v.Args[0].Args[0] + val := v.Args[1] + mem := v.Args[2] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVLstore) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(base) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (MOVLstore [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) val mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVLstoreidx4 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx val mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ4 { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + ptr := v.Args[0].Args[0] + idx := v.Args[0].Args[1] + val := v.Args[1] + mem := v.Args[2] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVLstoreidx4) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVLstoreconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVLstoreconst [sc] {s} (ADDQconst [off] ptr) mem) + // cond: ValAndOff(sc).canAdd(off) + // result: (MOVLstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) + for { + sc := v.AuxInt + s := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + off := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + mem := v.Args[1] + if !(ValAndOff(sc).canAdd(off)) { + break + } + v.reset(OpAMD64MOVLstoreconst) + v.AuxInt = ValAndOff(sc).add(off) + v.Aux = s + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (MOVLstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) + // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) + // result: (MOVLstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) + for { + sc := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ { + break + } + off := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + ptr := v.Args[0].Args[0] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { + break + } + v.reset(OpAMD64MOVLstoreconst) + v.AuxInt = ValAndOff(sc).add(off) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (MOVLstoreconst [x] {sym1} (LEAQ4 [off] {sym2} ptr idx) mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVLstoreconstidx4 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) + for { + x := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ4 { + break + } + off := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + ptr := v.Args[0].Args[0] + idx := v.Args[0].Args[1] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVLstoreconstidx4) + v.AuxInt = ValAndOff(x).add(off) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVLstoreconstidx4(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVLstoreconstidx4 [x] {sym} (ADDQconst [c] ptr) idx mem) + // cond: + // result: (MOVLstoreconstidx4 [ValAndOff(x).add(c)] {sym} ptr idx mem) + for { + x := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + c := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + idx := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVLstoreconstidx4) + v.AuxInt = ValAndOff(x).add(c) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + // match: (MOVLstoreconstidx4 [x] {sym} ptr (ADDQconst [c] idx) mem) + // cond: + // result: (MOVLstoreconstidx4 [ValAndOff(x).add(4*c)] {sym} ptr idx mem) + for { + x := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64ADDQconst { + break + } + c := v.Args[1].AuxInt + idx := v.Args[1].Args[0] + mem := v.Args[2] + v.reset(OpAMD64MOVLstoreconstidx4) + v.AuxInt = ValAndOff(x).add(4 * c) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVLstoreidx4(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVLstoreidx4 [c] {sym} (ADDQconst [d] ptr) idx val mem) + // cond: + // result: (MOVLstoreidx4 [c+d] {sym} ptr idx val mem) + for { + c := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + d := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + idx := v.Args[1] + val := v.Args[2] + mem := v.Args[3] + v.reset(OpAMD64MOVLstoreidx4) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (MOVLstoreidx4 [c] {sym} ptr (ADDQconst [d] idx) val mem) + // cond: + // result: (MOVLstoreidx4 [c+4*d] {sym} ptr idx val mem) + for { + c := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64ADDQconst { + break + } + d := v.Args[1].AuxInt + idx := v.Args[1].Args[0] + val := v.Args[2] + mem := v.Args[3] + v.reset(OpAMD64MOVLstoreidx4) + v.AuxInt = c + 4*d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVOload(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVOload [off1] {sym} (ADDQconst [off2] ptr) mem) + // cond: + // result: (MOVOload [addOff(off1, off2)] {sym} ptr mem) + for { + off1 := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + off2 := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + mem := v.Args[1] + v.reset(OpAMD64MOVOload) + v.AuxInt = addOff(off1, off2) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (MOVOload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVOload [addOff(off1,off2)] {mergeSym(sym1,sym2)} base mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + base := v.Args[0].Args[0] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVOload) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(base) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVOstore(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVOstore [off1] {sym} (ADDQconst [off2] ptr) val mem) + // cond: + // result: (MOVOstore [addOff(off1, off2)] {sym} ptr val mem) + for { + off1 := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + off2 := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + val := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVOstore) + v.AuxInt = addOff(off1, off2) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (MOVOstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVOstore [addOff(off1,off2)] {mergeSym(sym1,sym2)} base val mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + base := v.Args[0].Args[0] + val := v.Args[1] + mem := v.Args[2] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVOstore) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(base) + v.AddArg(val) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVQload(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVQload [off] {sym} ptr (MOVQstore [off2] {sym2} ptr2 x _)) + // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) + // result: x + for { + off := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64MOVQstore { + break + } + off2 := v.Args[1].AuxInt + sym2 := v.Args[1].Aux + ptr2 := v.Args[1].Args[0] + x := v.Args[1].Args[1] + if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (MOVQload [off1] {sym} (ADDQconst [off2] ptr) mem) + // cond: + // result: (MOVQload [addOff(off1, off2)] {sym} ptr mem) + for { + off1 := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + off2 := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + mem := v.Args[1] + v.reset(OpAMD64MOVQload) + v.AuxInt = addOff(off1, off2) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (MOVQload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVQload [addOff(off1,off2)] {mergeSym(sym1,sym2)} base mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + base := v.Args[0].Args[0] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVQload) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(base) + v.AddArg(mem) + return true + } + // match: (MOVQload [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVQloadidx8 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ8 { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + ptr := v.Args[0].Args[0] + idx := v.Args[0].Args[1] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVQloadidx8) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVQloadidx8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVQloadidx8 [c] {sym} (ADDQconst [d] ptr) idx mem) + // cond: + // result: (MOVQloadidx8 [c+d] {sym} ptr idx mem) + for { + c := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + d := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + idx := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVQloadidx8) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + // match: (MOVQloadidx8 [c] {sym} ptr (ADDQconst [d] idx) mem) + // cond: + // result: (MOVQloadidx8 [c+8*d] {sym} ptr idx mem) + for { + c := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64ADDQconst { + break + } + d := v.Args[1].AuxInt + idx := v.Args[1].Args[0] + mem := v.Args[2] + v.reset(OpAMD64MOVQloadidx8) + v.AuxInt = c + 8*d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVQstore(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVQstore [off1] {sym} (ADDQconst [off2] ptr) val mem) + // cond: + // result: (MOVQstore [addOff(off1, off2)] {sym} ptr val mem) + for { + off1 := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + off2 := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + val := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVQstore) + v.AuxInt = addOff(off1, off2) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (MOVQstore [off] {sym} ptr (MOVQconst [c]) mem) + // cond: validValAndOff(c,off) + // result: (MOVQstoreconst [makeValAndOff(c,off)] {sym} ptr mem) + for { + off := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64MOVQconst { + break + } + c := v.Args[1].AuxInt + mem := v.Args[2] + if !(validValAndOff(c, off)) { + break + } + v.reset(OpAMD64MOVQstoreconst) + v.AuxInt = makeValAndOff(c, off) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (MOVQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVQstore [addOff(off1,off2)] {mergeSym(sym1,sym2)} base val mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + base := v.Args[0].Args[0] + val := v.Args[1] + mem := v.Args[2] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVQstore) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(base) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (MOVQstore [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) val mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVQstoreidx8 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx val mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ8 { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + ptr := v.Args[0].Args[0] + idx := v.Args[0].Args[1] + val := v.Args[1] + mem := v.Args[2] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVQstoreidx8) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVQstoreconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVQstoreconst [sc] {s} (ADDQconst [off] ptr) mem) + // cond: ValAndOff(sc).canAdd(off) + // result: (MOVQstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) + for { + sc := v.AuxInt + s := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + off := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + mem := v.Args[1] + if !(ValAndOff(sc).canAdd(off)) { + break + } + v.reset(OpAMD64MOVQstoreconst) + v.AuxInt = ValAndOff(sc).add(off) + v.Aux = s + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (MOVQstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) + // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) + // result: (MOVQstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) + for { + sc := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ { + break + } + off := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + ptr := v.Args[0].Args[0] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { + break + } + v.reset(OpAMD64MOVQstoreconst) + v.AuxInt = ValAndOff(sc).add(off) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (MOVQstoreconst [x] {sym1} (LEAQ8 [off] {sym2} ptr idx) mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVQstoreconstidx8 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) + for { + x := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ8 { + break + } + off := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + ptr := v.Args[0].Args[0] + idx := v.Args[0].Args[1] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVQstoreconstidx8) + v.AuxInt = ValAndOff(x).add(off) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVQstoreconstidx8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVQstoreconstidx8 [x] {sym} (ADDQconst [c] ptr) idx mem) + // cond: + // result: (MOVQstoreconstidx8 [ValAndOff(x).add(c)] {sym} ptr idx mem) + for { + x := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + c := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + idx := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVQstoreconstidx8) + v.AuxInt = ValAndOff(x).add(c) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + // match: (MOVQstoreconstidx8 [x] {sym} ptr (ADDQconst [c] idx) mem) + // cond: + // result: (MOVQstoreconstidx8 [ValAndOff(x).add(8*c)] {sym} ptr idx mem) + for { + x := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64ADDQconst { + break + } + c := v.Args[1].AuxInt + idx := v.Args[1].Args[0] + mem := v.Args[2] + v.reset(OpAMD64MOVQstoreconstidx8) + v.AuxInt = ValAndOff(x).add(8 * c) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVQstoreidx8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVQstoreidx8 [c] {sym} (ADDQconst [d] ptr) idx val mem) + // cond: + // result: (MOVQstoreidx8 [c+d] {sym} ptr idx val mem) + for { + c := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + d := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + idx := v.Args[1] + val := v.Args[2] + mem := v.Args[3] + v.reset(OpAMD64MOVQstoreidx8) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (MOVQstoreidx8 [c] {sym} ptr (ADDQconst [d] idx) val mem) + // cond: + // result: (MOVQstoreidx8 [c+8*d] {sym} ptr idx val mem) + for { + c := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64ADDQconst { + break + } + d := v.Args[1].AuxInt + idx := v.Args[1].Args[0] + val := v.Args[2] + mem := v.Args[3] + v.reset(OpAMD64MOVQstoreidx8) + v.AuxInt = c + 8*d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVSDload(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVSDload [off1] {sym} (ADDQconst [off2] ptr) mem) + // cond: + // result: (MOVSDload [addOff(off1, off2)] {sym} ptr mem) + for { + off1 := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + off2 := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + mem := v.Args[1] + v.reset(OpAMD64MOVSDload) + v.AuxInt = addOff(off1, off2) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (MOVSDload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVSDload [addOff(off1,off2)] {mergeSym(sym1,sym2)} base mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + base := v.Args[0].Args[0] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVSDload) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(base) + v.AddArg(mem) + return true + } + // match: (MOVSDload [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVSDloadidx8 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ8 { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + ptr := v.Args[0].Args[0] + idx := v.Args[0].Args[1] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVSDloadidx8) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVSDloadidx8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVSDloadidx8 [c] {sym} (ADDQconst [d] ptr) idx mem) + // cond: + // result: (MOVSDloadidx8 [c+d] {sym} ptr idx mem) + for { + c := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + d := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + idx := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVSDloadidx8) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + // match: (MOVSDloadidx8 [c] {sym} ptr (ADDQconst [d] idx) mem) + // cond: + // result: (MOVSDloadidx8 [c+8*d] {sym} ptr idx mem) + for { + c := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64ADDQconst { + break + } + d := v.Args[1].AuxInt + idx := v.Args[1].Args[0] + mem := v.Args[2] + v.reset(OpAMD64MOVSDloadidx8) + v.AuxInt = c + 8*d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVSDstore(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVSDstore [off1] {sym} (ADDQconst [off2] ptr) val mem) + // cond: + // result: (MOVSDstore [addOff(off1, off2)] {sym} ptr val mem) + for { + off1 := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + off2 := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + val := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVSDstore) + v.AuxInt = addOff(off1, off2) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (MOVSDstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVSDstore [addOff(off1,off2)] {mergeSym(sym1,sym2)} base val mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + base := v.Args[0].Args[0] + val := v.Args[1] + mem := v.Args[2] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVSDstore) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(base) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (MOVSDstore [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) val mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVSDstoreidx8 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx val mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ8 { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + ptr := v.Args[0].Args[0] + idx := v.Args[0].Args[1] + val := v.Args[1] + mem := v.Args[2] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVSDstoreidx8) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVSDstoreidx8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVSDstoreidx8 [c] {sym} (ADDQconst [d] ptr) idx val mem) + // cond: + // result: (MOVSDstoreidx8 [c+d] {sym} ptr idx val mem) + for { + c := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + d := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + idx := v.Args[1] + val := v.Args[2] + mem := v.Args[3] + v.reset(OpAMD64MOVSDstoreidx8) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (MOVSDstoreidx8 [c] {sym} ptr (ADDQconst [d] idx) val mem) + // cond: + // result: (MOVSDstoreidx8 [c+8*d] {sym} ptr idx val mem) + for { + c := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64ADDQconst { + break + } + d := v.Args[1].AuxInt + idx := v.Args[1].Args[0] + val := v.Args[2] + mem := v.Args[3] + v.reset(OpAMD64MOVSDstoreidx8) + v.AuxInt = c + 8*d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVSSload(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVSSload [off1] {sym} (ADDQconst [off2] ptr) mem) + // cond: + // result: (MOVSSload [addOff(off1, off2)] {sym} ptr mem) + for { + off1 := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + off2 := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + mem := v.Args[1] + v.reset(OpAMD64MOVSSload) + v.AuxInt = addOff(off1, off2) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (MOVSSload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVSSload [addOff(off1,off2)] {mergeSym(sym1,sym2)} base mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + base := v.Args[0].Args[0] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVSSload) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(base) + v.AddArg(mem) + return true + } + // match: (MOVSSload [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVSSloadidx4 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ4 { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + ptr := v.Args[0].Args[0] + idx := v.Args[0].Args[1] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVSSloadidx4) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVSSloadidx4(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVSSloadidx4 [c] {sym} (ADDQconst [d] ptr) idx mem) + // cond: + // result: (MOVSSloadidx4 [c+d] {sym} ptr idx mem) + for { + c := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + d := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + idx := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVSSloadidx4) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + // match: (MOVSSloadidx4 [c] {sym} ptr (ADDQconst [d] idx) mem) + // cond: + // result: (MOVSSloadidx4 [c+4*d] {sym} ptr idx mem) + for { + c := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64ADDQconst { + break + } + d := v.Args[1].AuxInt + idx := v.Args[1].Args[0] + mem := v.Args[2] + v.reset(OpAMD64MOVSSloadidx4) + v.AuxInt = c + 4*d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVSSstore(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVSSstore [off1] {sym} (ADDQconst [off2] ptr) val mem) + // cond: + // result: (MOVSSstore [addOff(off1, off2)] {sym} ptr val mem) + for { + off1 := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + off2 := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + val := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVSSstore) + v.AuxInt = addOff(off1, off2) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (MOVSSstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVSSstore [addOff(off1,off2)] {mergeSym(sym1,sym2)} base val mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + base := v.Args[0].Args[0] + val := v.Args[1] + mem := v.Args[2] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVSSstore) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(base) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (MOVSSstore [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) val mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVSSstoreidx4 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx val mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ4 { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + ptr := v.Args[0].Args[0] + idx := v.Args[0].Args[1] + val := v.Args[1] + mem := v.Args[2] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVSSstoreidx4) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVSSstoreidx4(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVSSstoreidx4 [c] {sym} (ADDQconst [d] ptr) idx val mem) + // cond: + // result: (MOVSSstoreidx4 [c+d] {sym} ptr idx val mem) + for { + c := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + d := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + idx := v.Args[1] + val := v.Args[2] + mem := v.Args[3] + v.reset(OpAMD64MOVSSstoreidx4) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (MOVSSstoreidx4 [c] {sym} ptr (ADDQconst [d] idx) val mem) + // cond: + // result: (MOVSSstoreidx4 [c+4*d] {sym} ptr idx val mem) + for { + c := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64ADDQconst { + break + } + d := v.Args[1].AuxInt + idx := v.Args[1].Args[0] + val := v.Args[2] + mem := v.Args[3] + v.reset(OpAMD64MOVSSstoreidx4) + v.AuxInt = c + 4*d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVWQSX(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVWQSX (MOVWload [off] {sym} ptr mem)) + // cond: + // result: @v.Args[0].Block (MOVWQSXload <v.Type> [off] {sym} ptr mem) + for { + if v.Args[0].Op != OpAMD64MOVWload { + break + } + off := v.Args[0].AuxInt + sym := v.Args[0].Aux + ptr := v.Args[0].Args[0] + mem := v.Args[0].Args[1] + b = v.Args[0].Block + v0 := b.NewValue0(v.Line, OpAMD64MOVWQSXload, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = off + v0.Aux = sym + v0.AddArg(ptr) + v0.AddArg(mem) + return true + } + // match: (MOVWQSX (ANDWconst [c] x)) + // cond: c & 0x8000 == 0 + // result: (ANDQconst [c & 0x7fff] x) + for { + if v.Args[0].Op != OpAMD64ANDWconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[0].Args[0] + if !(c&0x8000 == 0) { + break + } + v.reset(OpAMD64ANDQconst) + v.AuxInt = c & 0x7fff + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVWQZX(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVWQZX (MOVWload [off] {sym} ptr mem)) + // cond: + // result: @v.Args[0].Block (MOVWQZXload <v.Type> [off] {sym} ptr mem) + for { + if v.Args[0].Op != OpAMD64MOVWload { + break + } + off := v.Args[0].AuxInt + sym := v.Args[0].Aux + ptr := v.Args[0].Args[0] + mem := v.Args[0].Args[1] + b = v.Args[0].Block + v0 := b.NewValue0(v.Line, OpAMD64MOVWQZXload, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = off + v0.Aux = sym + v0.AddArg(ptr) + v0.AddArg(mem) + return true + } + // match: (MOVWQZX (ANDWconst [c] x)) + // cond: + // result: (ANDQconst [c & 0xffff] x) + for { + if v.Args[0].Op != OpAMD64ANDWconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[0].Args[0] + v.reset(OpAMD64ANDQconst) + v.AuxInt = c & 0xffff + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVWload(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) + // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) + // result: x + for { + off := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64MOVWstore { + break + } + off2 := v.Args[1].AuxInt + sym2 := v.Args[1].Aux + ptr2 := v.Args[1].Args[0] + x := v.Args[1].Args[1] + if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (MOVWload [off1] {sym} (ADDQconst [off2] ptr) mem) + // cond: + // result: (MOVWload [addOff(off1, off2)] {sym} ptr mem) + for { + off1 := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + off2 := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + mem := v.Args[1] + v.reset(OpAMD64MOVWload) + v.AuxInt = addOff(off1, off2) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (MOVWload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVWload [addOff(off1,off2)] {mergeSym(sym1,sym2)} base mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + base := v.Args[0].Args[0] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVWload) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(base) + v.AddArg(mem) + return true + } + // match: (MOVWload [off1] {sym1} (LEAQ2 [off2] {sym2} ptr idx) mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVWloadidx2 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ2 { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + ptr := v.Args[0].Args[0] + idx := v.Args[0].Args[1] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVWloadidx2) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVWloadidx2(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVWloadidx2 [c] {sym} (ADDQconst [d] ptr) idx mem) + // cond: + // result: (MOVWloadidx2 [c+d] {sym} ptr idx mem) + for { + c := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + d := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + idx := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVWloadidx2) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + // match: (MOVWloadidx2 [c] {sym} ptr (ADDQconst [d] idx) mem) + // cond: + // result: (MOVWloadidx2 [c+2*d] {sym} ptr idx mem) + for { + c := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64ADDQconst { + break + } + d := v.Args[1].AuxInt + idx := v.Args[1].Args[0] + mem := v.Args[2] + v.reset(OpAMD64MOVWloadidx2) + v.AuxInt = c + 2*d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVWstore(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVWstore [off] {sym} ptr (MOVWQSX x) mem) + // cond: + // result: (MOVWstore [off] {sym} ptr x mem) + for { + off := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64MOVWQSX { + break + } + x := v.Args[1].Args[0] + mem := v.Args[2] + v.reset(OpAMD64MOVWstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(x) + v.AddArg(mem) + return true + } + // match: (MOVWstore [off] {sym} ptr (MOVWQZX x) mem) + // cond: + // result: (MOVWstore [off] {sym} ptr x mem) + for { + off := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64MOVWQZX { + break + } + x := v.Args[1].Args[0] + mem := v.Args[2] + v.reset(OpAMD64MOVWstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(x) + v.AddArg(mem) + return true + } + // match: (MOVWstore [off1] {sym} (ADDQconst [off2] ptr) val mem) + // cond: + // result: (MOVWstore [addOff(off1, off2)] {sym} ptr val mem) + for { + off1 := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + off2 := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + val := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVWstore) + v.AuxInt = addOff(off1, off2) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (MOVWstore [off] {sym} ptr (MOVWconst [c]) mem) + // cond: validOff(off) + // result: (MOVWstoreconst [makeValAndOff(int64(int16(c)),off)] {sym} ptr mem) + for { + off := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64MOVWconst { + break + } + c := v.Args[1].AuxInt + mem := v.Args[2] + if !(validOff(off)) { + break + } + v.reset(OpAMD64MOVWstoreconst) + v.AuxInt = makeValAndOff(int64(int16(c)), off) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (MOVWstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVWstore [addOff(off1,off2)] {mergeSym(sym1,sym2)} base val mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + base := v.Args[0].Args[0] + val := v.Args[1] + mem := v.Args[2] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVWstore) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(base) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (MOVWstore [off1] {sym1} (LEAQ2 [off2] {sym2} ptr idx) val mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVWstoreidx2 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx val mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ2 { + break + } + off2 := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + ptr := v.Args[0].Args[0] + idx := v.Args[0].Args[1] + val := v.Args[1] + mem := v.Args[2] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVWstoreidx2) + v.AuxInt = addOff(off1, off2) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVWstoreconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVWstoreconst [sc] {s} (ADDQconst [off] ptr) mem) + // cond: ValAndOff(sc).canAdd(off) + // result: (MOVWstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) + for { + sc := v.AuxInt + s := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + off := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + mem := v.Args[1] + if !(ValAndOff(sc).canAdd(off)) { + break + } + v.reset(OpAMD64MOVWstoreconst) + v.AuxInt = ValAndOff(sc).add(off) + v.Aux = s + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (MOVWstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) + // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) + // result: (MOVWstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) + for { + sc := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ { + break + } + off := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + ptr := v.Args[0].Args[0] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { + break + } + v.reset(OpAMD64MOVWstoreconst) + v.AuxInt = ValAndOff(sc).add(off) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (MOVWstoreconst [x] {sym1} (LEAQ2 [off] {sym2} ptr idx) mem) + // cond: canMergeSym(sym1, sym2) + // result: (MOVWstoreconstidx2 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) + for { + x := v.AuxInt + sym1 := v.Aux + if v.Args[0].Op != OpAMD64LEAQ2 { + break + } + off := v.Args[0].AuxInt + sym2 := v.Args[0].Aux + ptr := v.Args[0].Args[0] + idx := v.Args[0].Args[1] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpAMD64MOVWstoreconstidx2) + v.AuxInt = ValAndOff(x).add(off) + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVWstoreconstidx2(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVWstoreconstidx2 [x] {sym} (ADDQconst [c] ptr) idx mem) + // cond: + // result: (MOVWstoreconstidx2 [ValAndOff(x).add(c)] {sym} ptr idx mem) + for { + x := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + c := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + idx := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVWstoreconstidx2) + v.AuxInt = ValAndOff(x).add(c) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + // match: (MOVWstoreconstidx2 [x] {sym} ptr (ADDQconst [c] idx) mem) + // cond: + // result: (MOVWstoreconstidx2 [ValAndOff(x).add(2*c)] {sym} ptr idx mem) + for { + x := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64ADDQconst { + break + } + c := v.Args[1].AuxInt + idx := v.Args[1].Args[0] + mem := v.Args[2] + v.reset(OpAMD64MOVWstoreconstidx2) + v.AuxInt = ValAndOff(x).add(2 * c) + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MOVWstoreidx2(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVWstoreidx2 [c] {sym} (ADDQconst [d] ptr) idx val mem) + // cond: + // result: (MOVWstoreidx2 [c+d] {sym} ptr idx val mem) + for { + c := v.AuxInt + sym := v.Aux + if v.Args[0].Op != OpAMD64ADDQconst { + break + } + d := v.Args[0].AuxInt + ptr := v.Args[0].Args[0] + idx := v.Args[1] + val := v.Args[2] + mem := v.Args[3] + v.reset(OpAMD64MOVWstoreidx2) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (MOVWstoreidx2 [c] {sym} ptr (ADDQconst [d] idx) val mem) + // cond: + // result: (MOVWstoreidx2 [c+2*d] {sym} ptr idx val mem) + for { + c := v.AuxInt + sym := v.Aux + ptr := v.Args[0] + if v.Args[1].Op != OpAMD64ADDQconst { + break + } + d := v.Args[1].AuxInt + idx := v.Args[1].Args[0] + val := v.Args[2] + mem := v.Args[3] + v.reset(OpAMD64MOVWstoreidx2) + v.AuxInt = c + 2*d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MULB(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MULB x (MOVBconst [c])) + // cond: + // result: (MULBconst [c] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVBconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64MULBconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (MULB (MOVBconst [c]) x) + // cond: + // result: (MULBconst [c] x) + for { + if v.Args[0].Op != OpAMD64MOVBconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + v.reset(OpAMD64MULBconst) + v.AuxInt = c + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MULBconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MULBconst [c] (MOVBconst [d])) + // cond: + // result: (MOVBconst [c*d]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVBconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVBconst) + v.AuxInt = c * d + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MULL(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MULL x (MOVLconst [c])) + // cond: + // result: (MULLconst [c] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64MULLconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (MULL (MOVLconst [c]) x) + // cond: + // result: (MULLconst [c] x) + for { + if v.Args[0].Op != OpAMD64MOVLconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + v.reset(OpAMD64MULLconst) + v.AuxInt = c + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MULLconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MULLconst [c] (MOVLconst [d])) + // cond: + // result: (MOVLconst [c*d]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVLconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVLconst) + v.AuxInt = c * d + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MULQ(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MULQ x (MOVQconst [c])) + // cond: is32Bit(c) + // result: (MULQconst [c] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVQconst { + break + } + c := v.Args[1].AuxInt + if !(is32Bit(c)) { + break + } + v.reset(OpAMD64MULQconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (MULQ (MOVQconst [c]) x) + // cond: is32Bit(c) + // result: (MULQconst [c] x) + for { + if v.Args[0].Op != OpAMD64MOVQconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + if !(is32Bit(c)) { + break + } + v.reset(OpAMD64MULQconst) + v.AuxInt = c + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MULQconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MULQconst [-1] x) + // cond: + // result: (NEGQ x) + for { + if v.AuxInt != -1 { + break + } + x := v.Args[0] + v.reset(OpAMD64NEGQ) + v.AddArg(x) + return true + } + // match: (MULQconst [0] _) + // cond: + // result: (MOVQconst [0]) + for { + if v.AuxInt != 0 { + break + } + v.reset(OpAMD64MOVQconst) + v.AuxInt = 0 + return true + } + // match: (MULQconst [1] x) + // cond: + // result: x + for { + if v.AuxInt != 1 { + break + } + x := v.Args[0] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (MULQconst [3] x) + // cond: + // result: (LEAQ2 x x) + for { + if v.AuxInt != 3 { + break + } + x := v.Args[0] + v.reset(OpAMD64LEAQ2) + v.AddArg(x) + v.AddArg(x) + return true + } + // match: (MULQconst [5] x) + // cond: + // result: (LEAQ4 x x) + for { + if v.AuxInt != 5 { + break + } + x := v.Args[0] + v.reset(OpAMD64LEAQ4) + v.AddArg(x) + v.AddArg(x) + return true + } + // match: (MULQconst [9] x) + // cond: + // result: (LEAQ8 x x) + for { + if v.AuxInt != 9 { + break + } + x := v.Args[0] + v.reset(OpAMD64LEAQ8) + v.AddArg(x) + v.AddArg(x) + return true + } + // match: (MULQconst [c] x) + // cond: isPowerOfTwo(c) + // result: (SHLQconst [log2(c)] x) + for { + c := v.AuxInt + x := v.Args[0] + if !(isPowerOfTwo(c)) { + break + } + v.reset(OpAMD64SHLQconst) + v.AuxInt = log2(c) + v.AddArg(x) + return true + } + // match: (MULQconst [c] (MOVQconst [d])) + // cond: + // result: (MOVQconst [c*d]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVQconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVQconst) + v.AuxInt = c * d + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MULW(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MULW x (MOVWconst [c])) + // cond: + // result: (MULWconst [c] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVWconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64MULWconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (MULW (MOVWconst [c]) x) + // cond: + // result: (MULWconst [c] x) + for { + if v.Args[0].Op != OpAMD64MOVWconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + v.reset(OpAMD64MULWconst) + v.AuxInt = c + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64MULWconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MULWconst [c] (MOVWconst [d])) + // cond: + // result: (MOVWconst [c*d]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVWconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVWconst) + v.AuxInt = c * d + return true + } + return false +} +func rewriteValueAMD64_OpMod16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mod16 x y) + // cond: + // result: (MODW x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64MODW) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpMod16u(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mod16u x y) + // cond: + // result: (MODWU x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64MODWU) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpMod32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mod32 x y) + // cond: + // result: (MODL x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64MODL) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpMod32u(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mod32u x y) + // cond: + // result: (MODLU x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64MODLU) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpMod64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mod64 x y) + // cond: + // result: (MODQ x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64MODQ) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpMod64u(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mod64u x y) + // cond: + // result: (MODQU x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64MODQU) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpMod8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mod8 x y) + // cond: + // result: (MODW (SignExt8to16 x) (SignExt8to16 y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64MODW) + v0 := b.NewValue0(v.Line, OpSignExt8to16, config.fe.TypeInt16()) + v0.AddArg(x) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpSignExt8to16, config.fe.TypeInt16()) + v1.AddArg(y) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpMod8u(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mod8u x y) + // cond: + // result: (MODWU (ZeroExt8to16 x) (ZeroExt8to16 y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64MODWU) + v0 := b.NewValue0(v.Line, OpZeroExt8to16, config.fe.TypeUInt16()) + v0.AddArg(x) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpZeroExt8to16, config.fe.TypeUInt16()) + v1.AddArg(y) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpMove(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Move [0] _ _ mem) + // cond: + // result: mem + for { + if v.AuxInt != 0 { + break + } + mem := v.Args[2] + v.reset(OpCopy) + v.Type = mem.Type + v.AddArg(mem) + return true + } + // match: (Move [1] dst src mem) + // cond: + // result: (MOVBstore dst (MOVBload src mem) mem) + for { + if v.AuxInt != 1 { + break + } + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVBstore) + v.AddArg(dst) + v0 := b.NewValue0(v.Line, OpAMD64MOVBload, config.fe.TypeUInt8()) + v0.AddArg(src) + v0.AddArg(mem) + v.AddArg(v0) + v.AddArg(mem) + return true + } + // match: (Move [2] dst src mem) + // cond: + // result: (MOVWstore dst (MOVWload src mem) mem) + for { + if v.AuxInt != 2 { + break + } + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVWstore) + v.AddArg(dst) + v0 := b.NewValue0(v.Line, OpAMD64MOVWload, config.fe.TypeUInt16()) + v0.AddArg(src) + v0.AddArg(mem) + v.AddArg(v0) + v.AddArg(mem) + return true + } + // match: (Move [4] dst src mem) + // cond: + // result: (MOVLstore dst (MOVLload src mem) mem) + for { + if v.AuxInt != 4 { + break + } + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVLstore) + v.AddArg(dst) + v0 := b.NewValue0(v.Line, OpAMD64MOVLload, config.fe.TypeUInt32()) + v0.AddArg(src) + v0.AddArg(mem) + v.AddArg(v0) + v.AddArg(mem) + return true + } + // match: (Move [8] dst src mem) + // cond: + // result: (MOVQstore dst (MOVQload src mem) mem) + for { + if v.AuxInt != 8 { + break + } + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVQstore) + v.AddArg(dst) + v0 := b.NewValue0(v.Line, OpAMD64MOVQload, config.fe.TypeUInt64()) + v0.AddArg(src) + v0.AddArg(mem) + v.AddArg(v0) + v.AddArg(mem) + return true + } + // match: (Move [16] dst src mem) + // cond: + // result: (MOVOstore dst (MOVOload src mem) mem) + for { + if v.AuxInt != 16 { + break + } + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVOstore) + v.AddArg(dst) + v0 := b.NewValue0(v.Line, OpAMD64MOVOload, TypeInt128) + v0.AddArg(src) + v0.AddArg(mem) + v.AddArg(v0) + v.AddArg(mem) + return true + } + // match: (Move [3] dst src mem) + // cond: + // result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVWstore dst (MOVWload src mem) mem)) + for { + if v.AuxInt != 3 { + break + } + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVBstore) + v.AuxInt = 2 + v.AddArg(dst) + v0 := b.NewValue0(v.Line, OpAMD64MOVBload, config.fe.TypeUInt8()) + v0.AuxInt = 2 + v0.AddArg(src) + v0.AddArg(mem) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64MOVWstore, TypeMem) + v1.AddArg(dst) + v2 := b.NewValue0(v.Line, OpAMD64MOVWload, config.fe.TypeUInt16()) + v2.AddArg(src) + v2.AddArg(mem) + v1.AddArg(v2) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + // match: (Move [5] dst src mem) + // cond: + // result: (MOVBstore [4] dst (MOVBload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) + for { + if v.AuxInt != 5 { + break + } + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVBstore) + v.AuxInt = 4 + v.AddArg(dst) + v0 := b.NewValue0(v.Line, OpAMD64MOVBload, config.fe.TypeUInt8()) + v0.AuxInt = 4 + v0.AddArg(src) + v0.AddArg(mem) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64MOVLstore, TypeMem) + v1.AddArg(dst) + v2 := b.NewValue0(v.Line, OpAMD64MOVLload, config.fe.TypeUInt32()) + v2.AddArg(src) + v2.AddArg(mem) + v1.AddArg(v2) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + // match: (Move [6] dst src mem) + // cond: + // result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) + for { + if v.AuxInt != 6 { + break + } + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVWstore) + v.AuxInt = 4 + v.AddArg(dst) + v0 := b.NewValue0(v.Line, OpAMD64MOVWload, config.fe.TypeUInt16()) + v0.AuxInt = 4 + v0.AddArg(src) + v0.AddArg(mem) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64MOVLstore, TypeMem) + v1.AddArg(dst) + v2 := b.NewValue0(v.Line, OpAMD64MOVLload, config.fe.TypeUInt32()) + v2.AddArg(src) + v2.AddArg(mem) + v1.AddArg(v2) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + // match: (Move [7] dst src mem) + // cond: + // result: (MOVLstore [3] dst (MOVLload [3] src mem) (MOVLstore dst (MOVLload src mem) mem)) + for { + if v.AuxInt != 7 { + break + } + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVLstore) + v.AuxInt = 3 + v.AddArg(dst) + v0 := b.NewValue0(v.Line, OpAMD64MOVLload, config.fe.TypeUInt32()) + v0.AuxInt = 3 + v0.AddArg(src) + v0.AddArg(mem) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64MOVLstore, TypeMem) + v1.AddArg(dst) + v2 := b.NewValue0(v.Line, OpAMD64MOVLload, config.fe.TypeUInt32()) + v2.AddArg(src) + v2.AddArg(mem) + v1.AddArg(v2) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + // match: (Move [size] dst src mem) + // cond: size > 8 && size < 16 + // result: (MOVQstore [size-8] dst (MOVQload [size-8] src mem) (MOVQstore dst (MOVQload src mem) mem)) + for { + size := v.AuxInt + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + if !(size > 8 && size < 16) { + break + } + v.reset(OpAMD64MOVQstore) + v.AuxInt = size - 8 + v.AddArg(dst) + v0 := b.NewValue0(v.Line, OpAMD64MOVQload, config.fe.TypeUInt64()) + v0.AuxInt = size - 8 + v0.AddArg(src) + v0.AddArg(mem) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64MOVQstore, TypeMem) + v1.AddArg(dst) + v2 := b.NewValue0(v.Line, OpAMD64MOVQload, config.fe.TypeUInt64()) + v2.AddArg(src) + v2.AddArg(mem) + v1.AddArg(v2) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + // match: (Move [size] dst src mem) + // cond: size > 16 && size%16 != 0 && size%16 <= 8 + // result: (Move [size-size%16] (ADDQconst <dst.Type> dst [size%16]) (ADDQconst <src.Type> src [size%16]) (MOVQstore dst (MOVQload src mem) mem)) + for { + size := v.AuxInt + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + if !(size > 16 && size%16 != 0 && size%16 <= 8) { + break + } + v.reset(OpMove) + v.AuxInt = size - size%16 + v0 := b.NewValue0(v.Line, OpAMD64ADDQconst, dst.Type) + v0.AddArg(dst) + v0.AuxInt = size % 16 + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64ADDQconst, src.Type) + v1.AddArg(src) + v1.AuxInt = size % 16 + v.AddArg(v1) + v2 := b.NewValue0(v.Line, OpAMD64MOVQstore, TypeMem) + v2.AddArg(dst) + v3 := b.NewValue0(v.Line, OpAMD64MOVQload, config.fe.TypeUInt64()) + v3.AddArg(src) + v3.AddArg(mem) + v2.AddArg(v3) + v2.AddArg(mem) + v.AddArg(v2) + return true + } + // match: (Move [size] dst src mem) + // cond: size > 16 && size%16 != 0 && size%16 > 8 + // result: (Move [size-size%16] (ADDQconst <dst.Type> dst [size%16]) (ADDQconst <src.Type> src [size%16]) (MOVOstore dst (MOVOload src mem) mem)) + for { + size := v.AuxInt + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + if !(size > 16 && size%16 != 0 && size%16 > 8) { + break + } + v.reset(OpMove) + v.AuxInt = size - size%16 + v0 := b.NewValue0(v.Line, OpAMD64ADDQconst, dst.Type) + v0.AddArg(dst) + v0.AuxInt = size % 16 + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64ADDQconst, src.Type) + v1.AddArg(src) + v1.AuxInt = size % 16 + v.AddArg(v1) + v2 := b.NewValue0(v.Line, OpAMD64MOVOstore, TypeMem) + v2.AddArg(dst) + v3 := b.NewValue0(v.Line, OpAMD64MOVOload, TypeInt128) + v3.AddArg(src) + v3.AddArg(mem) + v2.AddArg(v3) + v2.AddArg(mem) + v.AddArg(v2) + return true + } + // match: (Move [size] dst src mem) + // cond: size >= 32 && size <= 16*64 && size%16 == 0 + // result: (DUFFCOPY [14*(64-size/16)] dst src mem) + for { + size := v.AuxInt + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + if !(size >= 32 && size <= 16*64 && size%16 == 0) { + break + } + v.reset(OpAMD64DUFFCOPY) + v.AuxInt = 14 * (64 - size/16) + v.AddArg(dst) + v.AddArg(src) + v.AddArg(mem) + return true + } + // match: (Move [size] dst src mem) + // cond: size > 16*64 && size%8 == 0 + // result: (REPMOVSQ dst src (MOVQconst [size/8]) mem) + for { + size := v.AuxInt + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + if !(size > 16*64 && size%8 == 0) { + break + } + v.reset(OpAMD64REPMOVSQ) + v.AddArg(dst) + v.AddArg(src) + v0 := b.NewValue0(v.Line, OpAMD64MOVQconst, config.fe.TypeUInt64()) + v0.AuxInt = size / 8 + v.AddArg(v0) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpMul16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mul16 x y) + // cond: + // result: (MULW x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64MULW) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpMul32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mul32 x y) + // cond: + // result: (MULL x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64MULL) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpMul32F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mul32F x y) + // cond: + // result: (MULSS x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64MULSS) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpMul64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mul64 x y) + // cond: + // result: (MULQ x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64MULQ) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpMul64F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mul64F x y) + // cond: + // result: (MULSD x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64MULSD) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpMul8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mul8 x y) + // cond: + // result: (MULB x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64MULB) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64NEGB(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (NEGB (MOVBconst [c])) + // cond: + // result: (MOVBconst [-c]) + for { + if v.Args[0].Op != OpAMD64MOVBconst { + break + } + c := v.Args[0].AuxInt + v.reset(OpAMD64MOVBconst) + v.AuxInt = -c + return true + } + return false +} +func rewriteValueAMD64_OpAMD64NEGL(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (NEGL (MOVLconst [c])) + // cond: + // result: (MOVLconst [-c]) + for { + if v.Args[0].Op != OpAMD64MOVLconst { + break + } + c := v.Args[0].AuxInt + v.reset(OpAMD64MOVLconst) + v.AuxInt = -c + return true + } + return false +} +func rewriteValueAMD64_OpAMD64NEGQ(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (NEGQ (MOVQconst [c])) + // cond: + // result: (MOVQconst [-c]) + for { + if v.Args[0].Op != OpAMD64MOVQconst { + break + } + c := v.Args[0].AuxInt + v.reset(OpAMD64MOVQconst) + v.AuxInt = -c + return true + } + return false +} +func rewriteValueAMD64_OpAMD64NEGW(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (NEGW (MOVWconst [c])) + // cond: + // result: (MOVWconst [-c]) + for { + if v.Args[0].Op != OpAMD64MOVWconst { + break + } + c := v.Args[0].AuxInt + v.reset(OpAMD64MOVWconst) + v.AuxInt = -c + return true + } + return false +} +func rewriteValueAMD64_OpAMD64NOTB(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (NOTB (MOVBconst [c])) + // cond: + // result: (MOVBconst [^c]) + for { + if v.Args[0].Op != OpAMD64MOVBconst { + break + } + c := v.Args[0].AuxInt + v.reset(OpAMD64MOVBconst) + v.AuxInt = ^c + return true + } + return false +} +func rewriteValueAMD64_OpAMD64NOTL(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (NOTL (MOVLconst [c])) + // cond: + // result: (MOVLconst [^c]) + for { + if v.Args[0].Op != OpAMD64MOVLconst { + break + } + c := v.Args[0].AuxInt + v.reset(OpAMD64MOVLconst) + v.AuxInt = ^c + return true + } + return false +} +func rewriteValueAMD64_OpAMD64NOTQ(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (NOTQ (MOVQconst [c])) + // cond: + // result: (MOVQconst [^c]) + for { + if v.Args[0].Op != OpAMD64MOVQconst { + break + } + c := v.Args[0].AuxInt + v.reset(OpAMD64MOVQconst) + v.AuxInt = ^c + return true + } + return false +} +func rewriteValueAMD64_OpAMD64NOTW(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (NOTW (MOVWconst [c])) + // cond: + // result: (MOVWconst [^c]) + for { + if v.Args[0].Op != OpAMD64MOVWconst { + break + } + c := v.Args[0].AuxInt + v.reset(OpAMD64MOVWconst) + v.AuxInt = ^c + return true + } + return false +} +func rewriteValueAMD64_OpNeg16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neg16 x) + // cond: + // result: (NEGW x) + for { + x := v.Args[0] + v.reset(OpAMD64NEGW) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpNeg32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neg32 x) + // cond: + // result: (NEGL x) + for { + x := v.Args[0] + v.reset(OpAMD64NEGL) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpNeg32F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neg32F x) + // cond: + // result: (PXOR x (MOVSSconst <config.Frontend().TypeFloat32()> [f2i(math.Copysign(0, -1))])) + for { + x := v.Args[0] + v.reset(OpAMD64PXOR) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpAMD64MOVSSconst, config.Frontend().TypeFloat32()) + v0.AuxInt = f2i(math.Copysign(0, -1)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpNeg64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neg64 x) + // cond: + // result: (NEGQ x) + for { + x := v.Args[0] + v.reset(OpAMD64NEGQ) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpNeg64F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neg64F x) + // cond: + // result: (PXOR x (MOVSDconst <config.Frontend().TypeFloat64()> [f2i(math.Copysign(0, -1))])) + for { + x := v.Args[0] + v.reset(OpAMD64PXOR) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpAMD64MOVSDconst, config.Frontend().TypeFloat64()) + v0.AuxInt = f2i(math.Copysign(0, -1)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpNeg8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neg8 x) + // cond: + // result: (NEGB x) + for { + x := v.Args[0] + v.reset(OpAMD64NEGB) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpNeq16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neq16 x y) + // cond: + // result: (SETNE (CMPW x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETNE) + v0 := b.NewValue0(v.Line, OpAMD64CMPW, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpNeq32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neq32 x y) + // cond: + // result: (SETNE (CMPL x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETNE) + v0 := b.NewValue0(v.Line, OpAMD64CMPL, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpNeq32F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neq32F x y) + // cond: + // result: (SETNEF (UCOMISS x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETNEF) + v0 := b.NewValue0(v.Line, OpAMD64UCOMISS, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpNeq64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neq64 x y) + // cond: + // result: (SETNE (CMPQ x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETNE) + v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpNeq64F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neq64F x y) + // cond: + // result: (SETNEF (UCOMISD x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETNEF) + v0 := b.NewValue0(v.Line, OpAMD64UCOMISD, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpNeq8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neq8 x y) + // cond: + // result: (SETNE (CMPB x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETNE) + v0 := b.NewValue0(v.Line, OpAMD64CMPB, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpNeqPtr(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (NeqPtr x y) + // cond: + // result: (SETNE (CMPQ x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SETNE) + v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpNilCheck(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (NilCheck ptr mem) + // cond: + // result: (LoweredNilCheck ptr mem) + for { + ptr := v.Args[0] + mem := v.Args[1] + v.reset(OpAMD64LoweredNilCheck) + v.AddArg(ptr) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpNot(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Not x) + // cond: + // result: (XORBconst [1] x) + for { + x := v.Args[0] + v.reset(OpAMD64XORBconst) + v.AuxInt = 1 + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ORB(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ORB x (MOVBconst [c])) + // cond: + // result: (ORBconst [c] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVBconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64ORBconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ORB (MOVBconst [c]) x) + // cond: + // result: (ORBconst [c] x) + for { + if v.Args[0].Op != OpAMD64MOVBconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + v.reset(OpAMD64ORBconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ORB x x) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ORBconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ORBconst [c] x) + // cond: int8(c)==0 + // result: x + for { + c := v.AuxInt + x := v.Args[0] + if !(int8(c) == 0) { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (ORBconst [c] _) + // cond: int8(c)==-1 + // result: (MOVBconst [-1]) + for { + c := v.AuxInt + if !(int8(c) == -1) { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = -1 + return true + } + // match: (ORBconst [c] (MOVBconst [d])) + // cond: + // result: (MOVBconst [c|d]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVBconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVBconst) + v.AuxInt = c | d + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ORL(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ORL x (MOVLconst [c])) + // cond: + // result: (ORLconst [c] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64ORLconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ORL (MOVLconst [c]) x) + // cond: + // result: (ORLconst [c] x) + for { + if v.Args[0].Op != OpAMD64MOVLconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + v.reset(OpAMD64ORLconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ORL x x) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ORLconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ORLconst [c] x) + // cond: int32(c)==0 + // result: x + for { + c := v.AuxInt + x := v.Args[0] + if !(int32(c) == 0) { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (ORLconst [c] _) + // cond: int32(c)==-1 + // result: (MOVLconst [-1]) + for { + c := v.AuxInt + if !(int32(c) == -1) { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = -1 + return true + } + // match: (ORLconst [c] (MOVLconst [d])) + // cond: + // result: (MOVLconst [c|d]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVLconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVLconst) + v.AuxInt = c | d + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ORQ(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ORQ x (MOVQconst [c])) + // cond: is32Bit(c) + // result: (ORQconst [c] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVQconst { + break + } + c := v.Args[1].AuxInt + if !(is32Bit(c)) { + break + } + v.reset(OpAMD64ORQconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ORQ (MOVQconst [c]) x) + // cond: is32Bit(c) + // result: (ORQconst [c] x) + for { + if v.Args[0].Op != OpAMD64MOVQconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + if !(is32Bit(c)) { + break + } + v.reset(OpAMD64ORQconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ORQ x x) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ORQconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ORQconst [0] x) + // cond: + // result: x + for { + if v.AuxInt != 0 { + break + } + x := v.Args[0] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (ORQconst [-1] _) + // cond: + // result: (MOVQconst [-1]) + for { + if v.AuxInt != -1 { + break + } + v.reset(OpAMD64MOVQconst) + v.AuxInt = -1 + return true + } + // match: (ORQconst [c] (MOVQconst [d])) + // cond: + // result: (MOVQconst [c|d]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVQconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVQconst) + v.AuxInt = c | d + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ORW(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ORW x (MOVWconst [c])) + // cond: + // result: (ORWconst [c] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVWconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64ORWconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ORW (MOVWconst [c]) x) + // cond: + // result: (ORWconst [c] x) + for { + if v.Args[0].Op != OpAMD64MOVWconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + v.reset(OpAMD64ORWconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (ORW x x) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64ORWconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ORWconst [c] x) + // cond: int16(c)==0 + // result: x + for { + c := v.AuxInt + x := v.Args[0] + if !(int16(c) == 0) { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (ORWconst [c] _) + // cond: int16(c)==-1 + // result: (MOVWconst [-1]) + for { + c := v.AuxInt + if !(int16(c) == -1) { + break + } + v.reset(OpAMD64MOVWconst) + v.AuxInt = -1 + return true + } + // match: (ORWconst [c] (MOVWconst [d])) + // cond: + // result: (MOVWconst [c|d]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVWconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVWconst) + v.AuxInt = c | d + return true + } + return false +} +func rewriteValueAMD64_OpOffPtr(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (OffPtr [off] ptr) + // cond: + // result: (ADDQconst [off] ptr) + for { + off := v.AuxInt + ptr := v.Args[0] + v.reset(OpAMD64ADDQconst) + v.AuxInt = off + v.AddArg(ptr) + return true + } + return false +} +func rewriteValueAMD64_OpOr16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Or16 x y) + // cond: + // result: (ORW x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ORW) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpOr32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Or32 x y) + // cond: + // result: (ORL x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ORL) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpOr64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Or64 x y) + // cond: + // result: (ORQ x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ORQ) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpOr8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Or8 x y) + // cond: + // result: (ORB x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ORB) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpRsh16Ux16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh16Ux16 <t> x y) + // cond: + // result: (ANDW (SHRW <t> x y) (SBBLcarrymask <t> (CMPWconst y [16]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDW) + v0 := b.NewValue0(v.Line, OpAMD64SHRW, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 16 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpRsh16Ux32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh16Ux32 <t> x y) + // cond: + // result: (ANDW (SHRW <t> x y) (SBBLcarrymask <t> (CMPLconst y [16]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDW) + v0 := b.NewValue0(v.Line, OpAMD64SHRW, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 16 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpRsh16Ux64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh16Ux64 <t> x y) + // cond: + // result: (ANDW (SHRW <t> x y) (SBBLcarrymask <t> (CMPQconst y [16]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDW) + v0 := b.NewValue0(v.Line, OpAMD64SHRW, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 16 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpRsh16Ux8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh16Ux8 <t> x y) + // cond: + // result: (ANDW (SHRW <t> x y) (SBBLcarrymask <t> (CMPBconst y [16]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDW) + v0 := b.NewValue0(v.Line, OpAMD64SHRW, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 16 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpRsh16x16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh16x16 <t> x y) + // cond: + // result: (SARW <t> x (ORW <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [16]))))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SARW) + v.Type = t + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpAMD64ORW, y.Type) + v0.AddArg(y) + v1 := b.NewValue0(v.Line, OpAMD64NOTL, y.Type) + v2 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, y.Type) + v3 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeFlags) + v3.AddArg(y) + v3.AuxInt = 16 + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpRsh16x32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh16x32 <t> x y) + // cond: + // result: (SARW <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [16]))))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SARW) + v.Type = t + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpAMD64ORL, y.Type) + v0.AddArg(y) + v1 := b.NewValue0(v.Line, OpAMD64NOTL, y.Type) + v2 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, y.Type) + v3 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeFlags) + v3.AddArg(y) + v3.AuxInt = 16 + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpRsh16x64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh16x64 <t> x y) + // cond: + // result: (SARW <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [16]))))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SARW) + v.Type = t + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpAMD64ORQ, y.Type) + v0.AddArg(y) + v1 := b.NewValue0(v.Line, OpAMD64NOTQ, y.Type) + v2 := b.NewValue0(v.Line, OpAMD64SBBQcarrymask, y.Type) + v3 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeFlags) + v3.AddArg(y) + v3.AuxInt = 16 + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpRsh16x8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh16x8 <t> x y) + // cond: + // result: (SARW <t> x (ORB <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [16]))))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SARW) + v.Type = t + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpAMD64ORB, y.Type) + v0.AddArg(y) + v1 := b.NewValue0(v.Line, OpAMD64NOTL, y.Type) + v2 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, y.Type) + v3 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeFlags) + v3.AddArg(y) + v3.AuxInt = 16 + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpRsh32Ux16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh32Ux16 <t> x y) + // cond: + // result: (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Line, OpAMD64SHRL, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 32 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpRsh32Ux32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh32Ux32 <t> x y) + // cond: + // result: (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Line, OpAMD64SHRL, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 32 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpRsh32Ux64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh32Ux64 <t> x y) + // cond: + // result: (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPQconst y [32]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Line, OpAMD64SHRL, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 32 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpRsh32Ux8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh32Ux8 <t> x y) + // cond: + // result: (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Line, OpAMD64SHRL, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 32 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpRsh32x16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh32x16 <t> x y) + // cond: + // result: (SARL <t> x (ORW <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [32]))))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SARL) + v.Type = t + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpAMD64ORW, y.Type) + v0.AddArg(y) + v1 := b.NewValue0(v.Line, OpAMD64NOTL, y.Type) + v2 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, y.Type) + v3 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeFlags) + v3.AddArg(y) + v3.AuxInt = 32 + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpRsh32x32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh32x32 <t> x y) + // cond: + // result: (SARL <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [32]))))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SARL) + v.Type = t + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpAMD64ORL, y.Type) + v0.AddArg(y) + v1 := b.NewValue0(v.Line, OpAMD64NOTL, y.Type) + v2 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, y.Type) + v3 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeFlags) + v3.AddArg(y) + v3.AuxInt = 32 + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpRsh32x64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh32x64 <t> x y) + // cond: + // result: (SARL <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [32]))))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SARL) + v.Type = t + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpAMD64ORQ, y.Type) + v0.AddArg(y) + v1 := b.NewValue0(v.Line, OpAMD64NOTQ, y.Type) + v2 := b.NewValue0(v.Line, OpAMD64SBBQcarrymask, y.Type) + v3 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeFlags) + v3.AddArg(y) + v3.AuxInt = 32 + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpRsh32x8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh32x8 <t> x y) + // cond: + // result: (SARL <t> x (ORB <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [32]))))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SARL) + v.Type = t + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpAMD64ORB, y.Type) + v0.AddArg(y) + v1 := b.NewValue0(v.Line, OpAMD64NOTL, y.Type) + v2 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, y.Type) + v3 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeFlags) + v3.AddArg(y) + v3.AuxInt = 32 + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpRsh64Ux16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh64Ux16 <t> x y) + // cond: + // result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPWconst y [64]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDQ) + v0 := b.NewValue0(v.Line, OpAMD64SHRQ, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBQcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 64 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpRsh64Ux32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh64Ux32 <t> x y) + // cond: + // result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPLconst y [64]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDQ) + v0 := b.NewValue0(v.Line, OpAMD64SHRQ, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBQcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 64 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpRsh64Ux64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh64Ux64 <t> x y) + // cond: + // result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPQconst y [64]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDQ) + v0 := b.NewValue0(v.Line, OpAMD64SHRQ, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBQcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 64 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpRsh64Ux8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh64Ux8 <t> x y) + // cond: + // result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPBconst y [64]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDQ) + v0 := b.NewValue0(v.Line, OpAMD64SHRQ, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBQcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 64 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpRsh64x16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh64x16 <t> x y) + // cond: + // result: (SARQ <t> x (ORW <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [64]))))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SARQ) + v.Type = t + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpAMD64ORW, y.Type) + v0.AddArg(y) + v1 := b.NewValue0(v.Line, OpAMD64NOTL, y.Type) + v2 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, y.Type) + v3 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeFlags) + v3.AddArg(y) + v3.AuxInt = 64 + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpRsh64x32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh64x32 <t> x y) + // cond: + // result: (SARQ <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [64]))))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SARQ) + v.Type = t + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpAMD64ORL, y.Type) + v0.AddArg(y) + v1 := b.NewValue0(v.Line, OpAMD64NOTL, y.Type) + v2 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, y.Type) + v3 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeFlags) + v3.AddArg(y) + v3.AuxInt = 64 + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpRsh64x64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh64x64 <t> x y) + // cond: + // result: (SARQ <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [64]))))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SARQ) + v.Type = t + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpAMD64ORQ, y.Type) + v0.AddArg(y) + v1 := b.NewValue0(v.Line, OpAMD64NOTQ, y.Type) + v2 := b.NewValue0(v.Line, OpAMD64SBBQcarrymask, y.Type) + v3 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeFlags) + v3.AddArg(y) + v3.AuxInt = 64 + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpRsh64x8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh64x8 <t> x y) + // cond: + // result: (SARQ <t> x (ORB <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [64]))))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SARQ) + v.Type = t + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpAMD64ORB, y.Type) + v0.AddArg(y) + v1 := b.NewValue0(v.Line, OpAMD64NOTL, y.Type) + v2 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, y.Type) + v3 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeFlags) + v3.AddArg(y) + v3.AuxInt = 64 + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpRsh8Ux16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh8Ux16 <t> x y) + // cond: + // result: (ANDB (SHRB <t> x y) (SBBLcarrymask <t> (CMPWconst y [8]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDB) + v0 := b.NewValue0(v.Line, OpAMD64SHRB, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 8 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpRsh8Ux32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh8Ux32 <t> x y) + // cond: + // result: (ANDB (SHRB <t> x y) (SBBLcarrymask <t> (CMPLconst y [8]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDB) + v0 := b.NewValue0(v.Line, OpAMD64SHRB, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 8 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpRsh8Ux64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh8Ux64 <t> x y) + // cond: + // result: (ANDB (SHRB <t> x y) (SBBLcarrymask <t> (CMPQconst y [8]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDB) + v0 := b.NewValue0(v.Line, OpAMD64SHRB, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 8 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpRsh8Ux8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh8Ux8 <t> x y) + // cond: + // result: (ANDB (SHRB <t> x y) (SBBLcarrymask <t> (CMPBconst y [8]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64ANDB) + v0 := b.NewValue0(v.Line, OpAMD64SHRB, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeFlags) + v2.AddArg(y) + v2.AuxInt = 8 + v1.AddArg(v2) + v.AddArg(v1) + return true + } + return false +} +func rewriteValueAMD64_OpRsh8x16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh8x16 <t> x y) + // cond: + // result: (SARB <t> x (ORW <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [8]))))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SARB) + v.Type = t + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpAMD64ORW, y.Type) + v0.AddArg(y) + v1 := b.NewValue0(v.Line, OpAMD64NOTL, y.Type) + v2 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, y.Type) + v3 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeFlags) + v3.AddArg(y) + v3.AuxInt = 8 + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpRsh8x32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh8x32 <t> x y) + // cond: + // result: (SARB <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [8]))))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SARB) + v.Type = t + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpAMD64ORL, y.Type) + v0.AddArg(y) + v1 := b.NewValue0(v.Line, OpAMD64NOTL, y.Type) + v2 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, y.Type) + v3 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeFlags) + v3.AddArg(y) + v3.AuxInt = 8 + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpRsh8x64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh8x64 <t> x y) + // cond: + // result: (SARB <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [8]))))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SARB) + v.Type = t + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpAMD64ORQ, y.Type) + v0.AddArg(y) + v1 := b.NewValue0(v.Line, OpAMD64NOTQ, y.Type) + v2 := b.NewValue0(v.Line, OpAMD64SBBQcarrymask, y.Type) + v3 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeFlags) + v3.AddArg(y) + v3.AuxInt = 8 + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpRsh8x8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh8x8 <t> x y) + // cond: + // result: (SARB <t> x (ORB <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [8]))))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SARB) + v.Type = t + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpAMD64ORB, y.Type) + v0.AddArg(y) + v1 := b.NewValue0(v.Line, OpAMD64NOTL, y.Type) + v2 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, y.Type) + v3 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeFlags) + v3.AddArg(y) + v3.AuxInt = 8 + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SARB(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SARB x (MOVQconst [c])) + // cond: + // result: (SARBconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVQconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SARBconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SARB x (MOVLconst [c])) + // cond: + // result: (SARBconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SARBconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SARB x (MOVWconst [c])) + // cond: + // result: (SARBconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVWconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SARBconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SARB x (MOVBconst [c])) + // cond: + // result: (SARBconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVBconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SARBconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SARBconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SARBconst [c] (MOVQconst [d])) + // cond: + // result: (MOVQconst [d>>uint64(c)]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVQconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVQconst) + v.AuxInt = d >> uint64(c) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SARL(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SARL x (MOVQconst [c])) + // cond: + // result: (SARLconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVQconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SARLconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SARL x (MOVLconst [c])) + // cond: + // result: (SARLconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SARLconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SARL x (MOVWconst [c])) + // cond: + // result: (SARLconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVWconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SARLconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SARL x (MOVBconst [c])) + // cond: + // result: (SARLconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVBconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SARLconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SARLconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SARLconst [c] (MOVQconst [d])) + // cond: + // result: (MOVQconst [d>>uint64(c)]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVQconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVQconst) + v.AuxInt = d >> uint64(c) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SARQ(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SARQ x (MOVQconst [c])) + // cond: + // result: (SARQconst [c&63] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVQconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SARQconst) + v.AuxInt = c & 63 + v.AddArg(x) + return true + } + // match: (SARQ x (MOVLconst [c])) + // cond: + // result: (SARQconst [c&63] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SARQconst) + v.AuxInt = c & 63 + v.AddArg(x) + return true + } + // match: (SARQ x (MOVWconst [c])) + // cond: + // result: (SARQconst [c&63] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVWconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SARQconst) + v.AuxInt = c & 63 + v.AddArg(x) + return true + } + // match: (SARQ x (MOVBconst [c])) + // cond: + // result: (SARQconst [c&63] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVBconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SARQconst) + v.AuxInt = c & 63 + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SARQconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SARQconst [c] (MOVQconst [d])) + // cond: + // result: (MOVQconst [d>>uint64(c)]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVQconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVQconst) + v.AuxInt = d >> uint64(c) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SARW(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SARW x (MOVQconst [c])) + // cond: + // result: (SARWconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVQconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SARWconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SARW x (MOVLconst [c])) + // cond: + // result: (SARWconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SARWconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SARW x (MOVWconst [c])) + // cond: + // result: (SARWconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVWconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SARWconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SARW x (MOVBconst [c])) + // cond: + // result: (SARWconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVBconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SARWconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SARWconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SARWconst [c] (MOVQconst [d])) + // cond: + // result: (MOVQconst [d>>uint64(c)]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVQconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVQconst) + v.AuxInt = d >> uint64(c) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SBBLcarrymask(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SBBLcarrymask (FlagEQ)) + // cond: + // result: (MOVLconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagEQ { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = 0 + return true + } + // match: (SBBLcarrymask (FlagLT_ULT)) + // cond: + // result: (MOVLconst [-1]) + for { + if v.Args[0].Op != OpAMD64FlagLT_ULT { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = -1 + return true + } + // match: (SBBLcarrymask (FlagLT_UGT)) + // cond: + // result: (MOVLconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagLT_UGT { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = 0 + return true + } + // match: (SBBLcarrymask (FlagGT_ULT)) + // cond: + // result: (MOVLconst [-1]) + for { + if v.Args[0].Op != OpAMD64FlagGT_ULT { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = -1 + return true + } + // match: (SBBLcarrymask (FlagGT_UGT)) + // cond: + // result: (MOVLconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagGT_UGT { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SBBQcarrymask(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SBBQcarrymask (FlagEQ)) + // cond: + // result: (MOVQconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagEQ { + break + } + v.reset(OpAMD64MOVQconst) + v.AuxInt = 0 + return true + } + // match: (SBBQcarrymask (FlagLT_ULT)) + // cond: + // result: (MOVQconst [-1]) + for { + if v.Args[0].Op != OpAMD64FlagLT_ULT { + break + } + v.reset(OpAMD64MOVQconst) + v.AuxInt = -1 + return true + } + // match: (SBBQcarrymask (FlagLT_UGT)) + // cond: + // result: (MOVQconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagLT_UGT { + break + } + v.reset(OpAMD64MOVQconst) + v.AuxInt = 0 + return true + } + // match: (SBBQcarrymask (FlagGT_ULT)) + // cond: + // result: (MOVQconst [-1]) + for { + if v.Args[0].Op != OpAMD64FlagGT_ULT { + break + } + v.reset(OpAMD64MOVQconst) + v.AuxInt = -1 + return true + } + // match: (SBBQcarrymask (FlagGT_UGT)) + // cond: + // result: (MOVQconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagGT_UGT { + break + } + v.reset(OpAMD64MOVQconst) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SETA(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SETA (InvertFlags x)) + // cond: + // result: (SETB x) + for { + if v.Args[0].Op != OpAMD64InvertFlags { + break + } + x := v.Args[0].Args[0] + v.reset(OpAMD64SETB) + v.AddArg(x) + return true + } + // match: (SETA (FlagEQ)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagEQ { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + // match: (SETA (FlagLT_ULT)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagLT_ULT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + // match: (SETA (FlagLT_UGT)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagLT_UGT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + // match: (SETA (FlagGT_ULT)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagGT_ULT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + // match: (SETA (FlagGT_UGT)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagGT_UGT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SETAE(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SETAE (InvertFlags x)) + // cond: + // result: (SETBE x) + for { + if v.Args[0].Op != OpAMD64InvertFlags { + break + } + x := v.Args[0].Args[0] + v.reset(OpAMD64SETBE) + v.AddArg(x) + return true + } + // match: (SETAE (FlagEQ)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagEQ { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + // match: (SETAE (FlagLT_ULT)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagLT_ULT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + // match: (SETAE (FlagLT_UGT)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagLT_UGT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + // match: (SETAE (FlagGT_ULT)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagGT_ULT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + // match: (SETAE (FlagGT_UGT)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagGT_UGT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SETB(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SETB (InvertFlags x)) + // cond: + // result: (SETA x) + for { + if v.Args[0].Op != OpAMD64InvertFlags { + break + } + x := v.Args[0].Args[0] + v.reset(OpAMD64SETA) + v.AddArg(x) + return true + } + // match: (SETB (FlagEQ)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagEQ { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + // match: (SETB (FlagLT_ULT)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagLT_ULT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + // match: (SETB (FlagLT_UGT)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagLT_UGT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + // match: (SETB (FlagGT_ULT)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagGT_ULT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + // match: (SETB (FlagGT_UGT)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagGT_UGT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SETBE(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SETBE (InvertFlags x)) + // cond: + // result: (SETAE x) + for { + if v.Args[0].Op != OpAMD64InvertFlags { + break + } + x := v.Args[0].Args[0] + v.reset(OpAMD64SETAE) + v.AddArg(x) + return true + } + // match: (SETBE (FlagEQ)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagEQ { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + // match: (SETBE (FlagLT_ULT)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagLT_ULT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + // match: (SETBE (FlagLT_UGT)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagLT_UGT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + // match: (SETBE (FlagGT_ULT)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagGT_ULT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + // match: (SETBE (FlagGT_UGT)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagGT_UGT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SETEQ(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SETEQ (InvertFlags x)) + // cond: + // result: (SETEQ x) + for { + if v.Args[0].Op != OpAMD64InvertFlags { + break + } + x := v.Args[0].Args[0] + v.reset(OpAMD64SETEQ) + v.AddArg(x) + return true + } + // match: (SETEQ (FlagEQ)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagEQ { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + // match: (SETEQ (FlagLT_ULT)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagLT_ULT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + // match: (SETEQ (FlagLT_UGT)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagLT_UGT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + // match: (SETEQ (FlagGT_ULT)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagGT_ULT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + // match: (SETEQ (FlagGT_UGT)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagGT_UGT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SETG(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SETG (InvertFlags x)) + // cond: + // result: (SETL x) + for { + if v.Args[0].Op != OpAMD64InvertFlags { + break + } + x := v.Args[0].Args[0] + v.reset(OpAMD64SETL) + v.AddArg(x) + return true + } + // match: (SETG (FlagEQ)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagEQ { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + // match: (SETG (FlagLT_ULT)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagLT_ULT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + // match: (SETG (FlagLT_UGT)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagLT_UGT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + // match: (SETG (FlagGT_ULT)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagGT_ULT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + // match: (SETG (FlagGT_UGT)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagGT_UGT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SETGE(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SETGE (InvertFlags x)) + // cond: + // result: (SETLE x) + for { + if v.Args[0].Op != OpAMD64InvertFlags { + break + } + x := v.Args[0].Args[0] + v.reset(OpAMD64SETLE) + v.AddArg(x) + return true + } + // match: (SETGE (FlagEQ)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagEQ { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + // match: (SETGE (FlagLT_ULT)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagLT_ULT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + // match: (SETGE (FlagLT_UGT)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagLT_UGT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + // match: (SETGE (FlagGT_ULT)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagGT_ULT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + // match: (SETGE (FlagGT_UGT)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagGT_UGT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SETL(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SETL (InvertFlags x)) + // cond: + // result: (SETG x) + for { + if v.Args[0].Op != OpAMD64InvertFlags { + break + } + x := v.Args[0].Args[0] + v.reset(OpAMD64SETG) + v.AddArg(x) + return true + } + // match: (SETL (FlagEQ)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagEQ { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + // match: (SETL (FlagLT_ULT)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagLT_ULT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + // match: (SETL (FlagLT_UGT)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagLT_UGT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + // match: (SETL (FlagGT_ULT)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagGT_ULT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + // match: (SETL (FlagGT_UGT)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagGT_UGT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SETLE(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SETLE (InvertFlags x)) + // cond: + // result: (SETGE x) + for { + if v.Args[0].Op != OpAMD64InvertFlags { + break + } + x := v.Args[0].Args[0] + v.reset(OpAMD64SETGE) + v.AddArg(x) + return true + } + // match: (SETLE (FlagEQ)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagEQ { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + // match: (SETLE (FlagLT_ULT)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagLT_ULT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + // match: (SETLE (FlagLT_UGT)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagLT_UGT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + // match: (SETLE (FlagGT_ULT)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagGT_ULT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + // match: (SETLE (FlagGT_UGT)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagGT_UGT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SETNE(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SETNE (InvertFlags x)) + // cond: + // result: (SETNE x) + for { + if v.Args[0].Op != OpAMD64InvertFlags { + break + } + x := v.Args[0].Args[0] + v.reset(OpAMD64SETNE) + v.AddArg(x) + return true + } + // match: (SETNE (FlagEQ)) + // cond: + // result: (MOVBconst [0]) + for { + if v.Args[0].Op != OpAMD64FlagEQ { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + // match: (SETNE (FlagLT_ULT)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagLT_ULT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + // match: (SETNE (FlagLT_UGT)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagLT_UGT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + // match: (SETNE (FlagGT_ULT)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagGT_ULT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + // match: (SETNE (FlagGT_UGT)) + // cond: + // result: (MOVBconst [1]) + for { + if v.Args[0].Op != OpAMD64FlagGT_UGT { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 1 + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SHLB(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SHLB x (MOVQconst [c])) + // cond: + // result: (SHLBconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVQconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHLBconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SHLB x (MOVLconst [c])) + // cond: + // result: (SHLBconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHLBconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SHLB x (MOVWconst [c])) + // cond: + // result: (SHLBconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVWconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHLBconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SHLB x (MOVBconst [c])) + // cond: + // result: (SHLBconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVBconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHLBconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SHLL(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SHLL x (MOVQconst [c])) + // cond: + // result: (SHLLconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVQconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHLLconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SHLL x (MOVLconst [c])) + // cond: + // result: (SHLLconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHLLconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SHLL x (MOVWconst [c])) + // cond: + // result: (SHLLconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVWconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHLLconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SHLL x (MOVBconst [c])) + // cond: + // result: (SHLLconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVBconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHLLconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SHLQ(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SHLQ x (MOVQconst [c])) + // cond: + // result: (SHLQconst [c&63] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVQconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHLQconst) + v.AuxInt = c & 63 + v.AddArg(x) + return true + } + // match: (SHLQ x (MOVLconst [c])) + // cond: + // result: (SHLQconst [c&63] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHLQconst) + v.AuxInt = c & 63 + v.AddArg(x) + return true + } + // match: (SHLQ x (MOVWconst [c])) + // cond: + // result: (SHLQconst [c&63] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVWconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHLQconst) + v.AuxInt = c & 63 + v.AddArg(x) + return true + } + // match: (SHLQ x (MOVBconst [c])) + // cond: + // result: (SHLQconst [c&63] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVBconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHLQconst) + v.AuxInt = c & 63 + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SHLW(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SHLW x (MOVQconst [c])) + // cond: + // result: (SHLWconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVQconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHLWconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SHLW x (MOVLconst [c])) + // cond: + // result: (SHLWconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHLWconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SHLW x (MOVWconst [c])) + // cond: + // result: (SHLWconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVWconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHLWconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SHLW x (MOVBconst [c])) + // cond: + // result: (SHLWconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVBconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHLWconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SHRB(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SHRB x (MOVQconst [c])) + // cond: + // result: (SHRBconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVQconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHRBconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SHRB x (MOVLconst [c])) + // cond: + // result: (SHRBconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHRBconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SHRB x (MOVWconst [c])) + // cond: + // result: (SHRBconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVWconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHRBconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SHRB x (MOVBconst [c])) + // cond: + // result: (SHRBconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVBconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHRBconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SHRL(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SHRL x (MOVQconst [c])) + // cond: + // result: (SHRLconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVQconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHRLconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SHRL x (MOVLconst [c])) + // cond: + // result: (SHRLconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHRLconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SHRL x (MOVWconst [c])) + // cond: + // result: (SHRLconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVWconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHRLconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SHRL x (MOVBconst [c])) + // cond: + // result: (SHRLconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVBconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHRLconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SHRQ(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SHRQ x (MOVQconst [c])) + // cond: + // result: (SHRQconst [c&63] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVQconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHRQconst) + v.AuxInt = c & 63 + v.AddArg(x) + return true + } + // match: (SHRQ x (MOVLconst [c])) + // cond: + // result: (SHRQconst [c&63] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHRQconst) + v.AuxInt = c & 63 + v.AddArg(x) + return true + } + // match: (SHRQ x (MOVWconst [c])) + // cond: + // result: (SHRQconst [c&63] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVWconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHRQconst) + v.AuxInt = c & 63 + v.AddArg(x) + return true + } + // match: (SHRQ x (MOVBconst [c])) + // cond: + // result: (SHRQconst [c&63] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVBconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHRQconst) + v.AuxInt = c & 63 + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SHRW(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SHRW x (MOVQconst [c])) + // cond: + // result: (SHRWconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVQconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHRWconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SHRW x (MOVLconst [c])) + // cond: + // result: (SHRWconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHRWconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SHRW x (MOVWconst [c])) + // cond: + // result: (SHRWconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVWconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHRWconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + // match: (SHRW x (MOVBconst [c])) + // cond: + // result: (SHRWconst [c&31] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVBconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SHRWconst) + v.AuxInt = c & 31 + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SUBB(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SUBB x (MOVBconst [c])) + // cond: + // result: (SUBBconst x [c]) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVBconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SUBBconst) + v.AddArg(x) + v.AuxInt = c + return true + } + // match: (SUBB (MOVBconst [c]) x) + // cond: + // result: (NEGB (SUBBconst <v.Type> x [c])) + for { + if v.Args[0].Op != OpAMD64MOVBconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + v.reset(OpAMD64NEGB) + v0 := b.NewValue0(v.Line, OpAMD64SUBBconst, v.Type) + v0.AddArg(x) + v0.AuxInt = c + v.AddArg(v0) + return true + } + // match: (SUBB x x) + // cond: + // result: (MOVBconst [0]) + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SUBBconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SUBBconst [c] x) + // cond: int8(c) == 0 + // result: x + for { + c := v.AuxInt + x := v.Args[0] + if !(int8(c) == 0) { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (SUBBconst [c] (MOVBconst [d])) + // cond: + // result: (MOVBconst [d-c]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVBconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVBconst) + v.AuxInt = d - c + return true + } + // match: (SUBBconst [c] (SUBBconst [d] x)) + // cond: + // result: (ADDBconst [-c-d] x) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64SUBBconst { + break + } + d := v.Args[0].AuxInt + x := v.Args[0].Args[0] + v.reset(OpAMD64ADDBconst) + v.AuxInt = -c - d + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SUBL(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SUBL x (MOVLconst [c])) + // cond: + // result: (SUBLconst x [c]) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SUBLconst) + v.AddArg(x) + v.AuxInt = c + return true + } + // match: (SUBL (MOVLconst [c]) x) + // cond: + // result: (NEGL (SUBLconst <v.Type> x [c])) + for { + if v.Args[0].Op != OpAMD64MOVLconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + v.reset(OpAMD64NEGL) + v0 := b.NewValue0(v.Line, OpAMD64SUBLconst, v.Type) + v0.AddArg(x) + v0.AuxInt = c + v.AddArg(v0) + return true + } + // match: (SUBL x x) + // cond: + // result: (MOVLconst [0]) + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SUBLconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SUBLconst [c] x) + // cond: int32(c) == 0 + // result: x + for { + c := v.AuxInt + x := v.Args[0] + if !(int32(c) == 0) { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (SUBLconst [c] (MOVLconst [d])) + // cond: + // result: (MOVLconst [d-c]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVLconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVLconst) + v.AuxInt = d - c + return true + } + // match: (SUBLconst [c] (SUBLconst [d] x)) + // cond: + // result: (ADDLconst [-c-d] x) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64SUBLconst { + break + } + d := v.Args[0].AuxInt + x := v.Args[0].Args[0] + v.reset(OpAMD64ADDLconst) + v.AuxInt = -c - d + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SUBQ(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SUBQ x (MOVQconst [c])) + // cond: is32Bit(c) + // result: (SUBQconst x [c]) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVQconst { + break + } + c := v.Args[1].AuxInt + if !(is32Bit(c)) { + break + } + v.reset(OpAMD64SUBQconst) + v.AddArg(x) + v.AuxInt = c + return true + } + // match: (SUBQ (MOVQconst [c]) x) + // cond: is32Bit(c) + // result: (NEGQ (SUBQconst <v.Type> x [c])) + for { + if v.Args[0].Op != OpAMD64MOVQconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + if !(is32Bit(c)) { + break + } + v.reset(OpAMD64NEGQ) + v0 := b.NewValue0(v.Line, OpAMD64SUBQconst, v.Type) + v0.AddArg(x) + v0.AuxInt = c + v.AddArg(v0) + return true + } + // match: (SUBQ x x) + // cond: + // result: (MOVQconst [0]) + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpAMD64MOVQconst) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SUBQconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SUBQconst [0] x) + // cond: + // result: x + for { + if v.AuxInt != 0 { + break + } + x := v.Args[0] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (SUBQconst [c] (MOVQconst [d])) + // cond: + // result: (MOVQconst [d-c]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVQconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVQconst) + v.AuxInt = d - c + return true + } + // match: (SUBQconst [c] (SUBQconst [d] x)) + // cond: + // result: (ADDQconst [-c-d] x) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64SUBQconst { + break + } + d := v.Args[0].AuxInt + x := v.Args[0].Args[0] + v.reset(OpAMD64ADDQconst) + v.AuxInt = -c - d + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SUBW(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SUBW x (MOVWconst [c])) + // cond: + // result: (SUBWconst x [c]) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVWconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64SUBWconst) + v.AddArg(x) + v.AuxInt = c + return true + } + // match: (SUBW (MOVWconst [c]) x) + // cond: + // result: (NEGW (SUBWconst <v.Type> x [c])) + for { + if v.Args[0].Op != OpAMD64MOVWconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + v.reset(OpAMD64NEGW) + v0 := b.NewValue0(v.Line, OpAMD64SUBWconst, v.Type) + v0.AddArg(x) + v0.AuxInt = c + v.AddArg(v0) + return true + } + // match: (SUBW x x) + // cond: + // result: (MOVWconst [0]) + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpAMD64MOVWconst) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SUBWconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SUBWconst [c] x) + // cond: int16(c) == 0 + // result: x + for { + c := v.AuxInt + x := v.Args[0] + if !(int16(c) == 0) { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (SUBWconst [c] (MOVWconst [d])) + // cond: + // result: (MOVWconst [d-c]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVWconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVWconst) + v.AuxInt = d - c + return true + } + // match: (SUBWconst [c] (SUBWconst [d] x)) + // cond: + // result: (ADDWconst [-c-d] x) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64SUBWconst { + break + } + d := v.Args[0].AuxInt + x := v.Args[0].Args[0] + v.reset(OpAMD64ADDWconst) + v.AuxInt = -c - d + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpSignExt16to32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SignExt16to32 x) + // cond: + // result: (MOVWQSX x) + for { + x := v.Args[0] + v.reset(OpAMD64MOVWQSX) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpSignExt16to64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SignExt16to64 x) + // cond: + // result: (MOVWQSX x) + for { + x := v.Args[0] + v.reset(OpAMD64MOVWQSX) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpSignExt32to64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SignExt32to64 x) + // cond: + // result: (MOVLQSX x) + for { + x := v.Args[0] + v.reset(OpAMD64MOVLQSX) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpSignExt8to16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SignExt8to16 x) + // cond: + // result: (MOVBQSX x) + for { + x := v.Args[0] + v.reset(OpAMD64MOVBQSX) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpSignExt8to32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SignExt8to32 x) + // cond: + // result: (MOVBQSX x) + for { + x := v.Args[0] + v.reset(OpAMD64MOVBQSX) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpSignExt8to64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SignExt8to64 x) + // cond: + // result: (MOVBQSX x) + for { + x := v.Args[0] + v.reset(OpAMD64MOVBQSX) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpSqrt(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Sqrt x) + // cond: + // result: (SQRTSD x) + for { + x := v.Args[0] + v.reset(OpAMD64SQRTSD) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpStaticCall(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (StaticCall [argwid] {target} mem) + // cond: + // result: (CALLstatic [argwid] {target} mem) + for { + argwid := v.AuxInt + target := v.Aux + mem := v.Args[0] + v.reset(OpAMD64CALLstatic) + v.AuxInt = argwid + v.Aux = target + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpStore(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Store [8] ptr val mem) + // cond: is64BitFloat(val.Type) + // result: (MOVSDstore ptr val mem) + for { + if v.AuxInt != 8 { + break + } + ptr := v.Args[0] + val := v.Args[1] + mem := v.Args[2] + if !(is64BitFloat(val.Type)) { + break + } + v.reset(OpAMD64MOVSDstore) + v.AddArg(ptr) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (Store [4] ptr val mem) + // cond: is32BitFloat(val.Type) + // result: (MOVSSstore ptr val mem) + for { + if v.AuxInt != 4 { + break + } + ptr := v.Args[0] + val := v.Args[1] + mem := v.Args[2] + if !(is32BitFloat(val.Type)) { + break + } + v.reset(OpAMD64MOVSSstore) + v.AddArg(ptr) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (Store [8] ptr val mem) + // cond: + // result: (MOVQstore ptr val mem) + for { + if v.AuxInt != 8 { + break + } + ptr := v.Args[0] + val := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVQstore) + v.AddArg(ptr) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (Store [4] ptr val mem) + // cond: + // result: (MOVLstore ptr val mem) + for { + if v.AuxInt != 4 { + break + } + ptr := v.Args[0] + val := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVLstore) + v.AddArg(ptr) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (Store [2] ptr val mem) + // cond: + // result: (MOVWstore ptr val mem) + for { + if v.AuxInt != 2 { + break + } + ptr := v.Args[0] + val := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVWstore) + v.AddArg(ptr) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (Store [1] ptr val mem) + // cond: + // result: (MOVBstore ptr val mem) + for { + if v.AuxInt != 1 { + break + } + ptr := v.Args[0] + val := v.Args[1] + mem := v.Args[2] + v.reset(OpAMD64MOVBstore) + v.AddArg(ptr) + v.AddArg(val) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpSub16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Sub16 x y) + // cond: + // result: (SUBW x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SUBW) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpSub32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Sub32 x y) + // cond: + // result: (SUBL x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SUBL) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpSub32F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Sub32F x y) + // cond: + // result: (SUBSS x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SUBSS) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpSub64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Sub64 x y) + // cond: + // result: (SUBQ x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SUBQ) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpSub64F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Sub64F x y) + // cond: + // result: (SUBSD x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SUBSD) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpSub8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Sub8 x y) + // cond: + // result: (SUBB x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SUBB) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpSubPtr(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SubPtr x y) + // cond: + // result: (SUBQ x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64SUBQ) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpTrunc16to8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Trunc16to8 x) + // cond: + // result: x + for { + x := v.Args[0] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpTrunc32to16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Trunc32to16 x) + // cond: + // result: x + for { + x := v.Args[0] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpTrunc32to8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Trunc32to8 x) + // cond: + // result: x + for { + x := v.Args[0] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpTrunc64to16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Trunc64to16 x) + // cond: + // result: x + for { + x := v.Args[0] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpTrunc64to32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Trunc64to32 x) + // cond: + // result: x + for { + x := v.Args[0] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpTrunc64to8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Trunc64to8 x) + // cond: + // result: x + for { + x := v.Args[0] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64XORB(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (XORB x (MOVBconst [c])) + // cond: + // result: (XORBconst [c] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVBconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64XORBconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (XORB (MOVBconst [c]) x) + // cond: + // result: (XORBconst [c] x) + for { + if v.Args[0].Op != OpAMD64MOVBconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + v.reset(OpAMD64XORBconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (XORB x x) + // cond: + // result: (MOVBconst [0]) + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpAMD64MOVBconst) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValueAMD64_OpAMD64XORBconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (XORBconst [c] x) + // cond: int8(c)==0 + // result: x + for { + c := v.AuxInt + x := v.Args[0] + if !(int8(c) == 0) { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (XORBconst [c] (MOVBconst [d])) + // cond: + // result: (MOVBconst [c^d]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVBconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVBconst) + v.AuxInt = c ^ d + return true + } + return false +} +func rewriteValueAMD64_OpAMD64XORL(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (XORL x (MOVLconst [c])) + // cond: + // result: (XORLconst [c] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVLconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64XORLconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (XORL (MOVLconst [c]) x) + // cond: + // result: (XORLconst [c] x) + for { + if v.Args[0].Op != OpAMD64MOVLconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + v.reset(OpAMD64XORLconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (XORL x x) + // cond: + // result: (MOVLconst [0]) + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpAMD64MOVLconst) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValueAMD64_OpAMD64XORLconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (XORLconst [c] x) + // cond: int32(c)==0 + // result: x + for { + c := v.AuxInt + x := v.Args[0] + if !(int32(c) == 0) { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (XORLconst [c] (MOVLconst [d])) + // cond: + // result: (MOVLconst [c^d]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVLconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVLconst) + v.AuxInt = c ^ d + return true + } + return false +} +func rewriteValueAMD64_OpAMD64XORQ(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (XORQ x (MOVQconst [c])) + // cond: is32Bit(c) + // result: (XORQconst [c] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVQconst { + break + } + c := v.Args[1].AuxInt + if !(is32Bit(c)) { + break + } + v.reset(OpAMD64XORQconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (XORQ (MOVQconst [c]) x) + // cond: is32Bit(c) + // result: (XORQconst [c] x) + for { + if v.Args[0].Op != OpAMD64MOVQconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + if !(is32Bit(c)) { + break + } + v.reset(OpAMD64XORQconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (XORQ x x) + // cond: + // result: (MOVQconst [0]) + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpAMD64MOVQconst) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValueAMD64_OpAMD64XORQconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (XORQconst [0] x) + // cond: + // result: x + for { + if v.AuxInt != 0 { + break + } + x := v.Args[0] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (XORQconst [c] (MOVQconst [d])) + // cond: + // result: (MOVQconst [c^d]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVQconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVQconst) + v.AuxInt = c ^ d + return true + } + return false +} +func rewriteValueAMD64_OpAMD64XORW(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (XORW x (MOVWconst [c])) + // cond: + // result: (XORWconst [c] x) + for { + x := v.Args[0] + if v.Args[1].Op != OpAMD64MOVWconst { + break + } + c := v.Args[1].AuxInt + v.reset(OpAMD64XORWconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (XORW (MOVWconst [c]) x) + // cond: + // result: (XORWconst [c] x) + for { + if v.Args[0].Op != OpAMD64MOVWconst { + break + } + c := v.Args[0].AuxInt + x := v.Args[1] + v.reset(OpAMD64XORWconst) + v.AuxInt = c + v.AddArg(x) + return true + } + // match: (XORW x x) + // cond: + // result: (MOVWconst [0]) + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpAMD64MOVWconst) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValueAMD64_OpAMD64XORWconst(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (XORWconst [c] x) + // cond: int16(c)==0 + // result: x + for { + c := v.AuxInt + x := v.Args[0] + if !(int16(c) == 0) { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (XORWconst [c] (MOVWconst [d])) + // cond: + // result: (MOVWconst [c^d]) + for { + c := v.AuxInt + if v.Args[0].Op != OpAMD64MOVWconst { + break + } + d := v.Args[0].AuxInt + v.reset(OpAMD64MOVWconst) + v.AuxInt = c ^ d + return true + } + return false +} +func rewriteValueAMD64_OpXor16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Xor16 x y) + // cond: + // result: (XORW x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64XORW) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpXor32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Xor32 x y) + // cond: + // result: (XORL x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64XORL) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpXor64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Xor64 x y) + // cond: + // result: (XORQ x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64XORQ) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpXor8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Xor8 x y) + // cond: + // result: (XORB x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpAMD64XORB) + v.AddArg(x) + v.AddArg(y) + return true + } + return false +} +func rewriteValueAMD64_OpZero(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Zero [0] _ mem) + // cond: + // result: mem + for { + if v.AuxInt != 0 { + break + } + mem := v.Args[1] + v.reset(OpCopy) + v.Type = mem.Type + v.AddArg(mem) + return true + } + // match: (Zero [1] destptr mem) + // cond: + // result: (MOVBstoreconst [0] destptr mem) + for { + if v.AuxInt != 1 { + break + } + destptr := v.Args[0] + mem := v.Args[1] + v.reset(OpAMD64MOVBstoreconst) + v.AuxInt = 0 + v.AddArg(destptr) + v.AddArg(mem) + return true + } + // match: (Zero [2] destptr mem) + // cond: + // result: (MOVWstoreconst [0] destptr mem) + for { + if v.AuxInt != 2 { + break + } + destptr := v.Args[0] + mem := v.Args[1] + v.reset(OpAMD64MOVWstoreconst) + v.AuxInt = 0 + v.AddArg(destptr) + v.AddArg(mem) + return true + } + // match: (Zero [4] destptr mem) + // cond: + // result: (MOVLstoreconst [0] destptr mem) + for { + if v.AuxInt != 4 { + break + } + destptr := v.Args[0] + mem := v.Args[1] + v.reset(OpAMD64MOVLstoreconst) + v.AuxInt = 0 + v.AddArg(destptr) + v.AddArg(mem) + return true + } + // match: (Zero [8] destptr mem) + // cond: + // result: (MOVQstoreconst [0] destptr mem) + for { + if v.AuxInt != 8 { + break + } + destptr := v.Args[0] + mem := v.Args[1] + v.reset(OpAMD64MOVQstoreconst) + v.AuxInt = 0 + v.AddArg(destptr) + v.AddArg(mem) + return true + } + // match: (Zero [3] destptr mem) + // cond: + // result: (MOVBstoreconst [makeValAndOff(0,2)] destptr (MOVWstoreconst [0] destptr mem)) + for { + if v.AuxInt != 3 { + break + } + destptr := v.Args[0] + mem := v.Args[1] + v.reset(OpAMD64MOVBstoreconst) + v.AuxInt = makeValAndOff(0, 2) + v.AddArg(destptr) + v0 := b.NewValue0(v.Line, OpAMD64MOVWstoreconst, TypeMem) + v0.AuxInt = 0 + v0.AddArg(destptr) + v0.AddArg(mem) + v.AddArg(v0) + return true + } + // match: (Zero [5] destptr mem) + // cond: + // result: (MOVBstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem)) + for { + if v.AuxInt != 5 { + break + } + destptr := v.Args[0] + mem := v.Args[1] + v.reset(OpAMD64MOVBstoreconst) + v.AuxInt = makeValAndOff(0, 4) + v.AddArg(destptr) + v0 := b.NewValue0(v.Line, OpAMD64MOVLstoreconst, TypeMem) + v0.AuxInt = 0 + v0.AddArg(destptr) + v0.AddArg(mem) + v.AddArg(v0) + return true + } + // match: (Zero [6] destptr mem) + // cond: + // result: (MOVWstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem)) + for { + if v.AuxInt != 6 { + break + } + destptr := v.Args[0] + mem := v.Args[1] + v.reset(OpAMD64MOVWstoreconst) + v.AuxInt = makeValAndOff(0, 4) + v.AddArg(destptr) + v0 := b.NewValue0(v.Line, OpAMD64MOVLstoreconst, TypeMem) + v0.AuxInt = 0 + v0.AddArg(destptr) + v0.AddArg(mem) + v.AddArg(v0) + return true + } + // match: (Zero [7] destptr mem) + // cond: + // result: (MOVLstoreconst [makeValAndOff(0,3)] destptr (MOVLstoreconst [0] destptr mem)) + for { + if v.AuxInt != 7 { + break + } + destptr := v.Args[0] + mem := v.Args[1] + v.reset(OpAMD64MOVLstoreconst) + v.AuxInt = makeValAndOff(0, 3) + v.AddArg(destptr) + v0 := b.NewValue0(v.Line, OpAMD64MOVLstoreconst, TypeMem) + v0.AuxInt = 0 + v0.AddArg(destptr) + v0.AddArg(mem) + v.AddArg(v0) + return true + } + // match: (Zero [size] destptr mem) + // cond: size%8 != 0 && size > 8 + // result: (Zero [size-size%8] (ADDQconst destptr [size%8]) (MOVQstoreconst [0] destptr mem)) + for { + size := v.AuxInt + destptr := v.Args[0] + mem := v.Args[1] + if !(size%8 != 0 && size > 8) { + break + } + v.reset(OpZero) + v.AuxInt = size - size%8 + v0 := b.NewValue0(v.Line, OpAMD64ADDQconst, config.fe.TypeUInt64()) + v0.AddArg(destptr) + v0.AuxInt = size % 8 + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64MOVQstoreconst, TypeMem) + v1.AuxInt = 0 + v1.AddArg(destptr) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + // match: (Zero [16] destptr mem) + // cond: + // result: (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [0] destptr mem)) + for { + if v.AuxInt != 16 { + break + } + destptr := v.Args[0] + mem := v.Args[1] + v.reset(OpAMD64MOVQstoreconst) + v.AuxInt = makeValAndOff(0, 8) + v.AddArg(destptr) + v0 := b.NewValue0(v.Line, OpAMD64MOVQstoreconst, TypeMem) + v0.AuxInt = 0 + v0.AddArg(destptr) + v0.AddArg(mem) + v.AddArg(v0) + return true + } + // match: (Zero [24] destptr mem) + // cond: + // result: (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [0] destptr mem))) + for { + if v.AuxInt != 24 { + break + } + destptr := v.Args[0] + mem := v.Args[1] + v.reset(OpAMD64MOVQstoreconst) + v.AuxInt = makeValAndOff(0, 16) + v.AddArg(destptr) + v0 := b.NewValue0(v.Line, OpAMD64MOVQstoreconst, TypeMem) + v0.AuxInt = makeValAndOff(0, 8) + v0.AddArg(destptr) + v1 := b.NewValue0(v.Line, OpAMD64MOVQstoreconst, TypeMem) + v1.AuxInt = 0 + v1.AddArg(destptr) + v1.AddArg(mem) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + // match: (Zero [32] destptr mem) + // cond: + // result: (MOVQstoreconst [makeValAndOff(0,24)] destptr (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [0] destptr mem)))) + for { + if v.AuxInt != 32 { + break + } + destptr := v.Args[0] + mem := v.Args[1] + v.reset(OpAMD64MOVQstoreconst) + v.AuxInt = makeValAndOff(0, 24) + v.AddArg(destptr) + v0 := b.NewValue0(v.Line, OpAMD64MOVQstoreconst, TypeMem) + v0.AuxInt = makeValAndOff(0, 16) + v0.AddArg(destptr) + v1 := b.NewValue0(v.Line, OpAMD64MOVQstoreconst, TypeMem) + v1.AuxInt = makeValAndOff(0, 8) + v1.AddArg(destptr) + v2 := b.NewValue0(v.Line, OpAMD64MOVQstoreconst, TypeMem) + v2.AuxInt = 0 + v2.AddArg(destptr) + v2.AddArg(mem) + v1.AddArg(v2) + v0.AddArg(v1) + v.AddArg(v0) + return true + } + // match: (Zero [size] destptr mem) + // cond: size <= 1024 && size%8 == 0 && size%16 != 0 + // result: (Zero [size-8] (ADDQconst [8] destptr) (MOVQstore destptr (MOVQconst [0]) mem)) + for { + size := v.AuxInt + destptr := v.Args[0] + mem := v.Args[1] + if !(size <= 1024 && size%8 == 0 && size%16 != 0) { + break + } + v.reset(OpZero) + v.AuxInt = size - 8 + v0 := b.NewValue0(v.Line, OpAMD64ADDQconst, config.fe.TypeUInt64()) + v0.AuxInt = 8 + v0.AddArg(destptr) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64MOVQstore, TypeMem) + v1.AddArg(destptr) + v2 := b.NewValue0(v.Line, OpAMD64MOVQconst, config.fe.TypeUInt64()) + v2.AuxInt = 0 + v1.AddArg(v2) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + // match: (Zero [size] destptr mem) + // cond: size <= 1024 && size%16 == 0 + // result: (DUFFZERO [duffStart(size)] (ADDQconst [duffAdj(size)] destptr) (MOVOconst [0]) mem) + for { + size := v.AuxInt + destptr := v.Args[0] + mem := v.Args[1] + if !(size <= 1024 && size%16 == 0) { + break + } + v.reset(OpAMD64DUFFZERO) + v.AuxInt = duffStart(size) + v0 := b.NewValue0(v.Line, OpAMD64ADDQconst, config.fe.TypeUInt64()) + v0.AuxInt = duffAdj(size) + v0.AddArg(destptr) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64MOVOconst, TypeInt128) + v1.AuxInt = 0 + v.AddArg(v1) + v.AddArg(mem) + return true + } + // match: (Zero [size] destptr mem) + // cond: size > 1024 && size%8 == 0 + // result: (REPSTOSQ destptr (MOVQconst [size/8]) (MOVQconst [0]) mem) + for { + size := v.AuxInt + destptr := v.Args[0] + mem := v.Args[1] + if !(size > 1024 && size%8 == 0) { + break + } + v.reset(OpAMD64REPSTOSQ) + v.AddArg(destptr) + v0 := b.NewValue0(v.Line, OpAMD64MOVQconst, config.fe.TypeUInt64()) + v0.AuxInt = size / 8 + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpAMD64MOVQconst, config.fe.TypeUInt64()) + v1.AuxInt = 0 + v.AddArg(v1) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueAMD64_OpZeroExt16to32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ZeroExt16to32 x) + // cond: + // result: (MOVWQZX x) + for { + x := v.Args[0] + v.reset(OpAMD64MOVWQZX) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpZeroExt16to64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ZeroExt16to64 x) + // cond: + // result: (MOVWQZX x) + for { + x := v.Args[0] + v.reset(OpAMD64MOVWQZX) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpZeroExt32to64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ZeroExt32to64 x) + // cond: + // result: (MOVLQZX x) + for { + x := v.Args[0] + v.reset(OpAMD64MOVLQZX) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpZeroExt8to16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ZeroExt8to16 x) + // cond: + // result: (MOVBQZX x) + for { + x := v.Args[0] + v.reset(OpAMD64MOVBQZX) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpZeroExt8to32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ZeroExt8to32 x) + // cond: + // result: (MOVBQZX x) + for { + x := v.Args[0] + v.reset(OpAMD64MOVBQZX) + v.AddArg(x) + return true + } + return false +} +func rewriteValueAMD64_OpZeroExt8to64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ZeroExt8to64 x) + // cond: + // result: (MOVBQZX x) + for { + x := v.Args[0] + v.reset(OpAMD64MOVBQZX) + v.AddArg(x) + return true + } + return false +} +func rewriteBlockAMD64(b *Block) bool { + switch b.Kind { + case BlockAMD64EQ: + // match: (EQ (InvertFlags cmp) yes no) + // cond: + // result: (EQ cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64InvertFlags { + break + } + cmp := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64EQ + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (EQ (FlagEQ) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagEQ { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (EQ (FlagLT_ULT) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagLT_ULT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + // match: (EQ (FlagLT_UGT) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagLT_UGT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + // match: (EQ (FlagGT_ULT) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagGT_ULT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + // match: (EQ (FlagGT_UGT) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagGT_UGT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + case BlockAMD64GE: + // match: (GE (InvertFlags cmp) yes no) + // cond: + // result: (LE cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64InvertFlags { + break + } + cmp := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64LE + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (GE (FlagEQ) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagEQ { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (GE (FlagLT_ULT) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagLT_ULT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + // match: (GE (FlagLT_UGT) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagLT_UGT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + // match: (GE (FlagGT_ULT) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagGT_ULT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (GE (FlagGT_UGT) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagGT_UGT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + case BlockAMD64GT: + // match: (GT (InvertFlags cmp) yes no) + // cond: + // result: (LT cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64InvertFlags { + break + } + cmp := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64LT + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (GT (FlagEQ) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagEQ { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + // match: (GT (FlagLT_ULT) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagLT_ULT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + // match: (GT (FlagLT_UGT) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagLT_UGT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + // match: (GT (FlagGT_ULT) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagGT_ULT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (GT (FlagGT_UGT) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagGT_UGT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + case BlockIf: + // match: (If (SETL cmp) yes no) + // cond: + // result: (LT cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64SETL { + break + } + cmp := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64LT + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (If (SETLE cmp) yes no) + // cond: + // result: (LE cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64SETLE { + break + } + cmp := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64LE + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (If (SETG cmp) yes no) + // cond: + // result: (GT cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64SETG { + break + } + cmp := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64GT + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (If (SETGE cmp) yes no) + // cond: + // result: (GE cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64SETGE { + break + } + cmp := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64GE + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (If (SETEQ cmp) yes no) + // cond: + // result: (EQ cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64SETEQ { + break + } + cmp := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64EQ + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (If (SETNE cmp) yes no) + // cond: + // result: (NE cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64SETNE { + break + } + cmp := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64NE + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (If (SETB cmp) yes no) + // cond: + // result: (ULT cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64SETB { + break + } + cmp := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64ULT + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (If (SETBE cmp) yes no) + // cond: + // result: (ULE cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64SETBE { + break + } + cmp := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64ULE + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (If (SETA cmp) yes no) + // cond: + // result: (UGT cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64SETA { + break + } + cmp := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64UGT + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (If (SETAE cmp) yes no) + // cond: + // result: (UGE cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64SETAE { + break + } + cmp := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64UGE + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (If (SETGF cmp) yes no) + // cond: + // result: (UGT cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64SETGF { + break + } + cmp := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64UGT + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (If (SETGEF cmp) yes no) + // cond: + // result: (UGE cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64SETGEF { + break + } + cmp := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64UGE + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (If (SETEQF cmp) yes no) + // cond: + // result: (EQF cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64SETEQF { + break + } + cmp := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64EQF + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (If (SETNEF cmp) yes no) + // cond: + // result: (NEF cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64SETNEF { + break + } + cmp := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64NEF + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (If cond yes no) + // cond: + // result: (NE (TESTB cond cond) yes no) + for { + v := b.Control + cond := v + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64NE + v0 := b.NewValue0(v.Line, OpAMD64TESTB, TypeFlags) + v0.AddArg(cond) + v0.AddArg(cond) + b.Control = v0 + b.Succs[0] = yes + b.Succs[1] = no + return true + } + case BlockAMD64LE: + // match: (LE (InvertFlags cmp) yes no) + // cond: + // result: (GE cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64InvertFlags { + break + } + cmp := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64GE + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (LE (FlagEQ) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagEQ { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (LE (FlagLT_ULT) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagLT_ULT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (LE (FlagLT_UGT) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagLT_UGT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (LE (FlagGT_ULT) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagGT_ULT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + // match: (LE (FlagGT_UGT) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagGT_UGT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + case BlockAMD64LT: + // match: (LT (InvertFlags cmp) yes no) + // cond: + // result: (GT cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64InvertFlags { + break + } + cmp := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64GT + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (LT (FlagEQ) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagEQ { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + // match: (LT (FlagLT_ULT) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagLT_ULT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (LT (FlagLT_UGT) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagLT_UGT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (LT (FlagGT_ULT) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagGT_ULT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + // match: (LT (FlagGT_UGT) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagGT_UGT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + case BlockAMD64NE: + // match: (NE (TESTB (SETL cmp)) yes no) + // cond: + // result: (LT cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64TESTB { + break + } + if v.Args[0].Op != OpAMD64SETL { + break + } + cmp := v.Args[0].Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64LT + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (NE (TESTB (SETLE cmp)) yes no) + // cond: + // result: (LE cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64TESTB { + break + } + if v.Args[0].Op != OpAMD64SETLE { + break + } + cmp := v.Args[0].Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64LE + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (NE (TESTB (SETG cmp)) yes no) + // cond: + // result: (GT cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64TESTB { + break + } + if v.Args[0].Op != OpAMD64SETG { + break + } + cmp := v.Args[0].Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64GT + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (NE (TESTB (SETGE cmp)) yes no) + // cond: + // result: (GE cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64TESTB { + break + } + if v.Args[0].Op != OpAMD64SETGE { + break + } + cmp := v.Args[0].Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64GE + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (NE (TESTB (SETEQ cmp)) yes no) + // cond: + // result: (EQ cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64TESTB { + break + } + if v.Args[0].Op != OpAMD64SETEQ { + break + } + cmp := v.Args[0].Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64EQ + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (NE (TESTB (SETNE cmp)) yes no) + // cond: + // result: (NE cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64TESTB { + break + } + if v.Args[0].Op != OpAMD64SETNE { + break + } + cmp := v.Args[0].Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64NE + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (NE (TESTB (SETB cmp)) yes no) + // cond: + // result: (ULT cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64TESTB { + break + } + if v.Args[0].Op != OpAMD64SETB { + break + } + cmp := v.Args[0].Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64ULT + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (NE (TESTB (SETBE cmp)) yes no) + // cond: + // result: (ULE cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64TESTB { + break + } + if v.Args[0].Op != OpAMD64SETBE { + break + } + cmp := v.Args[0].Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64ULE + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (NE (TESTB (SETA cmp)) yes no) + // cond: + // result: (UGT cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64TESTB { + break + } + if v.Args[0].Op != OpAMD64SETA { + break + } + cmp := v.Args[0].Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64UGT + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (NE (TESTB (SETAE cmp)) yes no) + // cond: + // result: (UGE cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64TESTB { + break + } + if v.Args[0].Op != OpAMD64SETAE { + break + } + cmp := v.Args[0].Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64UGE + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (NE (TESTB (SETGF cmp)) yes no) + // cond: + // result: (UGT cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64TESTB { + break + } + if v.Args[0].Op != OpAMD64SETGF { + break + } + cmp := v.Args[0].Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64UGT + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (NE (TESTB (SETGEF cmp)) yes no) + // cond: + // result: (UGE cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64TESTB { + break + } + if v.Args[0].Op != OpAMD64SETGEF { + break + } + cmp := v.Args[0].Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64UGE + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (NE (TESTB (SETEQF cmp)) yes no) + // cond: + // result: (EQF cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64TESTB { + break + } + if v.Args[0].Op != OpAMD64SETEQF { + break + } + cmp := v.Args[0].Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64EQF + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (NE (TESTB (SETNEF cmp)) yes no) + // cond: + // result: (NEF cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64TESTB { + break + } + if v.Args[0].Op != OpAMD64SETNEF { + break + } + cmp := v.Args[0].Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64NEF + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (NE (InvertFlags cmp) yes no) + // cond: + // result: (NE cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64InvertFlags { + break + } + cmp := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64NE + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (NE (FlagEQ) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagEQ { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + // match: (NE (FlagLT_ULT) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagLT_ULT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (NE (FlagLT_UGT) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagLT_UGT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (NE (FlagGT_ULT) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagGT_ULT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (NE (FlagGT_UGT) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagGT_UGT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + case BlockAMD64UGE: + // match: (UGE (InvertFlags cmp) yes no) + // cond: + // result: (ULE cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64InvertFlags { + break + } + cmp := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64ULE + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (UGE (FlagEQ) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagEQ { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (UGE (FlagLT_ULT) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagLT_ULT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + // match: (UGE (FlagLT_UGT) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagLT_UGT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (UGE (FlagGT_ULT) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagGT_ULT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + // match: (UGE (FlagGT_UGT) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagGT_UGT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + case BlockAMD64UGT: + // match: (UGT (InvertFlags cmp) yes no) + // cond: + // result: (ULT cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64InvertFlags { + break + } + cmp := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64ULT + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (UGT (FlagEQ) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagEQ { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + // match: (UGT (FlagLT_ULT) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagLT_ULT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + // match: (UGT (FlagLT_UGT) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagLT_UGT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (UGT (FlagGT_ULT) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagGT_ULT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + // match: (UGT (FlagGT_UGT) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagGT_UGT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + case BlockAMD64ULE: + // match: (ULE (InvertFlags cmp) yes no) + // cond: + // result: (UGE cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64InvertFlags { + break + } + cmp := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64UGE + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (ULE (FlagEQ) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagEQ { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (ULE (FlagLT_ULT) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagLT_ULT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (ULE (FlagLT_UGT) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagLT_UGT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + // match: (ULE (FlagGT_ULT) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagGT_ULT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (ULE (FlagGT_UGT) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagGT_UGT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + case BlockAMD64ULT: + // match: (ULT (InvertFlags cmp) yes no) + // cond: + // result: (UGT cmp yes no) + for { + v := b.Control + if v.Op != OpAMD64InvertFlags { + break + } + cmp := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockAMD64UGT + b.Control = cmp + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (ULT (FlagEQ) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagEQ { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + // match: (ULT (FlagLT_ULT) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagLT_ULT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (ULT (FlagLT_UGT) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagLT_UGT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + // match: (ULT (FlagGT_ULT) yes no) + // cond: + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpAMD64FlagGT_ULT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (ULT (FlagGT_UGT) yes no) + // cond: + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpAMD64FlagGT_UGT { + break + } + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + } + return false +} diff --git a/src/cmd/compile/internal/ssa/rewrite_test.go b/src/cmd/compile/internal/ssa/rewrite_test.go new file mode 100644 index 0000000000..b786df887b --- /dev/null +++ b/src/cmd/compile/internal/ssa/rewrite_test.go @@ -0,0 +1,102 @@ +// Copyright 2016 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import "testing" + +// TestNlzNto tests nlz/nto of the same number which is used in some of +// the rewrite rules. +func TestNlzNto(t *testing.T) { + // construct the bit pattern 000...111, nlz(x) + nto(0) = 64 + var x int64 + for i := int64(0); i < 64; i++ { + if got := nto(x); got != i { + t.Errorf("expected nto(0x%X) = %d, got %d", x, i, got) + } + if got := nlz(x); got != 64-i { + t.Errorf("expected nlz(0x%X) = %d, got %d", x, 64-i, got) + } + x = (x << 1) | 1 + } + + x = 0 + // construct the bit pattern 000...111, with bit 33 set as well. + for i := int64(0); i < 64; i++ { + tx := x | (1 << 32) + // nto should be the the number of bits we've shifted on, with an extra bit + // at iter 32 + ntoExp := i + if ntoExp == 32 { + ntoExp = 33 + } + if got := nto(tx); got != ntoExp { + t.Errorf("expected nto(0x%X) = %d, got %d", tx, ntoExp, got) + } + + // sinec bit 33 is set, nlz can be no greater than 31 + nlzExp := 64 - i + if nlzExp > 31 { + nlzExp = 31 + } + if got := nlz(tx); got != nlzExp { + t.Errorf("expected nlz(0x%X) = %d, got %d", tx, nlzExp, got) + } + x = (x << 1) | 1 + } + +} + +func TestNlz(t *testing.T) { + var nlzTests = []struct { + v int64 + exp int64 + }{{0x00, 64}, + {0x01, 63}, + {0x0F, 60}, + {0xFF, 56}, + {0xffffFFFF, 32}, + {-0x01, 0}} + + for _, tc := range nlzTests { + if got := nlz(tc.v); got != tc.exp { + t.Errorf("expected nlz(0x%X) = %d, got %d", tc.v, tc.exp, got) + } + } +} + +func TestNto(t *testing.T) { + var ntoTests = []struct { + v int64 + exp int64 + }{{0x00, 0}, + {0x01, 1}, + {0x0F, 4}, + {0xFF, 8}, + {0xffffFFFF, 32}, + {-0x01, 64}} + + for _, tc := range ntoTests { + if got := nto(tc.v); got != tc.exp { + t.Errorf("expected nto(0x%X) = %d, got %d", tc.v, tc.exp, got) + } + } +} + +func TestLog2(t *testing.T) { + var log2Tests = []struct { + v int64 + exp int64 + }{{0, -1}, // nlz expects log2(0) == -1 + {1, 0}, + {2, 1}, + {4, 2}, + {1024, 10}} + + for _, tc := range log2Tests { + if got := log2(tc.v); got != tc.exp { + t.Errorf("expected log2(%d) = %d, got %d", tc.v, tc.exp, got) + } + } +} diff --git a/src/cmd/compile/internal/ssa/rewritegeneric.go b/src/cmd/compile/internal/ssa/rewritegeneric.go new file mode 100644 index 0000000000..ad2abc5601 --- /dev/null +++ b/src/cmd/compile/internal/ssa/rewritegeneric.go @@ -0,0 +1,7936 @@ +// autogenerated from gen/generic.rules: do not edit! +// generated with: cd gen; go run *.go + +package ssa + +import "math" + +var _ = math.MinInt8 // in case not otherwise used +func rewriteValuegeneric(v *Value, config *Config) bool { + switch v.Op { + case OpAdd16: + return rewriteValuegeneric_OpAdd16(v, config) + case OpAdd32: + return rewriteValuegeneric_OpAdd32(v, config) + case OpAdd64: + return rewriteValuegeneric_OpAdd64(v, config) + case OpAdd8: + return rewriteValuegeneric_OpAdd8(v, config) + case OpAnd16: + return rewriteValuegeneric_OpAnd16(v, config) + case OpAnd32: + return rewriteValuegeneric_OpAnd32(v, config) + case OpAnd64: + return rewriteValuegeneric_OpAnd64(v, config) + case OpAnd8: + return rewriteValuegeneric_OpAnd8(v, config) + case OpArg: + return rewriteValuegeneric_OpArg(v, config) + case OpArrayIndex: + return rewriteValuegeneric_OpArrayIndex(v, config) + case OpCom16: + return rewriteValuegeneric_OpCom16(v, config) + case OpCom32: + return rewriteValuegeneric_OpCom32(v, config) + case OpCom64: + return rewriteValuegeneric_OpCom64(v, config) + case OpCom8: + return rewriteValuegeneric_OpCom8(v, config) + case OpComplexImag: + return rewriteValuegeneric_OpComplexImag(v, config) + case OpComplexReal: + return rewriteValuegeneric_OpComplexReal(v, config) + case OpConstInterface: + return rewriteValuegeneric_OpConstInterface(v, config) + case OpConstSlice: + return rewriteValuegeneric_OpConstSlice(v, config) + case OpConstString: + return rewriteValuegeneric_OpConstString(v, config) + case OpConvert: + return rewriteValuegeneric_OpConvert(v, config) + case OpDiv64: + return rewriteValuegeneric_OpDiv64(v, config) + case OpDiv64u: + return rewriteValuegeneric_OpDiv64u(v, config) + case OpEq16: + return rewriteValuegeneric_OpEq16(v, config) + case OpEq32: + return rewriteValuegeneric_OpEq32(v, config) + case OpEq64: + return rewriteValuegeneric_OpEq64(v, config) + case OpEq8: + return rewriteValuegeneric_OpEq8(v, config) + case OpEqInter: + return rewriteValuegeneric_OpEqInter(v, config) + case OpEqPtr: + return rewriteValuegeneric_OpEqPtr(v, config) + case OpEqSlice: + return rewriteValuegeneric_OpEqSlice(v, config) + case OpGeq16: + return rewriteValuegeneric_OpGeq16(v, config) + case OpGeq16U: + return rewriteValuegeneric_OpGeq16U(v, config) + case OpGeq32: + return rewriteValuegeneric_OpGeq32(v, config) + case OpGeq32U: + return rewriteValuegeneric_OpGeq32U(v, config) + case OpGeq64: + return rewriteValuegeneric_OpGeq64(v, config) + case OpGeq64U: + return rewriteValuegeneric_OpGeq64U(v, config) + case OpGeq8: + return rewriteValuegeneric_OpGeq8(v, config) + case OpGeq8U: + return rewriteValuegeneric_OpGeq8U(v, config) + case OpGreater16: + return rewriteValuegeneric_OpGreater16(v, config) + case OpGreater16U: + return rewriteValuegeneric_OpGreater16U(v, config) + case OpGreater32: + return rewriteValuegeneric_OpGreater32(v, config) + case OpGreater32U: + return rewriteValuegeneric_OpGreater32U(v, config) + case OpGreater64: + return rewriteValuegeneric_OpGreater64(v, config) + case OpGreater64U: + return rewriteValuegeneric_OpGreater64U(v, config) + case OpGreater8: + return rewriteValuegeneric_OpGreater8(v, config) + case OpGreater8U: + return rewriteValuegeneric_OpGreater8U(v, config) + case OpIData: + return rewriteValuegeneric_OpIData(v, config) + case OpITab: + return rewriteValuegeneric_OpITab(v, config) + case OpIsInBounds: + return rewriteValuegeneric_OpIsInBounds(v, config) + case OpIsSliceInBounds: + return rewriteValuegeneric_OpIsSliceInBounds(v, config) + case OpLeq16: + return rewriteValuegeneric_OpLeq16(v, config) + case OpLeq16U: + return rewriteValuegeneric_OpLeq16U(v, config) + case OpLeq32: + return rewriteValuegeneric_OpLeq32(v, config) + case OpLeq32U: + return rewriteValuegeneric_OpLeq32U(v, config) + case OpLeq64: + return rewriteValuegeneric_OpLeq64(v, config) + case OpLeq64U: + return rewriteValuegeneric_OpLeq64U(v, config) + case OpLeq8: + return rewriteValuegeneric_OpLeq8(v, config) + case OpLeq8U: + return rewriteValuegeneric_OpLeq8U(v, config) + case OpLess16: + return rewriteValuegeneric_OpLess16(v, config) + case OpLess16U: + return rewriteValuegeneric_OpLess16U(v, config) + case OpLess32: + return rewriteValuegeneric_OpLess32(v, config) + case OpLess32U: + return rewriteValuegeneric_OpLess32U(v, config) + case OpLess64: + return rewriteValuegeneric_OpLess64(v, config) + case OpLess64U: + return rewriteValuegeneric_OpLess64U(v, config) + case OpLess8: + return rewriteValuegeneric_OpLess8(v, config) + case OpLess8U: + return rewriteValuegeneric_OpLess8U(v, config) + case OpLoad: + return rewriteValuegeneric_OpLoad(v, config) + case OpLsh16x16: + return rewriteValuegeneric_OpLsh16x16(v, config) + case OpLsh16x32: + return rewriteValuegeneric_OpLsh16x32(v, config) + case OpLsh16x64: + return rewriteValuegeneric_OpLsh16x64(v, config) + case OpLsh16x8: + return rewriteValuegeneric_OpLsh16x8(v, config) + case OpLsh32x16: + return rewriteValuegeneric_OpLsh32x16(v, config) + case OpLsh32x32: + return rewriteValuegeneric_OpLsh32x32(v, config) + case OpLsh32x64: + return rewriteValuegeneric_OpLsh32x64(v, config) + case OpLsh32x8: + return rewriteValuegeneric_OpLsh32x8(v, config) + case OpLsh64x16: + return rewriteValuegeneric_OpLsh64x16(v, config) + case OpLsh64x32: + return rewriteValuegeneric_OpLsh64x32(v, config) + case OpLsh64x64: + return rewriteValuegeneric_OpLsh64x64(v, config) + case OpLsh64x8: + return rewriteValuegeneric_OpLsh64x8(v, config) + case OpLsh8x16: + return rewriteValuegeneric_OpLsh8x16(v, config) + case OpLsh8x32: + return rewriteValuegeneric_OpLsh8x32(v, config) + case OpLsh8x64: + return rewriteValuegeneric_OpLsh8x64(v, config) + case OpLsh8x8: + return rewriteValuegeneric_OpLsh8x8(v, config) + case OpMod64: + return rewriteValuegeneric_OpMod64(v, config) + case OpMod64u: + return rewriteValuegeneric_OpMod64u(v, config) + case OpMul16: + return rewriteValuegeneric_OpMul16(v, config) + case OpMul32: + return rewriteValuegeneric_OpMul32(v, config) + case OpMul64: + return rewriteValuegeneric_OpMul64(v, config) + case OpMul8: + return rewriteValuegeneric_OpMul8(v, config) + case OpNeg16: + return rewriteValuegeneric_OpNeg16(v, config) + case OpNeg32: + return rewriteValuegeneric_OpNeg32(v, config) + case OpNeg64: + return rewriteValuegeneric_OpNeg64(v, config) + case OpNeg8: + return rewriteValuegeneric_OpNeg8(v, config) + case OpNeq16: + return rewriteValuegeneric_OpNeq16(v, config) + case OpNeq32: + return rewriteValuegeneric_OpNeq32(v, config) + case OpNeq64: + return rewriteValuegeneric_OpNeq64(v, config) + case OpNeq8: + return rewriteValuegeneric_OpNeq8(v, config) + case OpNeqInter: + return rewriteValuegeneric_OpNeqInter(v, config) + case OpNeqPtr: + return rewriteValuegeneric_OpNeqPtr(v, config) + case OpNeqSlice: + return rewriteValuegeneric_OpNeqSlice(v, config) + case OpOr16: + return rewriteValuegeneric_OpOr16(v, config) + case OpOr32: + return rewriteValuegeneric_OpOr32(v, config) + case OpOr64: + return rewriteValuegeneric_OpOr64(v, config) + case OpOr8: + return rewriteValuegeneric_OpOr8(v, config) + case OpPhi: + return rewriteValuegeneric_OpPhi(v, config) + case OpPtrIndex: + return rewriteValuegeneric_OpPtrIndex(v, config) + case OpRsh16Ux16: + return rewriteValuegeneric_OpRsh16Ux16(v, config) + case OpRsh16Ux32: + return rewriteValuegeneric_OpRsh16Ux32(v, config) + case OpRsh16Ux64: + return rewriteValuegeneric_OpRsh16Ux64(v, config) + case OpRsh16Ux8: + return rewriteValuegeneric_OpRsh16Ux8(v, config) + case OpRsh16x16: + return rewriteValuegeneric_OpRsh16x16(v, config) + case OpRsh16x32: + return rewriteValuegeneric_OpRsh16x32(v, config) + case OpRsh16x64: + return rewriteValuegeneric_OpRsh16x64(v, config) + case OpRsh16x8: + return rewriteValuegeneric_OpRsh16x8(v, config) + case OpRsh32Ux16: + return rewriteValuegeneric_OpRsh32Ux16(v, config) + case OpRsh32Ux32: + return rewriteValuegeneric_OpRsh32Ux32(v, config) + case OpRsh32Ux64: + return rewriteValuegeneric_OpRsh32Ux64(v, config) + case OpRsh32Ux8: + return rewriteValuegeneric_OpRsh32Ux8(v, config) + case OpRsh32x16: + return rewriteValuegeneric_OpRsh32x16(v, config) + case OpRsh32x32: + return rewriteValuegeneric_OpRsh32x32(v, config) + case OpRsh32x64: + return rewriteValuegeneric_OpRsh32x64(v, config) + case OpRsh32x8: + return rewriteValuegeneric_OpRsh32x8(v, config) + case OpRsh64Ux16: + return rewriteValuegeneric_OpRsh64Ux16(v, config) + case OpRsh64Ux32: + return rewriteValuegeneric_OpRsh64Ux32(v, config) + case OpRsh64Ux64: + return rewriteValuegeneric_OpRsh64Ux64(v, config) + case OpRsh64Ux8: + return rewriteValuegeneric_OpRsh64Ux8(v, config) + case OpRsh64x16: + return rewriteValuegeneric_OpRsh64x16(v, config) + case OpRsh64x32: + return rewriteValuegeneric_OpRsh64x32(v, config) + case OpRsh64x64: + return rewriteValuegeneric_OpRsh64x64(v, config) + case OpRsh64x8: + return rewriteValuegeneric_OpRsh64x8(v, config) + case OpRsh8Ux16: + return rewriteValuegeneric_OpRsh8Ux16(v, config) + case OpRsh8Ux32: + return rewriteValuegeneric_OpRsh8Ux32(v, config) + case OpRsh8Ux64: + return rewriteValuegeneric_OpRsh8Ux64(v, config) + case OpRsh8Ux8: + return rewriteValuegeneric_OpRsh8Ux8(v, config) + case OpRsh8x16: + return rewriteValuegeneric_OpRsh8x16(v, config) + case OpRsh8x32: + return rewriteValuegeneric_OpRsh8x32(v, config) + case OpRsh8x64: + return rewriteValuegeneric_OpRsh8x64(v, config) + case OpRsh8x8: + return rewriteValuegeneric_OpRsh8x8(v, config) + case OpSliceCap: + return rewriteValuegeneric_OpSliceCap(v, config) + case OpSliceLen: + return rewriteValuegeneric_OpSliceLen(v, config) + case OpSlicePtr: + return rewriteValuegeneric_OpSlicePtr(v, config) + case OpStore: + return rewriteValuegeneric_OpStore(v, config) + case OpStringLen: + return rewriteValuegeneric_OpStringLen(v, config) + case OpStringPtr: + return rewriteValuegeneric_OpStringPtr(v, config) + case OpStructSelect: + return rewriteValuegeneric_OpStructSelect(v, config) + case OpSub16: + return rewriteValuegeneric_OpSub16(v, config) + case OpSub32: + return rewriteValuegeneric_OpSub32(v, config) + case OpSub64: + return rewriteValuegeneric_OpSub64(v, config) + case OpSub8: + return rewriteValuegeneric_OpSub8(v, config) + case OpTrunc16to8: + return rewriteValuegeneric_OpTrunc16to8(v, config) + case OpTrunc32to16: + return rewriteValuegeneric_OpTrunc32to16(v, config) + case OpTrunc32to8: + return rewriteValuegeneric_OpTrunc32to8(v, config) + case OpTrunc64to16: + return rewriteValuegeneric_OpTrunc64to16(v, config) + case OpTrunc64to32: + return rewriteValuegeneric_OpTrunc64to32(v, config) + case OpTrunc64to8: + return rewriteValuegeneric_OpTrunc64to8(v, config) + case OpXor16: + return rewriteValuegeneric_OpXor16(v, config) + case OpXor32: + return rewriteValuegeneric_OpXor32(v, config) + case OpXor64: + return rewriteValuegeneric_OpXor64(v, config) + case OpXor8: + return rewriteValuegeneric_OpXor8(v, config) + } + return false +} +func rewriteValuegeneric_OpAdd16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Add16 (Const16 [c]) (Const16 [d])) + // cond: + // result: (Const16 [c+d]) + for { + if v.Args[0].Op != OpConst16 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst16 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConst16) + v.AuxInt = c + d + return true + } + // match: (Add16 x (Const16 <t> [c])) + // cond: x.Op != OpConst16 + // result: (Add16 (Const16 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst16 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst16) { + break + } + v.reset(OpAdd16) + v0 := b.NewValue0(v.Line, OpConst16, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Add16 (Const16 [0]) x) + // cond: + // result: x + for { + if v.Args[0].Op != OpConst16 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + x := v.Args[1] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValuegeneric_OpAdd32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Add32 (Const32 [c]) (Const32 [d])) + // cond: + // result: (Const32 [c+d]) + for { + if v.Args[0].Op != OpConst32 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst32 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConst32) + v.AuxInt = c + d + return true + } + // match: (Add32 x (Const32 <t> [c])) + // cond: x.Op != OpConst32 + // result: (Add32 (Const32 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst32 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst32) { + break + } + v.reset(OpAdd32) + v0 := b.NewValue0(v.Line, OpConst32, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Add32 (Const32 [0]) x) + // cond: + // result: x + for { + if v.Args[0].Op != OpConst32 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + x := v.Args[1] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValuegeneric_OpAdd64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Add64 (Const64 [c]) (Const64 [d])) + // cond: + // result: (Const64 [c+d]) + for { + if v.Args[0].Op != OpConst64 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConst64) + v.AuxInt = c + d + return true + } + // match: (Add64 x (Const64 <t> [c])) + // cond: x.Op != OpConst64 + // result: (Add64 (Const64 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst64) { + break + } + v.reset(OpAdd64) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Add64 (Const64 [0]) x) + // cond: + // result: x + for { + if v.Args[0].Op != OpConst64 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + x := v.Args[1] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValuegeneric_OpAdd8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Add8 (Const8 [c]) (Const8 [d])) + // cond: + // result: (Const8 [c+d]) + for { + if v.Args[0].Op != OpConst8 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst8 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConst8) + v.AuxInt = c + d + return true + } + // match: (Add8 x (Const8 <t> [c])) + // cond: x.Op != OpConst8 + // result: (Add8 (Const8 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst8 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst8) { + break + } + v.reset(OpAdd8) + v0 := b.NewValue0(v.Line, OpConst8, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Add8 (Const8 [0]) x) + // cond: + // result: x + for { + if v.Args[0].Op != OpConst8 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + x := v.Args[1] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValuegeneric_OpAnd16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (And16 x (Const16 <t> [c])) + // cond: x.Op != OpConst16 + // result: (And16 (Const16 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst16 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst16) { + break + } + v.reset(OpAnd16) + v0 := b.NewValue0(v.Line, OpConst16, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (And16 x x) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (And16 (Const16 [-1]) x) + // cond: + // result: x + for { + if v.Args[0].Op != OpConst16 { + break + } + if v.Args[0].AuxInt != -1 { + break + } + x := v.Args[1] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (And16 (Const16 [0]) _) + // cond: + // result: (Const16 [0]) + for { + if v.Args[0].Op != OpConst16 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst16) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValuegeneric_OpAnd32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (And32 x (Const32 <t> [c])) + // cond: x.Op != OpConst32 + // result: (And32 (Const32 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst32 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst32) { + break + } + v.reset(OpAnd32) + v0 := b.NewValue0(v.Line, OpConst32, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (And32 x x) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (And32 (Const32 [-1]) x) + // cond: + // result: x + for { + if v.Args[0].Op != OpConst32 { + break + } + if v.Args[0].AuxInt != -1 { + break + } + x := v.Args[1] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (And32 (Const32 [0]) _) + // cond: + // result: (Const32 [0]) + for { + if v.Args[0].Op != OpConst32 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst32) + v.AuxInt = 0 + return true + } + // match: (And32 <t> (Const32 [y]) x) + // cond: nlz(int64(int32(y))) + nto(int64(int32(y))) == 64 + // result: (Rsh32Ux32 (Lsh32x32 <t> x (Const32 <t> [nlz(int64(int32(y)))-32])) (Const32 <t> [nlz(int64(int32(y)))-32])) + for { + t := v.Type + if v.Args[0].Op != OpConst32 { + break + } + y := v.Args[0].AuxInt + x := v.Args[1] + if !(nlz(int64(int32(y)))+nto(int64(int32(y))) == 64) { + break + } + v.reset(OpRsh32Ux32) + v0 := b.NewValue0(v.Line, OpLsh32x32, t) + v0.AddArg(x) + v1 := b.NewValue0(v.Line, OpConst32, t) + v1.AuxInt = nlz(int64(int32(y))) - 32 + v0.AddArg(v1) + v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst32, t) + v2.AuxInt = nlz(int64(int32(y))) - 32 + v.AddArg(v2) + return true + } + // match: (And32 <t> (Const32 [y]) x) + // cond: nlo(int64(int32(y))) + ntz(int64(int32(y))) == 64 + // result: (Lsh32x32 (Rsh32Ux32 <t> x (Const32 <t> [ntz(int64(int32(y)))])) (Const32 <t> [ntz(int64(int32(y)))])) + for { + t := v.Type + if v.Args[0].Op != OpConst32 { + break + } + y := v.Args[0].AuxInt + x := v.Args[1] + if !(nlo(int64(int32(y)))+ntz(int64(int32(y))) == 64) { + break + } + v.reset(OpLsh32x32) + v0 := b.NewValue0(v.Line, OpRsh32Ux32, t) + v0.AddArg(x) + v1 := b.NewValue0(v.Line, OpConst32, t) + v1.AuxInt = ntz(int64(int32(y))) + v0.AddArg(v1) + v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst32, t) + v2.AuxInt = ntz(int64(int32(y))) + v.AddArg(v2) + return true + } + return false +} +func rewriteValuegeneric_OpAnd64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (And64 x (Const64 <t> [c])) + // cond: x.Op != OpConst64 + // result: (And64 (Const64 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst64) { + break + } + v.reset(OpAnd64) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (And64 x x) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (And64 (Const64 [-1]) x) + // cond: + // result: x + for { + if v.Args[0].Op != OpConst64 { + break + } + if v.Args[0].AuxInt != -1 { + break + } + x := v.Args[1] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (And64 (Const64 [0]) _) + // cond: + // result: (Const64 [0]) + for { + if v.Args[0].Op != OpConst64 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst64) + v.AuxInt = 0 + return true + } + // match: (And64 <t> (Const64 [y]) x) + // cond: nlz(y) + nto(y) == 64 + // result: (Rsh64Ux64 (Lsh64x64 <t> x (Const64 <t> [nlz(y)])) (Const64 <t> [nlz(y)])) + for { + t := v.Type + if v.Args[0].Op != OpConst64 { + break + } + y := v.Args[0].AuxInt + x := v.Args[1] + if !(nlz(y)+nto(y) == 64) { + break + } + v.reset(OpRsh64Ux64) + v0 := b.NewValue0(v.Line, OpLsh64x64, t) + v0.AddArg(x) + v1 := b.NewValue0(v.Line, OpConst64, t) + v1.AuxInt = nlz(y) + v0.AddArg(v1) + v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = nlz(y) + v.AddArg(v2) + return true + } + // match: (And64 <t> (Const64 [y]) x) + // cond: nlo(y) + ntz(y) == 64 + // result: (Lsh64x64 (Rsh64Ux64 <t> x (Const64 <t> [ntz(y)])) (Const64 <t> [ntz(y)])) + for { + t := v.Type + if v.Args[0].Op != OpConst64 { + break + } + y := v.Args[0].AuxInt + x := v.Args[1] + if !(nlo(y)+ntz(y) == 64) { + break + } + v.reset(OpLsh64x64) + v0 := b.NewValue0(v.Line, OpRsh64Ux64, t) + v0.AddArg(x) + v1 := b.NewValue0(v.Line, OpConst64, t) + v1.AuxInt = ntz(y) + v0.AddArg(v1) + v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = ntz(y) + v.AddArg(v2) + return true + } + return false +} +func rewriteValuegeneric_OpAnd8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (And8 x (Const8 <t> [c])) + // cond: x.Op != OpConst8 + // result: (And8 (Const8 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst8 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst8) { + break + } + v.reset(OpAnd8) + v0 := b.NewValue0(v.Line, OpConst8, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (And8 x x) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (And8 (Const8 [-1]) x) + // cond: + // result: x + for { + if v.Args[0].Op != OpConst8 { + break + } + if v.Args[0].AuxInt != -1 { + break + } + x := v.Args[1] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (And8 (Const8 [0]) _) + // cond: + // result: (Const8 [0]) + for { + if v.Args[0].Op != OpConst8 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst8) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValuegeneric_OpArg(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Arg {n} [off]) + // cond: v.Type.IsString() + // result: (StringMake (Arg <config.fe.TypeBytePtr()> {n} [off]) (Arg <config.fe.TypeInt()> {n} [off+config.PtrSize])) + for { + n := v.Aux + off := v.AuxInt + if !(v.Type.IsString()) { + break + } + v.reset(OpStringMake) + v0 := b.NewValue0(v.Line, OpArg, config.fe.TypeBytePtr()) + v0.Aux = n + v0.AuxInt = off + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpArg, config.fe.TypeInt()) + v1.Aux = n + v1.AuxInt = off + config.PtrSize + v.AddArg(v1) + return true + } + // match: (Arg {n} [off]) + // cond: v.Type.IsSlice() + // result: (SliceMake (Arg <config.fe.TypeBytePtr()> {n} [off]) (Arg <config.fe.TypeInt()> {n} [off+config.PtrSize]) (Arg <config.fe.TypeInt()> {n} [off+2*config.PtrSize])) + for { + n := v.Aux + off := v.AuxInt + if !(v.Type.IsSlice()) { + break + } + v.reset(OpSliceMake) + v0 := b.NewValue0(v.Line, OpArg, config.fe.TypeBytePtr()) + v0.Aux = n + v0.AuxInt = off + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpArg, config.fe.TypeInt()) + v1.Aux = n + v1.AuxInt = off + config.PtrSize + v.AddArg(v1) + v2 := b.NewValue0(v.Line, OpArg, config.fe.TypeInt()) + v2.Aux = n + v2.AuxInt = off + 2*config.PtrSize + v.AddArg(v2) + return true + } + // match: (Arg {n} [off]) + // cond: v.Type.IsInterface() + // result: (IMake (Arg <config.fe.TypeBytePtr()> {n} [off]) (Arg <config.fe.TypeBytePtr()> {n} [off+config.PtrSize])) + for { + n := v.Aux + off := v.AuxInt + if !(v.Type.IsInterface()) { + break + } + v.reset(OpIMake) + v0 := b.NewValue0(v.Line, OpArg, config.fe.TypeBytePtr()) + v0.Aux = n + v0.AuxInt = off + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpArg, config.fe.TypeBytePtr()) + v1.Aux = n + v1.AuxInt = off + config.PtrSize + v.AddArg(v1) + return true + } + // match: (Arg {n} [off]) + // cond: v.Type.IsComplex() && v.Type.Size() == 16 + // result: (ComplexMake (Arg <config.fe.TypeFloat64()> {n} [off]) (Arg <config.fe.TypeFloat64()> {n} [off+8])) + for { + n := v.Aux + off := v.AuxInt + if !(v.Type.IsComplex() && v.Type.Size() == 16) { + break + } + v.reset(OpComplexMake) + v0 := b.NewValue0(v.Line, OpArg, config.fe.TypeFloat64()) + v0.Aux = n + v0.AuxInt = off + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpArg, config.fe.TypeFloat64()) + v1.Aux = n + v1.AuxInt = off + 8 + v.AddArg(v1) + return true + } + // match: (Arg {n} [off]) + // cond: v.Type.IsComplex() && v.Type.Size() == 8 + // result: (ComplexMake (Arg <config.fe.TypeFloat32()> {n} [off]) (Arg <config.fe.TypeFloat32()> {n} [off+4])) + for { + n := v.Aux + off := v.AuxInt + if !(v.Type.IsComplex() && v.Type.Size() == 8) { + break + } + v.reset(OpComplexMake) + v0 := b.NewValue0(v.Line, OpArg, config.fe.TypeFloat32()) + v0.Aux = n + v0.AuxInt = off + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpArg, config.fe.TypeFloat32()) + v1.Aux = n + v1.AuxInt = off + 4 + v.AddArg(v1) + return true + } + // match: (Arg <t>) + // cond: t.IsStruct() && t.NumFields() == 0 && config.fe.CanSSA(t) + // result: (StructMake0) + for { + t := v.Type + if !(t.IsStruct() && t.NumFields() == 0 && config.fe.CanSSA(t)) { + break + } + v.reset(OpStructMake0) + return true + } + // match: (Arg <t> {n} [off]) + // cond: t.IsStruct() && t.NumFields() == 1 && config.fe.CanSSA(t) + // result: (StructMake1 (Arg <t.FieldType(0)> {n} [off+t.FieldOff(0)])) + for { + t := v.Type + n := v.Aux + off := v.AuxInt + if !(t.IsStruct() && t.NumFields() == 1 && config.fe.CanSSA(t)) { + break + } + v.reset(OpStructMake1) + v0 := b.NewValue0(v.Line, OpArg, t.FieldType(0)) + v0.Aux = n + v0.AuxInt = off + t.FieldOff(0) + v.AddArg(v0) + return true + } + // match: (Arg <t> {n} [off]) + // cond: t.IsStruct() && t.NumFields() == 2 && config.fe.CanSSA(t) + // result: (StructMake2 (Arg <t.FieldType(0)> {n} [off+t.FieldOff(0)]) (Arg <t.FieldType(1)> {n} [off+t.FieldOff(1)])) + for { + t := v.Type + n := v.Aux + off := v.AuxInt + if !(t.IsStruct() && t.NumFields() == 2 && config.fe.CanSSA(t)) { + break + } + v.reset(OpStructMake2) + v0 := b.NewValue0(v.Line, OpArg, t.FieldType(0)) + v0.Aux = n + v0.AuxInt = off + t.FieldOff(0) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpArg, t.FieldType(1)) + v1.Aux = n + v1.AuxInt = off + t.FieldOff(1) + v.AddArg(v1) + return true + } + // match: (Arg <t> {n} [off]) + // cond: t.IsStruct() && t.NumFields() == 3 && config.fe.CanSSA(t) + // result: (StructMake3 (Arg <t.FieldType(0)> {n} [off+t.FieldOff(0)]) (Arg <t.FieldType(1)> {n} [off+t.FieldOff(1)]) (Arg <t.FieldType(2)> {n} [off+t.FieldOff(2)])) + for { + t := v.Type + n := v.Aux + off := v.AuxInt + if !(t.IsStruct() && t.NumFields() == 3 && config.fe.CanSSA(t)) { + break + } + v.reset(OpStructMake3) + v0 := b.NewValue0(v.Line, OpArg, t.FieldType(0)) + v0.Aux = n + v0.AuxInt = off + t.FieldOff(0) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpArg, t.FieldType(1)) + v1.Aux = n + v1.AuxInt = off + t.FieldOff(1) + v.AddArg(v1) + v2 := b.NewValue0(v.Line, OpArg, t.FieldType(2)) + v2.Aux = n + v2.AuxInt = off + t.FieldOff(2) + v.AddArg(v2) + return true + } + // match: (Arg <t> {n} [off]) + // cond: t.IsStruct() && t.NumFields() == 4 && config.fe.CanSSA(t) + // result: (StructMake4 (Arg <t.FieldType(0)> {n} [off+t.FieldOff(0)]) (Arg <t.FieldType(1)> {n} [off+t.FieldOff(1)]) (Arg <t.FieldType(2)> {n} [off+t.FieldOff(2)]) (Arg <t.FieldType(3)> {n} [off+t.FieldOff(3)])) + for { + t := v.Type + n := v.Aux + off := v.AuxInt + if !(t.IsStruct() && t.NumFields() == 4 && config.fe.CanSSA(t)) { + break + } + v.reset(OpStructMake4) + v0 := b.NewValue0(v.Line, OpArg, t.FieldType(0)) + v0.Aux = n + v0.AuxInt = off + t.FieldOff(0) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpArg, t.FieldType(1)) + v1.Aux = n + v1.AuxInt = off + t.FieldOff(1) + v.AddArg(v1) + v2 := b.NewValue0(v.Line, OpArg, t.FieldType(2)) + v2.Aux = n + v2.AuxInt = off + t.FieldOff(2) + v.AddArg(v2) + v3 := b.NewValue0(v.Line, OpArg, t.FieldType(3)) + v3.Aux = n + v3.AuxInt = off + t.FieldOff(3) + v.AddArg(v3) + return true + } + return false +} +func rewriteValuegeneric_OpArrayIndex(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ArrayIndex (Load ptr mem) idx) + // cond: b == v.Args[0].Block + // result: (Load (PtrIndex <v.Type.PtrTo()> ptr idx) mem) + for { + if v.Args[0].Op != OpLoad { + break + } + ptr := v.Args[0].Args[0] + mem := v.Args[0].Args[1] + idx := v.Args[1] + if !(b == v.Args[0].Block) { + break + } + v.reset(OpLoad) + v0 := b.NewValue0(v.Line, OpPtrIndex, v.Type.PtrTo()) + v0.AddArg(ptr) + v0.AddArg(idx) + v.AddArg(v0) + v.AddArg(mem) + return true + } + return false +} +func rewriteValuegeneric_OpCom16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Com16 (Com16 x)) + // cond: + // result: x + for { + if v.Args[0].Op != OpCom16 { + break + } + x := v.Args[0].Args[0] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValuegeneric_OpCom32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Com32 (Com32 x)) + // cond: + // result: x + for { + if v.Args[0].Op != OpCom32 { + break + } + x := v.Args[0].Args[0] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValuegeneric_OpCom64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Com64 (Com64 x)) + // cond: + // result: x + for { + if v.Args[0].Op != OpCom64 { + break + } + x := v.Args[0].Args[0] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValuegeneric_OpCom8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Com8 (Com8 x)) + // cond: + // result: x + for { + if v.Args[0].Op != OpCom8 { + break + } + x := v.Args[0].Args[0] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValuegeneric_OpComplexImag(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ComplexImag (ComplexMake _ imag )) + // cond: + // result: imag + for { + if v.Args[0].Op != OpComplexMake { + break + } + imag := v.Args[0].Args[1] + v.reset(OpCopy) + v.Type = imag.Type + v.AddArg(imag) + return true + } + return false +} +func rewriteValuegeneric_OpComplexReal(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ComplexReal (ComplexMake real _ )) + // cond: + // result: real + for { + if v.Args[0].Op != OpComplexMake { + break + } + real := v.Args[0].Args[0] + v.reset(OpCopy) + v.Type = real.Type + v.AddArg(real) + return true + } + return false +} +func rewriteValuegeneric_OpConstInterface(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ConstInterface) + // cond: + // result: (IMake (ConstNil <config.fe.TypeBytePtr()>) (ConstNil <config.fe.TypeBytePtr()>)) + for { + v.reset(OpIMake) + v0 := b.NewValue0(v.Line, OpConstNil, config.fe.TypeBytePtr()) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpConstNil, config.fe.TypeBytePtr()) + v.AddArg(v1) + return true + } + return false +} +func rewriteValuegeneric_OpConstSlice(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ConstSlice) + // cond: config.PtrSize == 4 + // result: (SliceMake (ConstNil <config.fe.TypeBytePtr()>) (Const32 <config.fe.TypeInt()> [0]) (Const32 <config.fe.TypeInt()> [0])) + for { + if !(config.PtrSize == 4) { + break + } + v.reset(OpSliceMake) + v0 := b.NewValue0(v.Line, OpConstNil, config.fe.TypeBytePtr()) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpConst32, config.fe.TypeInt()) + v1.AuxInt = 0 + v.AddArg(v1) + v2 := b.NewValue0(v.Line, OpConst32, config.fe.TypeInt()) + v2.AuxInt = 0 + v.AddArg(v2) + return true + } + // match: (ConstSlice) + // cond: config.PtrSize == 8 + // result: (SliceMake (ConstNil <config.fe.TypeBytePtr()>) (Const64 <config.fe.TypeInt()> [0]) (Const64 <config.fe.TypeInt()> [0])) + for { + if !(config.PtrSize == 8) { + break + } + v.reset(OpSliceMake) + v0 := b.NewValue0(v.Line, OpConstNil, config.fe.TypeBytePtr()) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpConst64, config.fe.TypeInt()) + v1.AuxInt = 0 + v.AddArg(v1) + v2 := b.NewValue0(v.Line, OpConst64, config.fe.TypeInt()) + v2.AuxInt = 0 + v.AddArg(v2) + return true + } + return false +} +func rewriteValuegeneric_OpConstString(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ConstString {s}) + // cond: config.PtrSize == 4 && s.(string) == "" + // result: (StringMake (ConstNil) (Const32 <config.fe.TypeInt()> [0])) + for { + s := v.Aux + if !(config.PtrSize == 4 && s.(string) == "") { + break + } + v.reset(OpStringMake) + v0 := b.NewValue0(v.Line, OpConstNil, config.fe.TypeBytePtr()) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpConst32, config.fe.TypeInt()) + v1.AuxInt = 0 + v.AddArg(v1) + return true + } + // match: (ConstString {s}) + // cond: config.PtrSize == 8 && s.(string) == "" + // result: (StringMake (ConstNil) (Const64 <config.fe.TypeInt()> [0])) + for { + s := v.Aux + if !(config.PtrSize == 8 && s.(string) == "") { + break + } + v.reset(OpStringMake) + v0 := b.NewValue0(v.Line, OpConstNil, config.fe.TypeBytePtr()) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpConst64, config.fe.TypeInt()) + v1.AuxInt = 0 + v.AddArg(v1) + return true + } + // match: (ConstString {s}) + // cond: config.PtrSize == 4 && s.(string) != "" + // result: (StringMake (Addr <config.fe.TypeBytePtr()> {config.fe.StringData(s.(string))} (SB)) (Const32 <config.fe.TypeInt()> [int64(len(s.(string)))])) + for { + s := v.Aux + if !(config.PtrSize == 4 && s.(string) != "") { + break + } + v.reset(OpStringMake) + v0 := b.NewValue0(v.Line, OpAddr, config.fe.TypeBytePtr()) + v0.Aux = config.fe.StringData(s.(string)) + v1 := b.NewValue0(v.Line, OpSB, config.fe.TypeUintptr()) + v0.AddArg(v1) + v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst32, config.fe.TypeInt()) + v2.AuxInt = int64(len(s.(string))) + v.AddArg(v2) + return true + } + // match: (ConstString {s}) + // cond: config.PtrSize == 8 && s.(string) != "" + // result: (StringMake (Addr <config.fe.TypeBytePtr()> {config.fe.StringData(s.(string))} (SB)) (Const64 <config.fe.TypeInt()> [int64(len(s.(string)))])) + for { + s := v.Aux + if !(config.PtrSize == 8 && s.(string) != "") { + break + } + v.reset(OpStringMake) + v0 := b.NewValue0(v.Line, OpAddr, config.fe.TypeBytePtr()) + v0.Aux = config.fe.StringData(s.(string)) + v1 := b.NewValue0(v.Line, OpSB, config.fe.TypeUintptr()) + v0.AddArg(v1) + v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst64, config.fe.TypeInt()) + v2.AuxInt = int64(len(s.(string))) + v.AddArg(v2) + return true + } + return false +} +func rewriteValuegeneric_OpConvert(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Convert (Add64 (Convert ptr mem) off) mem) + // cond: + // result: (Add64 ptr off) + for { + if v.Args[0].Op != OpAdd64 { + break + } + if v.Args[0].Args[0].Op != OpConvert { + break + } + ptr := v.Args[0].Args[0].Args[0] + mem := v.Args[0].Args[0].Args[1] + off := v.Args[0].Args[1] + if v.Args[1] != mem { + break + } + v.reset(OpAdd64) + v.AddArg(ptr) + v.AddArg(off) + return true + } + // match: (Convert (Add64 off (Convert ptr mem)) mem) + // cond: + // result: (Add64 ptr off) + for { + if v.Args[0].Op != OpAdd64 { + break + } + off := v.Args[0].Args[0] + if v.Args[0].Args[1].Op != OpConvert { + break + } + ptr := v.Args[0].Args[1].Args[0] + mem := v.Args[0].Args[1].Args[1] + if v.Args[1] != mem { + break + } + v.reset(OpAdd64) + v.AddArg(ptr) + v.AddArg(off) + return true + } + // match: (Convert (Convert ptr mem) mem) + // cond: + // result: ptr + for { + if v.Args[0].Op != OpConvert { + break + } + ptr := v.Args[0].Args[0] + mem := v.Args[0].Args[1] + if v.Args[1] != mem { + break + } + v.reset(OpCopy) + v.Type = ptr.Type + v.AddArg(ptr) + return true + } + return false +} +func rewriteValuegeneric_OpDiv64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Div64 <t> x (Const64 [c])) + // cond: c > 0 && smagic64ok(c) && smagic64m(c) > 0 + // result: (Sub64 <t> (Rsh64x64 <t> (Hmul64 <t> (Const64 <t> [smagic64m(c)]) x) (Const64 <t> [smagic64s(c)])) (Rsh64x64 <t> x (Const64 <t> [63]))) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + c := v.Args[1].AuxInt + if !(c > 0 && smagic64ok(c) && smagic64m(c) > 0) { + break + } + v.reset(OpSub64) + v.Type = t + v0 := b.NewValue0(v.Line, OpRsh64x64, t) + v1 := b.NewValue0(v.Line, OpHmul64, t) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = smagic64m(c) + v1.AddArg(v2) + v1.AddArg(x) + v0.AddArg(v1) + v3 := b.NewValue0(v.Line, OpConst64, t) + v3.AuxInt = smagic64s(c) + v0.AddArg(v3) + v.AddArg(v0) + v4 := b.NewValue0(v.Line, OpRsh64x64, t) + v4.AddArg(x) + v5 := b.NewValue0(v.Line, OpConst64, t) + v5.AuxInt = 63 + v4.AddArg(v5) + v.AddArg(v4) + return true + } + // match: (Div64 <t> x (Const64 [c])) + // cond: c > 0 && smagic64ok(c) && smagic64m(c) < 0 + // result: (Sub64 <t> (Rsh64x64 <t> (Add64 <t> (Hmul64 <t> (Const64 <t> [smagic64m(c)]) x) x) (Const64 <t> [smagic64s(c)])) (Rsh64x64 <t> x (Const64 <t> [63]))) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + c := v.Args[1].AuxInt + if !(c > 0 && smagic64ok(c) && smagic64m(c) < 0) { + break + } + v.reset(OpSub64) + v.Type = t + v0 := b.NewValue0(v.Line, OpRsh64x64, t) + v1 := b.NewValue0(v.Line, OpAdd64, t) + v2 := b.NewValue0(v.Line, OpHmul64, t) + v3 := b.NewValue0(v.Line, OpConst64, t) + v3.AuxInt = smagic64m(c) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v1.AddArg(x) + v0.AddArg(v1) + v4 := b.NewValue0(v.Line, OpConst64, t) + v4.AuxInt = smagic64s(c) + v0.AddArg(v4) + v.AddArg(v0) + v5 := b.NewValue0(v.Line, OpRsh64x64, t) + v5.AddArg(x) + v6 := b.NewValue0(v.Line, OpConst64, t) + v6.AuxInt = 63 + v5.AddArg(v6) + v.AddArg(v5) + return true + } + // match: (Div64 <t> x (Const64 [c])) + // cond: c < 0 && smagic64ok(c) && smagic64m(c) > 0 + // result: (Neg64 <t> (Sub64 <t> (Rsh64x64 <t> (Hmul64 <t> (Const64 <t> [smagic64m(c)]) x) (Const64 <t> [smagic64s(c)])) (Rsh64x64 <t> x (Const64 <t> [63])))) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + c := v.Args[1].AuxInt + if !(c < 0 && smagic64ok(c) && smagic64m(c) > 0) { + break + } + v.reset(OpNeg64) + v.Type = t + v0 := b.NewValue0(v.Line, OpSub64, t) + v1 := b.NewValue0(v.Line, OpRsh64x64, t) + v2 := b.NewValue0(v.Line, OpHmul64, t) + v3 := b.NewValue0(v.Line, OpConst64, t) + v3.AuxInt = smagic64m(c) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Line, OpConst64, t) + v4.AuxInt = smagic64s(c) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Line, OpRsh64x64, t) + v5.AddArg(x) + v6 := b.NewValue0(v.Line, OpConst64, t) + v6.AuxInt = 63 + v5.AddArg(v6) + v0.AddArg(v5) + v.AddArg(v0) + return true + } + // match: (Div64 <t> x (Const64 [c])) + // cond: c < 0 && smagic64ok(c) && smagic64m(c) < 0 + // result: (Neg64 <t> (Sub64 <t> (Rsh64x64 <t> (Add64 <t> (Hmul64 <t> (Const64 <t> [smagic64m(c)]) x) x) (Const64 <t> [smagic64s(c)])) (Rsh64x64 <t> x (Const64 <t> [63])))) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + c := v.Args[1].AuxInt + if !(c < 0 && smagic64ok(c) && smagic64m(c) < 0) { + break + } + v.reset(OpNeg64) + v.Type = t + v0 := b.NewValue0(v.Line, OpSub64, t) + v1 := b.NewValue0(v.Line, OpRsh64x64, t) + v2 := b.NewValue0(v.Line, OpAdd64, t) + v3 := b.NewValue0(v.Line, OpHmul64, t) + v4 := b.NewValue0(v.Line, OpConst64, t) + v4.AuxInt = smagic64m(c) + v3.AddArg(v4) + v3.AddArg(x) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v5 := b.NewValue0(v.Line, OpConst64, t) + v5.AuxInt = smagic64s(c) + v1.AddArg(v5) + v0.AddArg(v1) + v6 := b.NewValue0(v.Line, OpRsh64x64, t) + v6.AddArg(x) + v7 := b.NewValue0(v.Line, OpConst64, t) + v7.AuxInt = 63 + v6.AddArg(v7) + v0.AddArg(v6) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpDiv64u(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Div64u <t> x (Const64 [c])) + // cond: umagic64ok(c) && !umagic64a(c) + // result: (Rsh64Ux64 (Hmul64u <t> (Const64 <t> [umagic64m(c)]) x) (Const64 <t> [umagic64s(c)])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + c := v.Args[1].AuxInt + if !(umagic64ok(c) && !umagic64a(c)) { + break + } + v.reset(OpRsh64Ux64) + v0 := b.NewValue0(v.Line, OpHmul64u, t) + v1 := b.NewValue0(v.Line, OpConst64, t) + v1.AuxInt = umagic64m(c) + v0.AddArg(v1) + v0.AddArg(x) + v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = umagic64s(c) + v.AddArg(v2) + return true + } + // match: (Div64u <t> x (Const64 [c])) + // cond: umagic64ok(c) && umagic64a(c) + // result: (Rsh64Ux64 (Avg64u <t> (Hmul64u <t> x (Const64 <t> [umagic64m(c)])) x) (Const64 <t> [umagic64s(c)-1])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + c := v.Args[1].AuxInt + if !(umagic64ok(c) && umagic64a(c)) { + break + } + v.reset(OpRsh64Ux64) + v0 := b.NewValue0(v.Line, OpAvg64u, t) + v1 := b.NewValue0(v.Line, OpHmul64u, t) + v1.AddArg(x) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = umagic64m(c) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(x) + v.AddArg(v0) + v3 := b.NewValue0(v.Line, OpConst64, t) + v3.AuxInt = umagic64s(c) - 1 + v.AddArg(v3) + return true + } + return false +} +func rewriteValuegeneric_OpEq16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Eq16 x x) + // cond: + // result: (ConstBool [1]) + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpConstBool) + v.AuxInt = 1 + return true + } + // match: (Eq16 (Const16 <t> [c]) (Add16 (Const16 <t> [d]) x)) + // cond: + // result: (Eq16 (Const16 <t> [c-d]) x) + for { + if v.Args[0].Op != OpConst16 { + break + } + t := v.Args[0].Type + c := v.Args[0].AuxInt + if v.Args[1].Op != OpAdd16 { + break + } + if v.Args[1].Args[0].Op != OpConst16 { + break + } + if v.Args[1].Args[0].Type != v.Args[0].Type { + break + } + d := v.Args[1].Args[0].AuxInt + x := v.Args[1].Args[1] + v.reset(OpEq16) + v0 := b.NewValue0(v.Line, OpConst16, t) + v0.AuxInt = c - d + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Eq16 x (Const16 <t> [c])) + // cond: x.Op != OpConst16 + // result: (Eq16 (Const16 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst16 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst16) { + break + } + v.reset(OpEq16) + v0 := b.NewValue0(v.Line, OpConst16, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Eq16 (Const16 [c]) (Const16 [d])) + // cond: + // result: (ConstBool [b2i(int16(c) == int16(d))]) + for { + if v.Args[0].Op != OpConst16 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst16 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(int16(c) == int16(d)) + return true + } + return false +} +func rewriteValuegeneric_OpEq32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Eq32 x x) + // cond: + // result: (ConstBool [1]) + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpConstBool) + v.AuxInt = 1 + return true + } + // match: (Eq32 (Const32 <t> [c]) (Add32 (Const32 <t> [d]) x)) + // cond: + // result: (Eq32 (Const32 <t> [c-d]) x) + for { + if v.Args[0].Op != OpConst32 { + break + } + t := v.Args[0].Type + c := v.Args[0].AuxInt + if v.Args[1].Op != OpAdd32 { + break + } + if v.Args[1].Args[0].Op != OpConst32 { + break + } + if v.Args[1].Args[0].Type != v.Args[0].Type { + break + } + d := v.Args[1].Args[0].AuxInt + x := v.Args[1].Args[1] + v.reset(OpEq32) + v0 := b.NewValue0(v.Line, OpConst32, t) + v0.AuxInt = c - d + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Eq32 x (Const32 <t> [c])) + // cond: x.Op != OpConst32 + // result: (Eq32 (Const32 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst32 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst32) { + break + } + v.reset(OpEq32) + v0 := b.NewValue0(v.Line, OpConst32, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Eq32 (Const32 [c]) (Const32 [d])) + // cond: + // result: (ConstBool [b2i(int32(c) == int32(d))]) + for { + if v.Args[0].Op != OpConst32 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst32 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(int32(c) == int32(d)) + return true + } + return false +} +func rewriteValuegeneric_OpEq64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Eq64 x x) + // cond: + // result: (ConstBool [1]) + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpConstBool) + v.AuxInt = 1 + return true + } + // match: (Eq64 (Const64 <t> [c]) (Add64 (Const64 <t> [d]) x)) + // cond: + // result: (Eq64 (Const64 <t> [c-d]) x) + for { + if v.Args[0].Op != OpConst64 { + break + } + t := v.Args[0].Type + c := v.Args[0].AuxInt + if v.Args[1].Op != OpAdd64 { + break + } + if v.Args[1].Args[0].Op != OpConst64 { + break + } + if v.Args[1].Args[0].Type != v.Args[0].Type { + break + } + d := v.Args[1].Args[0].AuxInt + x := v.Args[1].Args[1] + v.reset(OpEq64) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = c - d + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Eq64 x (Const64 <t> [c])) + // cond: x.Op != OpConst64 + // result: (Eq64 (Const64 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst64) { + break + } + v.reset(OpEq64) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Eq64 (Const64 [c]) (Const64 [d])) + // cond: + // result: (ConstBool [b2i(int64(c) == int64(d))]) + for { + if v.Args[0].Op != OpConst64 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(int64(c) == int64(d)) + return true + } + return false +} +func rewriteValuegeneric_OpEq8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Eq8 x x) + // cond: + // result: (ConstBool [1]) + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpConstBool) + v.AuxInt = 1 + return true + } + // match: (Eq8 (ConstBool [c]) (ConstBool [d])) + // cond: + // result: (ConstBool [b2i((int8(c) != 0) == (int8(d) != 0))]) + for { + if v.Args[0].Op != OpConstBool { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConstBool { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i((int8(c) != 0) == (int8(d) != 0)) + return true + } + // match: (Eq8 (ConstBool [0]) x) + // cond: + // result: (Not x) + for { + if v.Args[0].Op != OpConstBool { + break + } + if v.Args[0].AuxInt != 0 { + break + } + x := v.Args[1] + v.reset(OpNot) + v.AddArg(x) + return true + } + // match: (Eq8 (ConstBool [1]) x) + // cond: + // result: x + for { + if v.Args[0].Op != OpConstBool { + break + } + if v.Args[0].AuxInt != 1 { + break + } + x := v.Args[1] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (Eq8 (Const8 <t> [c]) (Add8 (Const8 <t> [d]) x)) + // cond: + // result: (Eq8 (Const8 <t> [c-d]) x) + for { + if v.Args[0].Op != OpConst8 { + break + } + t := v.Args[0].Type + c := v.Args[0].AuxInt + if v.Args[1].Op != OpAdd8 { + break + } + if v.Args[1].Args[0].Op != OpConst8 { + break + } + if v.Args[1].Args[0].Type != v.Args[0].Type { + break + } + d := v.Args[1].Args[0].AuxInt + x := v.Args[1].Args[1] + v.reset(OpEq8) + v0 := b.NewValue0(v.Line, OpConst8, t) + v0.AuxInt = c - d + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Eq8 x (Const8 <t> [c])) + // cond: x.Op != OpConst8 + // result: (Eq8 (Const8 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst8 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst8) { + break + } + v.reset(OpEq8) + v0 := b.NewValue0(v.Line, OpConst8, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Eq8 x (ConstBool <t> [c])) + // cond: x.Op != OpConstBool + // result: (Eq8 (ConstBool <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConstBool { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConstBool) { + break + } + v.reset(OpEq8) + v0 := b.NewValue0(v.Line, OpConstBool, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Eq8 (Const8 [c]) (Const8 [d])) + // cond: + // result: (ConstBool [b2i(int8(c) == int8(d))]) + for { + if v.Args[0].Op != OpConst8 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst8 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(int8(c) == int8(d)) + return true + } + return false +} +func rewriteValuegeneric_OpEqInter(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (EqInter x y) + // cond: + // result: (EqPtr (ITab x) (ITab y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpEqPtr) + v0 := b.NewValue0(v.Line, OpITab, config.fe.TypeBytePtr()) + v0.AddArg(x) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpITab, config.fe.TypeBytePtr()) + v1.AddArg(y) + v.AddArg(v1) + return true + } + return false +} +func rewriteValuegeneric_OpEqPtr(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (EqPtr p (ConstNil)) + // cond: + // result: (Not (IsNonNil p)) + for { + p := v.Args[0] + if v.Args[1].Op != OpConstNil { + break + } + v.reset(OpNot) + v0 := b.NewValue0(v.Line, OpIsNonNil, config.fe.TypeBool()) + v0.AddArg(p) + v.AddArg(v0) + return true + } + // match: (EqPtr (ConstNil) p) + // cond: + // result: (Not (IsNonNil p)) + for { + if v.Args[0].Op != OpConstNil { + break + } + p := v.Args[1] + v.reset(OpNot) + v0 := b.NewValue0(v.Line, OpIsNonNil, config.fe.TypeBool()) + v0.AddArg(p) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpEqSlice(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (EqSlice x y) + // cond: + // result: (EqPtr (SlicePtr x) (SlicePtr y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpEqPtr) + v0 := b.NewValue0(v.Line, OpSlicePtr, config.fe.TypeBytePtr()) + v0.AddArg(x) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpSlicePtr, config.fe.TypeBytePtr()) + v1.AddArg(y) + v.AddArg(v1) + return true + } + return false +} +func rewriteValuegeneric_OpGeq16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Geq16 (Const16 [c]) (Const16 [d])) + // cond: + // result: (ConstBool [b2i(int16(c) >= int16(d))]) + for { + if v.Args[0].Op != OpConst16 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst16 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(int16(c) >= int16(d)) + return true + } + return false +} +func rewriteValuegeneric_OpGeq16U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Geq16U (Const16 [c]) (Const16 [d])) + // cond: + // result: (ConstBool [b2i(uint16(c) >= uint16(d))]) + for { + if v.Args[0].Op != OpConst16 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst16 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(uint16(c) >= uint16(d)) + return true + } + return false +} +func rewriteValuegeneric_OpGeq32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Geq32 (Const32 [c]) (Const32 [d])) + // cond: + // result: (ConstBool [b2i(int32(c) >= int32(d))]) + for { + if v.Args[0].Op != OpConst32 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst32 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(int32(c) >= int32(d)) + return true + } + return false +} +func rewriteValuegeneric_OpGeq32U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Geq32U (Const32 [c]) (Const32 [d])) + // cond: + // result: (ConstBool [b2i(uint32(c) >= uint32(d))]) + for { + if v.Args[0].Op != OpConst32 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst32 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(uint32(c) >= uint32(d)) + return true + } + return false +} +func rewriteValuegeneric_OpGeq64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Geq64 (Const64 [c]) (Const64 [d])) + // cond: + // result: (ConstBool [b2i(int64(c) >= int64(d))]) + for { + if v.Args[0].Op != OpConst64 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(int64(c) >= int64(d)) + return true + } + return false +} +func rewriteValuegeneric_OpGeq64U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Geq64U (Const64 [c]) (Const64 [d])) + // cond: + // result: (ConstBool [b2i(uint64(c) >= uint64(d))]) + for { + if v.Args[0].Op != OpConst64 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(uint64(c) >= uint64(d)) + return true + } + return false +} +func rewriteValuegeneric_OpGeq8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Geq8 (Const8 [c]) (Const8 [d])) + // cond: + // result: (ConstBool [b2i(int8(c) >= int8(d))]) + for { + if v.Args[0].Op != OpConst8 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst8 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(int8(c) >= int8(d)) + return true + } + return false +} +func rewriteValuegeneric_OpGeq8U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Geq8U (Const8 [c]) (Const8 [d])) + // cond: + // result: (ConstBool [b2i(uint8(c) >= uint8(d))]) + for { + if v.Args[0].Op != OpConst8 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst8 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(uint8(c) >= uint8(d)) + return true + } + return false +} +func rewriteValuegeneric_OpGreater16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Greater16 (Const16 [c]) (Const16 [d])) + // cond: + // result: (ConstBool [b2i(int16(c) > int16(d))]) + for { + if v.Args[0].Op != OpConst16 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst16 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(int16(c) > int16(d)) + return true + } + return false +} +func rewriteValuegeneric_OpGreater16U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Greater16U (Const16 [c]) (Const16 [d])) + // cond: + // result: (ConstBool [b2i(uint16(c) > uint16(d))]) + for { + if v.Args[0].Op != OpConst16 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst16 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(uint16(c) > uint16(d)) + return true + } + return false +} +func rewriteValuegeneric_OpGreater32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Greater32 (Const32 [c]) (Const32 [d])) + // cond: + // result: (ConstBool [b2i(int32(c) > int32(d))]) + for { + if v.Args[0].Op != OpConst32 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst32 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(int32(c) > int32(d)) + return true + } + return false +} +func rewriteValuegeneric_OpGreater32U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Greater32U (Const32 [c]) (Const32 [d])) + // cond: + // result: (ConstBool [b2i(uint32(c) > uint32(d))]) + for { + if v.Args[0].Op != OpConst32 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst32 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(uint32(c) > uint32(d)) + return true + } + return false +} +func rewriteValuegeneric_OpGreater64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Greater64 (Const64 [c]) (Const64 [d])) + // cond: + // result: (ConstBool [b2i(int64(c) > int64(d))]) + for { + if v.Args[0].Op != OpConst64 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(int64(c) > int64(d)) + return true + } + return false +} +func rewriteValuegeneric_OpGreater64U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Greater64U (Const64 [c]) (Const64 [d])) + // cond: + // result: (ConstBool [b2i(uint64(c) > uint64(d))]) + for { + if v.Args[0].Op != OpConst64 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(uint64(c) > uint64(d)) + return true + } + return false +} +func rewriteValuegeneric_OpGreater8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Greater8 (Const8 [c]) (Const8 [d])) + // cond: + // result: (ConstBool [b2i(int8(c) > int8(d))]) + for { + if v.Args[0].Op != OpConst8 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst8 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(int8(c) > int8(d)) + return true + } + return false +} +func rewriteValuegeneric_OpGreater8U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Greater8U (Const8 [c]) (Const8 [d])) + // cond: + // result: (ConstBool [b2i(uint8(c) > uint8(d))]) + for { + if v.Args[0].Op != OpConst8 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst8 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(uint8(c) > uint8(d)) + return true + } + return false +} +func rewriteValuegeneric_OpIData(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (IData (IMake _ data)) + // cond: + // result: data + for { + if v.Args[0].Op != OpIMake { + break + } + data := v.Args[0].Args[1] + v.reset(OpCopy) + v.Type = data.Type + v.AddArg(data) + return true + } + return false +} +func rewriteValuegeneric_OpITab(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (ITab (IMake itab _)) + // cond: + // result: itab + for { + if v.Args[0].Op != OpIMake { + break + } + itab := v.Args[0].Args[0] + v.reset(OpCopy) + v.Type = itab.Type + v.AddArg(itab) + return true + } + return false +} +func rewriteValuegeneric_OpIsInBounds(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (IsInBounds (Const32 [c]) (Const32 [d])) + // cond: + // result: (ConstBool [b2i(inBounds32(c,d))]) + for { + if v.Args[0].Op != OpConst32 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst32 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(inBounds32(c, d)) + return true + } + // match: (IsInBounds (Const64 [c]) (Const64 [d])) + // cond: + // result: (ConstBool [b2i(inBounds64(c,d))]) + for { + if v.Args[0].Op != OpConst64 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(inBounds64(c, d)) + return true + } + return false +} +func rewriteValuegeneric_OpIsSliceInBounds(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (IsSliceInBounds (Const32 [c]) (Const32 [d])) + // cond: + // result: (ConstBool [b2i(sliceInBounds32(c,d))]) + for { + if v.Args[0].Op != OpConst32 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst32 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(sliceInBounds32(c, d)) + return true + } + // match: (IsSliceInBounds (Const64 [c]) (Const64 [d])) + // cond: + // result: (ConstBool [b2i(sliceInBounds64(c,d))]) + for { + if v.Args[0].Op != OpConst64 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(sliceInBounds64(c, d)) + return true + } + return false +} +func rewriteValuegeneric_OpLeq16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Leq16 (Const16 [c]) (Const16 [d])) + // cond: + // result: (ConstBool [b2i(int16(c) <= int16(d))]) + for { + if v.Args[0].Op != OpConst16 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst16 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(int16(c) <= int16(d)) + return true + } + return false +} +func rewriteValuegeneric_OpLeq16U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Leq16U (Const16 [c]) (Const16 [d])) + // cond: + // result: (ConstBool [b2i(uint16(c) <= uint16(d))]) + for { + if v.Args[0].Op != OpConst16 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst16 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(uint16(c) <= uint16(d)) + return true + } + return false +} +func rewriteValuegeneric_OpLeq32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Leq32 (Const32 [c]) (Const32 [d])) + // cond: + // result: (ConstBool [b2i(int32(c) <= int32(d))]) + for { + if v.Args[0].Op != OpConst32 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst32 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(int32(c) <= int32(d)) + return true + } + return false +} +func rewriteValuegeneric_OpLeq32U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Leq32U (Const32 [c]) (Const32 [d])) + // cond: + // result: (ConstBool [b2i(uint32(c) <= uint32(d))]) + for { + if v.Args[0].Op != OpConst32 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst32 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(uint32(c) <= uint32(d)) + return true + } + return false +} +func rewriteValuegeneric_OpLeq64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Leq64 (Const64 [c]) (Const64 [d])) + // cond: + // result: (ConstBool [b2i(int64(c) <= int64(d))]) + for { + if v.Args[0].Op != OpConst64 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(int64(c) <= int64(d)) + return true + } + return false +} +func rewriteValuegeneric_OpLeq64U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Leq64U (Const64 [c]) (Const64 [d])) + // cond: + // result: (ConstBool [b2i(uint64(c) <= uint64(d))]) + for { + if v.Args[0].Op != OpConst64 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(uint64(c) <= uint64(d)) + return true + } + return false +} +func rewriteValuegeneric_OpLeq8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Leq8 (Const8 [c]) (Const8 [d])) + // cond: + // result: (ConstBool [b2i(int8(c) <= int8(d))]) + for { + if v.Args[0].Op != OpConst8 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst8 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(int8(c) <= int8(d)) + return true + } + return false +} +func rewriteValuegeneric_OpLeq8U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Leq8U (Const8 [c]) (Const8 [d])) + // cond: + // result: (ConstBool [b2i(uint8(c) <= uint8(d))]) + for { + if v.Args[0].Op != OpConst8 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst8 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(uint8(c) <= uint8(d)) + return true + } + return false +} +func rewriteValuegeneric_OpLess16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Less16 (Const16 [c]) (Const16 [d])) + // cond: + // result: (ConstBool [b2i(int16(c) < int16(d))]) + for { + if v.Args[0].Op != OpConst16 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst16 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(int16(c) < int16(d)) + return true + } + return false +} +func rewriteValuegeneric_OpLess16U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Less16U (Const16 [c]) (Const16 [d])) + // cond: + // result: (ConstBool [b2i(uint16(c) < uint16(d))]) + for { + if v.Args[0].Op != OpConst16 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst16 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(uint16(c) < uint16(d)) + return true + } + return false +} +func rewriteValuegeneric_OpLess32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Less32 (Const32 [c]) (Const32 [d])) + // cond: + // result: (ConstBool [b2i(int32(c) < int32(d))]) + for { + if v.Args[0].Op != OpConst32 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst32 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(int32(c) < int32(d)) + return true + } + return false +} +func rewriteValuegeneric_OpLess32U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Less32U (Const32 [c]) (Const32 [d])) + // cond: + // result: (ConstBool [b2i(uint32(c) < uint32(d))]) + for { + if v.Args[0].Op != OpConst32 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst32 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(uint32(c) < uint32(d)) + return true + } + return false +} +func rewriteValuegeneric_OpLess64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Less64 (Const64 [c]) (Const64 [d])) + // cond: + // result: (ConstBool [b2i(int64(c) < int64(d))]) + for { + if v.Args[0].Op != OpConst64 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(int64(c) < int64(d)) + return true + } + return false +} +func rewriteValuegeneric_OpLess64U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Less64U (Const64 [c]) (Const64 [d])) + // cond: + // result: (ConstBool [b2i(uint64(c) < uint64(d))]) + for { + if v.Args[0].Op != OpConst64 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(uint64(c) < uint64(d)) + return true + } + return false +} +func rewriteValuegeneric_OpLess8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Less8 (Const8 [c]) (Const8 [d])) + // cond: + // result: (ConstBool [b2i(int8(c) < int8(d))]) + for { + if v.Args[0].Op != OpConst8 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst8 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(int8(c) < int8(d)) + return true + } + return false +} +func rewriteValuegeneric_OpLess8U(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Less8U (Const8 [c]) (Const8 [d])) + // cond: + // result: (ConstBool [b2i(uint8(c) < uint8(d))]) + for { + if v.Args[0].Op != OpConst8 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst8 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(uint8(c) < uint8(d)) + return true + } + return false +} +func rewriteValuegeneric_OpLoad(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Load <t1> p1 (Store [w] p2 x _)) + // cond: isSamePtr(p1,p2) && t1.Compare(x.Type)==CMPeq && w == t1.Size() + // result: x + for { + t1 := v.Type + p1 := v.Args[0] + if v.Args[1].Op != OpStore { + break + } + w := v.Args[1].AuxInt + p2 := v.Args[1].Args[0] + x := v.Args[1].Args[1] + if !(isSamePtr(p1, p2) && t1.Compare(x.Type) == CMPeq && w == t1.Size()) { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (Load <t> _ _) + // cond: t.IsStruct() && t.NumFields() == 0 && config.fe.CanSSA(t) + // result: (StructMake0) + for { + t := v.Type + if !(t.IsStruct() && t.NumFields() == 0 && config.fe.CanSSA(t)) { + break + } + v.reset(OpStructMake0) + return true + } + // match: (Load <t> ptr mem) + // cond: t.IsStruct() && t.NumFields() == 1 && config.fe.CanSSA(t) + // result: (StructMake1 (Load <t.FieldType(0)> ptr mem)) + for { + t := v.Type + ptr := v.Args[0] + mem := v.Args[1] + if !(t.IsStruct() && t.NumFields() == 1 && config.fe.CanSSA(t)) { + break + } + v.reset(OpStructMake1) + v0 := b.NewValue0(v.Line, OpLoad, t.FieldType(0)) + v0.AddArg(ptr) + v0.AddArg(mem) + v.AddArg(v0) + return true + } + // match: (Load <t> ptr mem) + // cond: t.IsStruct() && t.NumFields() == 2 && config.fe.CanSSA(t) + // result: (StructMake2 (Load <t.FieldType(0)> ptr mem) (Load <t.FieldType(1)> (OffPtr <t.FieldType(1).PtrTo()> [t.FieldOff(1)] ptr) mem)) + for { + t := v.Type + ptr := v.Args[0] + mem := v.Args[1] + if !(t.IsStruct() && t.NumFields() == 2 && config.fe.CanSSA(t)) { + break + } + v.reset(OpStructMake2) + v0 := b.NewValue0(v.Line, OpLoad, t.FieldType(0)) + v0.AddArg(ptr) + v0.AddArg(mem) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpLoad, t.FieldType(1)) + v2 := b.NewValue0(v.Line, OpOffPtr, t.FieldType(1).PtrTo()) + v2.AuxInt = t.FieldOff(1) + v2.AddArg(ptr) + v1.AddArg(v2) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + // match: (Load <t> ptr mem) + // cond: t.IsStruct() && t.NumFields() == 3 && config.fe.CanSSA(t) + // result: (StructMake3 (Load <t.FieldType(0)> ptr mem) (Load <t.FieldType(1)> (OffPtr <t.FieldType(1).PtrTo()> [t.FieldOff(1)] ptr) mem) (Load <t.FieldType(2)> (OffPtr <t.FieldType(2).PtrTo()> [t.FieldOff(2)] ptr) mem)) + for { + t := v.Type + ptr := v.Args[0] + mem := v.Args[1] + if !(t.IsStruct() && t.NumFields() == 3 && config.fe.CanSSA(t)) { + break + } + v.reset(OpStructMake3) + v0 := b.NewValue0(v.Line, OpLoad, t.FieldType(0)) + v0.AddArg(ptr) + v0.AddArg(mem) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpLoad, t.FieldType(1)) + v2 := b.NewValue0(v.Line, OpOffPtr, t.FieldType(1).PtrTo()) + v2.AuxInt = t.FieldOff(1) + v2.AddArg(ptr) + v1.AddArg(v2) + v1.AddArg(mem) + v.AddArg(v1) + v3 := b.NewValue0(v.Line, OpLoad, t.FieldType(2)) + v4 := b.NewValue0(v.Line, OpOffPtr, t.FieldType(2).PtrTo()) + v4.AuxInt = t.FieldOff(2) + v4.AddArg(ptr) + v3.AddArg(v4) + v3.AddArg(mem) + v.AddArg(v3) + return true + } + // match: (Load <t> ptr mem) + // cond: t.IsStruct() && t.NumFields() == 4 && config.fe.CanSSA(t) + // result: (StructMake4 (Load <t.FieldType(0)> ptr mem) (Load <t.FieldType(1)> (OffPtr <t.FieldType(1).PtrTo()> [t.FieldOff(1)] ptr) mem) (Load <t.FieldType(2)> (OffPtr <t.FieldType(2).PtrTo()> [t.FieldOff(2)] ptr) mem) (Load <t.FieldType(3)> (OffPtr <t.FieldType(3).PtrTo()> [t.FieldOff(3)] ptr) mem)) + for { + t := v.Type + ptr := v.Args[0] + mem := v.Args[1] + if !(t.IsStruct() && t.NumFields() == 4 && config.fe.CanSSA(t)) { + break + } + v.reset(OpStructMake4) + v0 := b.NewValue0(v.Line, OpLoad, t.FieldType(0)) + v0.AddArg(ptr) + v0.AddArg(mem) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpLoad, t.FieldType(1)) + v2 := b.NewValue0(v.Line, OpOffPtr, t.FieldType(1).PtrTo()) + v2.AuxInt = t.FieldOff(1) + v2.AddArg(ptr) + v1.AddArg(v2) + v1.AddArg(mem) + v.AddArg(v1) + v3 := b.NewValue0(v.Line, OpLoad, t.FieldType(2)) + v4 := b.NewValue0(v.Line, OpOffPtr, t.FieldType(2).PtrTo()) + v4.AuxInt = t.FieldOff(2) + v4.AddArg(ptr) + v3.AddArg(v4) + v3.AddArg(mem) + v.AddArg(v3) + v5 := b.NewValue0(v.Line, OpLoad, t.FieldType(3)) + v6 := b.NewValue0(v.Line, OpOffPtr, t.FieldType(3).PtrTo()) + v6.AuxInt = t.FieldOff(3) + v6.AddArg(ptr) + v5.AddArg(v6) + v5.AddArg(mem) + v.AddArg(v5) + return true + } + // match: (Load <t> ptr mem) + // cond: t.IsComplex() && t.Size() == 8 + // result: (ComplexMake (Load <config.fe.TypeFloat32()> ptr mem) (Load <config.fe.TypeFloat32()> (OffPtr <config.fe.TypeFloat32().PtrTo()> [4] ptr) mem) ) + for { + t := v.Type + ptr := v.Args[0] + mem := v.Args[1] + if !(t.IsComplex() && t.Size() == 8) { + break + } + v.reset(OpComplexMake) + v0 := b.NewValue0(v.Line, OpLoad, config.fe.TypeFloat32()) + v0.AddArg(ptr) + v0.AddArg(mem) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpLoad, config.fe.TypeFloat32()) + v2 := b.NewValue0(v.Line, OpOffPtr, config.fe.TypeFloat32().PtrTo()) + v2.AuxInt = 4 + v2.AddArg(ptr) + v1.AddArg(v2) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + // match: (Load <t> ptr mem) + // cond: t.IsComplex() && t.Size() == 16 + // result: (ComplexMake (Load <config.fe.TypeFloat64()> ptr mem) (Load <config.fe.TypeFloat64()> (OffPtr <config.fe.TypeFloat64().PtrTo()> [8] ptr) mem) ) + for { + t := v.Type + ptr := v.Args[0] + mem := v.Args[1] + if !(t.IsComplex() && t.Size() == 16) { + break + } + v.reset(OpComplexMake) + v0 := b.NewValue0(v.Line, OpLoad, config.fe.TypeFloat64()) + v0.AddArg(ptr) + v0.AddArg(mem) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpLoad, config.fe.TypeFloat64()) + v2 := b.NewValue0(v.Line, OpOffPtr, config.fe.TypeFloat64().PtrTo()) + v2.AuxInt = 8 + v2.AddArg(ptr) + v1.AddArg(v2) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + // match: (Load <t> ptr mem) + // cond: t.IsString() + // result: (StringMake (Load <config.fe.TypeBytePtr()> ptr mem) (Load <config.fe.TypeInt()> (OffPtr <config.fe.TypeInt().PtrTo()> [config.PtrSize] ptr) mem)) + for { + t := v.Type + ptr := v.Args[0] + mem := v.Args[1] + if !(t.IsString()) { + break + } + v.reset(OpStringMake) + v0 := b.NewValue0(v.Line, OpLoad, config.fe.TypeBytePtr()) + v0.AddArg(ptr) + v0.AddArg(mem) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpLoad, config.fe.TypeInt()) + v2 := b.NewValue0(v.Line, OpOffPtr, config.fe.TypeInt().PtrTo()) + v2.AuxInt = config.PtrSize + v2.AddArg(ptr) + v1.AddArg(v2) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + // match: (Load <t> ptr mem) + // cond: t.IsSlice() + // result: (SliceMake (Load <config.fe.TypeBytePtr()> ptr mem) (Load <config.fe.TypeInt()> (OffPtr <config.fe.TypeInt().PtrTo()> [config.PtrSize] ptr) mem) (Load <config.fe.TypeInt()> (OffPtr <config.fe.TypeInt().PtrTo()> [2*config.PtrSize] ptr) mem)) + for { + t := v.Type + ptr := v.Args[0] + mem := v.Args[1] + if !(t.IsSlice()) { + break + } + v.reset(OpSliceMake) + v0 := b.NewValue0(v.Line, OpLoad, config.fe.TypeBytePtr()) + v0.AddArg(ptr) + v0.AddArg(mem) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpLoad, config.fe.TypeInt()) + v2 := b.NewValue0(v.Line, OpOffPtr, config.fe.TypeInt().PtrTo()) + v2.AuxInt = config.PtrSize + v2.AddArg(ptr) + v1.AddArg(v2) + v1.AddArg(mem) + v.AddArg(v1) + v3 := b.NewValue0(v.Line, OpLoad, config.fe.TypeInt()) + v4 := b.NewValue0(v.Line, OpOffPtr, config.fe.TypeInt().PtrTo()) + v4.AuxInt = 2 * config.PtrSize + v4.AddArg(ptr) + v3.AddArg(v4) + v3.AddArg(mem) + v.AddArg(v3) + return true + } + // match: (Load <t> ptr mem) + // cond: t.IsInterface() + // result: (IMake (Load <config.fe.TypeBytePtr()> ptr mem) (Load <config.fe.TypeBytePtr()> (OffPtr <config.fe.TypeBytePtr().PtrTo()> [config.PtrSize] ptr) mem)) + for { + t := v.Type + ptr := v.Args[0] + mem := v.Args[1] + if !(t.IsInterface()) { + break + } + v.reset(OpIMake) + v0 := b.NewValue0(v.Line, OpLoad, config.fe.TypeBytePtr()) + v0.AddArg(ptr) + v0.AddArg(mem) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpLoad, config.fe.TypeBytePtr()) + v2 := b.NewValue0(v.Line, OpOffPtr, config.fe.TypeBytePtr().PtrTo()) + v2.AuxInt = config.PtrSize + v2.AddArg(ptr) + v1.AddArg(v2) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + return false +} +func rewriteValuegeneric_OpLsh16x16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh16x16 <t> x (Const16 [c])) + // cond: + // result: (Lsh16x64 x (Const64 <t> [int64(uint16(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst16 { + break + } + c := v.Args[1].AuxInt + v.reset(OpLsh16x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint16(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpLsh16x32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh16x32 <t> x (Const32 [c])) + // cond: + // result: (Lsh16x64 x (Const64 <t> [int64(uint32(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst32 { + break + } + c := v.Args[1].AuxInt + v.reset(OpLsh16x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint32(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpLsh16x64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh16x64 (Const16 [c]) (Const64 [d])) + // cond: + // result: (Const16 [int64(int16(c) << uint64(d))]) + for { + if v.Args[0].Op != OpConst16 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConst16) + v.AuxInt = int64(int16(c) << uint64(d)) + return true + } + // match: (Lsh16x64 (Const16 [0]) _) + // cond: + // result: (Const16 [0]) + for { + if v.Args[0].Op != OpConst16 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst16) + v.AuxInt = 0 + return true + } + // match: (Lsh16x64 x (Const64 [0])) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + if v.Args[1].AuxInt != 0 { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (Lsh16x64 _ (Const64 [c])) + // cond: uint64(c) >= 16 + // result: (Const16 [0]) + for { + if v.Args[1].Op != OpConst64 { + break + } + c := v.Args[1].AuxInt + if !(uint64(c) >= 16) { + break + } + v.reset(OpConst16) + v.AuxInt = 0 + return true + } + // match: (Lsh16x64 <t> (Lsh16x64 x (Const64 [c])) (Const64 [d])) + // cond: !uaddOvf(c,d) + // result: (Lsh16x64 x (Const64 <t> [c+d])) + for { + t := v.Type + if v.Args[0].Op != OpLsh16x64 { + break + } + x := v.Args[0].Args[0] + if v.Args[0].Args[1].Op != OpConst64 { + break + } + c := v.Args[0].Args[1].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + if !(!uaddOvf(c, d)) { + break + } + v.reset(OpLsh16x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = c + d + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpLsh16x8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh16x8 <t> x (Const8 [c])) + // cond: + // result: (Lsh16x64 x (Const64 <t> [int64(uint8(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst8 { + break + } + c := v.Args[1].AuxInt + v.reset(OpLsh16x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint8(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpLsh32x16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh32x16 <t> x (Const16 [c])) + // cond: + // result: (Lsh32x64 x (Const64 <t> [int64(uint16(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst16 { + break + } + c := v.Args[1].AuxInt + v.reset(OpLsh32x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint16(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpLsh32x32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh32x32 <t> x (Const32 [c])) + // cond: + // result: (Lsh32x64 x (Const64 <t> [int64(uint32(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst32 { + break + } + c := v.Args[1].AuxInt + v.reset(OpLsh32x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint32(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpLsh32x64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh32x64 (Const32 [c]) (Const64 [d])) + // cond: + // result: (Const32 [int64(int32(c) << uint64(d))]) + for { + if v.Args[0].Op != OpConst32 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConst32) + v.AuxInt = int64(int32(c) << uint64(d)) + return true + } + // match: (Lsh32x64 (Const32 [0]) _) + // cond: + // result: (Const32 [0]) + for { + if v.Args[0].Op != OpConst32 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst32) + v.AuxInt = 0 + return true + } + // match: (Lsh32x64 x (Const64 [0])) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + if v.Args[1].AuxInt != 0 { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (Lsh32x64 _ (Const64 [c])) + // cond: uint64(c) >= 32 + // result: (Const32 [0]) + for { + if v.Args[1].Op != OpConst64 { + break + } + c := v.Args[1].AuxInt + if !(uint64(c) >= 32) { + break + } + v.reset(OpConst32) + v.AuxInt = 0 + return true + } + // match: (Lsh32x64 <t> (Lsh32x64 x (Const64 [c])) (Const64 [d])) + // cond: !uaddOvf(c,d) + // result: (Lsh32x64 x (Const64 <t> [c+d])) + for { + t := v.Type + if v.Args[0].Op != OpLsh32x64 { + break + } + x := v.Args[0].Args[0] + if v.Args[0].Args[1].Op != OpConst64 { + break + } + c := v.Args[0].Args[1].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + if !(!uaddOvf(c, d)) { + break + } + v.reset(OpLsh32x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = c + d + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpLsh32x8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh32x8 <t> x (Const8 [c])) + // cond: + // result: (Lsh32x64 x (Const64 <t> [int64(uint8(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst8 { + break + } + c := v.Args[1].AuxInt + v.reset(OpLsh32x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint8(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpLsh64x16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh64x16 <t> x (Const16 [c])) + // cond: + // result: (Lsh64x64 x (Const64 <t> [int64(uint16(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst16 { + break + } + c := v.Args[1].AuxInt + v.reset(OpLsh64x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint16(c)) + v.AddArg(v0) + return true + } + // match: (Lsh64x16 (Const64 [0]) _) + // cond: + // result: (Const64 [0]) + for { + if v.Args[0].Op != OpConst64 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst64) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValuegeneric_OpLsh64x32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh64x32 <t> x (Const32 [c])) + // cond: + // result: (Lsh64x64 x (Const64 <t> [int64(uint32(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst32 { + break + } + c := v.Args[1].AuxInt + v.reset(OpLsh64x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint32(c)) + v.AddArg(v0) + return true + } + // match: (Lsh64x32 (Const64 [0]) _) + // cond: + // result: (Const64 [0]) + for { + if v.Args[0].Op != OpConst64 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst64) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValuegeneric_OpLsh64x64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh64x64 (Const64 [c]) (Const64 [d])) + // cond: + // result: (Const64 [c << uint64(d)]) + for { + if v.Args[0].Op != OpConst64 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConst64) + v.AuxInt = c << uint64(d) + return true + } + // match: (Lsh64x64 (Const64 [0]) _) + // cond: + // result: (Const64 [0]) + for { + if v.Args[0].Op != OpConst64 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst64) + v.AuxInt = 0 + return true + } + // match: (Lsh64x64 x (Const64 [0])) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + if v.Args[1].AuxInt != 0 { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (Lsh64x64 (Const64 [0]) _) + // cond: + // result: (Const64 [0]) + for { + if v.Args[0].Op != OpConst64 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst64) + v.AuxInt = 0 + return true + } + // match: (Lsh64x64 _ (Const64 [c])) + // cond: uint64(c) >= 64 + // result: (Const64 [0]) + for { + if v.Args[1].Op != OpConst64 { + break + } + c := v.Args[1].AuxInt + if !(uint64(c) >= 64) { + break + } + v.reset(OpConst64) + v.AuxInt = 0 + return true + } + // match: (Lsh64x64 <t> (Lsh64x64 x (Const64 [c])) (Const64 [d])) + // cond: !uaddOvf(c,d) + // result: (Lsh64x64 x (Const64 <t> [c+d])) + for { + t := v.Type + if v.Args[0].Op != OpLsh64x64 { + break + } + x := v.Args[0].Args[0] + if v.Args[0].Args[1].Op != OpConst64 { + break + } + c := v.Args[0].Args[1].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + if !(!uaddOvf(c, d)) { + break + } + v.reset(OpLsh64x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = c + d + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpLsh64x8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh64x8 <t> x (Const8 [c])) + // cond: + // result: (Lsh64x64 x (Const64 <t> [int64(uint8(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst8 { + break + } + c := v.Args[1].AuxInt + v.reset(OpLsh64x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint8(c)) + v.AddArg(v0) + return true + } + // match: (Lsh64x8 (Const64 [0]) _) + // cond: + // result: (Const64 [0]) + for { + if v.Args[0].Op != OpConst64 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst64) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValuegeneric_OpLsh8x16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh8x16 <t> x (Const16 [c])) + // cond: + // result: (Lsh8x64 x (Const64 <t> [int64(uint16(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst16 { + break + } + c := v.Args[1].AuxInt + v.reset(OpLsh8x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint16(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpLsh8x32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh8x32 <t> x (Const32 [c])) + // cond: + // result: (Lsh8x64 x (Const64 <t> [int64(uint32(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst32 { + break + } + c := v.Args[1].AuxInt + v.reset(OpLsh8x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint32(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpLsh8x64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh8x64 (Const8 [c]) (Const64 [d])) + // cond: + // result: (Const8 [int64(int8(c) << uint64(d))]) + for { + if v.Args[0].Op != OpConst8 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConst8) + v.AuxInt = int64(int8(c) << uint64(d)) + return true + } + // match: (Lsh8x64 (Const8 [0]) _) + // cond: + // result: (Const8 [0]) + for { + if v.Args[0].Op != OpConst8 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst8) + v.AuxInt = 0 + return true + } + // match: (Lsh8x64 x (Const64 [0])) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + if v.Args[1].AuxInt != 0 { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (Lsh8x64 _ (Const64 [c])) + // cond: uint64(c) >= 8 + // result: (Const8 [0]) + for { + if v.Args[1].Op != OpConst64 { + break + } + c := v.Args[1].AuxInt + if !(uint64(c) >= 8) { + break + } + v.reset(OpConst8) + v.AuxInt = 0 + return true + } + // match: (Lsh8x64 <t> (Lsh8x64 x (Const64 [c])) (Const64 [d])) + // cond: !uaddOvf(c,d) + // result: (Lsh8x64 x (Const64 <t> [c+d])) + for { + t := v.Type + if v.Args[0].Op != OpLsh8x64 { + break + } + x := v.Args[0].Args[0] + if v.Args[0].Args[1].Op != OpConst64 { + break + } + c := v.Args[0].Args[1].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + if !(!uaddOvf(c, d)) { + break + } + v.reset(OpLsh8x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = c + d + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpLsh8x8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh8x8 <t> x (Const8 [c])) + // cond: + // result: (Lsh8x64 x (Const64 <t> [int64(uint8(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst8 { + break + } + c := v.Args[1].AuxInt + v.reset(OpLsh8x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint8(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpMod64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mod64 <t> x (Const64 [c])) + // cond: smagic64ok(c) + // result: (Sub64 x (Mul64 <t> (Div64 <t> x (Const64 <t> [c])) (Const64 <t> [c]))) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + c := v.Args[1].AuxInt + if !(smagic64ok(c)) { + break + } + v.reset(OpSub64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpMul64, t) + v1 := b.NewValue0(v.Line, OpDiv64, t) + v1.AddArg(x) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = c + v1.AddArg(v2) + v0.AddArg(v1) + v3 := b.NewValue0(v.Line, OpConst64, t) + v3.AuxInt = c + v0.AddArg(v3) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpMod64u(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mod64u <t> x (Const64 [c])) + // cond: umagic64ok(c) + // result: (Sub64 x (Mul64 <t> (Div64u <t> x (Const64 <t> [c])) (Const64 <t> [c]))) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + c := v.Args[1].AuxInt + if !(umagic64ok(c)) { + break + } + v.reset(OpSub64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpMul64, t) + v1 := b.NewValue0(v.Line, OpDiv64u, t) + v1.AddArg(x) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = c + v1.AddArg(v2) + v0.AddArg(v1) + v3 := b.NewValue0(v.Line, OpConst64, t) + v3.AuxInt = c + v0.AddArg(v3) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpMul16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mul16 (Const16 [c]) (Const16 [d])) + // cond: + // result: (Const16 [c*d]) + for { + if v.Args[0].Op != OpConst16 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst16 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConst16) + v.AuxInt = c * d + return true + } + // match: (Mul16 x (Const16 <t> [c])) + // cond: x.Op != OpConst16 + // result: (Mul16 (Const16 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst16 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst16) { + break + } + v.reset(OpMul16) + v0 := b.NewValue0(v.Line, OpConst16, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Mul16 (Const16 [0]) _) + // cond: + // result: (Const16 [0]) + for { + if v.Args[0].Op != OpConst16 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst16) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValuegeneric_OpMul32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mul32 (Const32 [c]) (Const32 [d])) + // cond: + // result: (Const32 [c*d]) + for { + if v.Args[0].Op != OpConst32 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst32 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConst32) + v.AuxInt = c * d + return true + } + // match: (Mul32 x (Const32 <t> [c])) + // cond: x.Op != OpConst32 + // result: (Mul32 (Const32 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst32 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst32) { + break + } + v.reset(OpMul32) + v0 := b.NewValue0(v.Line, OpConst32, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Mul32 (Const32 <t> [c]) (Add32 <t> (Const32 <t> [d]) x)) + // cond: + // result: (Add32 (Const32 <t> [c*d]) (Mul32 <t> (Const32 <t> [c]) x)) + for { + if v.Args[0].Op != OpConst32 { + break + } + t := v.Args[0].Type + c := v.Args[0].AuxInt + if v.Args[1].Op != OpAdd32 { + break + } + if v.Args[1].Type != v.Args[0].Type { + break + } + if v.Args[1].Args[0].Op != OpConst32 { + break + } + if v.Args[1].Args[0].Type != v.Args[0].Type { + break + } + d := v.Args[1].Args[0].AuxInt + x := v.Args[1].Args[1] + v.reset(OpAdd32) + v0 := b.NewValue0(v.Line, OpConst32, t) + v0.AuxInt = c * d + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpMul32, t) + v2 := b.NewValue0(v.Line, OpConst32, t) + v2.AuxInt = c + v1.AddArg(v2) + v1.AddArg(x) + v.AddArg(v1) + return true + } + // match: (Mul32 (Const32 [0]) _) + // cond: + // result: (Const32 [0]) + for { + if v.Args[0].Op != OpConst32 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst32) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValuegeneric_OpMul64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mul64 (Const64 [c]) (Const64 [d])) + // cond: + // result: (Const64 [c*d]) + for { + if v.Args[0].Op != OpConst64 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConst64) + v.AuxInt = c * d + return true + } + // match: (Mul64 x (Const64 <t> [c])) + // cond: x.Op != OpConst64 + // result: (Mul64 (Const64 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst64) { + break + } + v.reset(OpMul64) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Mul64 (Const64 <t> [c]) (Add64 <t> (Const64 <t> [d]) x)) + // cond: + // result: (Add64 (Const64 <t> [c*d]) (Mul64 <t> (Const64 <t> [c]) x)) + for { + if v.Args[0].Op != OpConst64 { + break + } + t := v.Args[0].Type + c := v.Args[0].AuxInt + if v.Args[1].Op != OpAdd64 { + break + } + if v.Args[1].Type != v.Args[0].Type { + break + } + if v.Args[1].Args[0].Op != OpConst64 { + break + } + if v.Args[1].Args[0].Type != v.Args[0].Type { + break + } + d := v.Args[1].Args[0].AuxInt + x := v.Args[1].Args[1] + v.reset(OpAdd64) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = c * d + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpMul64, t) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = c + v1.AddArg(v2) + v1.AddArg(x) + v.AddArg(v1) + return true + } + // match: (Mul64 (Const64 [0]) _) + // cond: + // result: (Const64 [0]) + for { + if v.Args[0].Op != OpConst64 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst64) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValuegeneric_OpMul8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mul8 (Const8 [c]) (Const8 [d])) + // cond: + // result: (Const8 [c*d]) + for { + if v.Args[0].Op != OpConst8 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst8 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConst8) + v.AuxInt = c * d + return true + } + // match: (Mul8 x (Const8 <t> [c])) + // cond: x.Op != OpConst8 + // result: (Mul8 (Const8 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst8 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst8) { + break + } + v.reset(OpMul8) + v0 := b.NewValue0(v.Line, OpConst8, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Mul8 (Const8 [0]) _) + // cond: + // result: (Const8 [0]) + for { + if v.Args[0].Op != OpConst8 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst8) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValuegeneric_OpNeg16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neg16 (Const16 [c])) + // cond: + // result: (Const16 [-c]) + for { + if v.Args[0].Op != OpConst16 { + break + } + c := v.Args[0].AuxInt + v.reset(OpConst16) + v.AuxInt = -c + return true + } + // match: (Neg16 (Sub16 x y)) + // cond: + // result: (Sub16 y x) + for { + if v.Args[0].Op != OpSub16 { + break + } + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + v.reset(OpSub16) + v.AddArg(y) + v.AddArg(x) + return true + } + return false +} +func rewriteValuegeneric_OpNeg32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neg32 (Const32 [c])) + // cond: + // result: (Const32 [-c]) + for { + if v.Args[0].Op != OpConst32 { + break + } + c := v.Args[0].AuxInt + v.reset(OpConst32) + v.AuxInt = -c + return true + } + // match: (Neg32 (Sub32 x y)) + // cond: + // result: (Sub32 y x) + for { + if v.Args[0].Op != OpSub32 { + break + } + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + v.reset(OpSub32) + v.AddArg(y) + v.AddArg(x) + return true + } + return false +} +func rewriteValuegeneric_OpNeg64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neg64 (Const64 [c])) + // cond: + // result: (Const64 [-c]) + for { + if v.Args[0].Op != OpConst64 { + break + } + c := v.Args[0].AuxInt + v.reset(OpConst64) + v.AuxInt = -c + return true + } + // match: (Neg64 (Sub64 x y)) + // cond: + // result: (Sub64 y x) + for { + if v.Args[0].Op != OpSub64 { + break + } + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + v.reset(OpSub64) + v.AddArg(y) + v.AddArg(x) + return true + } + return false +} +func rewriteValuegeneric_OpNeg8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neg8 (Const8 [c])) + // cond: + // result: (Const8 [-c]) + for { + if v.Args[0].Op != OpConst8 { + break + } + c := v.Args[0].AuxInt + v.reset(OpConst8) + v.AuxInt = -c + return true + } + // match: (Neg8 (Sub8 x y)) + // cond: + // result: (Sub8 y x) + for { + if v.Args[0].Op != OpSub8 { + break + } + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + v.reset(OpSub8) + v.AddArg(y) + v.AddArg(x) + return true + } + return false +} +func rewriteValuegeneric_OpNeq16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neq16 x x) + // cond: + // result: (ConstBool [0]) + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpConstBool) + v.AuxInt = 0 + return true + } + // match: (Neq16 (Const16 <t> [c]) (Add16 (Const16 <t> [d]) x)) + // cond: + // result: (Neq16 (Const16 <t> [c-d]) x) + for { + if v.Args[0].Op != OpConst16 { + break + } + t := v.Args[0].Type + c := v.Args[0].AuxInt + if v.Args[1].Op != OpAdd16 { + break + } + if v.Args[1].Args[0].Op != OpConst16 { + break + } + if v.Args[1].Args[0].Type != v.Args[0].Type { + break + } + d := v.Args[1].Args[0].AuxInt + x := v.Args[1].Args[1] + v.reset(OpNeq16) + v0 := b.NewValue0(v.Line, OpConst16, t) + v0.AuxInt = c - d + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Neq16 x (Const16 <t> [c])) + // cond: x.Op != OpConst16 + // result: (Neq16 (Const16 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst16 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst16) { + break + } + v.reset(OpNeq16) + v0 := b.NewValue0(v.Line, OpConst16, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Neq16 (Const16 [c]) (Const16 [d])) + // cond: + // result: (ConstBool [b2i(int16(c) != int16(d))]) + for { + if v.Args[0].Op != OpConst16 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst16 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(int16(c) != int16(d)) + return true + } + return false +} +func rewriteValuegeneric_OpNeq32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neq32 x x) + // cond: + // result: (ConstBool [0]) + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpConstBool) + v.AuxInt = 0 + return true + } + // match: (Neq32 (Const32 <t> [c]) (Add32 (Const32 <t> [d]) x)) + // cond: + // result: (Neq32 (Const32 <t> [c-d]) x) + for { + if v.Args[0].Op != OpConst32 { + break + } + t := v.Args[0].Type + c := v.Args[0].AuxInt + if v.Args[1].Op != OpAdd32 { + break + } + if v.Args[1].Args[0].Op != OpConst32 { + break + } + if v.Args[1].Args[0].Type != v.Args[0].Type { + break + } + d := v.Args[1].Args[0].AuxInt + x := v.Args[1].Args[1] + v.reset(OpNeq32) + v0 := b.NewValue0(v.Line, OpConst32, t) + v0.AuxInt = c - d + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Neq32 x (Const32 <t> [c])) + // cond: x.Op != OpConst32 + // result: (Neq32 (Const32 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst32 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst32) { + break + } + v.reset(OpNeq32) + v0 := b.NewValue0(v.Line, OpConst32, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Neq32 (Const32 [c]) (Const32 [d])) + // cond: + // result: (ConstBool [b2i(int32(c) != int32(d))]) + for { + if v.Args[0].Op != OpConst32 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst32 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(int32(c) != int32(d)) + return true + } + return false +} +func rewriteValuegeneric_OpNeq64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neq64 x x) + // cond: + // result: (ConstBool [0]) + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpConstBool) + v.AuxInt = 0 + return true + } + // match: (Neq64 (Const64 <t> [c]) (Add64 (Const64 <t> [d]) x)) + // cond: + // result: (Neq64 (Const64 <t> [c-d]) x) + for { + if v.Args[0].Op != OpConst64 { + break + } + t := v.Args[0].Type + c := v.Args[0].AuxInt + if v.Args[1].Op != OpAdd64 { + break + } + if v.Args[1].Args[0].Op != OpConst64 { + break + } + if v.Args[1].Args[0].Type != v.Args[0].Type { + break + } + d := v.Args[1].Args[0].AuxInt + x := v.Args[1].Args[1] + v.reset(OpNeq64) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = c - d + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Neq64 x (Const64 <t> [c])) + // cond: x.Op != OpConst64 + // result: (Neq64 (Const64 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst64) { + break + } + v.reset(OpNeq64) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Neq64 (Const64 [c]) (Const64 [d])) + // cond: + // result: (ConstBool [b2i(int64(c) != int64(d))]) + for { + if v.Args[0].Op != OpConst64 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(int64(c) != int64(d)) + return true + } + return false +} +func rewriteValuegeneric_OpNeq8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neq8 x x) + // cond: + // result: (ConstBool [0]) + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpConstBool) + v.AuxInt = 0 + return true + } + // match: (Neq8 (ConstBool [c]) (ConstBool [d])) + // cond: + // result: (ConstBool [b2i((int8(c) != 0) != (int8(d) != 0))]) + for { + if v.Args[0].Op != OpConstBool { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConstBool { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i((int8(c) != 0) != (int8(d) != 0)) + return true + } + // match: (Neq8 (ConstBool [0]) x) + // cond: + // result: x + for { + if v.Args[0].Op != OpConstBool { + break + } + if v.Args[0].AuxInt != 0 { + break + } + x := v.Args[1] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (Neq8 (ConstBool [1]) x) + // cond: + // result: (Not x) + for { + if v.Args[0].Op != OpConstBool { + break + } + if v.Args[0].AuxInt != 1 { + break + } + x := v.Args[1] + v.reset(OpNot) + v.AddArg(x) + return true + } + // match: (Neq8 (Const8 <t> [c]) (Add8 (Const8 <t> [d]) x)) + // cond: + // result: (Neq8 (Const8 <t> [c-d]) x) + for { + if v.Args[0].Op != OpConst8 { + break + } + t := v.Args[0].Type + c := v.Args[0].AuxInt + if v.Args[1].Op != OpAdd8 { + break + } + if v.Args[1].Args[0].Op != OpConst8 { + break + } + if v.Args[1].Args[0].Type != v.Args[0].Type { + break + } + d := v.Args[1].Args[0].AuxInt + x := v.Args[1].Args[1] + v.reset(OpNeq8) + v0 := b.NewValue0(v.Line, OpConst8, t) + v0.AuxInt = c - d + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Neq8 x (Const8 <t> [c])) + // cond: x.Op != OpConst8 + // result: (Neq8 (Const8 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst8 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst8) { + break + } + v.reset(OpNeq8) + v0 := b.NewValue0(v.Line, OpConst8, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Neq8 x (ConstBool <t> [c])) + // cond: x.Op != OpConstBool + // result: (Neq8 (ConstBool <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConstBool { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConstBool) { + break + } + v.reset(OpNeq8) + v0 := b.NewValue0(v.Line, OpConstBool, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Neq8 (Const8 [c]) (Const8 [d])) + // cond: + // result: (ConstBool [b2i(int8(c) != int8(d))]) + for { + if v.Args[0].Op != OpConst8 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst8 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConstBool) + v.AuxInt = b2i(int8(c) != int8(d)) + return true + } + return false +} +func rewriteValuegeneric_OpNeqInter(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (NeqInter x y) + // cond: + // result: (NeqPtr (ITab x) (ITab y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpNeqPtr) + v0 := b.NewValue0(v.Line, OpITab, config.fe.TypeBytePtr()) + v0.AddArg(x) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpITab, config.fe.TypeBytePtr()) + v1.AddArg(y) + v.AddArg(v1) + return true + } + return false +} +func rewriteValuegeneric_OpNeqPtr(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (NeqPtr p (ConstNil)) + // cond: + // result: (IsNonNil p) + for { + p := v.Args[0] + if v.Args[1].Op != OpConstNil { + break + } + v.reset(OpIsNonNil) + v.AddArg(p) + return true + } + // match: (NeqPtr (ConstNil) p) + // cond: + // result: (IsNonNil p) + for { + if v.Args[0].Op != OpConstNil { + break + } + p := v.Args[1] + v.reset(OpIsNonNil) + v.AddArg(p) + return true + } + return false +} +func rewriteValuegeneric_OpNeqSlice(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (NeqSlice x y) + // cond: + // result: (NeqPtr (SlicePtr x) (SlicePtr y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpNeqPtr) + v0 := b.NewValue0(v.Line, OpSlicePtr, config.fe.TypeBytePtr()) + v0.AddArg(x) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpSlicePtr, config.fe.TypeBytePtr()) + v1.AddArg(y) + v.AddArg(v1) + return true + } + return false +} +func rewriteValuegeneric_OpOr16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Or16 x (Const16 <t> [c])) + // cond: x.Op != OpConst16 + // result: (Or16 (Const16 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst16 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst16) { + break + } + v.reset(OpOr16) + v0 := b.NewValue0(v.Line, OpConst16, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Or16 x x) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (Or16 (Const16 [0]) x) + // cond: + // result: x + for { + if v.Args[0].Op != OpConst16 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + x := v.Args[1] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (Or16 (Const16 [-1]) _) + // cond: + // result: (Const16 [-1]) + for { + if v.Args[0].Op != OpConst16 { + break + } + if v.Args[0].AuxInt != -1 { + break + } + v.reset(OpConst16) + v.AuxInt = -1 + return true + } + return false +} +func rewriteValuegeneric_OpOr32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Or32 x (Const32 <t> [c])) + // cond: x.Op != OpConst32 + // result: (Or32 (Const32 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst32 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst32) { + break + } + v.reset(OpOr32) + v0 := b.NewValue0(v.Line, OpConst32, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Or32 x x) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (Or32 (Const32 [0]) x) + // cond: + // result: x + for { + if v.Args[0].Op != OpConst32 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + x := v.Args[1] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (Or32 (Const32 [-1]) _) + // cond: + // result: (Const32 [-1]) + for { + if v.Args[0].Op != OpConst32 { + break + } + if v.Args[0].AuxInt != -1 { + break + } + v.reset(OpConst32) + v.AuxInt = -1 + return true + } + return false +} +func rewriteValuegeneric_OpOr64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Or64 x (Const64 <t> [c])) + // cond: x.Op != OpConst64 + // result: (Or64 (Const64 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst64) { + break + } + v.reset(OpOr64) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Or64 x x) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (Or64 (Const64 [0]) x) + // cond: + // result: x + for { + if v.Args[0].Op != OpConst64 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + x := v.Args[1] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (Or64 (Const64 [-1]) _) + // cond: + // result: (Const64 [-1]) + for { + if v.Args[0].Op != OpConst64 { + break + } + if v.Args[0].AuxInt != -1 { + break + } + v.reset(OpConst64) + v.AuxInt = -1 + return true + } + return false +} +func rewriteValuegeneric_OpOr8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Or8 x (Const8 <t> [c])) + // cond: x.Op != OpConst8 + // result: (Or8 (Const8 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst8 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst8) { + break + } + v.reset(OpOr8) + v0 := b.NewValue0(v.Line, OpConst8, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Or8 x x) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (Or8 (Const8 [0]) x) + // cond: + // result: x + for { + if v.Args[0].Op != OpConst8 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + x := v.Args[1] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (Or8 (Const8 [-1]) _) + // cond: + // result: (Const8 [-1]) + for { + if v.Args[0].Op != OpConst8 { + break + } + if v.Args[0].AuxInt != -1 { + break + } + v.reset(OpConst8) + v.AuxInt = -1 + return true + } + return false +} +func rewriteValuegeneric_OpPhi(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Phi (Const8 [c]) (Const8 [d])) + // cond: int8(c) == int8(d) + // result: (Const8 [c]) + for { + if v.Args[0].Op != OpConst8 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst8 { + break + } + d := v.Args[1].AuxInt + if len(v.Args) != 2 { + break + } + if !(int8(c) == int8(d)) { + break + } + v.reset(OpConst8) + v.AuxInt = c + return true + } + // match: (Phi (Const16 [c]) (Const16 [d])) + // cond: int16(c) == int16(d) + // result: (Const16 [c]) + for { + if v.Args[0].Op != OpConst16 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst16 { + break + } + d := v.Args[1].AuxInt + if len(v.Args) != 2 { + break + } + if !(int16(c) == int16(d)) { + break + } + v.reset(OpConst16) + v.AuxInt = c + return true + } + // match: (Phi (Const32 [c]) (Const32 [d])) + // cond: int32(c) == int32(d) + // result: (Const32 [c]) + for { + if v.Args[0].Op != OpConst32 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst32 { + break + } + d := v.Args[1].AuxInt + if len(v.Args) != 2 { + break + } + if !(int32(c) == int32(d)) { + break + } + v.reset(OpConst32) + v.AuxInt = c + return true + } + // match: (Phi (Const64 [c]) (Const64 [c])) + // cond: + // result: (Const64 [c]) + for { + if v.Args[0].Op != OpConst64 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + if v.Args[1].AuxInt != v.Args[0].AuxInt { + break + } + if len(v.Args) != 2 { + break + } + v.reset(OpConst64) + v.AuxInt = c + return true + } + return false +} +func rewriteValuegeneric_OpPtrIndex(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (PtrIndex <t> ptr idx) + // cond: config.PtrSize == 4 + // result: (AddPtr ptr (Mul32 <config.fe.TypeInt()> idx (Const32 <config.fe.TypeInt()> [t.Elem().Size()]))) + for { + t := v.Type + ptr := v.Args[0] + idx := v.Args[1] + if !(config.PtrSize == 4) { + break + } + v.reset(OpAddPtr) + v.AddArg(ptr) + v0 := b.NewValue0(v.Line, OpMul32, config.fe.TypeInt()) + v0.AddArg(idx) + v1 := b.NewValue0(v.Line, OpConst32, config.fe.TypeInt()) + v1.AuxInt = t.Elem().Size() + v0.AddArg(v1) + v.AddArg(v0) + return true + } + // match: (PtrIndex <t> ptr idx) + // cond: config.PtrSize == 8 + // result: (AddPtr ptr (Mul64 <config.fe.TypeInt()> idx (Const64 <config.fe.TypeInt()> [t.Elem().Size()]))) + for { + t := v.Type + ptr := v.Args[0] + idx := v.Args[1] + if !(config.PtrSize == 8) { + break + } + v.reset(OpAddPtr) + v.AddArg(ptr) + v0 := b.NewValue0(v.Line, OpMul64, config.fe.TypeInt()) + v0.AddArg(idx) + v1 := b.NewValue0(v.Line, OpConst64, config.fe.TypeInt()) + v1.AuxInt = t.Elem().Size() + v0.AddArg(v1) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh16Ux16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh16Ux16 <t> x (Const16 [c])) + // cond: + // result: (Rsh16Ux64 x (Const64 <t> [int64(uint16(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst16 { + break + } + c := v.Args[1].AuxInt + v.reset(OpRsh16Ux64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint16(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh16Ux32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh16Ux32 <t> x (Const32 [c])) + // cond: + // result: (Rsh16Ux64 x (Const64 <t> [int64(uint32(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst32 { + break + } + c := v.Args[1].AuxInt + v.reset(OpRsh16Ux64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint32(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh16Ux64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh16Ux64 (Const16 [c]) (Const64 [d])) + // cond: + // result: (Const16 [int64(uint16(c) >> uint64(d))]) + for { + if v.Args[0].Op != OpConst16 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConst16) + v.AuxInt = int64(uint16(c) >> uint64(d)) + return true + } + // match: (Rsh16Ux64 (Const16 [0]) _) + // cond: + // result: (Const16 [0]) + for { + if v.Args[0].Op != OpConst16 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst16) + v.AuxInt = 0 + return true + } + // match: (Rsh16Ux64 x (Const64 [0])) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + if v.Args[1].AuxInt != 0 { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (Rsh16Ux64 _ (Const64 [c])) + // cond: uint64(c) >= 16 + // result: (Const16 [0]) + for { + if v.Args[1].Op != OpConst64 { + break + } + c := v.Args[1].AuxInt + if !(uint64(c) >= 16) { + break + } + v.reset(OpConst16) + v.AuxInt = 0 + return true + } + // match: (Rsh16Ux64 <t> (Rsh16Ux64 x (Const64 [c])) (Const64 [d])) + // cond: !uaddOvf(c,d) + // result: (Rsh16Ux64 x (Const64 <t> [c+d])) + for { + t := v.Type + if v.Args[0].Op != OpRsh16Ux64 { + break + } + x := v.Args[0].Args[0] + if v.Args[0].Args[1].Op != OpConst64 { + break + } + c := v.Args[0].Args[1].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + if !(!uaddOvf(c, d)) { + break + } + v.reset(OpRsh16Ux64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = c + d + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh16Ux8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh16Ux8 <t> x (Const8 [c])) + // cond: + // result: (Rsh16Ux64 x (Const64 <t> [int64(uint8(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst8 { + break + } + c := v.Args[1].AuxInt + v.reset(OpRsh16Ux64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint8(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh16x16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh16x16 <t> x (Const16 [c])) + // cond: + // result: (Rsh16x64 x (Const64 <t> [int64(uint16(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst16 { + break + } + c := v.Args[1].AuxInt + v.reset(OpRsh16x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint16(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh16x32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh16x32 <t> x (Const32 [c])) + // cond: + // result: (Rsh16x64 x (Const64 <t> [int64(uint32(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst32 { + break + } + c := v.Args[1].AuxInt + v.reset(OpRsh16x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint32(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh16x64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh16x64 (Const16 [c]) (Const64 [d])) + // cond: + // result: (Const16 [int64(int16(c) >> uint64(d))]) + for { + if v.Args[0].Op != OpConst16 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConst16) + v.AuxInt = int64(int16(c) >> uint64(d)) + return true + } + // match: (Rsh16x64 (Const16 [0]) _) + // cond: + // result: (Const16 [0]) + for { + if v.Args[0].Op != OpConst16 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst16) + v.AuxInt = 0 + return true + } + // match: (Rsh16x64 x (Const64 [0])) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + if v.Args[1].AuxInt != 0 { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (Rsh16x64 <t> (Rsh16x64 x (Const64 [c])) (Const64 [d])) + // cond: !uaddOvf(c,d) + // result: (Rsh16x64 x (Const64 <t> [c+d])) + for { + t := v.Type + if v.Args[0].Op != OpRsh16x64 { + break + } + x := v.Args[0].Args[0] + if v.Args[0].Args[1].Op != OpConst64 { + break + } + c := v.Args[0].Args[1].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + if !(!uaddOvf(c, d)) { + break + } + v.reset(OpRsh16x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = c + d + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh16x8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh16x8 <t> x (Const8 [c])) + // cond: + // result: (Rsh16x64 x (Const64 <t> [int64(uint8(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst8 { + break + } + c := v.Args[1].AuxInt + v.reset(OpRsh16x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint8(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh32Ux16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh32Ux16 <t> x (Const16 [c])) + // cond: + // result: (Rsh32Ux64 x (Const64 <t> [int64(uint16(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst16 { + break + } + c := v.Args[1].AuxInt + v.reset(OpRsh32Ux64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint16(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh32Ux32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh32Ux32 <t> x (Const32 [c])) + // cond: + // result: (Rsh32Ux64 x (Const64 <t> [int64(uint32(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst32 { + break + } + c := v.Args[1].AuxInt + v.reset(OpRsh32Ux64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint32(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh32Ux64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh32Ux64 (Const32 [c]) (Const64 [d])) + // cond: + // result: (Const32 [int64(uint32(c) >> uint64(d))]) + for { + if v.Args[0].Op != OpConst32 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConst32) + v.AuxInt = int64(uint32(c) >> uint64(d)) + return true + } + // match: (Rsh32Ux64 (Const32 [0]) _) + // cond: + // result: (Const32 [0]) + for { + if v.Args[0].Op != OpConst32 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst32) + v.AuxInt = 0 + return true + } + // match: (Rsh32Ux64 x (Const64 [0])) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + if v.Args[1].AuxInt != 0 { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (Rsh32Ux64 _ (Const64 [c])) + // cond: uint64(c) >= 32 + // result: (Const32 [0]) + for { + if v.Args[1].Op != OpConst64 { + break + } + c := v.Args[1].AuxInt + if !(uint64(c) >= 32) { + break + } + v.reset(OpConst32) + v.AuxInt = 0 + return true + } + // match: (Rsh32Ux64 <t> (Rsh32Ux64 x (Const64 [c])) (Const64 [d])) + // cond: !uaddOvf(c,d) + // result: (Rsh32Ux64 x (Const64 <t> [c+d])) + for { + t := v.Type + if v.Args[0].Op != OpRsh32Ux64 { + break + } + x := v.Args[0].Args[0] + if v.Args[0].Args[1].Op != OpConst64 { + break + } + c := v.Args[0].Args[1].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + if !(!uaddOvf(c, d)) { + break + } + v.reset(OpRsh32Ux64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = c + d + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh32Ux8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh32Ux8 <t> x (Const8 [c])) + // cond: + // result: (Rsh32Ux64 x (Const64 <t> [int64(uint8(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst8 { + break + } + c := v.Args[1].AuxInt + v.reset(OpRsh32Ux64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint8(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh32x16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh32x16 <t> x (Const16 [c])) + // cond: + // result: (Rsh32x64 x (Const64 <t> [int64(uint16(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst16 { + break + } + c := v.Args[1].AuxInt + v.reset(OpRsh32x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint16(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh32x32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh32x32 <t> x (Const32 [c])) + // cond: + // result: (Rsh32x64 x (Const64 <t> [int64(uint32(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst32 { + break + } + c := v.Args[1].AuxInt + v.reset(OpRsh32x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint32(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh32x64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh32x64 (Const32 [c]) (Const64 [d])) + // cond: + // result: (Const32 [int64(int32(c) >> uint64(d))]) + for { + if v.Args[0].Op != OpConst32 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConst32) + v.AuxInt = int64(int32(c) >> uint64(d)) + return true + } + // match: (Rsh32x64 (Const32 [0]) _) + // cond: + // result: (Const32 [0]) + for { + if v.Args[0].Op != OpConst32 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst32) + v.AuxInt = 0 + return true + } + // match: (Rsh32x64 x (Const64 [0])) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + if v.Args[1].AuxInt != 0 { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (Rsh32x64 <t> (Rsh32x64 x (Const64 [c])) (Const64 [d])) + // cond: !uaddOvf(c,d) + // result: (Rsh32x64 x (Const64 <t> [c+d])) + for { + t := v.Type + if v.Args[0].Op != OpRsh32x64 { + break + } + x := v.Args[0].Args[0] + if v.Args[0].Args[1].Op != OpConst64 { + break + } + c := v.Args[0].Args[1].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + if !(!uaddOvf(c, d)) { + break + } + v.reset(OpRsh32x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = c + d + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh32x8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh32x8 <t> x (Const8 [c])) + // cond: + // result: (Rsh32x64 x (Const64 <t> [int64(uint8(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst8 { + break + } + c := v.Args[1].AuxInt + v.reset(OpRsh32x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint8(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh64Ux16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh64Ux16 <t> x (Const16 [c])) + // cond: + // result: (Rsh64Ux64 x (Const64 <t> [int64(uint16(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst16 { + break + } + c := v.Args[1].AuxInt + v.reset(OpRsh64Ux64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint16(c)) + v.AddArg(v0) + return true + } + // match: (Rsh64Ux16 (Const64 [0]) _) + // cond: + // result: (Const64 [0]) + for { + if v.Args[0].Op != OpConst64 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst64) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValuegeneric_OpRsh64Ux32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh64Ux32 <t> x (Const32 [c])) + // cond: + // result: (Rsh64Ux64 x (Const64 <t> [int64(uint32(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst32 { + break + } + c := v.Args[1].AuxInt + v.reset(OpRsh64Ux64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint32(c)) + v.AddArg(v0) + return true + } + // match: (Rsh64Ux32 (Const64 [0]) _) + // cond: + // result: (Const64 [0]) + for { + if v.Args[0].Op != OpConst64 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst64) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValuegeneric_OpRsh64Ux64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh64Ux64 (Const64 [c]) (Const64 [d])) + // cond: + // result: (Const64 [int64(uint64(c) >> uint64(d))]) + for { + if v.Args[0].Op != OpConst64 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConst64) + v.AuxInt = int64(uint64(c) >> uint64(d)) + return true + } + // match: (Rsh64Ux64 (Const64 [0]) _) + // cond: + // result: (Const64 [0]) + for { + if v.Args[0].Op != OpConst64 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst64) + v.AuxInt = 0 + return true + } + // match: (Rsh64Ux64 x (Const64 [0])) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + if v.Args[1].AuxInt != 0 { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (Rsh64Ux64 (Const64 [0]) _) + // cond: + // result: (Const64 [0]) + for { + if v.Args[0].Op != OpConst64 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst64) + v.AuxInt = 0 + return true + } + // match: (Rsh64Ux64 _ (Const64 [c])) + // cond: uint64(c) >= 64 + // result: (Const64 [0]) + for { + if v.Args[1].Op != OpConst64 { + break + } + c := v.Args[1].AuxInt + if !(uint64(c) >= 64) { + break + } + v.reset(OpConst64) + v.AuxInt = 0 + return true + } + // match: (Rsh64Ux64 <t> (Rsh64Ux64 x (Const64 [c])) (Const64 [d])) + // cond: !uaddOvf(c,d) + // result: (Rsh64Ux64 x (Const64 <t> [c+d])) + for { + t := v.Type + if v.Args[0].Op != OpRsh64Ux64 { + break + } + x := v.Args[0].Args[0] + if v.Args[0].Args[1].Op != OpConst64 { + break + } + c := v.Args[0].Args[1].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + if !(!uaddOvf(c, d)) { + break + } + v.reset(OpRsh64Ux64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = c + d + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh64Ux8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh64Ux8 <t> x (Const8 [c])) + // cond: + // result: (Rsh64Ux64 x (Const64 <t> [int64(uint8(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst8 { + break + } + c := v.Args[1].AuxInt + v.reset(OpRsh64Ux64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint8(c)) + v.AddArg(v0) + return true + } + // match: (Rsh64Ux8 (Const64 [0]) _) + // cond: + // result: (Const64 [0]) + for { + if v.Args[0].Op != OpConst64 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst64) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValuegeneric_OpRsh64x16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh64x16 <t> x (Const16 [c])) + // cond: + // result: (Rsh64x64 x (Const64 <t> [int64(uint16(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst16 { + break + } + c := v.Args[1].AuxInt + v.reset(OpRsh64x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint16(c)) + v.AddArg(v0) + return true + } + // match: (Rsh64x16 (Const64 [0]) _) + // cond: + // result: (Const64 [0]) + for { + if v.Args[0].Op != OpConst64 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst64) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValuegeneric_OpRsh64x32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh64x32 <t> x (Const32 [c])) + // cond: + // result: (Rsh64x64 x (Const64 <t> [int64(uint32(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst32 { + break + } + c := v.Args[1].AuxInt + v.reset(OpRsh64x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint32(c)) + v.AddArg(v0) + return true + } + // match: (Rsh64x32 (Const64 [0]) _) + // cond: + // result: (Const64 [0]) + for { + if v.Args[0].Op != OpConst64 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst64) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValuegeneric_OpRsh64x64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh64x64 (Const64 [c]) (Const64 [d])) + // cond: + // result: (Const64 [c >> uint64(d)]) + for { + if v.Args[0].Op != OpConst64 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConst64) + v.AuxInt = c >> uint64(d) + return true + } + // match: (Rsh64x64 (Const64 [0]) _) + // cond: + // result: (Const64 [0]) + for { + if v.Args[0].Op != OpConst64 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst64) + v.AuxInt = 0 + return true + } + // match: (Rsh64x64 x (Const64 [0])) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + if v.Args[1].AuxInt != 0 { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (Rsh64x64 (Const64 [0]) _) + // cond: + // result: (Const64 [0]) + for { + if v.Args[0].Op != OpConst64 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst64) + v.AuxInt = 0 + return true + } + // match: (Rsh64x64 <t> (Rsh64x64 x (Const64 [c])) (Const64 [d])) + // cond: !uaddOvf(c,d) + // result: (Rsh64x64 x (Const64 <t> [c+d])) + for { + t := v.Type + if v.Args[0].Op != OpRsh64x64 { + break + } + x := v.Args[0].Args[0] + if v.Args[0].Args[1].Op != OpConst64 { + break + } + c := v.Args[0].Args[1].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + if !(!uaddOvf(c, d)) { + break + } + v.reset(OpRsh64x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = c + d + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh64x8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh64x8 <t> x (Const8 [c])) + // cond: + // result: (Rsh64x64 x (Const64 <t> [int64(uint8(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst8 { + break + } + c := v.Args[1].AuxInt + v.reset(OpRsh64x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint8(c)) + v.AddArg(v0) + return true + } + // match: (Rsh64x8 (Const64 [0]) _) + // cond: + // result: (Const64 [0]) + for { + if v.Args[0].Op != OpConst64 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst64) + v.AuxInt = 0 + return true + } + return false +} +func rewriteValuegeneric_OpRsh8Ux16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh8Ux16 <t> x (Const16 [c])) + // cond: + // result: (Rsh8Ux64 x (Const64 <t> [int64(uint16(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst16 { + break + } + c := v.Args[1].AuxInt + v.reset(OpRsh8Ux64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint16(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh8Ux32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh8Ux32 <t> x (Const32 [c])) + // cond: + // result: (Rsh8Ux64 x (Const64 <t> [int64(uint32(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst32 { + break + } + c := v.Args[1].AuxInt + v.reset(OpRsh8Ux64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint32(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh8Ux64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh8Ux64 (Const8 [c]) (Const64 [d])) + // cond: + // result: (Const8 [int64(uint8(c) >> uint64(d))]) + for { + if v.Args[0].Op != OpConst8 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConst8) + v.AuxInt = int64(uint8(c) >> uint64(d)) + return true + } + // match: (Rsh8Ux64 (Const8 [0]) _) + // cond: + // result: (Const8 [0]) + for { + if v.Args[0].Op != OpConst8 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst8) + v.AuxInt = 0 + return true + } + // match: (Rsh8Ux64 x (Const64 [0])) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + if v.Args[1].AuxInt != 0 { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (Rsh8Ux64 _ (Const64 [c])) + // cond: uint64(c) >= 8 + // result: (Const8 [0]) + for { + if v.Args[1].Op != OpConst64 { + break + } + c := v.Args[1].AuxInt + if !(uint64(c) >= 8) { + break + } + v.reset(OpConst8) + v.AuxInt = 0 + return true + } + // match: (Rsh8Ux64 <t> (Rsh8Ux64 x (Const64 [c])) (Const64 [d])) + // cond: !uaddOvf(c,d) + // result: (Rsh8Ux64 x (Const64 <t> [c+d])) + for { + t := v.Type + if v.Args[0].Op != OpRsh8Ux64 { + break + } + x := v.Args[0].Args[0] + if v.Args[0].Args[1].Op != OpConst64 { + break + } + c := v.Args[0].Args[1].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + if !(!uaddOvf(c, d)) { + break + } + v.reset(OpRsh8Ux64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = c + d + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh8Ux8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh8Ux8 <t> x (Const8 [c])) + // cond: + // result: (Rsh8Ux64 x (Const64 <t> [int64(uint8(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst8 { + break + } + c := v.Args[1].AuxInt + v.reset(OpRsh8Ux64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint8(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh8x16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh8x16 <t> x (Const16 [c])) + // cond: + // result: (Rsh8x64 x (Const64 <t> [int64(uint16(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst16 { + break + } + c := v.Args[1].AuxInt + v.reset(OpRsh8x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint16(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh8x32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh8x32 <t> x (Const32 [c])) + // cond: + // result: (Rsh8x64 x (Const64 <t> [int64(uint32(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst32 { + break + } + c := v.Args[1].AuxInt + v.reset(OpRsh8x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint32(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh8x64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh8x64 (Const8 [c]) (Const64 [d])) + // cond: + // result: (Const8 [int64(int8(c) >> uint64(d))]) + for { + if v.Args[0].Op != OpConst8 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConst8) + v.AuxInt = int64(int8(c) >> uint64(d)) + return true + } + // match: (Rsh8x64 (Const8 [0]) _) + // cond: + // result: (Const8 [0]) + for { + if v.Args[0].Op != OpConst8 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + v.reset(OpConst8) + v.AuxInt = 0 + return true + } + // match: (Rsh8x64 x (Const64 [0])) + // cond: + // result: x + for { + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + if v.Args[1].AuxInt != 0 { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (Rsh8x64 <t> (Rsh8x64 x (Const64 [c])) (Const64 [d])) + // cond: !uaddOvf(c,d) + // result: (Rsh8x64 x (Const64 <t> [c+d])) + for { + t := v.Type + if v.Args[0].Op != OpRsh8x64 { + break + } + x := v.Args[0].Args[0] + if v.Args[0].Args[1].Op != OpConst64 { + break + } + c := v.Args[0].Args[1].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + if !(!uaddOvf(c, d)) { + break + } + v.reset(OpRsh8x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = c + d + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpRsh8x8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Rsh8x8 <t> x (Const8 [c])) + // cond: + // result: (Rsh8x64 x (Const64 <t> [int64(uint8(c))])) + for { + t := v.Type + x := v.Args[0] + if v.Args[1].Op != OpConst8 { + break + } + c := v.Args[1].AuxInt + v.reset(OpRsh8x64) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = int64(uint8(c)) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpSliceCap(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SliceCap (SliceMake _ _ cap)) + // cond: + // result: cap + for { + if v.Args[0].Op != OpSliceMake { + break + } + cap := v.Args[0].Args[2] + v.reset(OpCopy) + v.Type = cap.Type + v.AddArg(cap) + return true + } + return false +} +func rewriteValuegeneric_OpSliceLen(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SliceLen (SliceMake _ len _)) + // cond: + // result: len + for { + if v.Args[0].Op != OpSliceMake { + break + } + len := v.Args[0].Args[1] + v.reset(OpCopy) + v.Type = len.Type + v.AddArg(len) + return true + } + return false +} +func rewriteValuegeneric_OpSlicePtr(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (SlicePtr (SliceMake ptr _ _ )) + // cond: + // result: ptr + for { + if v.Args[0].Op != OpSliceMake { + break + } + ptr := v.Args[0].Args[0] + v.reset(OpCopy) + v.Type = ptr.Type + v.AddArg(ptr) + return true + } + return false +} +func rewriteValuegeneric_OpStore(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Store _ (StructMake0) mem) + // cond: + // result: mem + for { + if v.Args[1].Op != OpStructMake0 { + break + } + mem := v.Args[2] + v.reset(OpCopy) + v.Type = mem.Type + v.AddArg(mem) + return true + } + // match: (Store dst (StructMake1 <t> f0) mem) + // cond: + // result: (Store [t.FieldType(0).Size()] dst f0 mem) + for { + dst := v.Args[0] + if v.Args[1].Op != OpStructMake1 { + break + } + t := v.Args[1].Type + f0 := v.Args[1].Args[0] + mem := v.Args[2] + v.reset(OpStore) + v.AuxInt = t.FieldType(0).Size() + v.AddArg(dst) + v.AddArg(f0) + v.AddArg(mem) + return true + } + // match: (Store dst (StructMake2 <t> f0 f1) mem) + // cond: + // result: (Store [t.FieldType(1).Size()] (OffPtr <t.FieldType(1).PtrTo()> [t.FieldOff(1)] dst) f1 (Store [t.FieldType(0).Size()] dst f0 mem)) + for { + dst := v.Args[0] + if v.Args[1].Op != OpStructMake2 { + break + } + t := v.Args[1].Type + f0 := v.Args[1].Args[0] + f1 := v.Args[1].Args[1] + mem := v.Args[2] + v.reset(OpStore) + v.AuxInt = t.FieldType(1).Size() + v0 := b.NewValue0(v.Line, OpOffPtr, t.FieldType(1).PtrTo()) + v0.AuxInt = t.FieldOff(1) + v0.AddArg(dst) + v.AddArg(v0) + v.AddArg(f1) + v1 := b.NewValue0(v.Line, OpStore, TypeMem) + v1.AuxInt = t.FieldType(0).Size() + v1.AddArg(dst) + v1.AddArg(f0) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + // match: (Store dst (StructMake3 <t> f0 f1 f2) mem) + // cond: + // result: (Store [t.FieldType(2).Size()] (OffPtr <t.FieldType(2).PtrTo()> [t.FieldOff(2)] dst) f2 (Store [t.FieldType(1).Size()] (OffPtr <t.FieldType(1).PtrTo()> [t.FieldOff(1)] dst) f1 (Store [t.FieldType(0).Size()] dst f0 mem))) + for { + dst := v.Args[0] + if v.Args[1].Op != OpStructMake3 { + break + } + t := v.Args[1].Type + f0 := v.Args[1].Args[0] + f1 := v.Args[1].Args[1] + f2 := v.Args[1].Args[2] + mem := v.Args[2] + v.reset(OpStore) + v.AuxInt = t.FieldType(2).Size() + v0 := b.NewValue0(v.Line, OpOffPtr, t.FieldType(2).PtrTo()) + v0.AuxInt = t.FieldOff(2) + v0.AddArg(dst) + v.AddArg(v0) + v.AddArg(f2) + v1 := b.NewValue0(v.Line, OpStore, TypeMem) + v1.AuxInt = t.FieldType(1).Size() + v2 := b.NewValue0(v.Line, OpOffPtr, t.FieldType(1).PtrTo()) + v2.AuxInt = t.FieldOff(1) + v2.AddArg(dst) + v1.AddArg(v2) + v1.AddArg(f1) + v3 := b.NewValue0(v.Line, OpStore, TypeMem) + v3.AuxInt = t.FieldType(0).Size() + v3.AddArg(dst) + v3.AddArg(f0) + v3.AddArg(mem) + v1.AddArg(v3) + v.AddArg(v1) + return true + } + // match: (Store dst (StructMake4 <t> f0 f1 f2 f3) mem) + // cond: + // result: (Store [t.FieldType(3).Size()] (OffPtr <t.FieldType(3).PtrTo()> [t.FieldOff(3)] dst) f3 (Store [t.FieldType(2).Size()] (OffPtr <t.FieldType(2).PtrTo()> [t.FieldOff(2)] dst) f2 (Store [t.FieldType(1).Size()] (OffPtr <t.FieldType(1).PtrTo()> [t.FieldOff(1)] dst) f1 (Store [t.FieldType(0).Size()] dst f0 mem)))) + for { + dst := v.Args[0] + if v.Args[1].Op != OpStructMake4 { + break + } + t := v.Args[1].Type + f0 := v.Args[1].Args[0] + f1 := v.Args[1].Args[1] + f2 := v.Args[1].Args[2] + f3 := v.Args[1].Args[3] + mem := v.Args[2] + v.reset(OpStore) + v.AuxInt = t.FieldType(3).Size() + v0 := b.NewValue0(v.Line, OpOffPtr, t.FieldType(3).PtrTo()) + v0.AuxInt = t.FieldOff(3) + v0.AddArg(dst) + v.AddArg(v0) + v.AddArg(f3) + v1 := b.NewValue0(v.Line, OpStore, TypeMem) + v1.AuxInt = t.FieldType(2).Size() + v2 := b.NewValue0(v.Line, OpOffPtr, t.FieldType(2).PtrTo()) + v2.AuxInt = t.FieldOff(2) + v2.AddArg(dst) + v1.AddArg(v2) + v1.AddArg(f2) + v3 := b.NewValue0(v.Line, OpStore, TypeMem) + v3.AuxInt = t.FieldType(1).Size() + v4 := b.NewValue0(v.Line, OpOffPtr, t.FieldType(1).PtrTo()) + v4.AuxInt = t.FieldOff(1) + v4.AddArg(dst) + v3.AddArg(v4) + v3.AddArg(f1) + v5 := b.NewValue0(v.Line, OpStore, TypeMem) + v5.AuxInt = t.FieldType(0).Size() + v5.AddArg(dst) + v5.AddArg(f0) + v5.AddArg(mem) + v3.AddArg(v5) + v1.AddArg(v3) + v.AddArg(v1) + return true + } + // match: (Store [8] dst (ComplexMake real imag) mem) + // cond: + // result: (Store [4] (OffPtr <config.fe.TypeFloat32().PtrTo()> [4] dst) imag (Store [4] dst real mem)) + for { + if v.AuxInt != 8 { + break + } + dst := v.Args[0] + if v.Args[1].Op != OpComplexMake { + break + } + real := v.Args[1].Args[0] + imag := v.Args[1].Args[1] + mem := v.Args[2] + v.reset(OpStore) + v.AuxInt = 4 + v0 := b.NewValue0(v.Line, OpOffPtr, config.fe.TypeFloat32().PtrTo()) + v0.AuxInt = 4 + v0.AddArg(dst) + v.AddArg(v0) + v.AddArg(imag) + v1 := b.NewValue0(v.Line, OpStore, TypeMem) + v1.AuxInt = 4 + v1.AddArg(dst) + v1.AddArg(real) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + // match: (Store [16] dst (ComplexMake real imag) mem) + // cond: + // result: (Store [8] (OffPtr <config.fe.TypeFloat64().PtrTo()> [8] dst) imag (Store [8] dst real mem)) + for { + if v.AuxInt != 16 { + break + } + dst := v.Args[0] + if v.Args[1].Op != OpComplexMake { + break + } + real := v.Args[1].Args[0] + imag := v.Args[1].Args[1] + mem := v.Args[2] + v.reset(OpStore) + v.AuxInt = 8 + v0 := b.NewValue0(v.Line, OpOffPtr, config.fe.TypeFloat64().PtrTo()) + v0.AuxInt = 8 + v0.AddArg(dst) + v.AddArg(v0) + v.AddArg(imag) + v1 := b.NewValue0(v.Line, OpStore, TypeMem) + v1.AuxInt = 8 + v1.AddArg(dst) + v1.AddArg(real) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + // match: (Store [2*config.PtrSize] dst (StringMake ptr len) mem) + // cond: + // result: (Store [config.PtrSize] (OffPtr <config.fe.TypeInt().PtrTo()> [config.PtrSize] dst) len (Store [config.PtrSize] dst ptr mem)) + for { + if v.AuxInt != 2*config.PtrSize { + break + } + dst := v.Args[0] + if v.Args[1].Op != OpStringMake { + break + } + ptr := v.Args[1].Args[0] + len := v.Args[1].Args[1] + mem := v.Args[2] + v.reset(OpStore) + v.AuxInt = config.PtrSize + v0 := b.NewValue0(v.Line, OpOffPtr, config.fe.TypeInt().PtrTo()) + v0.AuxInt = config.PtrSize + v0.AddArg(dst) + v.AddArg(v0) + v.AddArg(len) + v1 := b.NewValue0(v.Line, OpStore, TypeMem) + v1.AuxInt = config.PtrSize + v1.AddArg(dst) + v1.AddArg(ptr) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + // match: (Store [3*config.PtrSize] dst (SliceMake ptr len cap) mem) + // cond: + // result: (Store [config.PtrSize] (OffPtr <config.fe.TypeInt().PtrTo()> [2*config.PtrSize] dst) cap (Store [config.PtrSize] (OffPtr <config.fe.TypeInt().PtrTo()> [config.PtrSize] dst) len (Store [config.PtrSize] dst ptr mem))) + for { + if v.AuxInt != 3*config.PtrSize { + break + } + dst := v.Args[0] + if v.Args[1].Op != OpSliceMake { + break + } + ptr := v.Args[1].Args[0] + len := v.Args[1].Args[1] + cap := v.Args[1].Args[2] + mem := v.Args[2] + v.reset(OpStore) + v.AuxInt = config.PtrSize + v0 := b.NewValue0(v.Line, OpOffPtr, config.fe.TypeInt().PtrTo()) + v0.AuxInt = 2 * config.PtrSize + v0.AddArg(dst) + v.AddArg(v0) + v.AddArg(cap) + v1 := b.NewValue0(v.Line, OpStore, TypeMem) + v1.AuxInt = config.PtrSize + v2 := b.NewValue0(v.Line, OpOffPtr, config.fe.TypeInt().PtrTo()) + v2.AuxInt = config.PtrSize + v2.AddArg(dst) + v1.AddArg(v2) + v1.AddArg(len) + v3 := b.NewValue0(v.Line, OpStore, TypeMem) + v3.AuxInt = config.PtrSize + v3.AddArg(dst) + v3.AddArg(ptr) + v3.AddArg(mem) + v1.AddArg(v3) + v.AddArg(v1) + return true + } + // match: (Store [2*config.PtrSize] dst (IMake itab data) mem) + // cond: + // result: (Store [config.PtrSize] (OffPtr <config.fe.TypeBytePtr().PtrTo()> [config.PtrSize] dst) data (Store [config.PtrSize] dst itab mem)) + for { + if v.AuxInt != 2*config.PtrSize { + break + } + dst := v.Args[0] + if v.Args[1].Op != OpIMake { + break + } + itab := v.Args[1].Args[0] + data := v.Args[1].Args[1] + mem := v.Args[2] + v.reset(OpStore) + v.AuxInt = config.PtrSize + v0 := b.NewValue0(v.Line, OpOffPtr, config.fe.TypeBytePtr().PtrTo()) + v0.AuxInt = config.PtrSize + v0.AddArg(dst) + v.AddArg(v0) + v.AddArg(data) + v1 := b.NewValue0(v.Line, OpStore, TypeMem) + v1.AuxInt = config.PtrSize + v1.AddArg(dst) + v1.AddArg(itab) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + // match: (Store [size] dst (Load <t> src mem) mem) + // cond: !config.fe.CanSSA(t) + // result: (Move [size] dst src mem) + for { + size := v.AuxInt + dst := v.Args[0] + if v.Args[1].Op != OpLoad { + break + } + t := v.Args[1].Type + src := v.Args[1].Args[0] + mem := v.Args[1].Args[1] + if v.Args[2] != mem { + break + } + if !(!config.fe.CanSSA(t)) { + break + } + v.reset(OpMove) + v.AuxInt = size + v.AddArg(dst) + v.AddArg(src) + v.AddArg(mem) + return true + } + // match: (Store [size] dst (Load <t> src mem) (VarDef {x} mem)) + // cond: !config.fe.CanSSA(t) + // result: (Move [size] dst src (VarDef {x} mem)) + for { + size := v.AuxInt + dst := v.Args[0] + if v.Args[1].Op != OpLoad { + break + } + t := v.Args[1].Type + src := v.Args[1].Args[0] + mem := v.Args[1].Args[1] + if v.Args[2].Op != OpVarDef { + break + } + x := v.Args[2].Aux + if v.Args[2].Args[0] != mem { + break + } + if !(!config.fe.CanSSA(t)) { + break + } + v.reset(OpMove) + v.AuxInt = size + v.AddArg(dst) + v.AddArg(src) + v0 := b.NewValue0(v.Line, OpVarDef, TypeMem) + v0.Aux = x + v0.AddArg(mem) + v.AddArg(v0) + return true + } + return false +} +func rewriteValuegeneric_OpStringLen(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (StringLen (StringMake _ len)) + // cond: + // result: len + for { + if v.Args[0].Op != OpStringMake { + break + } + len := v.Args[0].Args[1] + v.reset(OpCopy) + v.Type = len.Type + v.AddArg(len) + return true + } + return false +} +func rewriteValuegeneric_OpStringPtr(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (StringPtr (StringMake ptr _)) + // cond: + // result: ptr + for { + if v.Args[0].Op != OpStringMake { + break + } + ptr := v.Args[0].Args[0] + v.reset(OpCopy) + v.Type = ptr.Type + v.AddArg(ptr) + return true + } + return false +} +func rewriteValuegeneric_OpStructSelect(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (StructSelect (StructMake1 x)) + // cond: + // result: x + for { + if v.Args[0].Op != OpStructMake1 { + break + } + x := v.Args[0].Args[0] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (StructSelect [0] (StructMake2 x _)) + // cond: + // result: x + for { + if v.AuxInt != 0 { + break + } + if v.Args[0].Op != OpStructMake2 { + break + } + x := v.Args[0].Args[0] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (StructSelect [1] (StructMake2 _ x)) + // cond: + // result: x + for { + if v.AuxInt != 1 { + break + } + if v.Args[0].Op != OpStructMake2 { + break + } + x := v.Args[0].Args[1] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (StructSelect [0] (StructMake3 x _ _)) + // cond: + // result: x + for { + if v.AuxInt != 0 { + break + } + if v.Args[0].Op != OpStructMake3 { + break + } + x := v.Args[0].Args[0] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (StructSelect [1] (StructMake3 _ x _)) + // cond: + // result: x + for { + if v.AuxInt != 1 { + break + } + if v.Args[0].Op != OpStructMake3 { + break + } + x := v.Args[0].Args[1] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (StructSelect [2] (StructMake3 _ _ x)) + // cond: + // result: x + for { + if v.AuxInt != 2 { + break + } + if v.Args[0].Op != OpStructMake3 { + break + } + x := v.Args[0].Args[2] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (StructSelect [0] (StructMake4 x _ _ _)) + // cond: + // result: x + for { + if v.AuxInt != 0 { + break + } + if v.Args[0].Op != OpStructMake4 { + break + } + x := v.Args[0].Args[0] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (StructSelect [1] (StructMake4 _ x _ _)) + // cond: + // result: x + for { + if v.AuxInt != 1 { + break + } + if v.Args[0].Op != OpStructMake4 { + break + } + x := v.Args[0].Args[1] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (StructSelect [2] (StructMake4 _ _ x _)) + // cond: + // result: x + for { + if v.AuxInt != 2 { + break + } + if v.Args[0].Op != OpStructMake4 { + break + } + x := v.Args[0].Args[2] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (StructSelect [3] (StructMake4 _ _ _ x)) + // cond: + // result: x + for { + if v.AuxInt != 3 { + break + } + if v.Args[0].Op != OpStructMake4 { + break + } + x := v.Args[0].Args[3] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + // match: (StructSelect [i] (Load <t> ptr mem)) + // cond: !config.fe.CanSSA(t) + // result: @v.Args[0].Block (Load <v.Type> (OffPtr <v.Type.PtrTo()> [t.FieldOff(i)] ptr) mem) + for { + i := v.AuxInt + if v.Args[0].Op != OpLoad { + break + } + t := v.Args[0].Type + ptr := v.Args[0].Args[0] + mem := v.Args[0].Args[1] + if !(!config.fe.CanSSA(t)) { + break + } + b = v.Args[0].Block + v0 := b.NewValue0(v.Line, OpLoad, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpOffPtr, v.Type.PtrTo()) + v.reset(OpCopy) + v.AddArg(v1) + v1.AuxInt = t.FieldOff(i) + v1.AddArg(ptr) + v0.AddArg(v1) + v0.AddArg(mem) + return true + } + return false +} +func rewriteValuegeneric_OpSub16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Sub16 (Const16 [c]) (Const16 [d])) + // cond: + // result: (Const16 [c-d]) + for { + if v.Args[0].Op != OpConst16 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst16 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConst16) + v.AuxInt = c - d + return true + } + // match: (Sub16 x (Const16 <t> [c])) + // cond: x.Op != OpConst16 + // result: (Add16 (Const16 <t> [-c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst16 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst16) { + break + } + v.reset(OpAdd16) + v0 := b.NewValue0(v.Line, OpConst16, t) + v0.AuxInt = -c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Sub16 x x) + // cond: + // result: (Const16 [0]) + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpConst16) + v.AuxInt = 0 + return true + } + // match: (Sub16 (Add16 x y) x) + // cond: + // result: y + for { + if v.Args[0].Op != OpAdd16 { + break + } + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + if v.Args[1] != x { + break + } + v.reset(OpCopy) + v.Type = y.Type + v.AddArg(y) + return true + } + // match: (Sub16 (Add16 x y) y) + // cond: + // result: x + for { + if v.Args[0].Op != OpAdd16 { + break + } + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + if v.Args[1] != y { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValuegeneric_OpSub32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Sub32 (Const32 [c]) (Const32 [d])) + // cond: + // result: (Const32 [c-d]) + for { + if v.Args[0].Op != OpConst32 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst32 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConst32) + v.AuxInt = c - d + return true + } + // match: (Sub32 x (Const32 <t> [c])) + // cond: x.Op != OpConst32 + // result: (Add32 (Const32 <t> [-c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst32 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst32) { + break + } + v.reset(OpAdd32) + v0 := b.NewValue0(v.Line, OpConst32, t) + v0.AuxInt = -c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Sub32 x x) + // cond: + // result: (Const32 [0]) + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpConst32) + v.AuxInt = 0 + return true + } + // match: (Sub32 (Add32 x y) x) + // cond: + // result: y + for { + if v.Args[0].Op != OpAdd32 { + break + } + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + if v.Args[1] != x { + break + } + v.reset(OpCopy) + v.Type = y.Type + v.AddArg(y) + return true + } + // match: (Sub32 (Add32 x y) y) + // cond: + // result: x + for { + if v.Args[0].Op != OpAdd32 { + break + } + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + if v.Args[1] != y { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValuegeneric_OpSub64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Sub64 (Const64 [c]) (Const64 [d])) + // cond: + // result: (Const64 [c-d]) + for { + if v.Args[0].Op != OpConst64 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst64 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConst64) + v.AuxInt = c - d + return true + } + // match: (Sub64 x (Const64 <t> [c])) + // cond: x.Op != OpConst64 + // result: (Add64 (Const64 <t> [-c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst64) { + break + } + v.reset(OpAdd64) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = -c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Sub64 x x) + // cond: + // result: (Const64 [0]) + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpConst64) + v.AuxInt = 0 + return true + } + // match: (Sub64 (Add64 x y) x) + // cond: + // result: y + for { + if v.Args[0].Op != OpAdd64 { + break + } + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + if v.Args[1] != x { + break + } + v.reset(OpCopy) + v.Type = y.Type + v.AddArg(y) + return true + } + // match: (Sub64 (Add64 x y) y) + // cond: + // result: x + for { + if v.Args[0].Op != OpAdd64 { + break + } + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + if v.Args[1] != y { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValuegeneric_OpSub8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Sub8 (Const8 [c]) (Const8 [d])) + // cond: + // result: (Const8 [c-d]) + for { + if v.Args[0].Op != OpConst8 { + break + } + c := v.Args[0].AuxInt + if v.Args[1].Op != OpConst8 { + break + } + d := v.Args[1].AuxInt + v.reset(OpConst8) + v.AuxInt = c - d + return true + } + // match: (Sub8 x (Const8 <t> [c])) + // cond: x.Op != OpConst8 + // result: (Add8 (Const8 <t> [-c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst8 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst8) { + break + } + v.reset(OpAdd8) + v0 := b.NewValue0(v.Line, OpConst8, t) + v0.AuxInt = -c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Sub8 x x) + // cond: + // result: (Const8 [0]) + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpConst8) + v.AuxInt = 0 + return true + } + // match: (Sub8 (Add8 x y) x) + // cond: + // result: y + for { + if v.Args[0].Op != OpAdd8 { + break + } + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + if v.Args[1] != x { + break + } + v.reset(OpCopy) + v.Type = y.Type + v.AddArg(y) + return true + } + // match: (Sub8 (Add8 x y) y) + // cond: + // result: x + for { + if v.Args[0].Op != OpAdd8 { + break + } + x := v.Args[0].Args[0] + y := v.Args[0].Args[1] + if v.Args[1] != y { + break + } + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValuegeneric_OpTrunc16to8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Trunc16to8 (Const16 [c])) + // cond: + // result: (Const8 [int64(int8(c))]) + for { + if v.Args[0].Op != OpConst16 { + break + } + c := v.Args[0].AuxInt + v.reset(OpConst8) + v.AuxInt = int64(int8(c)) + return true + } + return false +} +func rewriteValuegeneric_OpTrunc32to16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Trunc32to16 (Const32 [c])) + // cond: + // result: (Const16 [int64(int16(c))]) + for { + if v.Args[0].Op != OpConst32 { + break + } + c := v.Args[0].AuxInt + v.reset(OpConst16) + v.AuxInt = int64(int16(c)) + return true + } + return false +} +func rewriteValuegeneric_OpTrunc32to8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Trunc32to8 (Const32 [c])) + // cond: + // result: (Const8 [int64(int8(c))]) + for { + if v.Args[0].Op != OpConst32 { + break + } + c := v.Args[0].AuxInt + v.reset(OpConst8) + v.AuxInt = int64(int8(c)) + return true + } + return false +} +func rewriteValuegeneric_OpTrunc64to16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Trunc64to16 (Const64 [c])) + // cond: + // result: (Const16 [int64(int16(c))]) + for { + if v.Args[0].Op != OpConst64 { + break + } + c := v.Args[0].AuxInt + v.reset(OpConst16) + v.AuxInt = int64(int16(c)) + return true + } + return false +} +func rewriteValuegeneric_OpTrunc64to32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Trunc64to32 (Const64 [c])) + // cond: + // result: (Const32 [int64(int32(c))]) + for { + if v.Args[0].Op != OpConst64 { + break + } + c := v.Args[0].AuxInt + v.reset(OpConst32) + v.AuxInt = int64(int32(c)) + return true + } + return false +} +func rewriteValuegeneric_OpTrunc64to8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Trunc64to8 (Const64 [c])) + // cond: + // result: (Const8 [int64(int8(c))]) + for { + if v.Args[0].Op != OpConst64 { + break + } + c := v.Args[0].AuxInt + v.reset(OpConst8) + v.AuxInt = int64(int8(c)) + return true + } + return false +} +func rewriteValuegeneric_OpXor16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Xor16 x (Const16 <t> [c])) + // cond: x.Op != OpConst16 + // result: (Xor16 (Const16 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst16 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst16) { + break + } + v.reset(OpXor16) + v0 := b.NewValue0(v.Line, OpConst16, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Xor16 x x) + // cond: + // result: (Const16 [0]) + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpConst16) + v.AuxInt = 0 + return true + } + // match: (Xor16 (Const16 [0]) x) + // cond: + // result: x + for { + if v.Args[0].Op != OpConst16 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + x := v.Args[1] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValuegeneric_OpXor32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Xor32 x (Const32 <t> [c])) + // cond: x.Op != OpConst32 + // result: (Xor32 (Const32 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst32 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst32) { + break + } + v.reset(OpXor32) + v0 := b.NewValue0(v.Line, OpConst32, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Xor32 x x) + // cond: + // result: (Const32 [0]) + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpConst32) + v.AuxInt = 0 + return true + } + // match: (Xor32 (Const32 [0]) x) + // cond: + // result: x + for { + if v.Args[0].Op != OpConst32 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + x := v.Args[1] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValuegeneric_OpXor64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Xor64 x (Const64 <t> [c])) + // cond: x.Op != OpConst64 + // result: (Xor64 (Const64 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst64 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst64) { + break + } + v.reset(OpXor64) + v0 := b.NewValue0(v.Line, OpConst64, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Xor64 x x) + // cond: + // result: (Const64 [0]) + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpConst64) + v.AuxInt = 0 + return true + } + // match: (Xor64 (Const64 [0]) x) + // cond: + // result: x + for { + if v.Args[0].Op != OpConst64 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + x := v.Args[1] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteValuegeneric_OpXor8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Xor8 x (Const8 <t> [c])) + // cond: x.Op != OpConst8 + // result: (Xor8 (Const8 <t> [c]) x) + for { + x := v.Args[0] + if v.Args[1].Op != OpConst8 { + break + } + t := v.Args[1].Type + c := v.Args[1].AuxInt + if !(x.Op != OpConst8) { + break + } + v.reset(OpXor8) + v0 := b.NewValue0(v.Line, OpConst8, t) + v0.AuxInt = c + v.AddArg(v0) + v.AddArg(x) + return true + } + // match: (Xor8 x x) + // cond: + // result: (Const8 [0]) + for { + x := v.Args[0] + if v.Args[1] != x { + break + } + v.reset(OpConst8) + v.AuxInt = 0 + return true + } + // match: (Xor8 (Const8 [0]) x) + // cond: + // result: x + for { + if v.Args[0].Op != OpConst8 { + break + } + if v.Args[0].AuxInt != 0 { + break + } + x := v.Args[1] + v.reset(OpCopy) + v.Type = x.Type + v.AddArg(x) + return true + } + return false +} +func rewriteBlockgeneric(b *Block) bool { + switch b.Kind { + case BlockCheck: + // match: (Check (NilCheck (GetG _) _) next) + // cond: + // result: (Plain nil next) + for { + v := b.Control + if v.Op != OpNilCheck { + break + } + if v.Args[0].Op != OpGetG { + break + } + next := b.Succs[0] + b.Kind = BlockPlain + b.Control = nil + b.Succs[0] = next + b.Likely = BranchUnknown + return true + } + case BlockIf: + // match: (If (Not cond) yes no) + // cond: + // result: (If cond no yes) + for { + v := b.Control + if v.Op != OpNot { + break + } + cond := v.Args[0] + yes := b.Succs[0] + no := b.Succs[1] + b.Kind = BlockIf + b.Control = cond + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + // match: (If (ConstBool [c]) yes no) + // cond: c == 1 + // result: (First nil yes no) + for { + v := b.Control + if v.Op != OpConstBool { + break + } + c := v.AuxInt + yes := b.Succs[0] + no := b.Succs[1] + if !(c == 1) { + break + } + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = yes + b.Succs[1] = no + return true + } + // match: (If (ConstBool [c]) yes no) + // cond: c == 0 + // result: (First nil no yes) + for { + v := b.Control + if v.Op != OpConstBool { + break + } + c := v.AuxInt + yes := b.Succs[0] + no := b.Succs[1] + if !(c == 0) { + break + } + b.Kind = BlockFirst + b.Control = nil + b.Succs[0] = no + b.Succs[1] = yes + b.Likely *= -1 + return true + } + } + return false +} diff --git a/src/cmd/compile/internal/ssa/schedule.go b/src/cmd/compile/internal/ssa/schedule.go new file mode 100644 index 0000000000..dd0a42a5dd --- /dev/null +++ b/src/cmd/compile/internal/ssa/schedule.go @@ -0,0 +1,195 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +const ( + ScorePhi = iota // towards top of block + ScoreVarDef + ScoreMemory + ScoreDefault + ScoreFlags + ScoreControl // towards bottom of block + + ScoreCount // not a real score +) + +// Schedule the Values in each Block. After this phase returns, the +// order of b.Values matters and is the order in which those values +// will appear in the assembly output. For now it generates a +// reasonable valid schedule using a priority queue. TODO(khr): +// schedule smarter. +func schedule(f *Func) { + // For each value, the number of times it is used in the block + // by values that have not been scheduled yet. + uses := make([]int, f.NumValues()) + + // "priority" for a value + score := make([]uint8, f.NumValues()) + + // scheduling order. We queue values in this list in reverse order. + var order []*Value + + // priority queue of legally schedulable (0 unscheduled uses) values + var priq [ScoreCount][]*Value + + // maps mem values to the next live memory value + nextMem := make([]*Value, f.NumValues()) + // additional pretend arguments for each Value. Used to enforce load/store ordering. + additionalArgs := make([][]*Value, f.NumValues()) + + for _, b := range f.Blocks { + // Find store chain for block. + // Store chains for different blocks overwrite each other, so + // the calculated store chain is good only for this block. + for _, v := range b.Values { + if v.Op != OpPhi && v.Type.IsMemory() { + for _, w := range v.Args { + if w.Type.IsMemory() { + nextMem[w.ID] = v + } + } + } + } + + // Compute uses. + for _, v := range b.Values { + if v.Op == OpPhi { + // If a value is used by a phi, it does not induce + // a scheduling edge because that use is from the + // previous iteration. + continue + } + for _, w := range v.Args { + if w.Block == b { + uses[w.ID]++ + } + // Any load must come before the following store. + if v.Type.IsMemory() || !w.Type.IsMemory() { + continue // not a load + } + s := nextMem[w.ID] + if s == nil || s.Block != b { + continue + } + additionalArgs[s.ID] = append(additionalArgs[s.ID], v) + uses[v.ID]++ + } + } + // Compute score. Larger numbers are scheduled closer to the end of the block. + for _, v := range b.Values { + switch { + case v.Op == OpAMD64LoweredGetClosurePtr: + // We also score GetLoweredClosurePtr as early as possible to ensure that the + // context register is not stomped. GetLoweredClosurePtr should only appear + // in the entry block where there are no phi functions, so there is no + // conflict or ambiguity here. + if b != f.Entry { + f.Fatalf("LoweredGetClosurePtr appeared outside of entry block, b=%s", b.String()) + } + score[v.ID] = ScorePhi + case v.Op == OpPhi: + // We want all the phis first. + score[v.ID] = ScorePhi + case v.Op == OpVarDef: + // We want all the vardefs next. + score[v.ID] = ScoreVarDef + case v.Type.IsMemory(): + // Schedule stores as early as possible. This tends to + // reduce register pressure. It also helps make sure + // VARDEF ops are scheduled before the corresponding LEA. + score[v.ID] = ScoreMemory + case v.Type.IsFlags(): + // Schedule flag register generation as late as possible. + // This makes sure that we only have one live flags + // value at a time. + score[v.ID] = ScoreFlags + default: + score[v.ID] = ScoreDefault + } + } + if b.Control != nil && b.Control.Op != OpPhi { + // Force the control value to be scheduled at the end, + // unless it is a phi value (which must be first). + score[b.Control.ID] = ScoreControl + + // Schedule values dependent on the control value at the end. + // This reduces the number of register spills. We don't find + // all values that depend on the control, just values with a + // direct dependency. This is cheaper and in testing there + // was no difference in the number of spills. + for _, v := range b.Values { + if v.Op != OpPhi { + for _, a := range v.Args { + if a == b.Control { + score[v.ID] = ScoreControl + } + } + } + } + } + + // Initialize priority queue with schedulable values. + for i := range priq { + priq[i] = priq[i][:0] + } + for _, v := range b.Values { + if uses[v.ID] == 0 { + s := score[v.ID] + priq[s] = append(priq[s], v) + } + } + + // Schedule highest priority value, update use counts, repeat. + order = order[:0] + for { + // Find highest priority schedulable value. + var v *Value + for i := len(priq) - 1; i >= 0; i-- { + n := len(priq[i]) + if n == 0 { + continue + } + v = priq[i][n-1] + priq[i] = priq[i][:n-1] + break + } + if v == nil { + break + } + + // Add it to the schedule. + order = append(order, v) + + // Update use counts of arguments. + for _, w := range v.Args { + if w.Block != b { + continue + } + uses[w.ID]-- + if uses[w.ID] == 0 { + // All uses scheduled, w is now schedulable. + s := score[w.ID] + priq[s] = append(priq[s], w) + } + } + for _, w := range additionalArgs[v.ID] { + uses[w.ID]-- + if uses[w.ID] == 0 { + // All uses scheduled, w is now schedulable. + s := score[w.ID] + priq[s] = append(priq[s], w) + } + } + } + if len(order) != len(b.Values) { + f.Fatalf("schedule does not include all values") + } + for i := 0; i < len(b.Values); i++ { + b.Values[i] = order[len(b.Values)-1-i] + } + } + + f.scheduled = true +} diff --git a/src/cmd/compile/internal/ssa/schedule_test.go b/src/cmd/compile/internal/ssa/schedule_test.go new file mode 100644 index 0000000000..0ff57e3689 --- /dev/null +++ b/src/cmd/compile/internal/ssa/schedule_test.go @@ -0,0 +1,57 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import "testing" + +func TestSchedule(t *testing.T) { + c := testConfig(t) + cases := []fun{ + Fun(c, "entry", + Bloc("entry", + Valu("mem0", OpInitMem, TypeMem, 0, nil), + Valu("ptr", OpConst64, TypeInt64, 0xABCD, nil), + Valu("v", OpConst64, TypeInt64, 12, nil), + Valu("mem1", OpStore, TypeMem, 8, nil, "ptr", "v", "mem0"), + Valu("mem2", OpStore, TypeMem, 8, nil, "ptr", "v", "mem1"), + Valu("mem3", OpStore, TypeInt64, 8, nil, "ptr", "sum", "mem2"), + Valu("l1", OpLoad, TypeInt64, 0, nil, "ptr", "mem1"), + Valu("l2", OpLoad, TypeInt64, 0, nil, "ptr", "mem2"), + Valu("sum", OpAdd64, TypeInt64, 0, nil, "l1", "l2"), + Goto("exit")), + Bloc("exit", + Exit("mem3"))), + } + for _, c := range cases { + schedule(c.f) + if !isSingleLiveMem(c.f) { + t.Error("single-live-mem restriction not enforced by schedule for func:") + printFunc(c.f) + } + } +} + +func isSingleLiveMem(f *Func) bool { + for _, b := range f.Blocks { + var liveMem *Value + for _, v := range b.Values { + for _, w := range v.Args { + if w.Type.IsMemory() { + if liveMem == nil { + liveMem = w + continue + } + if w != liveMem { + return false + } + } + } + if v.Type.IsMemory() { + liveMem = v + } + } + } + return true +} diff --git a/src/cmd/compile/internal/ssa/shift_test.go b/src/cmd/compile/internal/ssa/shift_test.go new file mode 100644 index 0000000000..8d5e62f070 --- /dev/null +++ b/src/cmd/compile/internal/ssa/shift_test.go @@ -0,0 +1,48 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import ( + "testing" +) + +func TestShiftConstAMD64(t *testing.T) { + c := testConfig(t) + fun := makeConstShiftFunc(c, 18, OpLsh64x64, TypeUInt64) + checkOpcodeCounts(t, fun.f, map[Op]int{OpAMD64SHLQconst: 1, OpAMD64CMPQconst: 0, OpAMD64ANDQconst: 0}) + fun.f.Free() + fun = makeConstShiftFunc(c, 66, OpLsh64x64, TypeUInt64) + checkOpcodeCounts(t, fun.f, map[Op]int{OpAMD64SHLQconst: 0, OpAMD64CMPQconst: 0, OpAMD64ANDQconst: 0}) + fun.f.Free() + fun = makeConstShiftFunc(c, 18, OpRsh64Ux64, TypeUInt64) + checkOpcodeCounts(t, fun.f, map[Op]int{OpAMD64SHRQconst: 1, OpAMD64CMPQconst: 0, OpAMD64ANDQconst: 0}) + fun.f.Free() + fun = makeConstShiftFunc(c, 66, OpRsh64Ux64, TypeUInt64) + checkOpcodeCounts(t, fun.f, map[Op]int{OpAMD64SHRQconst: 0, OpAMD64CMPQconst: 0, OpAMD64ANDQconst: 0}) + fun.f.Free() + fun = makeConstShiftFunc(c, 18, OpRsh64x64, TypeInt64) + checkOpcodeCounts(t, fun.f, map[Op]int{OpAMD64SARQconst: 1, OpAMD64CMPQconst: 0}) + fun.f.Free() + fun = makeConstShiftFunc(c, 66, OpRsh64x64, TypeInt64) + checkOpcodeCounts(t, fun.f, map[Op]int{OpAMD64SARQconst: 1, OpAMD64CMPQconst: 0}) + fun.f.Free() +} + +func makeConstShiftFunc(c *Config, amount int64, op Op, typ Type) fun { + ptyp := &TypeImpl{Size_: 8, Ptr: true, Name: "ptr"} + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("SP", OpSP, TypeUInt64, 0, nil), + Valu("argptr", OpOffPtr, ptyp, 8, nil, "SP"), + Valu("resptr", OpOffPtr, ptyp, 16, nil, "SP"), + Valu("load", OpLoad, typ, 0, nil, "argptr", "mem"), + Valu("c", OpConst64, TypeUInt64, amount, nil), + Valu("shift", op, typ, 0, nil, "load", "c"), + Valu("store", OpStore, TypeMem, 8, nil, "resptr", "shift", "mem"), + Exit("store"))) + Compile(fun.f) + return fun +} diff --git a/src/cmd/compile/internal/ssa/shortcircuit.go b/src/cmd/compile/internal/ssa/shortcircuit.go new file mode 100644 index 0000000000..d22a61a0af --- /dev/null +++ b/src/cmd/compile/internal/ssa/shortcircuit.go @@ -0,0 +1,144 @@ +// Copyright 2016 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +// Shortcircuit finds situations where branch directions +// are always correlated and rewrites the CFG to take +// advantage of that fact. +// This optimization is useful for compiling && and || expressions. +func shortcircuit(f *Func) { + // Step 1: Replace a phi arg with a constant if that arg + // is the control value of a preceding If block. + // b1: + // If a goto b2 else b3 + // b2: <- b1 ... + // x = phi(a, ...) + // + // We can replace the "a" in the phi with the constant true. + ct := f.ConstBool(f.Entry.Line, f.Config.fe.TypeBool(), true) + cf := f.ConstBool(f.Entry.Line, f.Config.fe.TypeBool(), false) + for _, b := range f.Blocks { + for _, v := range b.Values { + if v.Op != OpPhi { + continue + } + if !v.Type.IsBoolean() { + continue + } + for i, a := range v.Args { + p := b.Preds[i] + if p.Kind != BlockIf { + continue + } + if p.Control != a { + continue + } + if p.Succs[0] == b { + v.Args[i] = ct + } else { + v.Args[i] = cf + } + } + } + } + + // Step 2: Compute which values are live across blocks. + live := make([]bool, f.NumValues()) + for _, b := range f.Blocks { + for _, v := range b.Values { + for _, a := range v.Args { + if a.Block != v.Block { + live[a.ID] = true + } + } + } + if b.Control != nil && b.Control.Block != b { + live[b.Control.ID] = true + } + } + + // Step 3: Redirect control flow around known branches. + // p: + // ... goto b ... + // b: <- p ... + // v = phi(true, ...) + // if v goto t else u + // We can redirect p to go directly to t instead of b. + // (If v is not live after b). + for _, b := range f.Blocks { + if b.Kind != BlockIf { + continue + } + if len(b.Values) != 1 { + continue + } + v := b.Values[0] + if v.Op != OpPhi { + continue + } + if b.Control != v { + continue + } + if live[v.ID] { + continue + } + for i := 0; i < len(v.Args); i++ { + a := v.Args[i] + if a.Op != OpConstBool { + continue + } + + // The predecessor we come in from. + p := b.Preds[i] + // The successor we always go to when coming in + // from that predecessor. + t := b.Succs[1-a.AuxInt] + + // Change the edge p->b to p->t. + for j, x := range p.Succs { + if x == b { + p.Succs[j] = t + break + } + } + + // Fix up t to have one more predecessor. + j := predIdx(t, b) + t.Preds = append(t.Preds, p) + for _, w := range t.Values { + if w.Op != OpPhi { + continue + } + w.Args = append(w.Args, w.Args[j]) + } + + // Fix up b to have one less predecessor. + n := len(b.Preds) - 1 + b.Preds[i] = b.Preds[n] + b.Preds[n] = nil + b.Preds = b.Preds[:n] + v.Args[i] = v.Args[n] + v.Args[n] = nil + v.Args = v.Args[:n] + if n == 1 { + v.Op = OpCopy + // No longer a phi, stop optimizing here. + break + } + i-- + } + } +} + +// predIdx returns the index where p appears in the predecessor list of b. +// p must be in the predecessor list of b. +func predIdx(b, p *Block) int { + for i, x := range b.Preds { + if x == p { + return i + } + } + panic("predecessor not found") +} diff --git a/src/cmd/compile/internal/ssa/shortcircuit_test.go b/src/cmd/compile/internal/ssa/shortcircuit_test.go new file mode 100644 index 0000000000..f208801fc1 --- /dev/null +++ b/src/cmd/compile/internal/ssa/shortcircuit_test.go @@ -0,0 +1,50 @@ +// Copyright 2016 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import "testing" + +func TestShortCircuit(t *testing.T) { + c := testConfig(t) + + fun := Fun(c, "entry", + Bloc("entry", + Valu("mem", OpInitMem, TypeMem, 0, nil), + Valu("arg1", OpArg, TypeInt64, 0, nil), + Valu("arg2", OpArg, TypeInt64, 0, nil), + Valu("arg3", OpArg, TypeInt64, 0, nil), + Goto("b1")), + Bloc("b1", + Valu("cmp1", OpLess64, TypeBool, 0, nil, "arg1", "arg2"), + If("cmp1", "b2", "b3")), + Bloc("b2", + Valu("cmp2", OpLess64, TypeBool, 0, nil, "arg2", "arg3"), + Goto("b3")), + Bloc("b3", + Valu("phi2", OpPhi, TypeBool, 0, nil, "cmp1", "cmp2"), + If("phi2", "b4", "b5")), + Bloc("b4", + Valu("cmp3", OpLess64, TypeBool, 0, nil, "arg3", "arg1"), + Goto("b5")), + Bloc("b5", + Valu("phi3", OpPhi, TypeBool, 0, nil, "phi2", "cmp3"), + If("phi3", "b6", "b7")), + Bloc("b6", + Exit("mem")), + Bloc("b7", + Exit("mem"))) + + CheckFunc(fun.f) + shortcircuit(fun.f) + CheckFunc(fun.f) + + for _, b := range fun.f.Blocks { + for _, v := range b.Values { + if v.Op == OpPhi { + t.Errorf("phi %s remains", v) + } + } + } +} diff --git a/src/cmd/compile/internal/ssa/sparsemap.go b/src/cmd/compile/internal/ssa/sparsemap.go new file mode 100644 index 0000000000..6c0043b230 --- /dev/null +++ b/src/cmd/compile/internal/ssa/sparsemap.go @@ -0,0 +1,69 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +// from http://research.swtch.com/sparse +// in turn, from Briggs and Torczon + +type sparseEntry struct { + key ID + val int32 +} + +type sparseMap struct { + dense []sparseEntry + sparse []int +} + +// newSparseMap returns a sparseMap that can map +// integers between 0 and n-1 to int32s. +func newSparseMap(n int) *sparseMap { + return &sparseMap{nil, make([]int, n)} +} + +func (s *sparseMap) size() int { + return len(s.dense) +} + +func (s *sparseMap) contains(k ID) bool { + i := s.sparse[k] + return i < len(s.dense) && s.dense[i].key == k +} + +func (s *sparseMap) get(k ID) int32 { + i := s.sparse[k] + if i < len(s.dense) && s.dense[i].key == k { + return s.dense[i].val + } + return -1 +} + +func (s *sparseMap) set(k ID, v int32) { + i := s.sparse[k] + if i < len(s.dense) && s.dense[i].key == k { + s.dense[i].val = v + return + } + s.dense = append(s.dense, sparseEntry{k, v}) + s.sparse[k] = len(s.dense) - 1 +} + +func (s *sparseMap) remove(k ID) { + i := s.sparse[k] + if i < len(s.dense) && s.dense[i].key == k { + y := s.dense[len(s.dense)-1] + s.dense[i] = y + s.sparse[y.key] = i + s.dense = s.dense[:len(s.dense)-1] + } +} + +func (s *sparseMap) clear() { + s.dense = s.dense[:0] +} + +func (s *sparseMap) contents() []sparseEntry { + return s.dense +} diff --git a/src/cmd/compile/internal/ssa/sparseset.go b/src/cmd/compile/internal/ssa/sparseset.go new file mode 100644 index 0000000000..66bebf139e --- /dev/null +++ b/src/cmd/compile/internal/ssa/sparseset.go @@ -0,0 +1,79 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +// from http://research.swtch.com/sparse +// in turn, from Briggs and Torczon + +type sparseSet struct { + dense []ID + sparse []int +} + +// newSparseSet returns a sparseSet that can represent +// integers between 0 and n-1 +func newSparseSet(n int) *sparseSet { + return &sparseSet{nil, make([]int, n)} +} + +func (s *sparseSet) cap() int { + return len(s.sparse) +} + +func (s *sparseSet) size() int { + return len(s.dense) +} + +func (s *sparseSet) contains(x ID) bool { + i := s.sparse[x] + return i < len(s.dense) && s.dense[i] == x +} + +func (s *sparseSet) add(x ID) { + i := s.sparse[x] + if i < len(s.dense) && s.dense[i] == x { + return + } + s.dense = append(s.dense, x) + s.sparse[x] = len(s.dense) - 1 +} + +func (s *sparseSet) addAll(a []ID) { + for _, x := range a { + s.add(x) + } +} + +func (s *sparseSet) addAllValues(a []*Value) { + for _, v := range a { + s.add(v.ID) + } +} + +func (s *sparseSet) remove(x ID) { + i := s.sparse[x] + if i < len(s.dense) && s.dense[i] == x { + y := s.dense[len(s.dense)-1] + s.dense[i] = y + s.sparse[y] = i + s.dense = s.dense[:len(s.dense)-1] + } +} + +// pop removes an arbitrary element from the set. +// The set must be nonempty. +func (s *sparseSet) pop() ID { + x := s.dense[len(s.dense)-1] + s.dense = s.dense[:len(s.dense)-1] + return x +} + +func (s *sparseSet) clear() { + s.dense = s.dense[:0] +} + +func (s *sparseSet) contents() []ID { + return s.dense +} diff --git a/src/cmd/compile/internal/ssa/sparsetree.go b/src/cmd/compile/internal/ssa/sparsetree.go new file mode 100644 index 0000000000..9a08f35d9d --- /dev/null +++ b/src/cmd/compile/internal/ssa/sparsetree.go @@ -0,0 +1,129 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +type sparseTreeNode struct { + child *Block + sibling *Block + parent *Block + + // Every block has 6 numbers associated with it: + // entry-1, entry, entry+1, exit-1, and exit, exit+1. + // entry and exit are conceptually the top of the block (phi functions) + // entry+1 and exit-1 are conceptually the bottom of the block (ordinary defs) + // entry-1 and exit+1 are conceptually "just before" the block (conditions flowing in) + // + // This simplifies life if we wish to query information about x + // when x is both an input to and output of a block. + entry, exit int32 +} + +const ( + // When used to lookup up definitions in a sparse tree, + // these adjustments to a block's entry (+adjust) and + // exit (-adjust) numbers allow a distinction to be made + // between assignments (typically branch-dependent + // conditionals) occurring "before" phi functions, the + // phi functions, and at the bottom of a block. + ADJUST_BEFORE = -1 // defined before phi + ADJUST_TOP = 0 // defined by phi + ADJUST_BOTTOM = 1 // defined within block +) + +// A sparseTree is a tree of Blocks. +// It allows rapid ancestor queries, +// such as whether one block dominates another. +type sparseTree []sparseTreeNode + +// newSparseTree creates a sparseTree from a block-to-parent map (array indexed by Block.ID) +func newSparseTree(f *Func, parentOf []*Block) sparseTree { + t := make(sparseTree, f.NumBlocks()) + for _, b := range f.Blocks { + n := &t[b.ID] + if p := parentOf[b.ID]; p != nil { + n.parent = p + n.sibling = t[p.ID].child + t[p.ID].child = b + } + } + t.numberBlock(f.Entry, 1) + return t +} + +// numberBlock assigns entry and exit numbers for b and b's +// children in an in-order walk from a gappy sequence, where n +// is the first number not yet assigned or reserved. N should +// be larger than zero. For each entry and exit number, the +// values one larger and smaller are reserved to indicate +// "strictly above" and "strictly below". numberBlock returns +// the smallest number not yet assigned or reserved (i.e., the +// exit number of the last block visited, plus two, because +// last.exit+1 is a reserved value.) +// +// examples: +// +// single node tree Root, call with n=1 +// entry=2 Root exit=5; returns 7 +// +// two node tree, Root->Child, call with n=1 +// entry=2 Root exit=11; returns 13 +// entry=5 Child exit=8 +// +// three node tree, Root->(Left, Right), call with n=1 +// entry=2 Root exit=17; returns 19 +// entry=5 Left exit=8; entry=11 Right exit=14 +// +// This is the in-order sequence of assigned and reserved numbers +// for the last example: +// root left left right right root +// 1 2e 3 | 4 5e 6 | 7 8x 9 | 10 11e 12 | 13 14x 15 | 16 17x 18 + +func (t sparseTree) numberBlock(b *Block, n int32) int32 { + // reserve n for entry-1, assign n+1 to entry + n++ + t[b.ID].entry = n + // reserve n+1 for entry+1, n+2 is next free number + n += 2 + for c := t[b.ID].child; c != nil; c = t[c.ID].sibling { + n = t.numberBlock(c, n) // preserves n = next free number + } + // reserve n for exit-1, assign n+1 to exit + n++ + t[b.ID].exit = n + // reserve n+1 for exit+1, n+2 is next free number, returned. + return n + 2 +} + +// Sibling returns a sibling of x in the dominator tree (i.e., +// a node with the same immediate dominator) or nil if there +// are no remaining siblings in the arbitrary but repeatable +// order chosen. Because the Child-Sibling order is used +// to assign entry and exit numbers in the treewalk, those +// numbers are also consistent with this order (i.e., +// Sibling(x) has entry number larger than x's exit number). +func (t sparseTree) Sibling(x *Block) *Block { + return t[x.ID].sibling +} + +// Child returns a child of x in the dominator tree, or +// nil if there are none. The choice of first child is +// arbitrary but repeatable. +func (t sparseTree) Child(x *Block) *Block { + return t[x.ID].child +} + +// isAncestorEq reports whether x is an ancestor of or equal to y. +func (t sparseTree) isAncestorEq(x, y *Block) bool { + xx := &t[x.ID] + yy := &t[y.ID] + return xx.entry <= yy.entry && yy.exit <= xx.exit +} + +// isAncestor reports whether x is a strict ancestor of y. +func (t sparseTree) isAncestor(x, y *Block) bool { + xx := &t[x.ID] + yy := &t[y.ID] + return xx.entry < yy.entry && yy.exit < xx.exit +} diff --git a/src/cmd/compile/internal/ssa/stackalloc.go b/src/cmd/compile/internal/ssa/stackalloc.go new file mode 100644 index 0000000000..0e6cae0924 --- /dev/null +++ b/src/cmd/compile/internal/ssa/stackalloc.go @@ -0,0 +1,321 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// TODO: live at start of block instead? + +package ssa + +import "fmt" + +const stackDebug = false // TODO: compiler flag + +type stackAllocState struct { + f *Func + values []stackValState + live [][]ID // live[b.id] = live values at the end of block b. + interfere [][]ID // interfere[v.id] = values that interfere with v. +} + +type stackValState struct { + typ Type + spill *Value + needSlot bool +} + +// stackalloc allocates storage in the stack frame for +// all Values that did not get a register. +// Returns a map from block ID to the stack values live at the end of that block. +func stackalloc(f *Func, spillLive [][]ID) [][]ID { + if stackDebug { + fmt.Println("before stackalloc") + fmt.Println(f.String()) + } + var s stackAllocState + s.init(f, spillLive) + s.stackalloc() + return s.live +} + +func (s *stackAllocState) init(f *Func, spillLive [][]ID) { + s.f = f + + // Initialize value information. + s.values = make([]stackValState, f.NumValues()) + for _, b := range f.Blocks { + for _, v := range b.Values { + s.values[v.ID].typ = v.Type + s.values[v.ID].needSlot = !v.Type.IsMemory() && !v.Type.IsVoid() && !v.Type.IsFlags() && f.getHome(v.ID) == nil && !v.rematerializeable() + if stackDebug && s.values[v.ID].needSlot { + fmt.Printf("%s needs a stack slot\n", v) + } + if v.Op == OpStoreReg { + s.values[v.Args[0].ID].spill = v + } + } + } + + // Compute liveness info for values needing a slot. + s.computeLive(spillLive) + + // Build interference graph among values needing a slot. + s.buildInterferenceGraph() +} + +func (s *stackAllocState) stackalloc() { + f := s.f + + // Build map from values to their names, if any. + // A value may be associated with more than one name (e.g. after + // the assignment i=j). This step picks one name per value arbitrarily. + names := make([]LocalSlot, f.NumValues()) + for _, name := range f.Names { + // Note: not "range f.NamedValues" above, because + // that would be nondeterministic. + for _, v := range f.NamedValues[name] { + names[v.ID] = name + } + } + + // Allocate args to their assigned locations. + for _, v := range f.Entry.Values { + if v.Op != OpArg { + continue + } + loc := LocalSlot{v.Aux.(GCNode), v.Type, v.AuxInt} + if stackDebug { + fmt.Printf("stackalloc %s to %s\n", v, loc.Name()) + } + f.setHome(v, loc) + } + + // For each type, we keep track of all the stack slots we + // have allocated for that type. + // TODO: share slots among equivalent types. We would need to + // only share among types with the same GC signature. See the + // type.Equal calls below for where this matters. + locations := map[Type][]LocalSlot{} + + // Each time we assign a stack slot to a value v, we remember + // the slot we used via an index into locations[v.Type]. + slots := make([]int, f.NumValues()) + for i := f.NumValues() - 1; i >= 0; i-- { + slots[i] = -1 + } + + // Pick a stack slot for each value needing one. + used := make([]bool, f.NumValues()) + for _, b := range f.Blocks { + for _, v := range b.Values { + if !s.values[v.ID].needSlot { + continue + } + if v.Op == OpArg { + continue // already picked + } + + // If this is a named value, try to use the name as + // the spill location. + var name LocalSlot + if v.Op == OpStoreReg { + name = names[v.Args[0].ID] + } else { + name = names[v.ID] + } + if name.N != nil && v.Type.Equal(name.Type) { + for _, id := range s.interfere[v.ID] { + h := f.getHome(id) + if h != nil && h.(LocalSlot) == name { + // A variable can interfere with itself. + // It is rare, but but it can happen. + goto noname + } + } + if stackDebug { + fmt.Printf("stackalloc %s to %s\n", v, name.Name()) + } + f.setHome(v, name) + continue + } + + noname: + // Set of stack slots we could reuse. + locs := locations[v.Type] + // Mark all positions in locs used by interfering values. + for i := 0; i < len(locs); i++ { + used[i] = false + } + for _, xid := range s.interfere[v.ID] { + slot := slots[xid] + if slot >= 0 { + used[slot] = true + } + } + // Find an unused stack slot. + var i int + for i = 0; i < len(locs); i++ { + if !used[i] { + break + } + } + // If there is no unused stack slot, allocate a new one. + if i == len(locs) { + locs = append(locs, LocalSlot{N: f.Config.fe.Auto(v.Type), Type: v.Type, Off: 0}) + locations[v.Type] = locs + } + // Use the stack variable at that index for v. + loc := locs[i] + if stackDebug { + fmt.Printf("stackalloc %s to %s\n", v, loc.Name()) + } + f.setHome(v, loc) + slots[v.ID] = i + } + } +} + +// computeLive computes a map from block ID to a list of +// stack-slot-needing value IDs live at the end of that block. +// TODO: this could be quadratic if lots of variables are live across lots of +// basic blocks. Figure out a way to make this function (or, more precisely, the user +// of this function) require only linear size & time. +func (s *stackAllocState) computeLive(spillLive [][]ID) { + s.live = make([][]ID, s.f.NumBlocks()) + var phis []*Value + live := s.f.newSparseSet(s.f.NumValues()) + defer s.f.retSparseSet(live) + t := s.f.newSparseSet(s.f.NumValues()) + defer s.f.retSparseSet(t) + + // Instead of iterating over f.Blocks, iterate over their postordering. + // Liveness information flows backward, so starting at the end + // increases the probability that we will stabilize quickly. + po := postorder(s.f) + for { + changed := false + for _, b := range po { + // Start with known live values at the end of the block + live.clear() + live.addAll(s.live[b.ID]) + + // Propagate backwards to the start of the block + phis = phis[:0] + for i := len(b.Values) - 1; i >= 0; i-- { + v := b.Values[i] + live.remove(v.ID) + if v.Op == OpPhi { + // Save phi for later. + // Note: its args might need a stack slot even though + // the phi itself doesn't. So don't use needSlot. + if !v.Type.IsMemory() && !v.Type.IsVoid() { + phis = append(phis, v) + } + continue + } + for _, a := range v.Args { + if s.values[a.ID].needSlot { + live.add(a.ID) + } + } + } + + // for each predecessor of b, expand its list of live-at-end values + // invariant: s contains the values live at the start of b (excluding phi inputs) + for i, p := range b.Preds { + t.clear() + t.addAll(s.live[p.ID]) + t.addAll(live.contents()) + t.addAll(spillLive[p.ID]) + for _, v := range phis { + a := v.Args[i] + if s.values[a.ID].needSlot { + t.add(a.ID) + } + if spill := s.values[a.ID].spill; spill != nil { + //TODO: remove? Subsumed by SpillUse? + t.add(spill.ID) + } + } + if t.size() == len(s.live[p.ID]) { + continue + } + // grow p's live set + s.live[p.ID] = append(s.live[p.ID][:0], t.contents()...) + changed = true + } + } + + if !changed { + break + } + } + if stackDebug { + for _, b := range s.f.Blocks { + fmt.Printf("stacklive %s %v\n", b, s.live[b.ID]) + } + } +} + +func (f *Func) getHome(vid ID) Location { + if int(vid) >= len(f.RegAlloc) { + return nil + } + return f.RegAlloc[vid] +} + +func (f *Func) setHome(v *Value, loc Location) { + for v.ID >= ID(len(f.RegAlloc)) { + f.RegAlloc = append(f.RegAlloc, nil) + } + f.RegAlloc[v.ID] = loc +} + +func (s *stackAllocState) buildInterferenceGraph() { + f := s.f + s.interfere = make([][]ID, f.NumValues()) + live := f.newSparseSet(f.NumValues()) + defer f.retSparseSet(live) + for _, b := range f.Blocks { + // Propagate liveness backwards to the start of the block. + // Two values interfere if one is defined while the other is live. + live.clear() + live.addAll(s.live[b.ID]) + for i := len(b.Values) - 1; i >= 0; i-- { + v := b.Values[i] + if s.values[v.ID].needSlot { + live.remove(v.ID) + for _, id := range live.contents() { + if s.values[v.ID].typ.Equal(s.values[id].typ) { + s.interfere[v.ID] = append(s.interfere[v.ID], id) + s.interfere[id] = append(s.interfere[id], v.ID) + } + } + } + for _, a := range v.Args { + if s.values[a.ID].needSlot { + live.add(a.ID) + } + } + if v.Op == OpArg && s.values[v.ID].needSlot { + // OpArg is an input argument which is pre-spilled. + // We add back v.ID here because we want this value + // to appear live even before this point. Being live + // all the way to the start of the entry block prevents other + // values from being allocated to the same slot and clobbering + // the input value before we have a chance to load it. + live.add(v.ID) + } + } + } + if stackDebug { + for vid, i := range s.interfere { + if len(i) > 0 { + fmt.Printf("v%d interferes with", vid) + for _, x := range i { + fmt.Printf(" v%d", x) + } + fmt.Println() + } + } + } +} diff --git a/src/cmd/compile/internal/ssa/tighten.go b/src/cmd/compile/internal/ssa/tighten.go new file mode 100644 index 0000000000..ecb43c101d --- /dev/null +++ b/src/cmd/compile/internal/ssa/tighten.go @@ -0,0 +1,88 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +// tighten moves Values closer to the Blocks in which they are used. +// This can reduce the amount of register spilling required, +// if it doesn't also create more live values. +// For now, it handles only the trivial case in which a +// Value with one or fewer args is only used in a single Block, +// and not in a phi value. +// TODO: Do something smarter. +// A Value can be moved to any block that +// dominates all blocks in which it is used. +// Figure out when that will be an improvement. +func tighten(f *Func) { + // For each value, the number of blocks in which it is used. + uses := make([]int32, f.NumValues()) + + // For each value, whether that value is ever an arg to a phi value. + phi := make([]bool, f.NumValues()) + + // For each value, one block in which that value is used. + home := make([]*Block, f.NumValues()) + + changed := true + for changed { + changed = false + + // Reset uses + for i := range uses { + uses[i] = 0 + } + // No need to reset home; any relevant values will be written anew anyway. + // No need to reset phi; once used in a phi, always used in a phi. + + for _, b := range f.Blocks { + for _, v := range b.Values { + for _, w := range v.Args { + if v.Op == OpPhi { + phi[w.ID] = true + } + uses[w.ID]++ + home[w.ID] = b + } + } + if b.Control != nil { + uses[b.Control.ID]++ + home[b.Control.ID] = b + } + } + + for _, b := range f.Blocks { + for i := 0; i < len(b.Values); i++ { + v := b.Values[i] + if v.Op == OpPhi || v.Op == OpGetClosurePtr || v.Op == OpConvert || v.Op == OpArg { + // GetClosurePtr & Arg must stay in entry block. + // OpConvert must not float over call sites. + // TODO do we instead need a dependence edge of some sort for OpConvert? + // Would memory do the trick, or do we need something else that relates + // to safe point operations? + continue + } + if len(v.Args) > 0 && v.Args[len(v.Args)-1].Type.IsMemory() { + // We can't move values which have a memory arg - it might + // make two memory values live across a block boundary. + continue + } + if uses[v.ID] == 1 && !phi[v.ID] && home[v.ID] != b && len(v.Args) < 2 { + // v is used in exactly one block, and it is not b. + // Furthermore, it takes at most one input, + // so moving it will not increase the + // number of live values anywhere. + // Move v to that block. + c := home[v.ID] + c.Values = append(c.Values, v) + v.Block = c + last := len(b.Values) - 1 + b.Values[i] = b.Values[last] + b.Values[last] = nil + b.Values = b.Values[:last] + changed = true + } + } + } + } +} diff --git a/src/cmd/compile/internal/ssa/trim.go b/src/cmd/compile/internal/ssa/trim.go new file mode 100644 index 0000000000..594d2aa372 --- /dev/null +++ b/src/cmd/compile/internal/ssa/trim.go @@ -0,0 +1,37 @@ +// Copyright 2016 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +// trim removes blocks with no code in them. +// These blocks were inserted to remove critical edges. +func trim(f *Func) { + i := 0 + for _, b := range f.Blocks { + if b.Kind != BlockPlain || len(b.Values) != 0 || len(b.Preds) != 1 { + f.Blocks[i] = b + i++ + continue + } + // TODO: handle len(b.Preds)>1 case. + + // Splice b out of the graph. + pred := b.Preds[0] + succ := b.Succs[0] + for j, s := range pred.Succs { + if s == b { + pred.Succs[j] = succ + } + } + for j, p := range succ.Preds { + if p == b { + succ.Preds[j] = pred + } + } + } + for j := i; j < len(f.Blocks); j++ { + f.Blocks[j] = nil + } + f.Blocks = f.Blocks[:i] +} diff --git a/src/cmd/compile/internal/ssa/type.go b/src/cmd/compile/internal/ssa/type.go new file mode 100644 index 0000000000..a23989c82e --- /dev/null +++ b/src/cmd/compile/internal/ssa/type.go @@ -0,0 +1,131 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +// TODO: use go/types instead? + +// A type interface used to import cmd/internal/gc:Type +// Type instances are not guaranteed to be canonical. +type Type interface { + Size() int64 // return the size in bytes + Alignment() int64 + + IsBoolean() bool // is a named or unnamed boolean type + IsInteger() bool // ... ditto for the others + IsSigned() bool + IsFloat() bool + IsComplex() bool + IsPtr() bool + IsString() bool + IsSlice() bool + IsArray() bool + IsStruct() bool + IsInterface() bool + + IsMemory() bool // special ssa-package-only types + IsFlags() bool + IsVoid() bool + + Elem() Type // given []T or *T or [n]T, return T + PtrTo() Type // given T, return *T + + NumFields() int64 // # of fields of a struct + FieldType(i int64) Type // type of ith field of the struct + FieldOff(i int64) int64 // offset of ith field of the struct + + NumElem() int64 // # of elements of an array + + String() string + SimpleString() string // a coarser generic description of T, e.g. T's underlying type + Equal(Type) bool + Compare(Type) Cmp // compare types, returning one of CMPlt, CMPeq, CMPgt. +} + +// Special compiler-only types. +type CompilerType struct { + Name string + Memory bool + Flags bool + Void bool + Int128 bool +} + +func (t *CompilerType) Size() int64 { return 0 } // Size in bytes +func (t *CompilerType) Alignment() int64 { return 0 } +func (t *CompilerType) IsBoolean() bool { return false } +func (t *CompilerType) IsInteger() bool { return false } +func (t *CompilerType) IsSigned() bool { return false } +func (t *CompilerType) IsFloat() bool { return false } +func (t *CompilerType) IsComplex() bool { return false } +func (t *CompilerType) IsPtr() bool { return false } +func (t *CompilerType) IsString() bool { return false } +func (t *CompilerType) IsSlice() bool { return false } +func (t *CompilerType) IsArray() bool { return false } +func (t *CompilerType) IsStruct() bool { return false } +func (t *CompilerType) IsInterface() bool { return false } +func (t *CompilerType) IsMemory() bool { return t.Memory } +func (t *CompilerType) IsFlags() bool { return t.Flags } +func (t *CompilerType) IsVoid() bool { return t.Void } +func (t *CompilerType) String() string { return t.Name } +func (t *CompilerType) SimpleString() string { return t.Name } +func (t *CompilerType) Elem() Type { panic("not implemented") } +func (t *CompilerType) PtrTo() Type { panic("not implemented") } +func (t *CompilerType) NumFields() int64 { panic("not implemented") } +func (t *CompilerType) FieldType(i int64) Type { panic("not implemented") } +func (t *CompilerType) FieldOff(i int64) int64 { panic("not implemented") } +func (t *CompilerType) NumElem() int64 { panic("not implemented") } + +// Cmp is a comparison between values a and b. +// -1 if a < b +// 0 if a == b +// 1 if a > b +type Cmp int8 + +const ( + CMPlt = Cmp(-1) + CMPeq = Cmp(0) + CMPgt = Cmp(1) +) + +func (t *CompilerType) Compare(u Type) Cmp { + x, ok := u.(*CompilerType) + // ssa.CompilerType is smaller than any other type + if !ok { + return CMPlt + } + if t == x { + return CMPeq + } + // desire fast sorting, not pretty sorting. + if len(t.Name) == len(x.Name) { + if t.Name == x.Name { + return CMPeq + } + if t.Name < x.Name { + return CMPlt + } + return CMPgt + } + if len(t.Name) > len(x.Name) { + return CMPgt + } + return CMPlt +} + +func (t *CompilerType) Equal(u Type) bool { + x, ok := u.(*CompilerType) + if !ok { + return false + } + return x == t +} + +var ( + TypeInvalid = &CompilerType{Name: "invalid"} + TypeMem = &CompilerType{Name: "mem", Memory: true} + TypeFlags = &CompilerType{Name: "flags", Flags: true} + TypeVoid = &CompilerType{Name: "void", Void: true} + TypeInt128 = &CompilerType{Name: "int128", Int128: true} +) diff --git a/src/cmd/compile/internal/ssa/type_test.go b/src/cmd/compile/internal/ssa/type_test.go new file mode 100644 index 0000000000..26c8223c62 --- /dev/null +++ b/src/cmd/compile/internal/ssa/type_test.go @@ -0,0 +1,100 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +// Stub implementation used for testing. +type TypeImpl struct { + Size_ int64 + Align int64 + Boolean bool + Integer bool + Signed bool + Float bool + Complex bool + Ptr bool + string bool + slice bool + array bool + struct_ bool + inter bool + Elem_ Type + + Name string +} + +func (t *TypeImpl) Size() int64 { return t.Size_ } +func (t *TypeImpl) Alignment() int64 { return t.Align } +func (t *TypeImpl) IsBoolean() bool { return t.Boolean } +func (t *TypeImpl) IsInteger() bool { return t.Integer } +func (t *TypeImpl) IsSigned() bool { return t.Signed } +func (t *TypeImpl) IsFloat() bool { return t.Float } +func (t *TypeImpl) IsComplex() bool { return t.Complex } +func (t *TypeImpl) IsPtr() bool { return t.Ptr } +func (t *TypeImpl) IsString() bool { return t.string } +func (t *TypeImpl) IsSlice() bool { return t.slice } +func (t *TypeImpl) IsArray() bool { return t.array } +func (t *TypeImpl) IsStruct() bool { return t.struct_ } +func (t *TypeImpl) IsInterface() bool { return t.inter } +func (t *TypeImpl) IsMemory() bool { return false } +func (t *TypeImpl) IsFlags() bool { return false } +func (t *TypeImpl) IsVoid() bool { return false } +func (t *TypeImpl) String() string { return t.Name } +func (t *TypeImpl) SimpleString() string { return t.Name } +func (t *TypeImpl) Elem() Type { return t.Elem_ } +func (t *TypeImpl) PtrTo() Type { panic("not implemented") } +func (t *TypeImpl) NumFields() int64 { panic("not implemented") } +func (t *TypeImpl) FieldType(i int64) Type { panic("not implemented") } +func (t *TypeImpl) FieldOff(i int64) int64 { panic("not implemented") } +func (t *TypeImpl) NumElem() int64 { panic("not implemented") } + +func (t *TypeImpl) Equal(u Type) bool { + x, ok := u.(*TypeImpl) + if !ok { + return false + } + return x == t +} + +func (t *TypeImpl) Compare(u Type) Cmp { + x, ok := u.(*TypeImpl) + // ssa.CompilerType < ssa.TypeImpl < gc.Type + if !ok { + _, ok := u.(*CompilerType) + if ok { + return CMPgt + } + return CMPlt + } + if t == x { + return CMPeq + } + if t.Name < x.Name { + return CMPlt + } + if t.Name > x.Name { + return CMPgt + } + return CMPeq + +} + +var ( + // shortcuts for commonly used basic types + TypeInt8 = &TypeImpl{Size_: 1, Align: 1, Integer: true, Signed: true, Name: "int8"} + TypeInt16 = &TypeImpl{Size_: 2, Align: 2, Integer: true, Signed: true, Name: "int16"} + TypeInt32 = &TypeImpl{Size_: 4, Align: 4, Integer: true, Signed: true, Name: "int32"} + TypeInt64 = &TypeImpl{Size_: 8, Align: 8, Integer: true, Signed: true, Name: "int64"} + TypeFloat32 = &TypeImpl{Size_: 4, Align: 4, Float: true, Name: "float32"} + TypeFloat64 = &TypeImpl{Size_: 8, Align: 8, Float: true, Name: "float64"} + TypeComplex64 = &TypeImpl{Size_: 8, Align: 4, Complex: true, Name: "complex64"} + TypeComplex128 = &TypeImpl{Size_: 16, Align: 8, Complex: true, Name: "complex128"} + TypeUInt8 = &TypeImpl{Size_: 1, Align: 1, Integer: true, Name: "uint8"} + TypeUInt16 = &TypeImpl{Size_: 2, Align: 2, Integer: true, Name: "uint16"} + TypeUInt32 = &TypeImpl{Size_: 4, Align: 4, Integer: true, Name: "uint32"} + TypeUInt64 = &TypeImpl{Size_: 8, Align: 8, Integer: true, Name: "uint64"} + TypeBool = &TypeImpl{Size_: 1, Align: 1, Boolean: true, Name: "bool"} + TypeBytePtr = &TypeImpl{Size_: 8, Align: 8, Ptr: true, Name: "*byte"} + TypeInt64Ptr = &TypeImpl{Size_: 8, Align: 8, Ptr: true, Name: "*int64"} +) diff --git a/src/cmd/compile/internal/ssa/value.go b/src/cmd/compile/internal/ssa/value.go new file mode 100644 index 0000000000..cc8c9fe871 --- /dev/null +++ b/src/cmd/compile/internal/ssa/value.go @@ -0,0 +1,259 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import ( + "fmt" + "math" +) + +// A Value represents a value in the SSA representation of the program. +// The ID and Type fields must not be modified. The remainder may be modified +// if they preserve the value of the Value (e.g. changing a (mul 2 x) to an (add x x)). +type Value struct { + // A unique identifier for the value. For performance we allocate these IDs + // densely starting at 1. There is no guarantee that there won't be occasional holes, though. + ID ID + + // The operation that computes this value. See op.go. + Op Op + + // The type of this value. Normally this will be a Go type, but there + // are a few other pseudo-types, see type.go. + Type Type + + // Auxiliary info for this value. The type of this information depends on the opcode and type. + // AuxInt is used for integer values, Aux is used for other values. + AuxInt int64 + Aux interface{} + + // Arguments of this value + Args []*Value + + // Containing basic block + Block *Block + + // Source line number + Line int32 + + // Storage for the first two args + argstorage [2]*Value +} + +// Examples: +// Opcode aux args +// OpAdd nil 2 +// OpConst string 0 string constant +// OpConst int64 0 int64 constant +// OpAddcq int64 1 amd64 op: v = arg[0] + constant + +// short form print. Just v#. +func (v *Value) String() string { + if v == nil { + return "nil" // should never happen, but not panicking helps with debugging + } + return fmt.Sprintf("v%d", v.ID) +} + +func (v *Value) AuxInt8() int8 { + if opcodeTable[v.Op].auxType != auxInt8 { + v.Fatalf("op %s doesn't have an int8 aux field", v.Op) + } + return int8(v.AuxInt) +} + +func (v *Value) AuxInt16() int16 { + if opcodeTable[v.Op].auxType != auxInt16 { + v.Fatalf("op %s doesn't have an int16 aux field", v.Op) + } + return int16(v.AuxInt) +} + +func (v *Value) AuxInt32() int32 { + if opcodeTable[v.Op].auxType != auxInt32 { + v.Fatalf("op %s doesn't have an int32 aux field", v.Op) + } + return int32(v.AuxInt) +} + +// AuxInt2Int64 is used to sign extend the lower bits of AuxInt according to +// the size of AuxInt specified in the opcode table. +func (v *Value) AuxInt2Int64() int64 { + switch opcodeTable[v.Op].auxType { + case auxInt64: + return v.AuxInt + case auxInt32: + return int64(int32(v.AuxInt)) + case auxInt16: + return int64(int16(v.AuxInt)) + case auxInt8: + return int64(int8(v.AuxInt)) + default: + v.Fatalf("op %s doesn't have an aux int field", v.Op) + return -1 + } +} + +func (v *Value) AuxFloat() float64 { + if opcodeTable[v.Op].auxType != auxFloat { + v.Fatalf("op %s doesn't have a float aux field", v.Op) + } + return math.Float64frombits(uint64(v.AuxInt)) +} +func (v *Value) AuxValAndOff() ValAndOff { + if opcodeTable[v.Op].auxType != auxSymValAndOff { + v.Fatalf("op %s doesn't have a ValAndOff aux field", v.Op) + } + return ValAndOff(v.AuxInt) +} + +// long form print. v# = opcode <type> [aux] args [: reg] +func (v *Value) LongString() string { + s := fmt.Sprintf("v%d = %s", v.ID, v.Op.String()) + s += " <" + v.Type.String() + ">" + switch opcodeTable[v.Op].auxType { + case auxBool: + if v.AuxInt == 0 { + s += " [false]" + } else { + s += " [true]" + } + case auxInt8: + s += fmt.Sprintf(" [%d]", v.AuxInt8()) + case auxInt16: + s += fmt.Sprintf(" [%d]", v.AuxInt16()) + case auxInt32: + s += fmt.Sprintf(" [%d]", v.AuxInt32()) + case auxInt64: + s += fmt.Sprintf(" [%d]", v.AuxInt) + case auxFloat: + s += fmt.Sprintf(" [%g]", v.AuxFloat()) + case auxString: + s += fmt.Sprintf(" {%s}", v.Aux) + case auxSym: + if v.Aux != nil { + s += fmt.Sprintf(" {%s}", v.Aux) + } + case auxSymOff: + if v.Aux != nil { + s += fmt.Sprintf(" {%s}", v.Aux) + } + s += fmt.Sprintf(" [%d]", v.AuxInt) + case auxSymValAndOff: + if v.Aux != nil { + s += fmt.Sprintf(" {%s}", v.Aux) + } + s += fmt.Sprintf(" [%s]", v.AuxValAndOff()) + } + for _, a := range v.Args { + s += fmt.Sprintf(" %v", a) + } + r := v.Block.Func.RegAlloc + if int(v.ID) < len(r) && r[v.ID] != nil { + s += " : " + r[v.ID].Name() + } + return s +} + +func (v *Value) AddArg(w *Value) { + if v.Args == nil { + v.resetArgs() // use argstorage + } + v.Args = append(v.Args, w) +} +func (v *Value) AddArgs(a ...*Value) { + if v.Args == nil { + v.resetArgs() // use argstorage + } + v.Args = append(v.Args, a...) +} +func (v *Value) SetArg(i int, w *Value) { + v.Args[i] = w +} +func (v *Value) RemoveArg(i int) { + copy(v.Args[i:], v.Args[i+1:]) + v.Args[len(v.Args)-1] = nil // aid GC + v.Args = v.Args[:len(v.Args)-1] +} +func (v *Value) SetArgs1(a *Value) { + v.resetArgs() + v.AddArg(a) +} +func (v *Value) SetArgs2(a *Value, b *Value) { + v.resetArgs() + v.AddArg(a) + v.AddArg(b) +} + +func (v *Value) resetArgs() { + v.argstorage[0] = nil + v.argstorage[1] = nil + v.Args = v.argstorage[:0] +} + +func (v *Value) reset(op Op) { + v.Op = op + v.resetArgs() + v.AuxInt = 0 + v.Aux = nil +} + +// copyInto makes a new value identical to v and adds it to the end of b. +func (v *Value) copyInto(b *Block) *Value { + c := b.NewValue0(v.Line, v.Op, v.Type) + c.Aux = v.Aux + c.AuxInt = v.AuxInt + c.AddArgs(v.Args...) + for _, a := range v.Args { + if a.Type.IsMemory() { + v.Fatalf("can't move a value with a memory arg %s", v.LongString()) + } + } + return c +} + +func (v *Value) Logf(msg string, args ...interface{}) { v.Block.Logf(msg, args...) } +func (v *Value) Log() bool { return v.Block.Log() } +func (v *Value) Fatalf(msg string, args ...interface{}) { + v.Block.Func.Config.Fatalf(v.Line, msg, args...) +} +func (v *Value) Unimplementedf(msg string, args ...interface{}) { + v.Block.Func.Config.Unimplementedf(v.Line, msg, args...) +} + +// ExternSymbol is an aux value that encodes a variable's +// constant offset from the static base pointer. +type ExternSymbol struct { + Typ Type // Go type + Sym fmt.Stringer // A *gc.Sym referring to a global variable + // Note: the offset for an external symbol is not + // calculated until link time. +} + +// ArgSymbol is an aux value that encodes an argument or result +// variable's constant offset from FP (FP = SP + framesize). +type ArgSymbol struct { + Typ Type // Go type + Node GCNode // A *gc.Node referring to the argument/result variable. +} + +// AutoSymbol is an aux value that encodes a local variable's +// constant offset from SP. +type AutoSymbol struct { + Typ Type // Go type + Node GCNode // A *gc.Node referring to a local (auto) variable. +} + +func (s *ExternSymbol) String() string { + return s.Sym.String() +} + +func (s *ArgSymbol) String() string { + return s.Node.String() +} + +func (s *AutoSymbol) String() string { + return s.Node.String() +} diff --git a/src/cmd/compile/internal/ssa/zcse.go b/src/cmd/compile/internal/ssa/zcse.go new file mode 100644 index 0000000000..664fbae9f0 --- /dev/null +++ b/src/cmd/compile/internal/ssa/zcse.go @@ -0,0 +1,90 @@ +// Copyright 2016 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +// zcse does an initial pass of common-subexpression elimination on the +// function for values with zero arguments to allow the more expensive cse +// to begin with a reduced number of values. Values are just relinked, +// nothing is deleted. A subsequent deadcode pass is required to actually +// remove duplicate expressions. +func zcse(f *Func) { + vals := make(map[vkey]*Value) + + for _, b := range f.Blocks { + for i := 0; i < len(b.Values); { + v := b.Values[i] + next := true + if opcodeTable[v.Op].argLen == 0 { + key := vkey{v.Op, keyFor(v), v.Aux, typeStr(v)} + if vals[key] == nil { + vals[key] = v + if b != f.Entry { + // Move v to the entry block so it will dominate every block + // where we might use it. This prevents the need for any dominator + // calculations in this pass. + v.Block = f.Entry + f.Entry.Values = append(f.Entry.Values, v) + last := len(b.Values) - 1 + b.Values[i] = b.Values[last] + b.Values[last] = nil + b.Values = b.Values[:last] + + // process b.Values[i] again + next = false + } + } + } + if next { + i++ + } + } + } + + for _, b := range f.Blocks { + for _, v := range b.Values { + for i, a := range v.Args { + if opcodeTable[a.Op].argLen == 0 { + key := vkey{a.Op, keyFor(a), a.Aux, typeStr(a)} + if rv, ok := vals[key]; ok { + v.Args[i] = rv + } + } + } + } + } +} + +// vkey is a type used to uniquely identify a zero arg value. +type vkey struct { + op Op + ai int64 // aux int + ax interface{} // aux + t string // type +} + +// typeStr returns a string version of the type of v. +func typeStr(v *Value) string { + if v.Type == nil { + return "" + } + return v.Type.String() +} + +// keyFor returns the AuxInt portion of a key structure uniquely identifying a +// zero arg value for the supported ops. +func keyFor(v *Value) int64 { + switch v.Op { + case OpConst64, OpConst64F, OpConst32F: + return v.AuxInt + case OpConst32: + return int64(int32(v.AuxInt)) + case OpConst16: + return int64(int16(v.AuxInt)) + case OpConst8, OpConstBool: + return int64(int8(v.AuxInt)) + default: + return v.AuxInt + } +} |