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-rw-r--r--src/cmd/asm/internal/arch/arm64.go31
-rw-r--r--src/cmd/asm/internal/asm/parse.go19
-rw-r--r--src/cmd/asm/internal/asm/testdata/arm64sveenc.s19
-rw-r--r--src/cmd/asm/internal/asm/testdata/arm64sveerror.s19
4 files changed, 81 insertions, 7 deletions
diff --git a/src/cmd/asm/internal/arch/arm64.go b/src/cmd/asm/internal/arch/arm64.go
index 5d5eee6627..24020a336b 100644
--- a/src/cmd/asm/internal/arch/arm64.go
+++ b/src/cmd/asm/internal/arch/arm64.go
@@ -209,9 +209,17 @@ func ARM64RegisterShift(reg, op, count int16) (int64, error) {
// ARM64RegisterArrangement constructs an ARM64 vector register arrangement.
func ARM64RegisterArrangement(reg int16, name, arng string) (int64, error) {
- var curQ, curSize uint16
- if name[0] != 'V' {
- return 0, errors.New("expect V0 through V31; found: " + name)
+ var curQ, curSize, prefix uint16
+ if name[0] != 'V' && name[0] != 'Z' && name[0] != 'P' {
+ return 0, errors.New("expect V0-V31, Z0-Z31, or P0-P15; found: " + name)
+ }
+ switch name[0] {
+ case 'V':
+ prefix = 0
+ case 'Z':
+ prefix = 1
+ case 'P':
+ prefix = 2
}
if reg < 0 {
return 0, errors.New("invalid register number: " + name)
@@ -241,8 +249,23 @@ func ARM64RegisterArrangement(reg int16, name, arng string) (int64, error) {
case "D2":
curSize = 3
curQ = 1
+ case "B":
+ curSize = 1
+ curQ = 2
+ case "H":
+ curSize = 2
+ curQ = 2
+ case "S":
+ curSize = 3
+ curQ = 2
+ case "D":
+ curSize = 1
+ curQ = 3
+ case "Q":
+ curSize = 2
+ curQ = 3
default:
return 0, errors.New("invalid arrangement in ARM64 register list")
}
- return (int64(curQ) & 1 << 30) | (int64(curSize&3) << 10), nil
+ return (int64(prefix) << 32) | (int64(curQ) & 3 << 30) | (int64(curSize&3) << 10), nil
}
diff --git a/src/cmd/asm/internal/asm/parse.go b/src/cmd/asm/internal/asm/parse.go
index 0990bc0b64..bf3bc033bc 100644
--- a/src/cmd/asm/internal/asm/parse.go
+++ b/src/cmd/asm/internal/asm/parse.go
@@ -1117,13 +1117,26 @@ ListLoop:
}
switch p.arch.Family {
case sys.ARM64:
- // Vn.T
+ // Vn.T, Zn.T, Pn.T
name := tok.String()
r, ok := p.registerReference(name)
if !ok {
p.errorf("invalid register: %s", name)
}
- reg := r - p.arch.Register["V0"]
+ var registerBase int16
+ registerCntMask := 31
+ switch name[0] {
+ case 'V':
+ registerBase = p.arch.Register["V0"]
+ case 'Z':
+ registerBase = p.arch.Register["Z0"]
+ case 'P':
+ registerBase = p.arch.Register["P0"]
+ registerCntMask = 15
+ default:
+ p.errorf("invalid register in register list: %s", name)
+ }
+ reg := r - registerBase
p.get('.')
tok := p.next()
ext := tok.String()
@@ -1142,7 +1155,7 @@ ListLoop:
p.errorf("incontiguous register in ARM64 register list: %s", name)
}
regCnt++
- nextReg = (nextReg + 1) % 32
+ nextReg = (nextReg + 1) & registerCntMask
case sys.ARM:
// Parse the upper and lower bounds.
lo := p.registerNumber(tok.String())
diff --git a/src/cmd/asm/internal/asm/testdata/arm64sveenc.s b/src/cmd/asm/internal/asm/testdata/arm64sveenc.s
index 369c047dfa..4a50cac41d 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64sveenc.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64sveenc.s
@@ -918,4 +918,23 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZUSHLLT $5, Z22.S, Z10.D // caae4545
ZUSRA $6, Z7.D, Z23.D // f7e4da45
ZXAR $6, Z23.B, Z21.B, Z21.B // f5362a04
+ PPEXT PN11[1], [P13.S, P14.S] // 7d75a025
+ PWHILEGE R2, R10, [P10.H, P11.H] // 5a516225
+ PWHILEGT R2, R10, [P10.H, P11.H] // 5b516225
+ PWHILEHI R2, R10, [P10.H, P11.H] // 5b596225
+ PWHILEHS R2, R10, [P10.H, P11.H] // 5a596225
+ PWHILELE R2, R10, [P10.H, P11.H] // 5b556225
+ PWHILELO R2, R10, [P10.H, P11.H] // 5a5d6225
+ PWHILELS R2, R10, [P10.H, P11.H] // 5b5d6225
+ PWHILELT R2, R10, [P10.H, P11.H] // 5a556225
+ ZEXT $6, [Z7.B, Z8.B], Z6.B // e6186005
+ ZLUTI2 Z6[3], [Z23.B], Z13.B // edb2e645
+ ZLUTI2 Z6[3], [Z23.H], Z13.H // edba6645
+ ZLUTI4 Z22[1], [Z2.B], Z10.B // 4aa4f645
+ ZLUTI4 Z6[3], [Z23.H, Z24.H], Z13.H // edb6e645
+ ZLUTI4 Z6[3], [Z23.H], Z13.H // edbee645
+ // TODO: LUTI6
+ // TODO: LUTI6
+ ZSPLICE [Z7.D, Z8.D], P4, Z13.D // ed90ed05
+ ZTBLQ Z7.D, [Z23.D], Z13.D // edfac744
RET
diff --git a/src/cmd/asm/internal/asm/testdata/arm64sveerror.s b/src/cmd/asm/internal/asm/testdata/arm64sveerror.s
index ade1c64ddc..0a7069ae69 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64sveerror.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64sveerror.s
@@ -917,4 +917,23 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZUSHLLT $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE"
ZUSRA $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE"
ZXAR $1, Z27.Q, Z25.Q, Z6.H // ERROR "illegal combination from SVE"
+ PPEXT PN6[3], [P5.D, P6.D] // ERROR "illegal combination from SVE"
+ PWHILEGE RSP, R27, [P13.S, P14.S] // ERROR "illegal combination from SVE"
+ PWHILEGT RSP, R27, [P13.S, P14.S] // ERROR "illegal combination from SVE"
+ PWHILEHI RSP, R27, [P13.S, P14.S] // ERROR "illegal combination from SVE"
+ PWHILEHS RSP, R27, [P13.S, P14.S] // ERROR "illegal combination from SVE"
+ PWHILELE RSP, R27, [P13.S, P14.S] // ERROR "illegal combination from SVE"
+ PWHILELO RSP, R27, [P13.S, P14.S] // ERROR "illegal combination from SVE"
+ PWHILELS RSP, R27, [P13.S, P14.S] // ERROR "illegal combination from SVE"
+ PWHILELT RSP, R27, [P13.S, P14.S] // ERROR "illegal combination from SVE"
+ ZEXT $1, [Z27.Q, Z28.Q], Z25.Q // ERROR "illegal combination from SVE"
+ ZLUTI2 Z27[1], [Z26.S], Z11.B // ERROR "illegal combination from SVE"
+ ZLUTI2 Z27[1], [Z26.S], Z11.B // ERROR "illegal combination from SVE"
+ ZLUTI4 Z27[1], [Z26.S], Z11.B // ERROR "illegal combination from SVE"
+ ZLUTI4 Z27[1], [Z26.S, Z27.S], Z11.B // ERROR "illegal combination from SVE"
+ ZLUTI4 Z27[1], [Z26.S], Z11.B // ERROR "illegal combination from SVE"
+ // TODO: LUTI6
+ // TODO: LUTI6
+ ZSPLICE [Z1.S, Z2.S], P13.Z, Z11.B // ERROR "illegal combination from SVE"
+ ZTBLQ Z1.S, [Z26.S], Z11.B // ERROR "illegal combination from SVE"
RET
generated by cgit v1.3 (git 2.53.0) at 2026-04-15 06:27:05 +0000