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-rw-r--r--src/cmd/asm/internal/arch/arm64.go31
-rw-r--r--src/cmd/asm/internal/asm/parse.go19
-rw-r--r--src/cmd/asm/internal/asm/testdata/arm64sveenc.s19
-rw-r--r--src/cmd/asm/internal/asm/testdata/arm64sveerror.s19
-rw-r--r--src/cmd/internal/obj/arm64/anames_gen.go4
-rw-r--r--src/cmd/internal/obj/arm64/encoding_gen.go161
-rw-r--r--src/cmd/internal/obj/arm64/goops_gen.go4
-rw-r--r--src/cmd/internal/obj/arm64/inst.go124
-rw-r--r--src/cmd/internal/obj/arm64/inst_gen.go465
-rw-r--r--src/cmd/internal/obj/arm64/list7.go33
10 files changed, 788 insertions, 91 deletions
diff --git a/src/cmd/asm/internal/arch/arm64.go b/src/cmd/asm/internal/arch/arm64.go
index 5d5eee6627..24020a336b 100644
--- a/src/cmd/asm/internal/arch/arm64.go
+++ b/src/cmd/asm/internal/arch/arm64.go
@@ -209,9 +209,17 @@ func ARM64RegisterShift(reg, op, count int16) (int64, error) {
// ARM64RegisterArrangement constructs an ARM64 vector register arrangement.
func ARM64RegisterArrangement(reg int16, name, arng string) (int64, error) {
- var curQ, curSize uint16
- if name[0] != 'V' {
- return 0, errors.New("expect V0 through V31; found: " + name)
+ var curQ, curSize, prefix uint16
+ if name[0] != 'V' && name[0] != 'Z' && name[0] != 'P' {
+ return 0, errors.New("expect V0-V31, Z0-Z31, or P0-P15; found: " + name)
+ }
+ switch name[0] {
+ case 'V':
+ prefix = 0
+ case 'Z':
+ prefix = 1
+ case 'P':
+ prefix = 2
}
if reg < 0 {
return 0, errors.New("invalid register number: " + name)
@@ -241,8 +249,23 @@ func ARM64RegisterArrangement(reg int16, name, arng string) (int64, error) {
case "D2":
curSize = 3
curQ = 1
+ case "B":
+ curSize = 1
+ curQ = 2
+ case "H":
+ curSize = 2
+ curQ = 2
+ case "S":
+ curSize = 3
+ curQ = 2
+ case "D":
+ curSize = 1
+ curQ = 3
+ case "Q":
+ curSize = 2
+ curQ = 3
default:
return 0, errors.New("invalid arrangement in ARM64 register list")
}
- return (int64(curQ) & 1 << 30) | (int64(curSize&3) << 10), nil
+ return (int64(prefix) << 32) | (int64(curQ) & 3 << 30) | (int64(curSize&3) << 10), nil
}
diff --git a/src/cmd/asm/internal/asm/parse.go b/src/cmd/asm/internal/asm/parse.go
index 0990bc0b64..bf3bc033bc 100644
--- a/src/cmd/asm/internal/asm/parse.go
+++ b/src/cmd/asm/internal/asm/parse.go
@@ -1117,13 +1117,26 @@ ListLoop:
}
switch p.arch.Family {
case sys.ARM64:
- // Vn.T
+ // Vn.T, Zn.T, Pn.T
name := tok.String()
r, ok := p.registerReference(name)
if !ok {
p.errorf("invalid register: %s", name)
}
- reg := r - p.arch.Register["V0"]
+ var registerBase int16
+ registerCntMask := 31
+ switch name[0] {
+ case 'V':
+ registerBase = p.arch.Register["V0"]
+ case 'Z':
+ registerBase = p.arch.Register["Z0"]
+ case 'P':
+ registerBase = p.arch.Register["P0"]
+ registerCntMask = 15
+ default:
+ p.errorf("invalid register in register list: %s", name)
+ }
+ reg := r - registerBase
p.get('.')
tok := p.next()
ext := tok.String()
@@ -1142,7 +1155,7 @@ ListLoop:
p.errorf("incontiguous register in ARM64 register list: %s", name)
}
regCnt++
- nextReg = (nextReg + 1) % 32
+ nextReg = (nextReg + 1) & registerCntMask
case sys.ARM:
// Parse the upper and lower bounds.
lo := p.registerNumber(tok.String())
diff --git a/src/cmd/asm/internal/asm/testdata/arm64sveenc.s b/src/cmd/asm/internal/asm/testdata/arm64sveenc.s
index 369c047dfa..4a50cac41d 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64sveenc.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64sveenc.s
@@ -918,4 +918,23 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZUSHLLT $5, Z22.S, Z10.D // caae4545
ZUSRA $6, Z7.D, Z23.D // f7e4da45
ZXAR $6, Z23.B, Z21.B, Z21.B // f5362a04
+ PPEXT PN11[1], [P13.S, P14.S] // 7d75a025
+ PWHILEGE R2, R10, [P10.H, P11.H] // 5a516225
+ PWHILEGT R2, R10, [P10.H, P11.H] // 5b516225
+ PWHILEHI R2, R10, [P10.H, P11.H] // 5b596225
+ PWHILEHS R2, R10, [P10.H, P11.H] // 5a596225
+ PWHILELE R2, R10, [P10.H, P11.H] // 5b556225
+ PWHILELO R2, R10, [P10.H, P11.H] // 5a5d6225
+ PWHILELS R2, R10, [P10.H, P11.H] // 5b5d6225
+ PWHILELT R2, R10, [P10.H, P11.H] // 5a556225
+ ZEXT $6, [Z7.B, Z8.B], Z6.B // e6186005
+ ZLUTI2 Z6[3], [Z23.B], Z13.B // edb2e645
+ ZLUTI2 Z6[3], [Z23.H], Z13.H // edba6645
+ ZLUTI4 Z22[1], [Z2.B], Z10.B // 4aa4f645
+ ZLUTI4 Z6[3], [Z23.H, Z24.H], Z13.H // edb6e645
+ ZLUTI4 Z6[3], [Z23.H], Z13.H // edbee645
+ // TODO: LUTI6
+ // TODO: LUTI6
+ ZSPLICE [Z7.D, Z8.D], P4, Z13.D // ed90ed05
+ ZTBLQ Z7.D, [Z23.D], Z13.D // edfac744
RET
diff --git a/src/cmd/asm/internal/asm/testdata/arm64sveerror.s b/src/cmd/asm/internal/asm/testdata/arm64sveerror.s
index ade1c64ddc..0a7069ae69 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64sveerror.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64sveerror.s
@@ -917,4 +917,23 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZUSHLLT $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE"
ZUSRA $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE"
ZXAR $1, Z27.Q, Z25.Q, Z6.H // ERROR "illegal combination from SVE"
+ PPEXT PN6[3], [P5.D, P6.D] // ERROR "illegal combination from SVE"
+ PWHILEGE RSP, R27, [P13.S, P14.S] // ERROR "illegal combination from SVE"
+ PWHILEGT RSP, R27, [P13.S, P14.S] // ERROR "illegal combination from SVE"
+ PWHILEHI RSP, R27, [P13.S, P14.S] // ERROR "illegal combination from SVE"
+ PWHILEHS RSP, R27, [P13.S, P14.S] // ERROR "illegal combination from SVE"
+ PWHILELE RSP, R27, [P13.S, P14.S] // ERROR "illegal combination from SVE"
+ PWHILELO RSP, R27, [P13.S, P14.S] // ERROR "illegal combination from SVE"
+ PWHILELS RSP, R27, [P13.S, P14.S] // ERROR "illegal combination from SVE"
+ PWHILELT RSP, R27, [P13.S, P14.S] // ERROR "illegal combination from SVE"
+ ZEXT $1, [Z27.Q, Z28.Q], Z25.Q // ERROR "illegal combination from SVE"
+ ZLUTI2 Z27[1], [Z26.S], Z11.B // ERROR "illegal combination from SVE"
+ ZLUTI2 Z27[1], [Z26.S], Z11.B // ERROR "illegal combination from SVE"
+ ZLUTI4 Z27[1], [Z26.S], Z11.B // ERROR "illegal combination from SVE"
+ ZLUTI4 Z27[1], [Z26.S, Z27.S], Z11.B // ERROR "illegal combination from SVE"
+ ZLUTI4 Z27[1], [Z26.S], Z11.B // ERROR "illegal combination from SVE"
+ // TODO: LUTI6
+ // TODO: LUTI6
+ ZSPLICE [Z1.S, Z2.S], P13.Z, Z11.B // ERROR "illegal combination from SVE"
+ ZTBLQ Z1.S, [Z26.S], Z11.B // ERROR "illegal combination from SVE"
RET
diff --git a/src/cmd/internal/obj/arm64/anames_gen.go b/src/cmd/internal/obj/arm64/anames_gen.go
index 9d15f9f801..0bb768900d 100644
--- a/src/cmd/internal/obj/arm64/anames_gen.go
+++ b/src/cmd/internal/obj/arm64/anames_gen.go
@@ -331,6 +331,9 @@ var sveAnames = []string{
"ZLSLR",
"ZLSR",
"ZLSRR",
+ "ZLUTI2",
+ "ZLUTI4",
+ "ZLUTI6",
"ZMAD",
"ZMADPT",
"ZMATCH",
@@ -487,6 +490,7 @@ var sveAnames = []string{
"ZSXTB",
"ZSXTH",
"ZSXTW",
+ "ZTBLQ",
"ZTBX",
"ZTBXQ",
"ZTRN1",
diff --git a/src/cmd/internal/obj/arm64/encoding_gen.go b/src/cmd/internal/obj/arm64/encoding_gen.go
index da5e6fea67..2743a2d7cf 100644
--- a/src/cmd/internal/obj/arm64/encoding_gen.go
+++ b/src/cmd/internal/obj/arm64/encoding_gen.go
@@ -352,6 +352,17 @@ func encodeSzByteHalfword(v uint32) (uint32, bool) {
return 0, false
}
+// encodeI22224 is the implementation of the following encoding logic:
+// For the "Byte" variant: is the vector segment index, in the range 0 to 3, encoded in the "i2" field.
+// bit range mappings:
+// i2: [22:24)
+func encodeI22224(v uint32) (uint32, bool) {
+ if v > 3 {
+ return 0, false
+ }
+ return v << 22, true
+}
+
// encodeSizeByteMergeZero is the implementation of the following encoding logic:
// For the "Byte, merging" and "Byte, zeroing" variants: is the size specifier,
// size <T>
@@ -373,6 +384,17 @@ func encodeSizeByteMergeZero(v uint32) (uint32, bool) {
return 0, false
}
+// encodeI12324B is the implementation of the following encoding logic:
+// For the "Byte, single register table" variant: is the vector segment index, in the range 0 to 1, encoded in the "i1" field.
+// bit range mappings:
+// i1: [23:24)
+func encodeI12324B(v uint32) (uint32, bool) {
+ if v > 1 {
+ return 0, false
+ }
+ return v << 23, true
+}
+
// encodeI1_2021_DoublePrecision is the implementation of the following encoding logic:
// For the "Double-precision" variant: is the immediate index, in the range 0 to 1, encoded in the "i1" field.
// bit range mappings:
@@ -474,6 +496,18 @@ func encodeI1_1718_Halfword(v uint32) (uint32, bool) {
return v << 17, true
}
+// encodeI3224I31213 is the implementation of the following encoding logic:
+// For the "Halfword" variant: is the vector segment index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
+// bit range mappings:
+// i3h: [22:24)
+// i3l: [12:13)
+func encodeI3224I31213(v uint32) (uint32, bool) {
+ if v > 7 {
+ return 0, false
+ }
+ return (v&1)<<12 | (v>>1)<<22, true
+}
+
// encodeSize0HalfwordMergeZero is the implementation of the following encoding logic:
// For the "Halfword, merging" and "Halfword, zeroing" variants: is the size specifier,
// size[0] <T>
@@ -491,6 +525,17 @@ func encodeSize0HalfwordMergeZero(v uint32) (uint32, bool) {
return 0, false
}
+// encodeI22224HW is the implementation of the following encoding logic:
+// For the "Halfword, single register table" and "Halfword, two register table" variants: is the vector segment index, in the range 0 to 3, encoded in the "i2" field.
+// bit range mappings:
+// i2: [22:24)
+func encodeI22224HW(v uint32) (uint32, bool) {
+ if v > 3 {
+ return 0, false
+ }
+ return v << 22, true
+}
+
// encodeImm7Unsigned_1421 is the implementation of the following encoding logic:
// For the "Higher or same", "Higher", "Lower or same", and "Lower" variants: is the unsigned immediate operand, in the range 0 to 127, encoded in the "imm7" field.
// bit range mappings:
@@ -1098,6 +1143,36 @@ func encodeZd(v uint32) (uint32, bool) {
return v, true
}
+// encodePd14 is the implementation of the following encoding logic:
+// Is the name of the first destination scalable predicate register, encoded as "Pd" times 2.
+// bit range mappings:
+// Pd: [1:4)
+func encodePd14(v uint32) (uint32, bool) {
+ if v > 14 {
+ return 0, false
+ }
+ if v&1 != 0 {
+ return 0, false
+ }
+ return v, true
+}
+
+// encodePd04 is the implementation of the following encoding logic:
+// Is the name of the first destination scalable predicate register, encoded in the "Pd" field.
+// bit range mappings:
+// Pd: [0:4)
+func encodePd04(v uint32) (uint32, bool) {
+ return v, true
+}
+
+// encodeZn510MultiSrc1 is the implementation of the following encoding logic:
+// Is the name of the first scalable vector register of the source multi-vector group, encoded in the "Zn" field.
+// bit range mappings:
+// Zn: [5:10)
+func encodeZn510MultiSrc1(v uint32) (uint32, bool) {
+ return v << 5, true
+}
+
// encodePdnDest is the implementation of the following encoding logic:
// Is the name of the first source and destination scalable predicate register, encoded in the "Pdn" field.
// bit range mappings:
@@ -1142,6 +1217,14 @@ func encodeZn510(v uint32) (uint32, bool) {
return v << 5, true
}
+// encodeZn510Table1 is the implementation of the following encoding logic:
+// Is the name of the first table vector register, encoded as "Zn".
+// bit range mappings:
+// Zn: [5:10)
+func encodeZn510Table1(v uint32) (uint32, bool) {
+ return v << 5, true
+}
+
// encodePg1013 is the implementation of the following encoding logic:
// Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
// bit range mappings:
@@ -1177,6 +1260,34 @@ func encodePg59(v uint32) (uint32, bool) {
return v << 5, true
}
+// encodePd14Plus1 is the implementation of the following encoding logic:
+// Is the name of the second destination scalable predicate register, encoded as "Pd" times 2 plus 1.
+// bit range mappings:
+// Pd: [1:4)
+func encodePd14Plus1(v uint32) (uint32, bool) {
+ if v&1 == 0 {
+ return 0, false
+ }
+ return v - 1, true
+}
+
+// encodePd04Plus1 is the implementation of the following encoding logic:
+// Is the name of the second destination scalable predicate register, encoded in the "Pd" field.
+// bit range mappings:
+// Pd: [0:4)
+func encodePd04Plus1(v uint32) (uint32, bool) {
+ // This "second destination" incurs Pd + 1 == v
+ return v - 1, true
+}
+
+// encodeZn510MultiSrc2 is the implementation of the following encoding logic:
+// Is the name of the second scalable vector register of the source multi-vector group, encoded in the "Zn" field.
+// bit range mappings:
+// Zn: [5:10)
+func encodeZn510MultiSrc2(v uint32) (uint32, bool) {
+ return (v - 1) << 5, true
+}
+
// encodePdmDest is the implementation of the following encoding logic:
// Is the name of the second source and destination scalable predicate register, encoded in the "Pdm" field.
// bit range mappings:
@@ -1212,11 +1323,11 @@ func encodeZm_1619_Range0_7V2(v uint32) (uint32, bool) {
return 0, false
}
-// encodeZm1621 is the implementation of the following encoding logic:
+// encodeZm1621V2 is the implementation of the following encoding logic:
// Is the name of the second source scalable vector register, encoded in the "Zm" field.
// bit range mappings:
// Zm: [16:21)
-func encodeZm1621(v uint32) (uint32, bool) {
+func encodeZm1621V2(v uint32) (uint32, bool) {
return v << 16, true
}
@@ -1228,6 +1339,14 @@ func encodeZm510V1(v uint32) (uint32, bool) {
return (v & 31) << 5, true
}
+// encodeZn510Table2 is the implementation of the following encoding logic:
+// Is the name of the second table vector register, encoded as "Zn" plus 1 modulo 32.
+// bit range mappings:
+// Zn: [5:10)
+func encodeZn510Table2(v uint32) (uint32, bool) {
+ return ((v - 1) & 0x1f) << 5, true
+}
+
// encodePdnSrcDst is the implementation of the following encoding logic:
// Is the name of the source and destination scalable predicate register, encoded in the "Pdn" field.
// bit range mappings:
@@ -1260,6 +1379,14 @@ func encodePn59v2(v uint32) (uint32, bool) {
return v << 5, true
}
+// encodeZm1621V1 is the implementation of the following encoding logic:
+// Is the name of the source scalable vector register, encoded in the "Zm" field.
+// bit range mappings:
+// Zm: [16:21)
+func encodeZm1621V1(v uint32) (uint32, bool) {
+ return v << 16, true
+}
+
// encodeZm510V2 is the implementation of the following encoding logic:
// Is the name of the source scalable vector register, encoded in the "Zm" field.
// bit range mappings:
@@ -1276,6 +1403,14 @@ func encodeZn510Src(v uint32) (uint32, bool) {
return (v & 31) << 5, true
}
+// encodeZn510Table3 is the implementation of the following encoding logic:
+// Is the name of the table vector register, encoded in the "Zn" field.
+// bit range mappings:
+// Zn: [5:10)
+func encodeZn510Table3(v uint32) (uint32, bool) {
+ return v << 5, true
+}
+
// encodeZda3RdSrcDst is the implementation of the following encoding logic:
// Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.
// bit range mappings:
@@ -1434,6 +1569,17 @@ func encodeVdn05(v uint32) (uint32, bool) {
return v & 31, true
}
+// encodeI189 is the implementation of the following encoding logic:
+// Is the portion index, in the range 0 to 1, encoded in the "i1" field.
+// bit range mappings:
+// i1: [8:9)
+func encodeI189(v uint32) (uint32, bool) {
+ if v > 1 {
+ return 0, false
+ }
+ return v << 8, true
+}
+
// encodeImm2_810 is the implementation of the following encoding logic:
// Is the portion index, in the range 0 to 3, encoded in the "imm2" field.
// bit range mappings:
@@ -2185,6 +2331,17 @@ func encodeImm3Unsigned_1619(v uint32) (uint32, bool) {
return 0, false
}
+// encodeI12324 is the implementation of the following encoding logic:
+// Is the vector segment index, in the range 0 to 1, encoded in the "i1" field.
+// bit range mappings:
+// i1: [23:24)
+func encodeI12324(v uint32) (uint32, bool) {
+ if v > 1 {
+ return 0, false
+ }
+ return v << 23, true
+}
+
// encodeNoop is the implementation of the following encoding logic:
// No-op check, returns true
func encodeNoop(v uint32) (uint32, bool) {
diff --git a/src/cmd/internal/obj/arm64/goops_gen.go b/src/cmd/internal/obj/arm64/goops_gen.go
index f479bbd7df..ceb403eb66 100644
--- a/src/cmd/internal/obj/arm64/goops_gen.go
+++ b/src/cmd/internal/obj/arm64/goops_gen.go
@@ -332,6 +332,9 @@ const (
AZLSLR
AZLSR
AZLSRR
+ AZLUTI2
+ AZLUTI4
+ AZLUTI6
AZMAD
AZMADPT
AZMATCH
@@ -488,6 +491,7 @@ const (
AZSXTB
AZSXTH
AZSXTW
+ AZTBLQ
AZTBX
AZTBXQ
AZTRN1
diff --git a/src/cmd/internal/obj/arm64/inst.go b/src/cmd/internal/obj/arm64/inst.go
index 131d0211af..688e990bcf 100644
--- a/src/cmd/internal/obj/arm64/inst.go
+++ b/src/cmd/internal/obj/arm64/inst.go
@@ -131,6 +131,18 @@ func aclass(a *obj.Addr) AClass {
if a.Type == obj.TYPE_CONST || a.Type == obj.TYPE_FCONST {
return AC_IMM
}
+ if a.Type == obj.TYPE_REGLIST {
+ switch (a.Offset >> 12) & 0xf {
+ case 0x7:
+ return AC_REGLIST1
+ case 0xa:
+ return AC_REGLIST2
+ case 0x6:
+ return AC_REGLIST3
+ case 0x2:
+ return AC_REGLIST4
+ }
+ }
panic("unknown AClass")
}
@@ -224,6 +236,99 @@ func addrComponent(a *obj.Addr, acl AClass, index int) uint32 {
default:
panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl))
}
+ // AClass: AC_REGLIST1, AC_REGLIST2, AC_REGLIST3, AC_REGLIST4
+ // GNU mnemonic: {reg1.T, reg2.T, ...}
+ // Go mnemonic:
+ // [reg1.T, reg2.T, ...]
+ // Encoding:
+ // Type = TYPE_REGLIST
+ // Offset = register prefix | register count | arrangement (opcode) | first register
+ case AC_REGLIST1, AC_REGLIST2, AC_REGLIST3, AC_REGLIST4:
+ firstReg := int(a.Offset & 31)
+ prefix := a.Offset >> 32 & 0b11
+ sum := 32
+ if prefix == 2 {
+ sum = 16
+ }
+ switch acl {
+ case AC_REGLIST1:
+ if index > 2 {
+ panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl))
+ }
+ case AC_REGLIST2:
+ if index > 4 {
+ panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl))
+ }
+ case AC_REGLIST3:
+ if index > 6 {
+ panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl))
+ }
+ case AC_REGLIST4:
+ if index > 8 {
+ panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl))
+ }
+ }
+ switch index % 2 {
+ case 0:
+ // register
+ return uint32((firstReg + index/2) % sum)
+ case 1:
+ // arrangement
+ curQ := a.Offset >> 30 & 0b11
+ curSize := a.Offset >> 10 & 0b11
+ switch curQ {
+ case 0:
+ switch curSize {
+ case 0:
+ return ARNG_8B
+ case 1:
+ return ARNG_4H
+ case 2:
+ return ARNG_2S
+ case 3:
+ return ARNG_1D
+ default:
+ panic(fmt.Errorf("unknown size value at %d in AClass %d", index, acl))
+ }
+ case 1:
+ switch curSize {
+ case 0:
+ return ARNG_16B
+ case 1:
+ return ARNG_8H
+ case 2:
+ return ARNG_4S
+ case 3:
+ return ARNG_2D
+ default:
+ panic(fmt.Errorf("unknown size value at %d in AClass %d", index, acl))
+ }
+ case 2:
+ switch curSize {
+ case 1:
+ return ARNG_B
+ case 2:
+ return ARNG_H
+ case 3:
+ return ARNG_S
+ default:
+ panic(fmt.Errorf("unknown size value at %d in AClass %d", index, acl))
+ }
+ case 3:
+ switch curSize {
+ case 1:
+ return ARNG_D
+ case 2:
+ return ARNG_Q
+ default:
+ panic(fmt.Errorf("unknown size value at %d in AClass %d", index, acl))
+ }
+ default:
+ panic(fmt.Errorf("unknown Q value at %d in AClass %d", index, acl))
+ }
+ default:
+ panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl))
+ }
}
// TODO: handle more AClasses.
panic(fmt.Errorf("unknown AClass %d", acl))
@@ -528,17 +633,18 @@ func (i *instEncoder) tryEncode(p *obj.Prog) (uint32, bool) {
// For example { <Zn1>.<Tb>-<Zn2>.<Tb> }.
// The 2 instances of <Tb> must encode to the same value.
encoded := map[component]uint32{}
- opIdx := 0
var addrs []*obj.Addr
for addr := range opsInProg(p) {
addrs = append(addrs, addr)
}
- for ii, addr := range addrs {
+ if len(addrs) != len(i.args) {
+ return 0, false
+ }
+ for opIdx, addr := range addrs {
if opIdx >= len(i.args) {
return 0, false
}
op := i.args[opIdx]
- opIdx++
acl := aclass(addr)
if acl != op.class {
return 0, false
@@ -566,13 +672,13 @@ func (i *instEncoder) tryEncode(p *obj.Prog) (uint32, bool) {
case codeImm2Tsz:
b, ok = encodeImm2Tsz(val, addrComponent(addr, acl, i-1))
case codeShift161919212223:
- b, ok = encodeShiftTriple(val, [6]int{16, 19, 19, 21, 22, 23}, addrs[ii+1], p.As)
+ b, ok = encodeShiftTriple(val, [6]int{16, 19, 19, 21, 22, 23}, addrs[opIdx+1], p.As)
case codeShift161919212224:
- b, ok = encodeShiftTriple(val, [6]int{16, 19, 19, 21, 22, 24}, addrs[ii+1], p.As)
+ b, ok = encodeShiftTriple(val, [6]int{16, 19, 19, 21, 22, 24}, addrs[opIdx+1], p.As)
case codeShift588102224:
- b, ok = encodeShiftTriple(val, [6]int{5, 8, 8, 10, 22, 24}, addrs[ii+1], p.As)
+ b, ok = encodeShiftTriple(val, [6]int{5, 8, 8, 10, 22, 24}, addrs[opIdx+1], p.As)
case codeLogicalImmArrEncoding:
- b, ok = encodeLogicalImmArrEncoding(val, addrs[ii+1])
+ b, ok = encodeLogicalImmArrEncoding(val, addrs[opIdx+1])
case codeNoOp:
b, ok = 0, true
default:
@@ -598,8 +704,6 @@ func (i *instEncoder) tryEncode(p *obj.Prog) (uint32, bool) {
}
}
}
- if opIdx != len(i.args) {
- return 0, false
- }
+
return bin, true
}
diff --git a/src/cmd/internal/obj/arm64/inst_gen.go b/src/cmd/internal/obj/arm64/inst_gen.go
index cd13e3e022..ada9c32fa7 100644
--- a/src/cmd/internal/obj/arm64/inst_gen.go
+++ b/src/cmd/internal/obj/arm64/inst_gen.go
@@ -329,6 +329,12 @@ var insts = [][]instEncoder{
fixedBits: 0x25207010,
args: PNn_imm___Pd_T,
},
+ // PPEXT <PNn>[<imm>], { <Pd1>.<T>, <Pd2>.<T> }
+ {
+ goOp: APPEXT,
+ fixedBits: 0x25207410,
+ args: PNn_imm____Pd1_T__Pd2_T_,
+ },
},
// PPFALSE
{
@@ -551,6 +557,12 @@ var insts = [][]instEncoder{
fixedBits: 0x25201000,
args: Rm__Rn__Pd_T,
},
+ // PWHILEGE <Xm>, <Xn>, { <Pd1>.<T>, <Pd2>.<T> }
+ {
+ goOp: APWHILEGE,
+ fixedBits: 0x25205010,
+ args: Xm__Xn___Pd1_T__Pd2_T_,
+ },
},
// PWHILEGEW
{
@@ -569,6 +581,12 @@ var insts = [][]instEncoder{
fixedBits: 0x25201010,
args: Rm__Rn__Pd_T,
},
+ // PWHILEGT <Xm>, <Xn>, { <Pd1>.<T>, <Pd2>.<T> }
+ {
+ goOp: APWHILEGT,
+ fixedBits: 0x25205011,
+ args: Xm__Xn___Pd1_T__Pd2_T_,
+ },
},
// PWHILEGTW
{
@@ -587,6 +605,12 @@ var insts = [][]instEncoder{
fixedBits: 0x25201810,
args: Rm__Rn__Pd_T,
},
+ // PWHILEHI <Xm>, <Xn>, { <Pd1>.<T>, <Pd2>.<T> }
+ {
+ goOp: APWHILEHI,
+ fixedBits: 0x25205811,
+ args: Xm__Xn___Pd1_T__Pd2_T_,
+ },
},
// PWHILEHIW
{
@@ -605,6 +629,12 @@ var insts = [][]instEncoder{
fixedBits: 0x25201800,
args: Rm__Rn__Pd_T,
},
+ // PWHILEHS <Xm>, <Xn>, { <Pd1>.<T>, <Pd2>.<T> }
+ {
+ goOp: APWHILEHS,
+ fixedBits: 0x25205810,
+ args: Xm__Xn___Pd1_T__Pd2_T_,
+ },
},
// PWHILEHSW
{
@@ -623,6 +653,12 @@ var insts = [][]instEncoder{
fixedBits: 0x25201410,
args: Rm__Rn__Pd_T,
},
+ // PWHILELE <Xm>, <Xn>, { <Pd1>.<T>, <Pd2>.<T> }
+ {
+ goOp: APWHILELE,
+ fixedBits: 0x25205411,
+ args: Xm__Xn___Pd1_T__Pd2_T_,
+ },
},
// PWHILELEW
{
@@ -641,6 +677,12 @@ var insts = [][]instEncoder{
fixedBits: 0x25201c00,
args: Rm__Rn__Pd_T,
},
+ // PWHILELO <Xm>, <Xn>, { <Pd1>.<T>, <Pd2>.<T> }
+ {
+ goOp: APWHILELO,
+ fixedBits: 0x25205c10,
+ args: Xm__Xn___Pd1_T__Pd2_T_,
+ },
},
// PWHILELOW
{
@@ -659,6 +701,12 @@ var insts = [][]instEncoder{
fixedBits: 0x25201c10,
args: Rm__Rn__Pd_T,
},
+ // PWHILELS <Xm>, <Xn>, { <Pd1>.<T>, <Pd2>.<T> }
+ {
+ goOp: APWHILELS,
+ fixedBits: 0x25205c11,
+ args: Xm__Xn___Pd1_T__Pd2_T_,
+ },
},
// PWHILELSW
{
@@ -677,6 +725,12 @@ var insts = [][]instEncoder{
fixedBits: 0x25201400,
args: Rm__Rn__Pd_T,
},
+ // PWHILELT <Xm>, <Xn>, { <Pd1>.<T>, <Pd2>.<T> }
+ {
+ goOp: APWHILELT,
+ fixedBits: 0x25205410,
+ args: Xm__Xn___Pd1_T__Pd2_T_,
+ },
},
// PWHILELTW
{
@@ -2060,6 +2114,12 @@ var insts = [][]instEncoder{
fixedBits: 0x5200000,
args: cimm__Zm_B__Zdn_B__Zdn_B__1,
},
+ // ZEXT #<imm>, { <Zn1>.B, <Zn2>.B }, <Zd>.B
+ {
+ goOp: AZEXT,
+ fixedBits: 0x5600000,
+ args: cimm___Zn1_B__Zn2_B___Zd_B,
+ },
},
// ZEXTQ
{
@@ -4035,6 +4095,57 @@ var insts = [][]instEncoder{
args: Zm_T__Zdn_T__PgM__Zdn_T__1,
},
},
+ // ZLUTI2
+ {
+ // ZLUTI2 <Zm>[<index>], { <Zn>.B }, <Zd>.B
+ {
+ goOp: AZLUTI2,
+ fixedBits: 0x4520b000,
+ args: Zm_index____Zn_B___Zd_B__1,
+ },
+ // ZLUTI2 <Zm>[<index>], { <Zn>.H }, <Zd>.H
+ {
+ goOp: AZLUTI2,
+ fixedBits: 0x4520a800,
+ args: Zm_index____Zn_H___Zd_H__1,
+ },
+ },
+ // ZLUTI4
+ {
+ // ZLUTI4 <Zm>[<index>], { <Zn1>.H, <Zn2>.H }, <Zd>.H
+ {
+ goOp: AZLUTI4,
+ fixedBits: 0x4520b400,
+ args: Zm_index____Zn1_H__Zn2_H___Zd_H__1,
+ },
+ // ZLUTI4 <Zm>[<index>], { <Zn>.B }, <Zd>.B
+ {
+ goOp: AZLUTI4,
+ fixedBits: 0x4560a400,
+ args: Zm_index____Zn_B___Zd_B__2,
+ },
+ // ZLUTI4 <Zm>[<index>], { <Zn>.H }, <Zd>.H
+ {
+ goOp: AZLUTI4,
+ fixedBits: 0x4520bc00,
+ args: Zm_index____Zn_H___Zd_H__2,
+ },
+ },
+ // ZLUTI6
+ {
+ // ZLUTI6 <Zm>, { <Zn1>.B, <Zn2>.B }, <Zd>.B
+ {
+ goOp: AZLUTI6,
+ fixedBits: 0x4520ac00,
+ args: Zm___Zn1_B__Zn2_B___Zd_B,
+ },
+ // ZLUTI6 <Zm>[<index>], { <Zn1>.H, <Zn2>.H }, <Zd>.H
+ {
+ goOp: AZLUTI6,
+ fixedBits: 0x4560ac00,
+ args: Zm_index____Zn1_H__Zn2_H___Zd_H__2,
+ },
+ },
// ZMAD
{
// ZMAD <Za>.<T>, <Zm>.<T>, <Pg>/M, <Zdn>.<T>
@@ -5234,6 +5345,12 @@ var insts = [][]instEncoder{
fixedBits: 0x52c8000,
args: Zm_T__Zdn_T__Pv__Zdn_T,
},
+ // ZSPLICE { <Zn1>.<T>, <Zn2>.<T> }, <Pv>, <Zd>.<T>
+ {
+ goOp: AZSPLICE,
+ fixedBits: 0x52d8000,
+ args: _Zn1_T__Zn2_T___Pv__Zd_T,
+ },
},
// ZSQABS
{
@@ -6069,6 +6186,15 @@ var insts = [][]instEncoder{
args: Zn_D__PgZ__Zd_D,
},
},
+ // ZTBLQ
+ {
+ // ZTBLQ <Zm>.<T>, { <Zn>.<T> }, <Zd>.<T>
+ {
+ goOp: AZTBLQ,
+ fixedBits: 0x4400f800,
+ args: Zm_T___Zn_T___Zd_T,
+ },
+ },
// ZTBX
{
// ZTBX <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
@@ -7988,107 +8114,107 @@ var a_ARNG_Zk5103Rd_ArngDCheck = operand{
},
}
-var a_ARNG_Zm1621_ArngBCheck = operand{
+var a_ARNG_Zm1621V2_ArngBCheck = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
- {encodeZm1621, enc_Zm},
+ {encodeZm1621V2, enc_Zm},
{encodeArngBCheck, enc_NIL},
},
}
-var a_ARNG_Zm1621_ArngDCheck = operand{
+var a_ARNG_Zm1621V2_ArngDCheck = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
- {encodeZm1621, enc_Zm},
+ {encodeZm1621V2, enc_Zm},
{encodeArngDCheck, enc_NIL},
},
}
-var a_ARNG_Zm1621_ArngHCheck = operand{
+var a_ARNG_Zm1621V2_ArngHCheck = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
- {encodeZm1621, enc_Zm},
+ {encodeZm1621V2, enc_Zm},
{encodeArngHCheck, enc_NIL},
},
}
-var a_ARNG_Zm1621_ArngQCheck = operand{
+var a_ARNG_Zm1621V2_ArngQCheck = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
- {encodeZm1621, enc_Zm},
+ {encodeZm1621V2, enc_Zm},
{encodeArngQCheck, enc_NIL},
},
}
-var a_ARNG_Zm1621_ArngSCheck = operand{
+var a_ARNG_Zm1621V2_ArngSCheck = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
- {encodeZm1621, enc_Zm},
+ {encodeZm1621V2, enc_Zm},
{encodeArngSCheck, enc_NIL},
},
}
-var a_ARNG_Zm1621_Size0BH2223 = operand{
+var a_ARNG_Zm1621V2_Size0BH2223 = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
- {encodeZm1621, enc_Zm},
+ {encodeZm1621V2, enc_Zm},
{encodeSize0BH2223, enc_size0},
},
}
-var a_ARNG_Zm1621_Size0SD2223 = operand{
+var a_ARNG_Zm1621V2_Size0SD2223 = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
- {encodeZm1621, enc_Zm},
+ {encodeZm1621V2, enc_Zm},
{encodeSize0SD2223, enc_size0},
},
}
-var a_ARNG_Zm1621_Size0TbBH2223 = operand{
+var a_ARNG_Zm1621V2_Size0TbBH2223 = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
- {encodeZm1621, enc_Zm},
+ {encodeZm1621V2, enc_Zm},
{encodeSize0TbBH2223, enc_size0},
},
}
-var a_ARNG_Zm1621_SizeBHSD2224 = operand{
+var a_ARNG_Zm1621V2_SizeBHSD2224 = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
- {encodeZm1621, enc_Zm},
+ {encodeZm1621V2, enc_Zm},
{encodeSizeBHSD2224, enc_size},
},
}
-var a_ARNG_Zm1621_SizeHSD2224 = operand{
+var a_ARNG_Zm1621V2_SizeHSD2224 = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
- {encodeZm1621, enc_Zm},
+ {encodeZm1621V2, enc_Zm},
{encodeSizeHSD2224, enc_size},
},
}
-var a_ARNG_Zm1621_SizeHSD2224No00 = operand{
+var a_ARNG_Zm1621V2_SizeHSD2224No00 = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
- {encodeZm1621, enc_Zm},
+ {encodeZm1621V2, enc_Zm},
{encodeSizeHSD2224No00, enc_size},
},
}
-var a_ARNG_Zm1621_SizeTbBHS2224 = operand{
+var a_ARNG_Zm1621V2_SizeTbBHS2224 = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
- {encodeZm1621, enc_Zm},
+ {encodeZm1621V2, enc_Zm},
{encodeSizeTbBHS2224, enc_size},
},
}
-var a_ARNG_Zm1621_SizeTbBS2224 = operand{
+var a_ARNG_Zm1621V2_SizeTbBS2224 = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
- {encodeZm1621, enc_Zm},
+ {encodeZm1621V2, enc_Zm},
{encodeSizeTbBS2224, enc_size},
},
}
-var a_ARNG_Zm1621_SizeTbHSD2224Offset1 = operand{
+var a_ARNG_Zm1621V2_SizeTbHSD2224Offset1 = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
- {encodeZm1621, enc_Zm},
+ {encodeZm1621V2, enc_Zm},
{encodeSizeTbHSD2224Offset1, enc_size},
},
}
-var a_ARNG_Zm1621_SzSD2223 = operand{
+var a_ARNG_Zm1621V2_SzSD2223 = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
- {encodeZm1621, enc_Zm},
+ {encodeZm1621V2, enc_Zm},
{encodeSzSD2223, enc_sz},
},
}
@@ -8630,6 +8756,14 @@ var a_IMM_ShiftTsz58Range1 = operand{
},
}
+var a_PREGIDX_PnN_58_Noop_I189 = operand{
+ class: AC_PREGIDX, elemEncoders: []elemEncoder{
+ {encodePnN_58, enc_PNn},
+ {encodeNoop, enc_NIL},
+ {encodeI189, enc_i1},
+ },
+}
+
var a_PREGIDX_PnN_58_Noop_Imm2_810 = operand{
class: AC_PREGIDX, elemEncoders: []elemEncoder{
{encodePnN_58, enc_PNn},
@@ -8736,6 +8870,81 @@ var a_PREG_Pv59_Noop = operand{
},
}
+var a_REGLIST1_Zn510Table3_ArngBCheck = operand{
+ class: AC_REGLIST1, elemEncoders: []elemEncoder{
+ {encodeZn510Table3, enc_Zn},
+ {encodeArngBCheck, enc_NIL},
+ },
+}
+
+var a_REGLIST1_Zn510Table3_ArngHCheck = operand{
+ class: AC_REGLIST1, elemEncoders: []elemEncoder{
+ {encodeZn510Table3, enc_Zn},
+ {encodeArngHCheck, enc_NIL},
+ },
+}
+
+var a_REGLIST1_Zn510_SizeBHSD2224 = operand{
+ class: AC_REGLIST1, elemEncoders: []elemEncoder{
+ {encodeZn510, enc_Zn},
+ {encodeSizeBHSD2224, enc_size},
+ },
+}
+
+var a_REGLIST2_Pd04_SizeBHSD2224_Pd04Plus1_SizeBHSD2224 = operand{
+ class: AC_REGLIST2, elemEncoders: []elemEncoder{
+ {encodePd04, enc_Pd},
+ {encodeSizeBHSD2224, enc_size},
+ {encodePd04Plus1, enc_Pd},
+ {encodeSizeBHSD2224, enc_size},
+ },
+}
+
+var a_REGLIST2_Pd14_SizeBHSD2224_Pd14Plus1_SizeBHSD2224 = operand{
+ class: AC_REGLIST2, elemEncoders: []elemEncoder{
+ {encodePd14, enc_Pd},
+ {encodeSizeBHSD2224, enc_size},
+ {encodePd14Plus1, enc_Pd},
+ {encodeSizeBHSD2224, enc_size},
+ },
+}
+
+var a_REGLIST2_Zn510MultiSrc1_ArngBCheck_Zn510MultiSrc2_ArngBCheck = operand{
+ class: AC_REGLIST2, elemEncoders: []elemEncoder{
+ {encodeZn510MultiSrc1, enc_Zn},
+ {encodeArngBCheck, enc_NIL},
+ {encodeZn510MultiSrc2, enc_Zn},
+ {encodeArngBCheck, enc_NIL},
+ },
+}
+
+var a_REGLIST2_Zn510MultiSrc1_SizeBHSD2224_Zn510MultiSrc2_SizeBHSD2224 = operand{
+ class: AC_REGLIST2, elemEncoders: []elemEncoder{
+ {encodeZn510MultiSrc1, enc_Zn},
+ {encodeSizeBHSD2224, enc_size},
+ {encodeZn510MultiSrc2, enc_Zn},
+ {encodeSizeBHSD2224, enc_size},
+ },
+}
+
+var a_REGLIST2_Zn510Table1_ArngBCheck_Zn510Table2_ArngBCheck = operand{
+ class: AC_REGLIST2, elemEncoders: []elemEncoder{
+ {encodeZn510Table1, enc_Zn},
+ {encodeArngBCheck, enc_NIL},
+ {encodeZn510Table2, enc_Zn},
+ {encodeArngBCheck, enc_NIL},
+ },
+}
+
+var a_REGLIST2_Zn510Table1_ArngHCheck_Zn510Table2_ArngHCheck = operand{
+ class: AC_REGLIST2, elemEncoders: []elemEncoder{
+ {encodeZn510Table1, enc_Zn},
+ {encodeArngHCheck, enc_NIL},
+ {encodeZn510Table2, enc_Zn},
+ {encodeArngHCheck, enc_NIL},
+ },
+}
+
var a_SPZGREG_Noop_Rd05 = operand{
class: AC_SPZGREG, elemEncoders: []elemEncoder{
{encodeNoop, enc_NIL},
@@ -8886,6 +9095,46 @@ var a_ZREGIDX_Zd_Noop_I3hI3l_1722_Doubleword = operand{
},
}
+var a_ZREGIDX_Zm1621V1_Noop_I12324 = operand{
+ class: AC_ZREGIDX, elemEncoders: []elemEncoder{
+ {encodeZm1621V1, enc_Zm},
+ {encodeNoop, enc_NIL},
+ {encodeI12324, enc_i1},
+ },
+}
+
+var a_ZREGIDX_Zm1621V1_Noop_I12324B = operand{
+ class: AC_ZREGIDX, elemEncoders: []elemEncoder{
+ {encodeZm1621V1, enc_Zm},
+ {encodeNoop, enc_NIL},
+ {encodeI12324B, enc_i1},
+ },
+}
+
+var a_ZREGIDX_Zm1621V1_Noop_I22224 = operand{
+ class: AC_ZREGIDX, elemEncoders: []elemEncoder{
+ {encodeZm1621V1, enc_Zm},
+ {encodeNoop, enc_NIL},
+ {encodeI22224, enc_i2},
+ },
+}
+
+var a_ZREGIDX_Zm1621V1_Noop_I22224HW = operand{
+ class: AC_ZREGIDX, elemEncoders: []elemEncoder{
+ {encodeZm1621V1, enc_Zm},
+ {encodeNoop, enc_NIL},
+ {encodeI22224HW, enc_i2},
+ },
+}
+
+var a_ZREGIDX_Zm1621V1_Noop_I3224I31213 = operand{
+ class: AC_ZREGIDX, elemEncoders: []elemEncoder{
+ {encodeZm1621V1, enc_Zm},
+ {encodeNoop, enc_NIL},
+ {encodeI3224I31213, enc_i3h_i3l},
+ },
+}
+
var a_ZREGIDX_Zn510Src_Noop_I1_1718_Halfword = operand{
class: AC_ZREGIDX, elemEncoders: []elemEncoder{
{encodeZn510Src, enc_Zn},
@@ -8917,6 +9166,13 @@ var a_ZREG_Zd_Noop = operand{
},
}
+var a_ZREG_Zm1621V1_Noop = operand{
+ class: AC_ZREG, elemEncoders: []elemEncoder{
+ {encodeZm1621V1, enc_Zm},
+ {encodeNoop, enc_NIL},
+ },
+}
+
var a_ZREG_Zn510Src_Noop = operand{
class: AC_ZREG, elemEncoders: []elemEncoder{
{encodeZn510Src, enc_Zn},
@@ -8933,6 +9189,11 @@ var PNn_imm___Pd_T = []operand{
a_ARNG_Pd_SizeBHSD2224,
}
+var PNn_imm____Pd1_T__Pd2_T_ = []operand{
+ a_PREGIDX_PnN_58_Noop_I189,
+ a_REGLIST2_Pd04_SizeBHSD2224_Pd04Plus1_SizeBHSD2224,
+}
+
var Pd_B = []operand{
a_ARNG_Pd_ArngBCheck,
}
@@ -9115,9 +9376,15 @@ var Xm__Xn__Pd_T = []operand{
a_ARNG_Pd_SizeBHSD2224,
}
+var Xm__Xn___Pd1_T__Pd2_T_ = []operand{
+ a_SPZGREG_Noop_Rm1621,
+ a_SPZGREG_Noop_Rn510,
+ a_REGLIST2_Pd14_SizeBHSD2224_Pd14Plus1_SizeBHSD2224,
+}
+
var Za_D__Zm_D__Zdn_D = []operand{
a_ARNG_Za5103Rd_ArngDCheck,
- a_ARNG_Zm1621_ArngDCheck,
+ a_ARNG_Zm1621V2_ArngDCheck,
a_ARNG_ZdnDest_ArngDCheck,
}
@@ -9130,7 +9397,7 @@ var Za_T__Zm_T__PgM__Zdn_T__1 = []operand{
var Za_T__Zm_T__PgM__Zdn_T__2 = []operand{
a_ARNG_Za5103Rd_SizeBHSD2224,
- a_ARNG_Zm1621_SizeBHSD2224,
+ a_ARNG_Zm1621V2_SizeBHSD2224,
a_PREGZM_Pg1013_MergePredCheck,
a_ARNG_ZdnDest_SizeBHSD2224,
}
@@ -9142,7 +9409,7 @@ var Zdn_B__Zdn_B = []operand{
var Zk_D__Zm_D__Zdn_D__Zdn_D = []operand{
a_ARNG_Zk5103Rd_ArngDCheck,
- a_ARNG_Zm1621_ArngDCheck,
+ a_ARNG_Zm1621V2_ArngDCheck,
a_ARNG_ZdnDest_ArngDCheck,
a_ARNG_ZdnDest_ArngDCheck,
}
@@ -9154,19 +9421,19 @@ var Zm_B__Zdn_B__Zdn_B = []operand{
}
var Zm_B__Zn_B__Zd_B = []operand{
- a_ARNG_Zm1621_ArngBCheck,
+ a_ARNG_Zm1621V2_ArngBCheck,
a_ARNG_Zn510_ArngBCheck,
a_ARNG_Zd_ArngBCheck,
}
var Zm_B__Zn_B__Zda_H = []operand{
- a_ARNG_Zm1621_ArngBCheck,
+ a_ARNG_Zm1621V2_ArngBCheck,
a_ARNG_Zn510_ArngBCheck,
a_ARNG_Zda3RdSrcDst_ArngHCheck,
}
var Zm_B__Zn_B__Zda_S = []operand{
- a_ARNG_Zm1621_ArngBCheck,
+ a_ARNG_Zm1621V2_ArngBCheck,
a_ARNG_Zn510_ArngBCheck,
a_ARNG_Zda3RdSrcDst_ArngSCheck,
}
@@ -9222,32 +9489,32 @@ var Zm_D__Zdn_T__PgM__Zdn_T = []operand{
}
var Zm_D__Zn_D__Zd_D = []operand{
- a_ARNG_Zm1621_ArngDCheck,
+ a_ARNG_Zm1621V2_ArngDCheck,
a_ARNG_Zn510_ArngDCheck,
a_ARNG_Zd_ArngDCheck,
}
var Zm_D__Zn_D__Zd_Q = []operand{
- a_ARNG_Zm1621_ArngDCheck,
+ a_ARNG_Zm1621V2_ArngDCheck,
a_ARNG_Zn510_ArngDCheck,
a_ARNG_Zd_ArngQCheck,
}
var Zm_D__Zn_D__Zda_D = []operand{
- a_ARNG_Zm1621_ArngDCheck,
+ a_ARNG_Zm1621V2_ArngDCheck,
a_ARNG_Zn510_ArngDCheck,
a_ARNG_Zda3RdSrcDst_ArngDCheck,
}
var Zm_D__Zn_T__PgZ__Pd_T = []operand{
- a_ARNG_Zm1621_ArngDCheck,
+ a_ARNG_Zm1621V2_ArngDCheck,
a_ARNG_Zn510_SizeBHS2224,
a_PREGZM_Pg1013_ZeroPredCheck,
a_ARNG_Pd_SizeBHS2224,
}
var Zm_D__Zn_T__Zd_T = []operand{
- a_ARNG_Zm1621_ArngDCheck,
+ a_ARNG_Zm1621V2_ArngDCheck,
a_ARNG_Zn510_SizeBHS2224,
a_ARNG_Zd_SizeBHS2224,
}
@@ -9284,26 +9551,26 @@ var Zm_H__Zdn_H__PgM__Zdn_H = []operand{
}
var Zm_H__Zn_H__PgM__Zda_H = []operand{
- a_ARNG_Zm1621_ArngHCheck,
+ a_ARNG_Zm1621V2_ArngHCheck,
a_ARNG_Zn510_ArngHCheck,
a_PREGZM_Pg1013_MergePredCheck,
a_ARNG_Zda3RdSrcDst_ArngHCheck,
}
var Zm_H__Zn_H__Zd_H = []operand{
- a_ARNG_Zm1621_ArngHCheck,
+ a_ARNG_Zm1621V2_ArngHCheck,
a_ARNG_Zn510_ArngHCheck,
a_ARNG_Zd_ArngHCheck,
}
var Zm_H__Zn_H__Zda_H = []operand{
- a_ARNG_Zm1621_ArngHCheck,
+ a_ARNG_Zm1621V2_ArngHCheck,
a_ARNG_Zn510_ArngHCheck,
a_ARNG_Zda3RdSrcDst_ArngHCheck,
}
var Zm_H__Zn_H__Zda_S = []operand{
- a_ARNG_Zm1621_ArngHCheck,
+ a_ARNG_Zm1621V2_ArngHCheck,
a_ARNG_Zn510_ArngHCheck,
a_ARNG_Zda3RdSrcDst_ArngSCheck,
}
@@ -9381,7 +9648,7 @@ var Zm_H_imm___Zn_H__Zda_S__4 = []operand{
}
var Zm_Q__Zn_Q__Zd_Q = []operand{
- a_ARNG_Zm1621_ArngQCheck,
+ a_ARNG_Zm1621V2_ArngQCheck,
a_ARNG_Zn510_ArngQCheck,
a_ARNG_Zd_ArngQCheck,
}
@@ -9393,13 +9660,13 @@ var Zm_S__Zdn_S__Zdn_S = []operand{
}
var Zm_S__Zn_S__Zd_S = []operand{
- a_ARNG_Zm1621_ArngSCheck,
+ a_ARNG_Zm1621V2_ArngSCheck,
a_ARNG_Zn510_ArngSCheck,
a_ARNG_Zd_ArngSCheck,
}
var Zm_S__Zn_S__Zda_S = []operand{
- a_ARNG_Zm1621_ArngSCheck,
+ a_ARNG_Zm1621V2_ArngSCheck,
a_ARNG_Zn510_ArngSCheck,
a_ARNG_Zda3RdSrcDst_ArngSCheck,
}
@@ -9504,120 +9771,168 @@ var Zm_T__Zdn_T__Pv__Zdn_T = []operand{
}
var Zm_T__Zn_T__PgM__Zda_T__1 = []operand{
- a_ARNG_Zm1621_SizeHSD2224No00,
+ a_ARNG_Zm1621V2_SizeHSD2224No00,
a_ARNG_Zn510_SizeHSD2224No00,
a_PREGZM_Pg1013_MergePredCheck,
a_ARNG_Zda3RdSrcDst_SizeHSD2224No00,
}
var Zm_T__Zn_T__PgM__Zda_T__2 = []operand{
- a_ARNG_Zm1621_SizeBHSD2224,
+ a_ARNG_Zm1621V2_SizeBHSD2224,
a_ARNG_Zn510_SizeBHSD2224,
a_PREGZM_Pg1013_MergePredCheck,
a_ARNG_Zda3RdSrcDst_SizeBHSD2224,
}
var Zm_T__Zn_T__PgZ__Pd_T__1 = []operand{
- a_ARNG_Zm1621_SizeHSD2224,
+ a_ARNG_Zm1621V2_SizeHSD2224,
a_ARNG_Zn510_SizeHSD2224,
a_PREGZM_Pg1013_ZeroPredCheck,
a_ARNG_Pd_SizeHSD2224,
}
var Zm_T__Zn_T__PgZ__Pd_T__2 = []operand{
- a_ARNG_Zm1621_SizeBHSD2224,
+ a_ARNG_Zm1621V2_SizeBHSD2224,
a_ARNG_Zn510_SizeBHSD2224,
a_PREGZM_Pg1013_ZeroPredCheck,
a_ARNG_Pd_SizeBHSD2224,
}
var Zm_T__Zn_T__PgZ__Pd_T__3 = []operand{
- a_ARNG_Zm1621_Size0BH2223,
+ a_ARNG_Zm1621V2_Size0BH2223,
a_ARNG_Zn510_Size0BH2223,
a_PREGZM_Pg1013_ZeroPredCheck,
a_ARNG_Pd_Size0BH2223,
}
var Zm_T__Zn_T__PgZ__Zd_T = []operand{
- a_ARNG_Zm1621_Size0SD2223,
+ a_ARNG_Zm1621V2_Size0SD2223,
a_ARNG_Zn510_Size0SD2223,
a_PREGZM_Pg1013_ZeroPredCheck,
a_ARNG_Zd_Size0SD2223,
}
var Zm_T__Zn_T__Pv__Zd_T = []operand{
- a_ARNG_Zm1621_SizeBHSD2224,
+ a_ARNG_Zm1621V2_SizeBHSD2224,
a_ARNG_Zn510_SizeBHSD2224,
a_PREG_Pv1014_Noop,
a_ARNG_Zd_SizeBHSD2224,
}
var Zm_T__Zn_T__Zd_T__1 = []operand{
- a_ARNG_Zm1621_SizeBHSD2224,
+ a_ARNG_Zm1621V2_SizeBHSD2224,
a_ARNG_Zn510_SizeBHSD2224,
a_ARNG_Zd_SizeBHSD2224,
}
var Zm_T__Zn_T__Zd_T__2 = []operand{
- a_ARNG_Zm1621_SizeHSD2224No00,
+ a_ARNG_Zm1621V2_SizeHSD2224No00,
a_ARNG_Zn510_SizeHSD2224No00,
a_ARNG_Zd_SizeHSD2224No00,
}
var Zm_T__Zn_T__Zd_T__3 = []operand{
- a_ARNG_Zm1621_SizeHSD2224,
+ a_ARNG_Zm1621V2_SizeHSD2224,
a_ARNG_Zn510_SizeHSD2224,
a_ARNG_Zd_SizeHSD2224,
}
var Zm_T__Zn_T__Zda_T__1 = []operand{
- a_ARNG_Zm1621_SzSD2223,
+ a_ARNG_Zm1621V2_SzSD2223,
a_ARNG_Zn510_SzSD2223,
a_ARNG_Zda3RdSrcDst_SzSD2223,
}
var Zm_T__Zn_T__Zda_T__2 = []operand{
- a_ARNG_Zm1621_SizeBHSD2224,
+ a_ARNG_Zm1621V2_SizeBHSD2224,
a_ARNG_Zn510_SizeBHSD2224,
a_ARNG_Zda3RdSrcDst_SizeBHSD2224,
}
+var Zm_T___Zn_T___Zd_T = []operand{
+ a_ARNG_Zm1621V2_SizeBHSD2224,
+ a_REGLIST1_Zn510_SizeBHSD2224,
+ a_ARNG_Zd_SizeBHSD2224,
+}
+
var Zm_Tb__Zn_T__Zd_T = []operand{
- a_ARNG_Zm1621_SizeTbBHS2224,
+ a_ARNG_Zm1621V2_SizeTbBHS2224,
a_ARNG_Zn510_SizeHSD2224,
a_ARNG_Zd_SizeHSD2224,
}
var Zm_Tb__Zn_Tb__Zd_T__1 = []operand{
- a_ARNG_Zm1621_SizeTbBHS2224,
+ a_ARNG_Zm1621V2_SizeTbBHS2224,
a_ARNG_Zn510_SizeTbBHS2224,
a_ARNG_Zd_SizeHSD2224,
}
var Zm_Tb__Zn_Tb__Zd_T__2 = []operand{
- a_ARNG_Zm1621_SizeTbHSD2224Offset1,
+ a_ARNG_Zm1621V2_SizeTbHSD2224Offset1,
a_ARNG_Zn510_SizeTbHSD2224Offset1,
a_ARNG_Zd_SizeBHS2224Offset1,
}
var Zm_Tb__Zn_Tb__Zd_T__3 = []operand{
- a_ARNG_Zm1621_SizeTbBS2224,
+ a_ARNG_Zm1621V2_SizeTbBS2224,
a_ARNG_Zn510_SizeTbBS2224,
a_ARNG_Zd_SizeHD2224,
}
var Zm_Tb__Zn_Tb__Zda_T__1 = []operand{
- a_ARNG_Zm1621_SizeTbBHS2224,
+ a_ARNG_Zm1621V2_SizeTbBHS2224,
a_ARNG_Zn510_SizeTbBHS2224,
a_ARNG_Zda3RdSrcDst_SizeHSD2224,
}
var Zm_Tb__Zn_Tb__Zda_T__2 = []operand{
- a_ARNG_Zm1621_Size0TbBH2223,
+ a_ARNG_Zm1621V2_Size0TbBH2223,
a_ARNG_Zn510_Size0TbBH2223,
a_ARNG_Zda3RdSrcDst_Size0SD2223,
}
+var Zm___Zn1_B__Zn2_B___Zd_B = []operand{
+ a_ZREG_Zm1621V1_Noop,
+ a_REGLIST2_Zn510Table1_ArngBCheck_Zn510Table2_ArngBCheck,
+ a_ARNG_Zd_ArngBCheck,
+}
+
+var Zm_index____Zn1_H__Zn2_H___Zd_H__1 = []operand{
+ a_ZREGIDX_Zm1621V1_Noop_I22224HW,
+ a_REGLIST2_Zn510Table1_ArngHCheck_Zn510Table2_ArngHCheck,
+ a_ARNG_Zd_ArngHCheck,
+}
+
+var Zm_index____Zn1_H__Zn2_H___Zd_H__2 = []operand{
+ a_ZREGIDX_Zm1621V1_Noop_I12324,
+ a_REGLIST2_Zn510Table1_ArngHCheck_Zn510Table2_ArngHCheck,
+ a_ARNG_Zd_ArngHCheck,
+}
+
+var Zm_index____Zn_B___Zd_B__1 = []operand{
+ a_ZREGIDX_Zm1621V1_Noop_I22224,
+ a_REGLIST1_Zn510Table3_ArngBCheck,
+ a_ARNG_Zd_ArngBCheck,
+}
+
+var Zm_index____Zn_B___Zd_B__2 = []operand{
+ a_ZREGIDX_Zm1621V1_Noop_I12324B,
+ a_REGLIST1_Zn510Table3_ArngBCheck,
+ a_ARNG_Zd_ArngBCheck,
+}
+
+var Zm_index____Zn_H___Zd_H__1 = []operand{
+ a_ZREGIDX_Zm1621V1_Noop_I3224I31213,
+ a_REGLIST1_Zn510Table3_ArngHCheck,
+ a_ARNG_Zd_ArngHCheck,
+}
+
+var Zm_index____Zn_H___Zd_H__2 = []operand{
+ a_ZREGIDX_Zm1621V1_Noop_I22224HW,
+ a_REGLIST1_Zn510Table3_ArngHCheck,
+ a_ARNG_Zd_ArngHCheck,
+}
+
var Zn_B__Zd_H = []operand{
a_ARNG_Zn510Src_ArngBCheck,
a_ARNG_Zd_ArngHCheck,
@@ -9942,6 +10257,12 @@ var Zn_imm___Pd_S = []operand{
a_ARNG_Pd_ArngSCheck,
}
+var _Zn1_T__Zn2_T___Pv__Zd_T = []operand{
+ a_REGLIST2_Zn510MultiSrc1_SizeBHSD2224_Zn510MultiSrc2_SizeBHSD2224,
+ a_PREG_Pv1013_Noop,
+ a_ARNG_Zd_SizeBHSD2224,
+}
+
var c0_0__Zn_T__PgZ__Pd_T = []operand{
a_IMM_Fimm0_0_56,
a_ARNG_Zn510Src_SizeHSD2224,
@@ -10092,6 +10413,12 @@ var cimm__Zn_T__PgZ__Pd_T__2 = []operand{
a_ARNG_Pd_SizeBHSD2224,
}
+var cimm___Zn1_B__Zn2_B___Zd_B = []operand{
+ a_IMM_Imm8hImm8l_Unsigned,
+ a_REGLIST2_Zn510MultiSrc1_ArngBCheck_Zn510MultiSrc2_ArngBCheck,
+ a_ARNG_Zd_ArngBCheck,
+}
+
var cimm__shift__PgM__Zd_T = []operand{
a_IMM_Imm8SignedLsl8,
a_PREGZM_Pg1620_MergePredCheck,
@@ -10195,7 +10522,7 @@ var const__Zm_T__Zdn_T__Zdn_T = []operand{
var const__Zm_T__Zn_T__PgM__Zda_T = []operand{
a_IMM_Rot0_90_180_270_1315,
- a_ARNG_Zm1621_SizeHSD2224,
+ a_ARNG_Zm1621V2_SizeHSD2224,
a_ARNG_Zn510_SizeHSD2224,
a_PREGZM_Pg1013_MergePredCheck,
a_ARNG_Zda3RdSrcDst_SizeHSD2224,
@@ -10203,14 +10530,14 @@ var const__Zm_T__Zn_T__PgM__Zda_T = []operand{
var const__Zm_T__Zn_T__Zda_T = []operand{
a_IMM_Rot0_90_180_270_1012,
- a_ARNG_Zm1621_SizeBHSD2224,
+ a_ARNG_Zm1621V2_SizeBHSD2224,
a_ARNG_Zn510_SizeBHSD2224,
a_ARNG_Zda3RdSrcDst_SizeBHSD2224,
}
var const__Zm_Tb__Zn_Tb__Zda_T = []operand{
a_IMM_Rot0_90_180_270_1012,
- a_ARNG_Zm1621_Size0TbBH2223,
+ a_ARNG_Zm1621V2_Size0TbBH2223,
a_ARNG_Zn510_Size0TbBH2223,
a_ARNG_Zda3RdSrcDst_Size0SD2223,
}
diff --git a/src/cmd/internal/obj/arm64/list7.go b/src/cmd/internal/obj/arm64/list7.go
index 3ce949f465..b33bf690bf 100644
--- a/src/cmd/internal/obj/arm64/list7.go
+++ b/src/cmd/internal/obj/arm64/list7.go
@@ -229,11 +229,18 @@ func SPCconv(a int64) string {
func rlconv(list int64) string {
str := ""
- // ARM64 register list follows ARM64 instruction decode schema
+ // For SIMD&FP register list in ARM64, the conv
+ // follows the ARM64 instruction decode schema
// | 31 | 30 | ... | 15 - 12 | 11 - 10 | ... |
// +----+----+-----+---------+---------+-----+
// | | Q | ... | opcode | size | ... |
+ // For Scalable Vector register lists, the conv
+ // follows:
+ // | 33 - 32 | 31 - 30 | ... | 15 - 12 | 11 - 10 | ... | 5 - 0 |
+ // +----+----+----+----+-----+---------+---------+-----+-------+
+ // |regprefix| class 1 | ... | reg cnt | class 2 | ... | reg |
+
firstReg := int(list & 31)
opcode := (list >> 12) & 15
var regCnt int
@@ -251,7 +258,17 @@ func rlconv(list int64) string {
regCnt = -1
}
// Q:size
- arng := ((list>>30)&1)<<2 | (list>>10)&3
+ var regPrefix string
+ regType := (list >> 32) & 3
+ switch regType {
+ case 0:
+ regPrefix = "V"
+ case 1:
+ regPrefix = "Z"
+ case 2:
+ regPrefix = "P"
+ }
+ arng := ((list>>30)&3)<<2 | (list>>10)&3
switch arng {
case 0:
t = "B8"
@@ -269,6 +286,16 @@ func rlconv(list int64) string {
t = "D1"
case 7:
t = "D2"
+ case 9:
+ t = "B"
+ case 10:
+ t = "H"
+ case 11:
+ t = "S"
+ case 13:
+ t = "D"
+ case 14:
+ t = "Q"
}
for i := 0; i < regCnt; i++ {
if str == "" {
@@ -276,7 +303,7 @@ func rlconv(list int64) string {
} else {
str += ","
}
- str += fmt.Sprintf("V%d.", (firstReg+i)&31)
+ str += fmt.Sprintf("%s%d.", regPrefix, (firstReg+i)&31)
str += t
}
str += "]"
generated by cgit v1.3 (git 2.53.0) at 2026-04-15 06:03:18 +0000