cmd/asm, cmd/internal/obj/arm64: add GP and SIMD reg support for SVE

The GP registers and SIMD registers are comforming to the existing Go
syntax: they are V or R registers, their widths are specified in the
Opcode, the rules to specify them is:
- if that instruction only contains one GP or SIMD register:
   If it's 32-bit GP, then append W to the end of the opcode.
   If it's 64-bit GP, no changes.
   If it's SIMD register with BHWD width specification, BHSDQ will just
be appended to the end of the opcode.
- if it contains multiple GP or SIMD registers, then manual observation
  found that they are either specified the same width, or they are fixed
width. We distinguish them by their first Go ASM operand width. The rule
to append suffixes are the same to the single-reg case above.

This CL is generated by CL 759280.

Change-Id: Icc819cc30dd8fd1609de31ba7bcb4e3ac83c465e
Reviewed-on: https://go-review.googlesource.com/c/go/+/759261
Reviewed-by: David Chase <drchase@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>

1 files changed, 23 insertions, 0 deletions

diff --git a/src/cmd/internal/obj/arm64/inst.go b/src/cmd/internal/obj/arm64/inst.go
index abd464eb00..28ff139d66 100644
--- a/src/cmd/internal/obj/arm64/inst.go
+++ b/src/cmd/internal/obj/arm64/inst.go
@@ -109,6 +109,12 @@ func aclass(a *obj.Addr) AClass {
 				return AC_ARNG
 			}
 		}
+		if a.Reg >= REG_V0 && a.Reg <= REG_V31 {
+			return AC_VREG
+		}
+		if a.Reg >= REG_R0 && a.Reg <= REG_R31 || a.Reg == REG_RSP {
+			return AC_SPZGREG
+		}
 	}
 	panic("unknown AClass")
 }
@@ -143,6 +149,23 @@ func addrComponent(a *obj.Addr, acl AClass, index int) uint32 {
 		default:
 			panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl))
 		}
+	//	AClass: AC_SPZGREG, AC_VREG
+	//	GNU mnemonic: <width><reg>
+	//	Go mnemonic:
+	//		reg (the width is already represented in the opcode)
+	//	Encoding:
+	//		Type = TYPE_REG
+	// 		Reg = reg
+	case AC_SPZGREG, AC_VREG:
+		switch index {
+		case 0:
+			// These are all width checks, they should map to no-op checks altogether.
+			return 0
+		case 1:
+			return uint32(a.Reg)
+		default:
+			panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl))
+		}
 	}
 	// TODO: handle more AClasses.
 	panic(fmt.Errorf("unknown AClass %d", acl))