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authorJunyang Shao <shaojunyang@google.com>2026-03-25 19:05:16 +0000
committerJunyang Shao <shaojunyang@google.com>2026-04-10 07:24:57 -0700
commit926a1bef08ae6b93b50a96eedb15210e1d8c4733 (patch)
tree92a08ca4ec8ac6f4f374d29d387548334e854aca /src/cmd
parent0e31741044d519065f62a5e96499909d6cd230dc (diff)
downloadgo-926a1bef08ae6b93b50a96eedb15210e1d8c4733.tar.xz
cmd/asm, cmd/internal/obj/arm64: add GP and SIMD reg support for SVE
The GP registers and SIMD registers are comforming to the existing Go syntax: they are V or R registers, their widths are specified in the Opcode, the rules to specify them is: - if that instruction only contains one GP or SIMD register: If it's 32-bit GP, then append W to the end of the opcode. If it's 64-bit GP, no changes. If it's SIMD register with BHWD width specification, BHSDQ will just be appended to the end of the opcode. - if it contains multiple GP or SIMD registers, then manual observation found that they are either specified the same width, or they are fixed width. We distinguish them by their first Go ASM operand width. The rule to append suffixes are the same to the single-reg case above. This CL is generated by CL 759280. Change-Id: Icc819cc30dd8fd1609de31ba7bcb4e3ac83c465e Reviewed-on: https://go-review.googlesource.com/c/go/+/759261 Reviewed-by: David Chase <drchase@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Diffstat (limited to 'src/cmd')
-rw-r--r--src/cmd/asm/internal/asm/testdata/arm64sveenc.s245
-rw-r--r--src/cmd/asm/internal/asm/testdata/arm64sveerror.s165
-rw-r--r--src/cmd/internal/obj/arm64/a.out.go24
-rw-r--r--src/cmd/internal/obj/arm64/anames_gen.go121
-rw-r--r--src/cmd/internal/obj/arm64/encoding_gen.go190
-rw-r--r--src/cmd/internal/obj/arm64/goops_gen.go123
-rw-r--r--src/cmd/internal/obj/arm64/inst.go23
-rw-r--r--src/cmd/internal/obj/arm64/inst_gen.go2327
8 files changed, 2640 insertions, 578 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/arm64sveenc.s b/src/cmd/asm/internal/asm/testdata/arm64sveenc.s
index 09c876f13f..5aa29f4325 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64sveenc.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64sveenc.s
@@ -34,8 +34,8 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
PPTRUE PN14.S // 1678a025
PPUNPKHI P14.B, P0.H // c0413105
PPUNPKLO P14.B, P0.H // c0413005
- PRDFFR P13.B // 0df01925
PRDFFR P14.Z, P0.B // c0f11825
+ PRDFFR P13.B // 0df01925
PRDFFRS P14.Z, P0.B // c0f15825
PREV P14.S, P13.S // cd41b405
PSEL P4.B, P2.B, P1, P14.B // 5e460425
@@ -68,8 +68,8 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZAND Z15.B, Z0.B, P3.M, Z0.B // e00d1a04
ZAND Z7.D, Z6.D, Z23.D // d7302704
ZANDQV Z25.S, P3, V5.S4 // 252f9e04
- ZASR Z2.D, Z10.D, P3.M, Z10.D // 4a8cd004
ZASR Z15.B, Z0.B, P3.M, Z0.B // e08d1004
+ ZASR Z2.D, Z10.D, P3.M, Z10.D // 4a8cd004
ZASR Z7.D, Z6.H, Z13.H // cd806704
ZASRR Z15.B, Z0.B, P3.M, Z0.B // e08d1404
ZBCAX Z23.D, Z13.D, Z21.D, Z21.D // f53a6d04
@@ -82,8 +82,8 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZBFADD Z23.H, Z13.H, P1.M, Z13.H // ed860065
ZBFADD Z7.H, Z6.H, Z23.H // d7000765
ZBFCLAMP Z7.H, Z6.H, Z23.H // d7242764
- ZBFCVT Z13.S, P1.Z, Z22.H // b6c59a64
ZBFCVT Z13.S, P1.M, Z22.H // b6a58a65
+ ZBFCVT Z13.S, P1.Z, Z22.H // b6c59a64
ZBFCVTNT Z13.S, P1.M, Z22.H // b6a58a64
ZBFCVTNT Z13.S, P1.Z, Z22.H // b6a58264
ZBFDOT Z7.H, Z6.H, Z23.S // d7806764
@@ -102,8 +102,8 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZBFMUL Z23.H, Z13.H, P1.M, Z13.H // ed860265
ZBFMUL Z7.H, Z6.H, Z23.H // d7080765
ZBFSCALE Z23.H, Z13.H, P1.M, Z13.H // ed860965
- ZBFSUB Z7.H, Z6.H, Z23.H // d7040765
ZBFSUB Z23.H, Z13.H, P1.M, Z13.H // ed860165
+ ZBFSUB Z7.H, Z6.H, Z23.H // d7040765
ZBGRP Z7.D, Z23.D, Z13.D // edbac745
ZBIC Z15.B, Z0.B, P3.M, Z0.B // e00d1b04
ZBIC Z7.D, Z6.D, Z23.D // d730e704
@@ -112,26 +112,26 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZBSL2N Z23.D, Z13.D, Z21.D, Z21.D // f53ead04
ZCLASTA Z15.B, Z0.B, P3, Z0.B // e08d2805
ZCLASTB Z15.B, Z0.B, P3, Z0.B // e08d2905
- ZCLS Z7.D, P4.Z, Z13.D // edb0c804
ZCLS Z7.D, P4.M, Z13.D // edb0d804
- ZCLZ Z7.D, P4.Z, Z13.D // edb0c904
+ ZCLS Z7.D, P4.Z, Z13.D // edb0c804
ZCLZ Z7.D, P4.M, Z13.D // edb0d904
+ ZCLZ Z7.D, P4.Z, Z13.D // edb0c904
ZCMPEQ Z0.H, Z2.H, P0.Z, P14.H // 4ea04024
ZCMPEQ Z0.D, Z12.S, P0.Z, P14.S // 8e218024
ZCMPGE Z0.H, Z2.H, P0.Z, P14.H // 4e804024
ZCMPGE Z0.D, Z12.S, P0.Z, P14.S // 8e418024
ZCMPGT Z0.H, Z2.H, P0.Z, P14.H // 5e804024
ZCMPGT Z0.D, Z12.S, P0.Z, P14.S // 9e418024
- ZCMPHI Z0.D, Z12.S, P0.Z, P14.S // 9ec18024
ZCMPHI Z0.H, Z2.H, P0.Z, P14.H // 5e004024
+ ZCMPHI Z0.D, Z12.S, P0.Z, P14.S // 9ec18024
ZCMPHS Z0.H, Z2.H, P0.Z, P14.H // 4e004024
ZCMPHS Z0.D, Z12.S, P0.Z, P14.S // 8ec18024
// TODO: CMPLE
// TODO: CMPLO
// TODO: CMPLS
// TODO: CMPLT
- ZCMPNE Z0.D, Z12.S, P0.Z, P14.S // 9e218024
ZCMPNE Z0.H, Z2.H, P0.Z, P14.H // 5ea04024
+ ZCMPNE Z0.D, Z12.S, P0.Z, P14.S // 9e218024
ZCNOT Z7.D, P4.M, Z13.D // edb0db04
ZCNOT Z7.D, P4.Z, Z13.D // edb0cb04
ZCNT Z7.D, P4.M, Z13.D // edb0da04
@@ -151,8 +151,8 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZF2CVT Z11.B, Z6.H // 66350865
ZF2CVTLT Z11.B, Z6.H // 66350965
ZFABD Z25.S, Z2.S, P1.M, Z2.S // 22878865
- ZFABS Z7.D, P4.Z, Z13.D // edb0cc04
ZFABS Z7.D, P4.M, Z13.D // edb0dc04
+ ZFABS Z7.D, P4.Z, Z13.D // edb0cc04
ZFACGE Z0.H, Z2.H, P0.Z, P14.H // 5ec04065
ZFACGT Z0.H, Z2.H, P0.Z, P14.H // 5ee04065
ZFADD Z25.S, Z2.S, P1.M, Z2.S // 22878065
@@ -168,12 +168,12 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZFCMNE Z0.H, Z2.H, P0.Z, P14.H // 5e604065
ZFCMUO Z0.H, Z2.H, P0.Z, P14.H // 4ec04065
ZFCVT Z13.H, P1.M, Z22.S // b6a58965
- ZFCVT Z13.S, P1.M, Z22.D // b6a5cb65
ZFCVT Z13.H, P1.Z, Z22.S // b6a59a64
ZFCVT Z13.H, P1.M, Z22.D // b6a5c965
ZFCVT Z13.H, P1.Z, Z22.D // b6a5da64
ZFCVT Z13.S, P1.M, Z22.H // b6a58865
ZFCVT Z13.S, P1.Z, Z22.H // b6859a64
+ ZFCVT Z13.S, P1.M, Z22.D // b6a5cb65
ZFCVT Z13.S, P1.Z, Z22.D // b6e5da64
ZFCVT Z13.D, P1.M, Z22.H // b6a5c865
ZFCVT Z13.D, P1.Z, Z22.H // b685da64
@@ -187,8 +187,8 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZFCVTNT Z13.S, P1.Z, Z22.H // b6a58064
ZFCVTNT Z13.D, P1.M, Z22.S // b6a5ca64
ZFCVTNT Z13.D, P1.Z, Z22.S // b6a5c264
- ZFCVTX Z13.D, P1.Z, Z22.S // b6c51a64
ZFCVTX Z13.D, P1.M, Z22.S // b6a50a65
+ ZFCVTX Z13.D, P1.Z, Z22.S // b6c51a64
ZFCVTXNT Z13.D, P1.M, Z22.S // b6a50a64
ZFCVTXNT Z13.D, P1.Z, Z22.S // b6a50264
ZFCVTZS Z13.H, P1.M, Z22.H // b6a55a65
@@ -205,25 +205,25 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZFCVTZS Z13.D, P1.Z, Z22.S // b685de64
ZFCVTZS Z13.D, P1.M, Z22.D // b6a5de65
ZFCVTZS Z13.D, P1.Z, Z22.D // b6c5df64
- ZFCVTZU Z13.D, P1.Z, Z22.S // b6a5de64
- ZFCVTZU Z13.H, P1.M, Z22.D // b6a55f65
ZFCVTZU Z13.H, P1.M, Z22.H // b6a55b65
ZFCVTZU Z13.H, P1.Z, Z22.H // b6e55e64
- ZFCVTZU Z13.D, P1.Z, Z22.D // b6e5df64
ZFCVTZU Z13.H, P1.M, Z22.S // b6a55d65
ZFCVTZU Z13.H, P1.Z, Z22.S // b6a55f64
+ ZFCVTZU Z13.H, P1.M, Z22.D // b6a55f65
ZFCVTZU Z13.H, P1.Z, Z22.D // b6e55f64
- ZFCVTZU Z13.D, P1.M, Z22.D // b6a5df65
ZFCVTZU Z13.S, P1.M, Z22.S // b6a59d65
- ZFCVTZU Z13.D, P1.M, Z22.S // b6a5d965
- ZFCVTZU Z13.S, P1.Z, Z22.D // b6a5df64
- ZFCVTZU Z13.S, P1.M, Z22.D // b6a5dd65
ZFCVTZU Z13.S, P1.Z, Z22.S // b6a59f64
+ ZFCVTZU Z13.S, P1.M, Z22.D // b6a5dd65
+ ZFCVTZU Z13.S, P1.Z, Z22.D // b6a5df64
+ ZFCVTZU Z13.D, P1.M, Z22.S // b6a5d965
+ ZFCVTZU Z13.D, P1.Z, Z22.S // b6a5de64
+ ZFCVTZU Z13.D, P1.M, Z22.D // b6a5df65
+ ZFCVTZU Z13.D, P1.Z, Z22.D // b6e5df64
ZFDIV Z25.S, Z2.S, P1.M, Z2.S // 22878d65
ZFDIVR Z25.S, Z2.S, P1.M, Z2.S // 22878c65
- ZFDOT Z7.B, Z6.B, Z23.S // d7846764
- ZFDOT Z7.B, Z6.B, Z23.H // d7842764
ZFDOT Z7.H, Z6.H, Z23.S // d7802764
+ ZFDOT Z7.B, Z6.B, Z23.H // d7842764
+ ZFDOT Z7.B, Z6.B, Z23.S // d7846764
ZFEXPA Z1.S, Z26.S // 3ab8a004
ZFLOGB Z7.D, P4.M, Z13.D // edb01e65
ZFLOGB Z7.D, P4.Z, Z13.D // edf01e64
@@ -247,8 +247,8 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZFMLALLBT Z7.B, Z6.B, Z23.S // d7982764
ZFMLALLTB Z7.B, Z6.B, Z23.S // d7a82764
ZFMLALLTT Z7.B, Z6.B, Z23.S // d7b82764
- ZFMLALT Z7.B, Z6.B, Z23.H // d798a764
ZFMLALT Z7.H, Z6.H, Z23.S // d784a764
+ ZFMLALT Z7.B, Z6.B, Z23.H // d798a764
ZFMLS Z0.H, Z2.H, P0.M, Z14.H // 4e206065
ZFMLSLB Z7.H, Z6.H, Z23.S // d7a0a764
ZFMLSLT Z7.H, Z6.H, Z23.S // d7a4a764
@@ -259,8 +259,8 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZFMMLA Z7.B, Z6.B, Z23.H // d7e06764
ZFMMLA Z7.B, Z6.B, Z23.S // d7e02764
ZFMSB Z0.H, Z2.H, P0.M, Z14.H // 4ea06065
- ZFMUL Z7.D, Z23.D, Z13.D // ed0ac765
ZFMUL Z25.S, Z2.S, P1.M, Z2.S // 22878265
+ ZFMUL Z7.D, Z23.D, Z13.D // ed0ac765
ZFMULX Z25.S, Z2.S, P1.M, Z2.S // 22878a65
ZFNEG Z7.D, P4.M, Z13.D // edb0dd04
ZFNEG Z7.D, P4.Z, Z13.D // edb0cd04
@@ -274,33 +274,33 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZFRECPX Z7.D, P4.Z, Z13.D // ed90db64
ZFRINT32X Z7.D, P4.M, Z13.D // edb01365
ZFRINT32X Z7.D, P4.Z, Z13.D // edf01c64
- ZFRINT32Z Z7.D, P4.Z, Z13.D // edd01c64
ZFRINT32Z Z7.D, P4.M, Z13.D // edb01265
- ZFRINT64X Z7.D, P4.Z, Z13.D // edf01d64
+ ZFRINT32Z Z7.D, P4.Z, Z13.D // edd01c64
ZFRINT64X Z7.D, P4.M, Z13.D // edb01765
+ ZFRINT64X Z7.D, P4.Z, Z13.D // edf01d64
ZFRINT64Z Z7.D, P4.M, Z13.D // edb01665
ZFRINT64Z Z7.D, P4.Z, Z13.D // edd01d64
ZFRINTA Z7.D, P4.M, Z13.D // edb0c465
ZFRINTA Z7.D, P4.Z, Z13.D // ed90d964
- ZFRINTI Z7.D, P4.Z, Z13.D // edf0d964
ZFRINTI Z7.D, P4.M, Z13.D // edb0c765
- ZFRINTM Z7.D, P4.Z, Z13.D // edd0d864
+ ZFRINTI Z7.D, P4.Z, Z13.D // edf0d964
ZFRINTM Z7.D, P4.M, Z13.D // edb0c265
+ ZFRINTM Z7.D, P4.Z, Z13.D // edd0d864
ZFRINTN Z7.D, P4.M, Z13.D // edb0c065
ZFRINTN Z7.D, P4.Z, Z13.D // ed90d864
ZFRINTP Z7.D, P4.M, Z13.D // edb0c165
ZFRINTP Z7.D, P4.Z, Z13.D // edb0d864
- ZFRINTX Z7.D, P4.Z, Z13.D // edd0d964
ZFRINTX Z7.D, P4.M, Z13.D // edb0c665
+ ZFRINTX Z7.D, P4.Z, Z13.D // edd0d964
ZFRINTZ Z7.D, P4.M, Z13.D // edb0c365
ZFRINTZ Z7.D, P4.Z, Z13.D // edf0d864
ZFRSQRTE Z1.S, Z26.S // 3a308f65
ZFRSQRTS Z7.D, Z23.D, Z13.D // ed1ec765
ZFSCALE Z25.S, Z2.S, P1.M, Z2.S // 22878965
- ZFSQRT Z7.D, P4.Z, Z13.D // edb0db64
ZFSQRT Z7.D, P4.M, Z13.D // edb0cd65
- ZFSUB Z7.D, Z23.D, Z13.D // ed06c765
+ ZFSQRT Z7.D, P4.Z, Z13.D // edb0db64
ZFSUB Z25.S, Z2.S, P1.M, Z2.S // 22878165
+ ZFSUB Z7.D, Z23.D, Z13.D // ed06c765
ZFSUBR Z25.S, Z2.S, P1.M, Z2.S // 22878365
ZFTSMUL Z7.D, Z23.D, Z13.D // ed0ec765
ZFTSSEL Z7.D, Z23.D, Z13.D // edb2e704
@@ -312,8 +312,8 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZLSL Z7.D, Z6.H, Z13.H // cd8c6704
ZLSLR Z15.B, Z0.B, P3.M, Z0.B // e08d1704
ZLSR Z15.B, Z0.B, P3.M, Z0.B // e08d1104
- ZLSR Z7.D, Z6.H, Z13.H // cd846704
ZLSR Z2.D, Z10.D, P3.M, Z10.D // 4a8cd104
+ ZLSR Z7.D, Z6.H, Z13.H // cd846704
ZLSRR Z15.B, Z0.B, P3.M, Z0.B // e08d1504
ZMAD Z0.H, Z2.H, P0.M, Z14.H // 0ec04204
ZMADPT Z7.D, Z6.D, Z23.D // f7d8c644
@@ -324,8 +324,8 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZMOVPRFX Z7.D, P4.Z, Z21.D // f530d004
ZMOVPRFX Z11, Z6 // 66bd2004
ZMSB Z0.H, Z2.H, P0.M, Z14.H // 0ee04204
- ZMUL Z7.D, Z23.D, Z13.D // ed62e704
ZMUL Z15.B, Z0.B, P3.M, Z0.B // e00d1004
+ ZMUL Z7.D, Z23.D, Z13.D // ed62e704
ZNBSL Z23.D, Z13.D, Z21.D, Z21.D // f53eed04
ZNEG Z7.D, P4.M, Z13.D // edb0d704
ZNEG Z7.D, P4.Z, Z13.D // edb0c704
@@ -335,27 +335,27 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZORQV Z25.S, P3, V5.S4 // 252f9c04
ZORR Z15.B, Z0.B, P3.M, Z0.B // e00d1804
ZORR Z7.D, Z6.D, Z23.D // d7306704
- ZPMOV P14.B, Z6 // c6392b05
ZPMOV Z11, P0.B // 60392a05
+ ZPMOV P14.B, Z6 // c6392b05
ZPMUL Z7.B, Z6.B, Z23.B // d7642704
ZPMULLB Z8.B, Z4.B, Z30.H // 9e684845
ZPMULLB Z7.D, Z6.D, Z23.Q // d7680745
- ZPMULLT Z7.D, Z6.D, Z23.Q // d76c0745
ZPMULLT Z8.B, Z4.B, Z30.H // 9e6c4845
+ ZPMULLT Z7.D, Z6.D, Z23.Q // d76c0745
ZRADDHNB Z22.S, Z10.S, Z8.H // 4869b645
ZRADDHNT Z22.S, Z10.S, Z8.H // 486db645
ZRAX1 Z7.D, Z6.D, Z23.D // d7f42745
- ZRBIT Z7.D, P4.Z, Z13.D // edb0e705
ZRBIT Z7.D, P4.M, Z13.D // ed90e705
+ ZRBIT Z7.D, P4.Z, Z13.D // edb0e705
ZREV Z1.S, Z26.S // 3a38b805
- ZREVB Z7.D, P4.Z, Z13.D // edb0e405
ZREVB Z7.D, P4.M, Z13.D // ed90e405
+ ZREVB Z7.D, P4.Z, Z13.D // edb0e405
ZREVD Z13.Q, P1.M, Z22.Q // b6852e05
ZREVD Z13.Q, P1.Z, Z22.Q // b6a52e05
- ZREVH Z7.D, P4.Z, Z13.D // edb0e505
ZREVH Z7.D, P4.M, Z13.D // ed90e505
- ZREVW Z13.D, P1.Z, Z22.D // b6a5e605
+ ZREVH Z7.D, P4.Z, Z13.D // edb0e505
ZREVW Z13.D, P1.M, Z22.D // b685e605
+ ZREVW Z13.D, P1.Z, Z22.D // b6a5e605
ZRSUBHNB Z22.S, Z10.S, Z8.H // 4879b645
ZRSUBHNT Z22.S, Z10.S, Z8.H // 487db645
ZSABA Z7.D, Z23.D, Z13.D // edfac745
@@ -374,27 +374,27 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZSBCLB Z7.D, Z23.D, Z13.D // edd2c745
ZSBCLT Z7.D, Z23.D, Z13.D // edd6c745
ZSCLAMP Z7.D, Z23.D, Z13.D // edc2c744
- ZSCVTF Z13.S, P1.M, Z22.D // b6a5d065
// TODO: SCVTF <Zd>.<T>, <Zn>.<Tb>
- ZSCVTF Z13.D, P1.M, Z22.S // b6a5d465
- ZSCVTF Z13.D, P1.Z, Z22.S // b685dd64
- ZSCVTF Z13.D, P1.M, Z22.D // b6a5d665
- ZSCVTF Z13.D, P1.Z, Z22.D // b6c5dd64
+ ZSCVTF Z13.H, P1.M, Z22.H // b6a55265
ZSCVTF Z13.H, P1.Z, Z22.H // b6c55c64
ZSCVTF Z13.S, P1.M, Z22.H // b6a55465
ZSCVTF Z13.S, P1.Z, Z22.H // b6855d64
- ZSCVTF Z13.D, P1.Z, Z22.H // b6c55d64
- ZSCVTF Z13.D, P1.M, Z22.H // b6a55665
- ZSCVTF Z13.S, P1.Z, Z22.D // b685dc64
- ZSCVTF Z13.H, P1.M, Z22.H // b6a55265
- ZSCVTF Z13.S, P1.Z, Z22.S // b6859d64
ZSCVTF Z13.S, P1.M, Z22.S // b6a59465
+ ZSCVTF Z13.S, P1.Z, Z22.S // b6859d64
+ ZSCVTF Z13.S, P1.M, Z22.D // b6a5d065
+ ZSCVTF Z13.S, P1.Z, Z22.D // b685dc64
+ ZSCVTF Z13.D, P1.M, Z22.H // b6a55665
+ ZSCVTF Z13.D, P1.Z, Z22.H // b6c55d64
+ ZSCVTF Z13.D, P1.M, Z22.S // b6a5d465
+ ZSCVTF Z13.D, P1.Z, Z22.S // b685dd64
+ ZSCVTF Z13.D, P1.M, Z22.D // b6a5d665
+ ZSCVTF Z13.D, P1.Z, Z22.D // b6c5dd64
// TODO: SCVTFLT
ZSDIV Z25.S, Z2.S, P1.M, Z2.S // 22079404
ZSDIVR Z25.S, Z2.S, P1.M, Z2.S // 22079604
- ZSDOT Z15.B, Z0.B, Z12.S // 0c008f44
- ZSDOT Z7.H, Z6.H, Z23.S // d7c80744
// TODO: SDOT <Zda>.H, <Zn>.B, <Zm>.B
+ ZSDOT Z7.H, Z6.H, Z23.S // d7c80744
+ ZSDOT Z15.B, Z0.B, Z12.S // 0c008f44
ZSEL Z23.B, Z21.B, P14, Z2.B // a2fa3705
ZSHADD Z15.B, Z0.B, P3.M, Z0.B // e08d1044
ZSHSUB Z15.B, Z0.B, P3.M, Z0.B // e08d1244
@@ -412,15 +412,15 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZSMLSLB Z8.B, Z4.B, Z30.H // 9e504844
ZSMLSLT Z8.B, Z4.B, Z30.H // 9e544844
ZSMMLA Z7.B, Z6.B, Z23.S // d7980745
- ZSMULH Z7.D, Z23.D, Z13.D // ed6ae704
ZSMULH Z15.B, Z0.B, P3.M, Z0.B // e00d1204
+ ZSMULH Z7.D, Z23.D, Z13.D // ed6ae704
ZSMULLB Z8.B, Z4.B, Z30.H // 9e704845
ZSMULLT Z8.B, Z4.B, Z30.H // 9e744845
ZSPLICE Z15.B, Z0.B, P3, Z0.B // e08d2c05
ZSQABS Z7.D, P4.M, Z13.D // edb0c844
ZSQABS Z7.D, P4.Z, Z13.D // edb0ca44
- ZSQADD Z7.D, Z23.D, Z13.D // ed12e704
ZSQADD Z15.B, Z0.B, P3.M, Z0.B // e08d1844
+ ZSQADD Z7.D, Z23.D, Z13.D // ed12e704
ZSQDECP P14.S, Z26.S // da81aa25
ZSQDMLALB Z8.B, Z4.B, Z30.H // 9e604844
ZSQDMLALBT Z8.B, Z4.B, Z30.H // 9e084844
@@ -441,8 +441,8 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZSQRSHLR Z15.B, Z0.B, P3.M, Z0.B // e08d0e44
ZSQSHL Z15.B, Z0.B, P3.M, Z0.B // e08d0844
ZSQSHLR Z15.B, Z0.B, P3.M, Z0.B // e08d0c44
- ZSQSUB Z7.D, Z23.D, Z13.D // ed1ae704
ZSQSUB Z15.B, Z0.B, P3.M, Z0.B // e08d1a44
+ ZSQSUB Z7.D, Z23.D, Z13.D // ed1ae704
ZSQSUBR Z15.B, Z0.B, P3.M, Z0.B // e08d1e44
ZSQXTNB Z30.D, Z29.S // dd436045
ZSQXTNT Z30.D, Z29.S // dd476045
@@ -457,19 +457,19 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZSSUBLTB Z8.B, Z4.B, Z30.H // 9e8c4845
ZSSUBWB Z22.S, Z10.D, Z5.D // 4551d645
ZSSUBWT Z22.S, Z10.D, Z5.D // 4555d645
- ZSUB Z7.D, Z23.D, Z13.D // ed06e704
ZSUB Z15.B, Z0.B, P3.M, Z0.B // e00d0104
+ ZSUB Z7.D, Z23.D, Z13.D // ed06e704
ZSUBHNB Z22.S, Z10.S, Z8.H // 4871b645
ZSUBHNT Z22.S, Z10.S, Z8.H // 4875b645
// TODO: SUBP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
- ZSUBPT Z7.D, Z6.D, Z23.D // d70ce704
ZSUBPT Z23.D, Z13.D, P1.M, Z13.D // ed06c504
+ ZSUBPT Z7.D, Z6.D, Z23.D // d70ce704
ZSUBR Z15.B, Z0.B, P3.M, Z0.B // e00d0304
ZSUNPKHI Z15.B, Z0.H // e0397105
ZSUNPKLO Z15.B, Z0.H // e0397005
ZSUQADD Z15.B, Z0.B, P3.M, Z0.B // e08d1c44
- ZSXTB Z7.D, P4.Z, Z13.D // edb0c004
ZSXTB Z7.D, P4.M, Z13.D // edb0d004
+ ZSXTB Z7.D, P4.Z, Z13.D // edb0c004
ZSXTH Z7.D, P4.M, Z13.D // edb0d204
ZSXTH Z7.D, P4.Z, Z13.D // edb0c204
ZSXTW Z13.D, P1.M, Z22.D // b6a5d404
@@ -493,21 +493,21 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZUADDWB Z22.S, Z10.D, Z5.D // 4549d645
ZUADDWT Z22.S, Z10.D, Z5.D // 454dd645
ZUCLAMP Z7.D, Z23.D, Z13.D // edc6c744
- ZUCVTF Z13.D, P1.Z, Z22.S // b6a5dd64
- ZUCVTF Z13.D, P1.M, Z22.H // b6a55765
+ // TODO: UCVTF <Zd>.<T>, <Zn>.<Tb>
+ ZUCVTF Z13.H, P1.M, Z22.H // b6a55365
+ ZUCVTF Z13.H, P1.Z, Z22.H // b6e55c64
+ ZUCVTF Z13.S, P1.M, Z22.H // b6a55565
ZUCVTF Z13.S, P1.Z, Z22.H // b6a55d64
ZUCVTF Z13.S, P1.M, Z22.S // b6a59565
ZUCVTF Z13.S, P1.Z, Z22.S // b6a59d64
ZUCVTF Z13.S, P1.M, Z22.D // b6a5d165
ZUCVTF Z13.S, P1.Z, Z22.D // b6a5dc64
- ZUCVTF Z13.H, P1.M, Z22.H // b6a55365
+ ZUCVTF Z13.D, P1.M, Z22.H // b6a55765
ZUCVTF Z13.D, P1.Z, Z22.H // b6e55d64
ZUCVTF Z13.D, P1.M, Z22.S // b6a5d565
- ZUCVTF Z13.H, P1.Z, Z22.H // b6e55c64
+ ZUCVTF Z13.D, P1.Z, Z22.S // b6a5dd64
ZUCVTF Z13.D, P1.M, Z22.D // b6a5d765
ZUCVTF Z13.D, P1.Z, Z22.D // b6e5dd64
- ZUCVTF Z13.S, P1.M, Z22.H // b6a55565
- // TODO: UCVTF <Zd>.<T>, <Zn>.<Tb>
// TODO: UCVTFLT
ZUDIV Z25.S, Z2.S, P1.M, Z2.S // 22079504
ZUDIVR Z25.S, Z2.S, P1.M, Z2.S // 22079704
@@ -579,4 +579,127 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZZIP2 Z7.Q, Z6.Q, Z23.Q // d704a705
ZZIPQ1 Z7.D, Z23.D, Z13.D // ede2c744
ZZIPQ2 Z7.D, Z23.D, Z13.D // ede6c744
+ CTERMEQ ZR, R25 // 2023ff25
+ CTERMEQW ZR, R25 // 2023bf25
+ CTERMNE ZR, R25 // 3023ff25
+ CTERMNEW ZR, R25 // 3023bf25
+ PCNTP P2.B, P14, R2 // 42b82025
+ PDECP P14.S, ZR // df89ad25
+ PFIRSTP P2.B, P14, R2 // 42b82125
+ PINCP P14.S, ZR // df89ac25
+ PLASTP P2.B, P14, R2 // 42b82225
+ PSQDECP P14.S, ZR // df8daa25
+ PSQDECPW R8, P10.D, R8 // 4889ea25
+ PSQINCP P14.S, ZR // df8da825
+ PSQINCPW R8, P10.D, R8 // 4889e825
+ PUQDECP P14.S, ZR // df8dab25
+ PUQDECPW P14.S, ZR // df89ab25
+ PUQINCP P14.S, ZR // df8da925
+ PUQINCPW P14.S, ZR // df89a925
+ PWHILEGE R2, R10, P10.H // 4a116225
+ PWHILEGEW R2, R10, P10.H // 4a016225
+ PWHILEGT R2, R10, P10.H // 5a116225
+ PWHILEGTW R2, R10, P10.H // 5a016225
+ PWHILEHI R2, R10, P10.H // 5a196225
+ PWHILEHIW R2, R10, P10.H // 5a096225
+ PWHILEHS R2, R10, P10.H // 4a196225
+ PWHILEHSW R2, R10, P10.H // 4a096225
+ PWHILELE R2, R10, P10.H // 5a156225
+ PWHILELEW R2, R10, P10.H // 5a056225
+ PWHILELO R2, R10, P10.H // 4a1d6225
+ PWHILELOW R2, R10, P10.H // 4a0d6225
+ PWHILELS R2, R10, P10.H // 5a1d6225
+ PWHILELSW R2, R10, P10.H // 5a0d6225
+ PWHILELT R2, R10, P10.H // 4a156225
+ PWHILELTW R2, R10, P10.H // 4a056225
+ PWHILERW R2, R10, P10.H // 5a316225
+ PWHILEWR R2, R10, P10.H // 4a316225
+ ZANDVB Z6.B, P3, V2 // c22c1a04
+ ZANDVD Z10.D, P3, V15 // 4f2dda04
+ ZANDVH Z3.H, P1, V29 // 7d245a04
+ ZANDVS Z17.S, P1, V27 // 3b269a04
+ ZCLASTA Z9.D, R10, P2, R10 // 2aa9f005
+ ZCLASTAB Z2.B, V29, P1, V29 // 5d842a05
+ ZCLASTAD Z9.D, V10, P2, V10 // 2a89ea05
+ ZCLASTAH Z8.H, V15, P2, V15 // 0f896a05
+ ZCLASTAS Z26.S, V30, P7, V30 // 5e9faa05
+ ZCLASTAW Z8.H, R15, P2, R15 // 0fa97005
+ ZCLASTB Z9.D, R10, P2, R10 // 2aa9f105
+ ZCLASTBB Z2.B, V29, P1, V29 // 5d842b05
+ ZCLASTBD Z9.D, V10, P2, V10 // 2a89eb05
+ ZCLASTBH Z8.H, V15, P2, V15 // 0f896b05
+ ZCLASTBS Z26.S, V30, P7, V30 // 5e9fab05
+ ZCLASTBW Z8.H, R15, P2, R15 // 0fa97105
+ ZCPY R20, P1.M, Z2.D // 82a6e805
+ ZCPYB V4, P1.M, Z16.B // 90842005
+ ZCPYD V20, P1.M, Z2.D // 8286e005
+ ZCPYH V7, P6.M, Z23.H // f7986005
+ ZCPYS V13, P1.M, Z22.S // b685a005
+ ZCPYW RSP, P5.M, Z6.H // e6b76805
+ ZDUP R2, Z10.D // 4a38e005
+ ZDUPW R25, Z11.B // 2b3b2005
+ ZEORVB Z6.B, P3, V2 // c22c1904
+ ZEORVD Z10.D, P3, V15 // 4f2dd904
+ ZEORVH Z3.H, P1, V29 // 7d245904
+ ZEORVS Z17.S, P1, V27 // 3b269904
+ ZFADDAD Z9.D, V10, P2, V10 // 2a29d865
+ ZFADDAH Z8.H, V15, P2, V15 // 0f295865
+ ZFADDAS Z26.S, V30, P7, V30 // 5e3f9865
+ ZFADDVD Z10.D, P3, V15 // 4f2dc065
+ ZFADDVH Z3.H, P1, V29 // 7d244065
+ ZFADDVS Z17.S, P1, V27 // 3b268065
+ ZFMAXNMVD Z10.D, P3, V15 // 4f2dc465
+ ZFMAXNMVH Z3.H, P1, V29 // 7d244465
+ ZFMAXNMVS Z17.S, P1, V27 // 3b268465
+ ZFMAXVD Z10.D, P3, V15 // 4f2dc665
+ ZFMAXVH Z3.H, P1, V29 // 7d244665
+ ZFMAXVS Z17.S, P1, V27 // 3b268665
+ ZFMINNMVD Z10.D, P3, V15 // 4f2dc565
+ ZFMINNMVH Z3.H, P1, V29 // 7d244565
+ ZFMINNMVS Z17.S, P1, V27 // 3b268565
+ ZFMINVD Z10.D, P3, V15 // 4f2dc765
+ ZFMINVH Z3.H, P1, V29 // 7d244765
+ ZFMINVS Z17.S, P1, V27 // 3b268765
+ ZINDEX R13, R20, Z9.D // 894eed04
+ ZINDEXW R2, R10, Z8.H // 484d6204
+ ZINSR R2, Z10.D // 4a38e405
+ ZINSRB V25, Z11.B // 2b3b3405
+ ZINSRD V2, Z10.D // 4a38f405
+ ZINSRH V7, Z6.H // e6387405
+ ZINSRS V14, Z8.S // c839b405
+ ZINSRW R25, Z11.B // 2b3b2405
+ ZLASTA Z10.D, P3, R15 // 4fade005
+ ZLASTAB Z6.B, P3, V2 // c28c2205
+ ZLASTAD Z10.D, P3, V15 // 4f8de205
+ ZLASTAH Z3.H, P1, V29 // 7d846205
+ ZLASTAS Z17.S, P1, V27 // 3b86a205
+ ZLASTAW Z6.B, P3, R2 // c2ac2005
+ ZLASTB Z10.D, P3, R15 // 4fade105
+ ZLASTBB Z6.B, P3, V2 // c28c2305
+ ZLASTBD Z10.D, P3, V15 // 4f8de305
+ ZLASTBH Z3.H, P1, V29 // 7d846305
+ ZLASTBS Z17.S, P1, V27 // 3b86a305
+ ZLASTBW Z6.B, P3, R2 // c2ac2105
+ ZORVB Z6.B, P3, V2 // c22c1804
+ ZORVD Z10.D, P3, V15 // 4f2dd804
+ ZORVH Z3.H, P1, V29 // 7d245804
+ ZORVS Z17.S, P1, V27 // 3b269804
+ ZSADDVD Z6.B, P3, V2 // c22c0004
+ ZSMAXVB Z6.B, P3, V2 // c22c0804
+ ZSMAXVD Z10.D, P3, V15 // 4f2dc804
+ ZSMAXVH Z3.H, P1, V29 // 7d244804
+ ZSMAXVS Z17.S, P1, V27 // 3b268804
+ ZSMINVB Z6.B, P3, V2 // c22c0a04
+ ZSMINVD Z10.D, P3, V15 // 4f2dca04
+ ZSMINVH Z3.H, P1, V29 // 7d244a04
+ ZSMINVS Z17.S, P1, V27 // 3b268a04
+ ZUADDVD Z10.D, P3, V15 // 4f2dc104
+ ZUMAXVB Z6.B, P3, V2 // c22c0904
+ ZUMAXVD Z10.D, P3, V15 // 4f2dc904
+ ZUMAXVH Z3.H, P1, V29 // 7d244904
+ ZUMAXVS Z17.S, P1, V27 // 3b268904
+ ZUMINVB Z6.B, P3, V2 // c22c0b04
+ ZUMINVD Z10.D, P3, V15 // 4f2dcb04
+ ZUMINVH Z3.H, P1, V29 // 7d244b04
+ ZUMINVS Z17.S, P1, V27 // 3b268b04
RET
diff --git a/src/cmd/asm/internal/asm/testdata/arm64sveerror.s b/src/cmd/asm/internal/asm/testdata/arm64sveerror.s
index edb21051a5..83b9a1b0b7 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64sveerror.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64sveerror.s
@@ -34,8 +34,8 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
PPTRUE PN5.D // ERROR "illegal combination from SVE"
PPUNPKHI P14.S, P13.S // ERROR "illegal combination from SVE"
PPUNPKLO P14.S, P13.S // ERROR "illegal combination from SVE"
- PRDFFR P14.S // ERROR "illegal combination from SVE"
PRDFFR P14.Z, P13.S // ERROR "illegal combination from SVE"
+ PRDFFR P14.S // ERROR "illegal combination from SVE"
PRDFFRS P14.Z, P13.S // ERROR "illegal combination from SVE"
PREV P14.B, P5.D // ERROR "illegal combination from SVE"
PSEL P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE"
@@ -50,13 +50,13 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZABS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZADCLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZADCLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
- ZADD Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
+ ZADD Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZADDHNB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZADDHNT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZADDP Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
- ZADDPT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZADDPT Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
+ ZADDPT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
// TODO: ADDQP
ZADDQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE"
// TODO: ADDSUBP
@@ -67,9 +67,9 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZAND Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZAND Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZANDQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE"
- ZASR Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZASR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZASR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
+ ZASR Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZASRR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZBCAX Z1.S, Z26.S, Z11.B, Z7.D // ERROR "illegal combination from SVE"
ZBDEP Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
@@ -78,8 +78,8 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZBF1CVTLT Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZBF2CVT Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZBF2CVTLT Z1.S, Z26.S // ERROR "illegal combination from SVE"
- ZBFADD Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZBFADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
+ ZBFADD Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZBFCLAMP Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZBFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZBFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
@@ -101,8 +101,8 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZBFMUL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZBFMUL Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZBFSCALE Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
- ZBFSUB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZBFSUB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
+ ZBFSUB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZBGRP Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZBIC Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZBIC Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
@@ -138,8 +138,8 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZCOMPACT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZCOMPACT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZDECP P14.B, Z7.D // ERROR "illegal combination from SVE"
- ZEOR Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZEOR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
+ ZEOR Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZEOR3 Z1.S, Z26.S, Z11.B, Z7.D // ERROR "illegal combination from SVE"
ZEORBT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZEORQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE"
@@ -251,15 +251,15 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZFMLS Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFMLSLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFMLSLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
+ // TODO: FMMLA <Zda>.H, <Zn>.H, <Zm>.H
ZFMMLA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFMMLA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFMMLA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFMMLA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFMMLA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
- // TODO: FMMLA <Zda>.H, <Zn>.H, <Zm>.H
ZFMSB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
- ZFMUL Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFMUL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
+ ZFMUL Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFMULX Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFNEG Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFNEG Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
@@ -306,13 +306,13 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZHISTCNT Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZHISTSEG Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZINCP P14.B, Z7.D // ERROR "illegal combination from SVE"
- ZLSL Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZLSL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZLSL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
+ ZLSL Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZLSLR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
- ZLSR Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZLSR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZLSR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
+ ZLSR Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZLSRR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZMAD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZMADPT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
@@ -323,8 +323,8 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZMOVPRFX Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZMOVPRFX Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZMSB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
- ZMUL Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZMUL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
+ ZMUL Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZNBSL Z1.S, Z26.S, Z11.B, Z7.D // ERROR "illegal combination from SVE"
ZNEG Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZNEG Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
@@ -334,8 +334,8 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZORQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE"
ZORR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZORR Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
- ZPMOV P14.S, Z26.S // ERROR "illegal combination from SVE"
ZPMOV Z1.S, P13.S // ERROR "illegal combination from SVE"
+ ZPMOV P14.S, Z26.S // ERROR "illegal combination from SVE"
ZPMUL Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZPMULLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZPMULLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
@@ -373,6 +373,7 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZSBCLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSBCLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSCLAMP Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
+ // TODO: SCVTF <Zd>.<T>, <Zn>.<Tb>
ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
@@ -380,7 +381,6 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
- // TODO: SCVTF <Zd>.<T>, <Zn>.<Tb>
ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
@@ -391,9 +391,9 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
// TODO: SCVTFLT
ZSDIV Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSDIVR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
+ // TODO: SDOT <Zda>.H, <Zn>.B, <Zm>.B
ZSDOT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSDOT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
- // TODO: SDOT <Zda>.H, <Zn>.B, <Zm>.B
ZSEL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSHADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSHSUB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
@@ -411,15 +411,15 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZSMLSLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSMLSLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSMMLA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
- ZSMULH Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSMULH Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
+ ZSMULH Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSMULLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSMULLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSPLICE Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSQABS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSQABS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
- ZSQADD Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSQADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
+ ZSQADD Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSQDECP P14.B, Z7.D // ERROR "illegal combination from SVE"
ZSQDMLALB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSQDMLALBT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
@@ -440,8 +440,8 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZSQRSHLR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSQSHL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSQSHLR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
- ZSQSUB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSQSUB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
+ ZSQSUB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSQSUBR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSQXTNB Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZSQXTNT Z1.S, Z26.S // ERROR "illegal combination from SVE"
@@ -456,13 +456,13 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZSSUBLTB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSSUBWB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSSUBWT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
- ZSUB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSUB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
+ ZSUB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSUBHNB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSUBHNT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
// TODO: SUBP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
- ZSUBPT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSUBPT Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
+ ZSUBPT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSUBR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSUNPKHI Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZSUNPKLO Z1.S, Z26.S // ERROR "illegal combination from SVE"
@@ -492,6 +492,7 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZUADDWB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUADDWT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUCLAMP Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
+ // TODO: UCVTF <Zd>.<T>, <Zn>.<Tb>
ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
@@ -506,7 +507,6 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
- // TODO: UCVTF <Zd>.<T>, <Zn>.<Tb>
// TODO: UCVTFLT
ZUDIV Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZUDIVR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
@@ -578,4 +578,127 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZZIP2 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZZIPQ1 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZZIPQ2 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
+ CTERMEQ RSP, R27 // ERROR "illegal combination from SVE"
+ CTERMEQW RSP, R27 // ERROR "illegal combination from SVE"
+ CTERMNE RSP, R27 // ERROR "illegal combination from SVE"
+ CTERMNEW RSP, R27 // ERROR "illegal combination from SVE"
+ PCNTP P14.S, P13.Z, R11 // ERROR "illegal combination from SVE"
+ PDECP P7.Q, RSP // ERROR "illegal combination from SVE"
+ PFIRSTP P14.S, P13.Z, R11 // ERROR "illegal combination from SVE"
+ PINCP P7.Q, RSP // ERROR "illegal combination from SVE"
+ PLASTP P14.S, P13.Z, R11 // ERROR "illegal combination from SVE"
+ PSQDECP P7.Q, RSP // ERROR "illegal combination from SVE"
+ PSQDECPW RSP, P7.Q, R25 // ERROR "illegal combination from SVE"
+ PSQINCP P7.Q, RSP // ERROR "illegal combination from SVE"
+ PSQINCPW RSP, P7.Q, R25 // ERROR "illegal combination from SVE"
+ PUQDECP P7.Q, RSP // ERROR "illegal combination from SVE"
+ PUQDECPW P7.Q, RSP // ERROR "illegal combination from SVE"
+ PUQINCP P7.Q, RSP // ERROR "illegal combination from SVE"
+ PUQINCPW P7.Q, RSP // ERROR "illegal combination from SVE"
+ PWHILEGE RSP, R27, P13.S // ERROR "illegal combination from SVE"
+ PWHILEGEW RSP, R27, P13.S // ERROR "illegal combination from SVE"
+ PWHILEGT RSP, R27, P13.S // ERROR "illegal combination from SVE"
+ PWHILEGTW RSP, R27, P13.S // ERROR "illegal combination from SVE"
+ PWHILEHI RSP, R27, P13.S // ERROR "illegal combination from SVE"
+ PWHILEHIW RSP, R27, P13.S // ERROR "illegal combination from SVE"
+ PWHILEHS RSP, R27, P13.S // ERROR "illegal combination from SVE"
+ PWHILEHSW RSP, R27, P13.S // ERROR "illegal combination from SVE"
+ PWHILELE RSP, R27, P13.S // ERROR "illegal combination from SVE"
+ PWHILELEW RSP, R27, P13.S // ERROR "illegal combination from SVE"
+ PWHILELO RSP, R27, P13.S // ERROR "illegal combination from SVE"
+ PWHILELOW RSP, R27, P13.S // ERROR "illegal combination from SVE"
+ PWHILELS RSP, R27, P13.S // ERROR "illegal combination from SVE"
+ PWHILELSW RSP, R27, P13.S // ERROR "illegal combination from SVE"
+ PWHILELT RSP, R27, P13.S // ERROR "illegal combination from SVE"
+ PWHILELTW RSP, R27, P13.S // ERROR "illegal combination from SVE"
+ PWHILERW RSP, R27, P13.S // ERROR "illegal combination from SVE"
+ PWHILEWR RSP, R27, P13.S // ERROR "illegal combination from SVE"
+ ZANDVB Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZANDVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZANDVH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZANDVS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZCLASTA Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE"
+ ZCLASTAB Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE"
+ ZCLASTAD Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE"
+ ZCLASTAH Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE"
+ ZCLASTAS Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE"
+ ZCLASTAW Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE"
+ ZCLASTB Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE"
+ ZCLASTBB Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE"
+ ZCLASTBD Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE"
+ ZCLASTBH Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE"
+ ZCLASTBS Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE"
+ ZCLASTBW Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE"
+ ZCPY RSP, P7.M, Z25.Q // ERROR "illegal combination from SVE"
+ ZCPYB RSP, P7.M, Z25.Q // ERROR "illegal combination from SVE"
+ ZCPYD RSP, P7.M, Z25.Q // ERROR "illegal combination from SVE"
+ ZCPYH RSP, P7.M, Z25.Q // ERROR "illegal combination from SVE"
+ ZCPYS RSP, P7.M, Z25.Q // ERROR "illegal combination from SVE"
+ ZCPYW RSP, P7.M, Z25.Q // ERROR "illegal combination from SVE"
+ ZDUP RSP, Z27.Q // ERROR "illegal combination from SVE"
+ ZDUPW RSP, Z27.Q // ERROR "illegal combination from SVE"
+ ZEORVB Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZEORVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZEORVH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZEORVS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZFADDAD Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE"
+ ZFADDAH Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE"
+ ZFADDAS Z1.S, ZR, P7.Z, RSP // ERROR "illegal combination from SVE"
+ ZFADDVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZFADDVH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZFADDVS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZFMAXNMVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZFMAXNMVH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZFMAXNMVS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZFMAXVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZFMAXVH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZFMAXVS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZFMINNMVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZFMINNMVH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZFMINNMVS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZFMINVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZFMINVH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZFMINVS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZINDEX RSP, R27, Z26.S // ERROR "illegal combination from SVE"
+ ZINDEXW RSP, R27, Z26.S // ERROR "illegal combination from SVE"
+ ZINSR RSP, Z27.Q // ERROR "illegal combination from SVE"
+ ZINSRB RSP, Z27.Q // ERROR "illegal combination from SVE"
+ ZINSRD RSP, Z27.Q // ERROR "illegal combination from SVE"
+ ZINSRH RSP, Z27.Q // ERROR "illegal combination from SVE"
+ ZINSRS RSP, Z27.Q // ERROR "illegal combination from SVE"
+ ZINSRW RSP, Z27.Q // ERROR "illegal combination from SVE"
+ ZLASTA Z1.S, P13.Z, R11 // ERROR "illegal combination from SVE"
+ ZLASTAB Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZLASTAD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZLASTAH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZLASTAS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZLASTAW Z1.S, P13.Z, R11 // ERROR "illegal combination from SVE"
+ ZLASTB Z1.S, P13.Z, R11 // ERROR "illegal combination from SVE"
+ ZLASTBB Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZLASTBD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZLASTBH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZLASTBS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZLASTBW Z1.S, P13.Z, R11 // ERROR "illegal combination from SVE"
+ ZORVB Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZORVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZORVH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZORVS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZSADDVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZSMAXVB Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZSMAXVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZSMAXVH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZSMAXVS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZSMINVB Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZSMINVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZSMINVH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZSMINVS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZUADDVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZUMAXVB Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZUMAXVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZUMAXVH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZUMAXVS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZUMINVB Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZUMINVD Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZUMINVH Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
+ ZUMINVS Z1.S, P13.Z, V11 // ERROR "illegal combination from SVE"
RET
diff --git a/src/cmd/internal/obj/arm64/a.out.go b/src/cmd/internal/obj/arm64/a.out.go
index f6ef1681f2..72e0d519d7 100644
--- a/src/cmd/internal/obj/arm64/a.out.go
+++ b/src/cmd/internal/obj/arm64/a.out.go
@@ -614,18 +614,18 @@ type AClass uint16 // operand type
// [insts] is sorted based on the order of these constants and the first match is chosen.
const (
- AC_NONE AClass = iota
- AC_REG // general purpose registers R0..R30 and ZR
- AC_RSP // general purpose registers R0..R30 and RSP
- AC_VREG // vector registers, such as V1
- AC_ZREG // the scalable vector registers, such as Z1
- AC_PREG // the scalable predicate registers, such as P1
- AC_PREGZM // Pg.Z or Pg.M
- AC_REGIDX // P8[1]
- AC_ZREGIDX // Z1[1]
- AC_PREGIDX // P0[R1, 1]
- AC_ARNG // vector register with arrangement, such as Z1.D
- AC_ARNGIDX // vector register with arrangement and index, such as Z1.D[1]
+ AC_NONE AClass = iota
+ // TODO: probably make this AClass split into AC_REG (R0...R30), AC_RSP (R0...R30, RSP), AC_ZR (R0...R30, ZR).
+ AC_SPZGREG // general purpose registers R0..R30 and RSP and ZR
+ AC_VREG // vector registers, such as V1
+ AC_ZREG // the scalable vector registers, such as Z1
+ AC_PREG // the scalable predicate registers, such as P1
+ AC_PREGZM // Pg.Z or Pg.M
+ AC_REGIDX // P8[1]
+ AC_ZREGIDX // Z1[1]
+ AC_PREGIDX // P0[R1, 1]
+ AC_ARNG // vector register with arrangement, such as Z1.D
+ AC_ARNGIDX // vector register with arrangement and index, such as Z1.D[1]
AC_IMM // constants
diff --git a/src/cmd/internal/obj/arm64/anames_gen.go b/src/cmd/internal/obj/arm64/anames_gen.go
index c7b8a17664..b929487b3c 100644
--- a/src/cmd/internal/obj/arm64/anames_gen.go
+++ b/src/cmd/internal/obj/arm64/anames_gen.go
@@ -4,6 +4,10 @@ package arm64
var sveAnames = []string{
"SVESTART",
+ "CTERMEQ",
+ "CTERMEQW",
+ "CTERMNE",
+ "CTERMNEW",
"PAND",
"PANDS",
"PBIC",
@@ -18,8 +22,13 @@ var sveAnames = []string{
"PBRKPAS",
"PBRKPB",
"PBRKPBS",
+ "PCNTP",
+ "PDECP",
"PEOR",
"PEORS",
+ "PFIRSTP",
+ "PINCP",
+ "PLASTP",
"PNAND",
"PNANDS",
"PNOR",
@@ -39,10 +48,36 @@ var sveAnames = []string{
"PRDFFRS",
"PREV",
"PSEL",
+ "PSQDECP",
+ "PSQDECPW",
+ "PSQINCP",
+ "PSQINCPW",
"PTRN1",
"PTRN2",
+ "PUQDECP",
+ "PUQDECPW",
+ "PUQINCP",
+ "PUQINCPW",
"PUZP1",
"PUZP2",
+ "PWHILEGE",
+ "PWHILEGEW",
+ "PWHILEGT",
+ "PWHILEGTW",
+ "PWHILEHI",
+ "PWHILEHIW",
+ "PWHILEHS",
+ "PWHILEHSW",
+ "PWHILELE",
+ "PWHILELEW",
+ "PWHILELO",
+ "PWHILELOW",
+ "PWHILELS",
+ "PWHILELSW",
+ "PWHILELT",
+ "PWHILELTW",
+ "PWHILERW",
+ "PWHILEWR",
"PWRFFR",
"PZIP1",
"PZIP2",
@@ -64,6 +99,10 @@ var sveAnames = []string{
"ZAESMC",
"ZAND",
"ZANDQV",
+ "ZANDVB",
+ "ZANDVD",
+ "ZANDVH",
+ "ZANDVS",
"ZASR",
"ZASRR",
"ZBCAX",
@@ -98,7 +137,17 @@ var sveAnames = []string{
"ZBSL1N",
"ZBSL2N",
"ZCLASTA",
+ "ZCLASTAB",
+ "ZCLASTAD",
+ "ZCLASTAH",
+ "ZCLASTAS",
+ "ZCLASTAW",
"ZCLASTB",
+ "ZCLASTBB",
+ "ZCLASTBD",
+ "ZCLASTBH",
+ "ZCLASTBS",
+ "ZCLASTBW",
"ZCLS",
"ZCLZ",
"ZCMPEQ",
@@ -114,12 +163,24 @@ var sveAnames = []string{
"ZCNOT",
"ZCNT",
"ZCOMPACT",
+ "ZCPY",
+ "ZCPYB",
+ "ZCPYD",
+ "ZCPYH",
+ "ZCPYS",
+ "ZCPYW",
"ZDECP",
+ "ZDUP",
+ "ZDUPW",
"ZEOR",
"ZEOR3",
"ZEORBT",
"ZEORQV",
"ZEORTB",
+ "ZEORVB",
+ "ZEORVD",
+ "ZEORVH",
+ "ZEORVS",
"ZEXPAND",
"ZF1CVT",
"ZF1CVTLT",
@@ -130,8 +191,14 @@ var sveAnames = []string{
"ZFACGE",
"ZFACGT",
"ZFADD",
+ "ZFADDAD",
+ "ZFADDAH",
+ "ZFADDAS",
"ZFADDP",
"ZFADDQV",
+ "ZFADDVD",
+ "ZFADDVH",
+ "ZFADDVS",
"ZFAMAX",
"ZFAMIN",
"ZFCLAMP",
@@ -157,14 +224,26 @@ var sveAnames = []string{
"ZFMAXNM",
"ZFMAXNMP",
"ZFMAXNMQV",
+ "ZFMAXNMVD",
+ "ZFMAXNMVH",
+ "ZFMAXNMVS",
"ZFMAXP",
"ZFMAXQV",
+ "ZFMAXVD",
+ "ZFMAXVH",
+ "ZFMAXVS",
"ZFMIN",
"ZFMINNM",
"ZFMINNMP",
"ZFMINNMQV",
+ "ZFMINNMVD",
+ "ZFMINNMVH",
+ "ZFMINNMVS",
"ZFMINP",
"ZFMINQV",
+ "ZFMINVD",
+ "ZFMINVH",
+ "ZFMINVS",
"ZFMLA",
"ZFMLALB",
"ZFMLALLBB",
@@ -209,6 +288,26 @@ var sveAnames = []string{
"ZHISTCNT",
"ZHISTSEG",
"ZINCP",
+ "ZINDEX",
+ "ZINDEXW",
+ "ZINSR",
+ "ZINSRB",
+ "ZINSRD",
+ "ZINSRH",
+ "ZINSRS",
+ "ZINSRW",
+ "ZLASTA",
+ "ZLASTAB",
+ "ZLASTAD",
+ "ZLASTAH",
+ "ZLASTAS",
+ "ZLASTAW",
+ "ZLASTB",
+ "ZLASTBB",
+ "ZLASTBD",
+ "ZLASTBH",
+ "ZLASTBS",
+ "ZLASTBW",
"ZLSL",
"ZLSLR",
"ZLSR",
@@ -228,6 +327,10 @@ var sveAnames = []string{
"ZNOT",
"ZORQV",
"ZORR",
+ "ZORVB",
+ "ZORVD",
+ "ZORVH",
+ "ZORVS",
"ZPMOV",
"ZPMUL",
"ZPMULLB",
@@ -254,6 +357,7 @@ var sveAnames = []string{
"ZSADDLB",
"ZSADDLBT",
"ZSADDLT",
+ "ZSADDVD",
"ZSADDWB",
"ZSADDWT",
"ZSBCLB",
@@ -273,9 +377,17 @@ var sveAnames = []string{
"ZSMAX",
"ZSMAXP",
"ZSMAXQV",
+ "ZSMAXVB",
+ "ZSMAXVD",
+ "ZSMAXVH",
+ "ZSMAXVS",
"ZSMIN",
"ZSMINP",
"ZSMINQV",
+ "ZSMINVB",
+ "ZSMINVD",
+ "ZSMINVH",
+ "ZSMINVS",
"ZSMLALB",
"ZSMLALT",
"ZSMLSLB",
@@ -347,6 +459,7 @@ var sveAnames = []string{
"ZUADALP",
"ZUADDLB",
"ZUADDLT",
+ "ZUADDVD",
"ZUADDWB",
"ZUADDWT",
"ZUCLAMP",
@@ -361,9 +474,17 @@ var sveAnames = []string{
"ZUMAX",
"ZUMAXP",
"ZUMAXQV",
+ "ZUMAXVB",
+ "ZUMAXVD",
+ "ZUMAXVH",
+ "ZUMAXVS",
"ZUMIN",
"ZUMINP",
"ZUMINQV",
+ "ZUMINVB",
+ "ZUMINVD",
+ "ZUMINVH",
+ "ZUMINVS",
"ZUMLALB",
"ZUMLALT",
"ZUMLSLB",
diff --git a/src/cmd/internal/obj/arm64/encoding_gen.go b/src/cmd/internal/obj/arm64/encoding_gen.go
index e15f9b67fb..3885c8d534 100644
--- a/src/cmd/internal/obj/arm64/encoding_gen.go
+++ b/src/cmd/internal/obj/arm64/encoding_gen.go
@@ -14,7 +14,14 @@ const (
enc_Pm
enc_Pn
enc_Pv
+ enc_Rd
+ enc_Rdn
+ enc_Rm
+ enc_Rn
enc_Vd
+ enc_Vdn
+ enc_Vm
+ enc_Vn
enc_Za
enc_Zd
enc_Zda
@@ -206,12 +213,75 @@ func encodeSize8H4S2D(v uint32) (uint32, bool) {
return 0, false
}
+// encodeWdn05 is the implementation of the following encoding logic:
+// Is the 32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
+// bit range mappings:
+// Rdn: [0:5)
+func encodeWdn05(v uint32) (uint32, bool) {
+ if v == REG_RSP {
+ return 0, false
+ }
+ return v & 31, true
+}
+
+// encodeVd0564 is the implementation of the following encoding logic:
+// Is the 64-bit name of the destination SIMD&FP register, encoded in the "Vd" field.
+// bit range mappings:
+// Vd: [0:5)
+func encodeVd0564(v uint32) (uint32, bool) {
+ return v & 31, true
+}
+
+// encodeRd05 is the implementation of the following encoding logic:
+// Is the 64-bit name of the destination general-purpose register, encoded in the "Rd" field.
+// bit range mappings:
+// Rd: [0:5)
+func encodeRd05(v uint32) (uint32, bool) {
+ if v == REG_RSP {
+ return 0, false
+ }
+ return v & 31, true
+}
+
+// encodeRn510 is the implementation of the following encoding logic:
+// Is the 64-bit name of the first source general-purpose register, encoded in the "Rn" field.
+// bit range mappings:
+// Rn: [5:10)
+func encodeRn510(v uint32) (uint32, bool) {
+ if v == REG_RSP {
+ return 0, false
+ }
+ return (v & 31) << 5, true
+}
+
+// encodeRm1621 is the implementation of the following encoding logic:
+// Is the 64-bit name of the second source general-purpose register, encoded in the "Rm" field.
+// bit range mappings:
+// Rm: [16:21)
+func encodeRm1621(v uint32) (uint32, bool) {
+ if v == REG_RSP {
+ return 0, false
+ }
+ return (v & 31) << 16, true
+}
+
+// encodeXdn05 is the implementation of the following encoding logic:
+// Is the 64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
+// bit range mappings:
+// Rdn: [0:5)
+func encodeXdn05(v uint32) (uint32, bool) {
+ if v == REG_RSP {
+ return 0, false
+ }
+ return v & 31, true
+}
+
// encodeVd is the implementation of the following encoding logic:
// Is the name of the destination SIMD&FP register, encoded in the "Vd" field.
// bit range mappings:
// Vd: [0:5)
func encodeVd(v uint32) (uint32, bool) {
- return v, true
+ return v & 31, true
}
// encodePNd is the implementation of the following encoding logic:
@@ -333,12 +403,12 @@ func encodeZm1621(v uint32) (uint32, bool) {
return v << 16, true
}
-// encodeZm510 is the implementation of the following encoding logic:
+// encodeZm510V1 is the implementation of the following encoding logic:
// Is the name of the second source scalable vector register, encoded in the "Zm" field.
// bit range mappings:
// Zm: [5:10)
-func encodeZm510(v uint32) (uint32, bool) {
- return v << 5, true
+func encodeZm510V1(v uint32) (uint32, bool) {
+ return (v & 31) << 5, true
}
// encodePdnSrcDst is the implementation of the following encoding logic:
@@ -373,12 +443,20 @@ func encodePn59v2(v uint32) (uint32, bool) {
return v << 5, true
}
+// encodeZm510V2 is the implementation of the following encoding logic:
+// Is the name of the source scalable vector register, encoded in the "Zm" field.
+// bit range mappings:
+// Zm: [5:10)
+func encodeZm510V2(v uint32) (uint32, bool) {
+ return (v & 31) << 5, true
+}
+
// encodeZn510Src is the implementation of the following encoding logic:
// Is the name of the source scalable vector register, encoded in the "Zn" field.
// bit range mappings:
// Zn: [5:10)
func encodeZn510Src(v uint32) (uint32, bool) {
- return v << 5, true
+ return (v & 31) << 5, true
}
// encodeZda3RdSrcDst is the implementation of the following encoding logic:
@@ -437,6 +515,108 @@ func encodePv59(v uint32) (uint32, bool) {
return v << 5, true
}
+// encodeRd05ZR is the implementation of the following encoding logic:
+// Is the number [0-30] of the destination general-purpose register or the name ZR (31), encoded in the "Rd" field.
+// bit range mappings:
+// Rd: [0:5)
+func encodeRd05ZR(v uint32) (uint32, bool) {
+ if v == REG_RSP {
+ return 0, false
+ }
+ // ZR is just R31
+ return v & 31, true
+}
+
+// encodeRn510SP is the implementation of the following encoding logic:
+// Is the number [0-30] of the general-purpose source register or the name SP (31), encoded in the "Rn" field.
+// bit range mappings:
+// Rn: [5:10)
+func encodeRn510SP(v uint32) (uint32, bool) {
+ if v == REG_R31 {
+ return 0, false
+ }
+ if v == REG_RSP {
+ return (REG_R31 & 31) << 5, true
+ }
+ return (v & 31) << 5, true
+}
+
+// encodeRdn05ZR is the implementation of the following encoding logic:
+// Is the number [0-30] of the source and destination general-purpose register or the name ZR (31), encoded in the "Rdn" field.
+// bit range mappings:
+// Rdn: [0:5)
+func encodeRdn05ZR(v uint32) (uint32, bool) {
+ if v == REG_RSP {
+ return 0, false
+ }
+ return v & 31, true
+}
+
+// encodeRm1621ZR is the implementation of the following encoding logic:
+// Is the number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field.
+// bit range mappings:
+// Rm: [16:21)
+func encodeRm1621ZR(v uint32) (uint32, bool) {
+ if v == REG_RSP {
+ return 0, false
+ }
+ return (v & 31) << 16, true
+}
+
+// encodeRm510ZR is the implementation of the following encoding logic:
+// Is the number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field.
+// bit range mappings:
+// Rm: [5:10)
+func encodeRm510ZR(v uint32) (uint32, bool) {
+ if v == REG_RSP {
+ return 0, false
+ }
+ return (v & 31) << 5, true
+}
+
+// encodeRn510ZR is the implementation of the following encoding logic:
+// Is the number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rn" field.
+// bit range mappings:
+// Rn: [5:10)
+func encodeRn510ZR(v uint32) (uint32, bool) {
+ if v == REG_RSP {
+ return 0, false
+ }
+ return (v & 31) << 5, true
+}
+
+// encodeVd05 is the implementation of the following encoding logic:
+// Is the number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field.
+// bit range mappings:
+// Vd: [0:5)
+func encodeVd05(v uint32) (uint32, bool) {
+ return v & 31, true
+}
+
+// encodeVm510 is the implementation of the following encoding logic:
+// Is the number [0-31] of the source SIMD&FP register, encoded in the "Vm" field.
+// bit range mappings:
+// Vm: [5:10)
+func encodeVm510(v uint32) (uint32, bool) {
+ return (v & 31) << 5, true
+}
+
+// encodeVn510 is the implementation of the following encoding logic:
+// Is the number [0-31] of the source SIMD&FP register, encoded in the "Vn" field.
+// bit range mappings:
+// Vn: [5:10)
+func encodeVn510(v uint32) (uint32, bool) {
+ return (v & 31) << 5, true
+}
+
+// encodeVdn05 is the implementation of the following encoding logic:
+// Is the number [0-31] of the source and destination SIMD&FP register, encoded in the "Vdn" field.
+// bit range mappings:
+// Vdn: [0:5)
+func encodeVdn05(v uint32) (uint32, bool) {
+ return v & 31, true
+}
+
// encodePredQualM1617 is the implementation of the following encoding logic:
// Is the predication qualifier,
// M <ZM>
diff --git a/src/cmd/internal/obj/arm64/goops_gen.go b/src/cmd/internal/obj/arm64/goops_gen.go
index 52ce71d744..2f1a475e04 100644
--- a/src/cmd/internal/obj/arm64/goops_gen.go
+++ b/src/cmd/internal/obj/arm64/goops_gen.go
@@ -5,7 +5,11 @@ package arm64
import "cmd/internal/obj"
const (
- APAND obj.As = ASVESTART + 1 + iota
+ ACTERMEQ obj.As = ASVESTART + 1 + iota
+ ACTERMEQW
+ ACTERMNE
+ ACTERMNEW
+ APAND
APANDS
APBIC
APBICS
@@ -19,8 +23,13 @@ const (
APBRKPAS
APBRKPB
APBRKPBS
+ APCNTP
+ APDECP
APEOR
APEORS
+ APFIRSTP
+ APINCP
+ APLASTP
APNAND
APNANDS
APNOR
@@ -40,10 +49,36 @@ const (
APRDFFRS
APREV
APSEL
+ APSQDECP
+ APSQDECPW
+ APSQINCP
+ APSQINCPW
APTRN1
APTRN2
+ APUQDECP
+ APUQDECPW
+ APUQINCP
+ APUQINCPW
APUZP1
APUZP2
+ APWHILEGE
+ APWHILEGEW
+ APWHILEGT
+ APWHILEGTW
+ APWHILEHI
+ APWHILEHIW
+ APWHILEHS
+ APWHILEHSW
+ APWHILELE
+ APWHILELEW
+ APWHILELO
+ APWHILELOW
+ APWHILELS
+ APWHILELSW
+ APWHILELT
+ APWHILELTW
+ APWHILERW
+ APWHILEWR
APWRFFR
APZIP1
APZIP2
@@ -65,6 +100,10 @@ const (
AZAESMC
AZAND
AZANDQV
+ AZANDVB
+ AZANDVD
+ AZANDVH
+ AZANDVS
AZASR
AZASRR
AZBCAX
@@ -99,7 +138,17 @@ const (
AZBSL1N
AZBSL2N
AZCLASTA
+ AZCLASTAB
+ AZCLASTAD
+ AZCLASTAH
+ AZCLASTAS
+ AZCLASTAW
AZCLASTB
+ AZCLASTBB
+ AZCLASTBD
+ AZCLASTBH
+ AZCLASTBS
+ AZCLASTBW
AZCLS
AZCLZ
AZCMPEQ
@@ -115,12 +164,24 @@ const (
AZCNOT
AZCNT
AZCOMPACT
+ AZCPY
+ AZCPYB
+ AZCPYD
+ AZCPYH
+ AZCPYS
+ AZCPYW
AZDECP
+ AZDUP
+ AZDUPW
AZEOR
AZEOR3
AZEORBT
AZEORQV
AZEORTB
+ AZEORVB
+ AZEORVD
+ AZEORVH
+ AZEORVS
AZEXPAND
AZF1CVT
AZF1CVTLT
@@ -131,8 +192,14 @@ const (
AZFACGE
AZFACGT
AZFADD
+ AZFADDAD
+ AZFADDAH
+ AZFADDAS
AZFADDP
AZFADDQV
+ AZFADDVD
+ AZFADDVH
+ AZFADDVS
AZFAMAX
AZFAMIN
AZFCLAMP
@@ -158,14 +225,26 @@ const (
AZFMAXNM
AZFMAXNMP
AZFMAXNMQV
+ AZFMAXNMVD
+ AZFMAXNMVH
+ AZFMAXNMVS
AZFMAXP
AZFMAXQV
+ AZFMAXVD
+ AZFMAXVH
+ AZFMAXVS
AZFMIN
AZFMINNM
AZFMINNMP
AZFMINNMQV
+ AZFMINNMVD
+ AZFMINNMVH
+ AZFMINNMVS
AZFMINP
AZFMINQV
+ AZFMINVD
+ AZFMINVH
+ AZFMINVS
AZFMLA
AZFMLALB
AZFMLALLBB
@@ -210,6 +289,26 @@ const (
AZHISTCNT
AZHISTSEG
AZINCP
+ AZINDEX
+ AZINDEXW
+ AZINSR
+ AZINSRB
+ AZINSRD
+ AZINSRH
+ AZINSRS
+ AZINSRW
+ AZLASTA
+ AZLASTAB
+ AZLASTAD
+ AZLASTAH
+ AZLASTAS
+ AZLASTAW
+ AZLASTB
+ AZLASTBB
+ AZLASTBD
+ AZLASTBH
+ AZLASTBS
+ AZLASTBW
AZLSL
AZLSLR
AZLSR
@@ -229,6 +328,10 @@ const (
AZNOT
AZORQV
AZORR
+ AZORVB
+ AZORVD
+ AZORVH
+ AZORVS
AZPMOV
AZPMUL
AZPMULLB
@@ -255,6 +358,7 @@ const (
AZSADDLB
AZSADDLBT
AZSADDLT
+ AZSADDVD
AZSADDWB
AZSADDWT
AZSBCLB
@@ -274,9 +378,17 @@ const (
AZSMAX
AZSMAXP
AZSMAXQV
+ AZSMAXVB
+ AZSMAXVD
+ AZSMAXVH
+ AZSMAXVS
AZSMIN
AZSMINP
AZSMINQV
+ AZSMINVB
+ AZSMINVD
+ AZSMINVH
+ AZSMINVS
AZSMLALB
AZSMLALT
AZSMLSLB
@@ -348,6 +460,7 @@ const (
AZUADALP
AZUADDLB
AZUADDLT
+ AZUADDVD
AZUADDWB
AZUADDWT
AZUCLAMP
@@ -362,9 +475,17 @@ const (
AZUMAX
AZUMAXP
AZUMAXQV
+ AZUMAXVB
+ AZUMAXVD
+ AZUMAXVH
+ AZUMAXVS
AZUMIN
AZUMINP
AZUMINQV
+ AZUMINVB
+ AZUMINVD
+ AZUMINVH
+ AZUMINVS
AZUMLALB
AZUMLALT
AZUMLSLB
diff --git a/src/cmd/internal/obj/arm64/inst.go b/src/cmd/internal/obj/arm64/inst.go
index abd464eb00..28ff139d66 100644
--- a/src/cmd/internal/obj/arm64/inst.go
+++ b/src/cmd/internal/obj/arm64/inst.go
@@ -109,6 +109,12 @@ func aclass(a *obj.Addr) AClass {
return AC_ARNG
}
}
+ if a.Reg >= REG_V0 && a.Reg <= REG_V31 {
+ return AC_VREG
+ }
+ if a.Reg >= REG_R0 && a.Reg <= REG_R31 || a.Reg == REG_RSP {
+ return AC_SPZGREG
+ }
}
panic("unknown AClass")
}
@@ -143,6 +149,23 @@ func addrComponent(a *obj.Addr, acl AClass, index int) uint32 {
default:
panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl))
}
+ // AClass: AC_SPZGREG, AC_VREG
+ // GNU mnemonic: <width><reg>
+ // Go mnemonic:
+ // reg (the width is already represented in the opcode)
+ // Encoding:
+ // Type = TYPE_REG
+ // Reg = reg
+ case AC_SPZGREG, AC_VREG:
+ switch index {
+ case 0:
+ // These are all width checks, they should map to no-op checks altogether.
+ return 0
+ case 1:
+ return uint32(a.Reg)
+ default:
+ panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl))
+ }
}
// TODO: handle more AClasses.
panic(fmt.Errorf("unknown AClass %d", acl))
diff --git a/src/cmd/internal/obj/arm64/inst_gen.go b/src/cmd/internal/obj/arm64/inst_gen.go
index cb05ef50bc..376dc0fe13 100644
--- a/src/cmd/internal/obj/arm64/inst_gen.go
+++ b/src/cmd/internal/obj/arm64/inst_gen.go
@@ -6,6 +6,42 @@ package arm64
// insts are grouped by [goOp].
var insts = [][]instEncoder{
+ // CTERMEQ
+ {
+ // CTERMEQ <R><m>, <R><n>
+ {
+ goOp: ACTERMEQ,
+ fixedBits: 0x25e02000,
+ args: Rm__Rn,
+ },
+ },
+ // CTERMEQW
+ {
+ // CTERMEQW <R><m>, <R><n>
+ {
+ goOp: ACTERMEQW,
+ fixedBits: 0x25a02000,
+ args: Rm__Rn,
+ },
+ },
+ // CTERMNE
+ {
+ // CTERMNE <R><m>, <R><n>
+ {
+ goOp: ACTERMNE,
+ fixedBits: 0x25e02010,
+ args: Rm__Rn,
+ },
+ },
+ // CTERMNEW
+ {
+ // CTERMNEW <R><m>, <R><n>
+ {
+ goOp: ACTERMNEW,
+ fixedBits: 0x25a02010,
+ args: Rm__Rn,
+ },
+ },
// PAND
{
// PAND <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
@@ -132,6 +168,24 @@ var insts = [][]instEncoder{
args: Pm_B__Pn_B__PgZ__Pd_B,
},
},
+ // PCNTP
+ {
+ // PCNTP <Pn>.<T>, <Pg>, <Xd>
+ {
+ goOp: APCNTP,
+ fixedBits: 0x25208000,
+ args: Pn_T__Pg__Xd,
+ },
+ },
+ // PDECP
+ {
+ // PDECP <Pm>.<T>, <Xdn>
+ {
+ goOp: APDECP,
+ fixedBits: 0x252d8800,
+ args: Pm_T__Xdn,
+ },
+ },
// PEOR
{
// PEOR <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
@@ -150,6 +204,33 @@ var insts = [][]instEncoder{
args: Pm_B__Pn_B__PgZ__Pd_B,
},
},
+ // PFIRSTP
+ {
+ // PFIRSTP <Pn>.<T>, <Pg>, <Xd>
+ {
+ goOp: APFIRSTP,
+ fixedBits: 0x25218000,
+ args: Pn_T__Pg__Xd,
+ },
+ },
+ // PINCP
+ {
+ // PINCP <Pm>.<T>, <Xdn>
+ {
+ goOp: APINCP,
+ fixedBits: 0x252c8800,
+ args: Pm_T__Xdn,
+ },
+ },
+ // PLASTP
+ {
+ // PLASTP <Pn>.<T>, <Pg>, <Xd>
+ {
+ goOp: APLASTP,
+ fixedBits: 0x25228000,
+ args: Pn_T__Pg__Xd,
+ },
+ },
// PNAND
{
// PNAND <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
@@ -327,6 +408,42 @@ var insts = [][]instEncoder{
args: Pm_B__Pn_B__Pg__Pd_B,
},
},
+ // PSQDECP
+ {
+ // PSQDECP <Pm>.<T>, <Xdn>
+ {
+ goOp: APSQDECP,
+ fixedBits: 0x252a8c00,
+ args: Pm_T__Xdn,
+ },
+ },
+ // PSQDECPW
+ {
+ // PSQDECPW <Wdn>, <Pm>.<T>, <Xdn>
+ {
+ goOp: APSQDECPW,
+ fixedBits: 0x252a8800,
+ args: Wdn__Pm_T__Xdn,
+ },
+ },
+ // PSQINCP
+ {
+ // PSQINCP <Pm>.<T>, <Xdn>
+ {
+ goOp: APSQINCP,
+ fixedBits: 0x25288c00,
+ args: Pm_T__Xdn,
+ },
+ },
+ // PSQINCPW
+ {
+ // PSQINCPW <Wdn>, <Pm>.<T>, <Xdn>
+ {
+ goOp: APSQINCPW,
+ fixedBits: 0x25288800,
+ args: Wdn__Pm_T__Xdn,
+ },
+ },
// PTRN1
{
// PTRN1 <Pm>.<T>, <Pn>.<T>, <Pd>.<T>
@@ -345,6 +462,42 @@ var insts = [][]instEncoder{
args: Pm_T__Pn_T__Pd_T,
},
},
+ // PUQDECP
+ {
+ // PUQDECP <Pm>.<T>, <Xdn>
+ {
+ goOp: APUQDECP,
+ fixedBits: 0x252b8c00,
+ args: Pm_T__Xdn,
+ },
+ },
+ // PUQDECPW
+ {
+ // PUQDECPW <Pm>.<T>, <Wdn>
+ {
+ goOp: APUQDECPW,
+ fixedBits: 0x252b8800,
+ args: Pm_T__Wdn,
+ },
+ },
+ // PUQINCP
+ {
+ // PUQINCP <Pm>.<T>, <Xdn>
+ {
+ goOp: APUQINCP,
+ fixedBits: 0x25298c00,
+ args: Pm_T__Xdn,
+ },
+ },
+ // PUQINCPW
+ {
+ // PUQINCPW <Pm>.<T>, <Wdn>
+ {
+ goOp: APUQINCPW,
+ fixedBits: 0x25298800,
+ args: Pm_T__Wdn,
+ },
+ },
// PUZP1
{
// PUZP1 <Pm>.<T>, <Pn>.<T>, <Pd>.<T>
@@ -363,6 +516,168 @@ var insts = [][]instEncoder{
args: Pm_T__Pn_T__Pd_T,
},
},
+ // PWHILEGE
+ {
+ // PWHILEGE <R><m>, <R><n>, <Pd>.<T>
+ {
+ goOp: APWHILEGE,
+ fixedBits: 0x25201000,
+ args: Rm__Rn__Pd_T,
+ },
+ },
+ // PWHILEGEW
+ {
+ // PWHILEGEW <R><m>, <R><n>, <Pd>.<T>
+ {
+ goOp: APWHILEGEW,
+ fixedBits: 0x25200000,
+ args: Rm__Rn__Pd_T,
+ },
+ },
+ // PWHILEGT
+ {
+ // PWHILEGT <R><m>, <R><n>, <Pd>.<T>
+ {
+ goOp: APWHILEGT,
+ fixedBits: 0x25201010,
+ args: Rm__Rn__Pd_T,
+ },
+ },
+ // PWHILEGTW
+ {
+ // PWHILEGTW <R><m>, <R><n>, <Pd>.<T>
+ {
+ goOp: APWHILEGTW,
+ fixedBits: 0x25200010,
+ args: Rm__Rn__Pd_T,
+ },
+ },
+ // PWHILEHI
+ {
+ // PWHILEHI <R><m>, <R><n>, <Pd>.<T>
+ {
+ goOp: APWHILEHI,
+ fixedBits: 0x25201810,
+ args: Rm__Rn__Pd_T,
+ },
+ },
+ // PWHILEHIW
+ {
+ // PWHILEHIW <R><m>, <R><n>, <Pd>.<T>
+ {
+ goOp: APWHILEHIW,
+ fixedBits: 0x25200810,
+ args: Rm__Rn__Pd_T,
+ },
+ },
+ // PWHILEHS
+ {
+ // PWHILEHS <R><m>, <R><n>, <Pd>.<T>
+ {
+ goOp: APWHILEHS,
+ fixedBits: 0x25201800,
+ args: Rm__Rn__Pd_T,
+ },
+ },
+ // PWHILEHSW
+ {
+ // PWHILEHSW <R><m>, <R><n>, <Pd>.<T>
+ {
+ goOp: APWHILEHSW,
+ fixedBits: 0x25200800,
+ args: Rm__Rn__Pd_T,
+ },
+ },
+ // PWHILELE
+ {
+ // PWHILELE <R><m>, <R><n>, <Pd>.<T>
+ {
+ goOp: APWHILELE,
+ fixedBits: 0x25201410,
+ args: Rm__Rn__Pd_T,
+ },
+ },
+ // PWHILELEW
+ {
+ // PWHILELEW <R><m>, <R><n>, <Pd>.<T>
+ {
+ goOp: APWHILELEW,
+ fixedBits: 0x25200410,
+ args: Rm__Rn__Pd_T,
+ },
+ },
+ // PWHILELO
+ {
+ // PWHILELO <R><m>, <R><n>, <Pd>.<T>
+ {
+ goOp: APWHILELO,
+ fixedBits: 0x25201c00,
+ args: Rm__Rn__Pd_T,
+ },
+ },
+ // PWHILELOW
+ {
+ // PWHILELOW <R><m>, <R><n>, <Pd>.<T>
+ {
+ goOp: APWHILELOW,
+ fixedBits: 0x25200c00,
+ args: Rm__Rn__Pd_T,
+ },
+ },
+ // PWHILELS
+ {
+ // PWHILELS <R><m>, <R><n>, <Pd>.<T>
+ {
+ goOp: APWHILELS,
+ fixedBits: 0x25201c10,
+ args: Rm__Rn__Pd_T,
+ },
+ },
+ // PWHILELSW
+ {
+ // PWHILELSW <R><m>, <R><n>, <Pd>.<T>
+ {
+ goOp: APWHILELSW,
+ fixedBits: 0x25200c10,
+ args: Rm__Rn__Pd_T,
+ },
+ },
+ // PWHILELT
+ {
+ // PWHILELT <R><m>, <R><n>, <Pd>.<T>
+ {
+ goOp: APWHILELT,
+ fixedBits: 0x25201400,
+ args: Rm__Rn__Pd_T,
+ },
+ },
+ // PWHILELTW
+ {
+ // PWHILELTW <R><m>, <R><n>, <Pd>.<T>
+ {
+ goOp: APWHILELTW,
+ fixedBits: 0x25200400,
+ args: Rm__Rn__Pd_T,
+ },
+ },
+ // PWHILERW
+ {
+ // PWHILERW <Xm>, <Xn>, <Pd>.<T>
+ {
+ goOp: APWHILERW,
+ fixedBits: 0x25203010,
+ args: Xm__Xn__Pd_T,
+ },
+ },
+ // PWHILEWR
+ {
+ // PWHILEWR <Xm>, <Xn>, <Pd>.<T>
+ {
+ goOp: APWHILEWR,
+ fixedBits: 0x25203000,
+ args: Xm__Xn__Pd_T,
+ },
+ },
// PWRFFR
{
// PWRFFR <Pn>.B
@@ -576,20 +891,56 @@ var insts = [][]instEncoder{
args: Zn_Tb__Pg__Vd_T__1,
},
},
- // ZASR
+ // ZANDVB
{
- // ZASR <Zm>.D, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ // ZANDVB <Zn>.<T>, <Pg>, <V><d>
{
- goOp: AZASR,
- fixedBits: 0x4188000,
- args: Zm_D__Zdn_T__PgM__Zdn_T,
+ goOp: AZANDVB,
+ fixedBits: 0x41a2000,
+ args: Zn_T__Pg__Vd__1,
},
+ },
+ // ZANDVD
+ {
+ // ZANDVD <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZANDVD,
+ fixedBits: 0x4da2000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZANDVH
+ {
+ // ZANDVH <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZANDVH,
+ fixedBits: 0x45a2000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZANDVS
+ {
+ // ZANDVS <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZANDVS,
+ fixedBits: 0x49a2000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZASR
+ {
// ZASR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
{
goOp: AZASR,
fixedBits: 0x4108000,
args: Zm_T__Zdn_T__PgM__Zdn_T__1,
},
+ // ZASR <Zm>.D, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZASR,
+ fixedBits: 0x4188000,
+ args: Zm_D__Zdn_T__PgM__Zdn_T,
+ },
// ZASR <Zm>.D, <Zn>.<T>, <Zd>.<T>
{
goOp: AZASR,
@@ -824,33 +1175,33 @@ var insts = [][]instEncoder{
},
// ZBFMMLA
{
- // ZBFMMLA <Zm>.H, <Zn>.H, <Zda>.H
- {
- goOp: AZBFMMLA,
- fixedBits: 0x64e0e000,
- args: Zm_H__Zn_H__Zda_H,
- },
// ZBFMMLA <Zm>.H, <Zn>.H, <Zda>.S
{
goOp: AZBFMMLA,
fixedBits: 0x6460e400,
args: Zm_H__Zn_H__Zda_S,
},
+ // ZBFMMLA <Zm>.H, <Zn>.H, <Zda>.H
+ {
+ goOp: AZBFMMLA,
+ fixedBits: 0x64e0e000,
+ args: Zm_H__Zn_H__Zda_H,
+ },
},
// ZBFMUL
{
- // ZBFMUL <Zm>.H, <Zdn>.H, <Pg>/M, <Zdn>.H
- {
- goOp: AZBFMUL,
- fixedBits: 0x65028000,
- args: Zm_H__Zdn_H__PgM__Zdn_H,
- },
// ZBFMUL <Zm>.H, <Zn>.H, <Zd>.H
{
goOp: AZBFMUL,
fixedBits: 0x65000800,
args: Zm_H__Zn_H__Zd_H,
},
+ // ZBFMUL <Zm>.H, <Zdn>.H, <Pg>/M, <Zdn>.H
+ {
+ goOp: AZBFMUL,
+ fixedBits: 0x65028000,
+ args: Zm_H__Zdn_H__PgM__Zdn_H,
+ },
},
// ZBFSCALE
{
@@ -929,6 +1280,12 @@ var insts = [][]instEncoder{
},
// ZCLASTA
{
+ // ZCLASTA <Zm>.<T>, <R><dn>, <Pg>, <R><dn>
+ {
+ goOp: AZCLASTA,
+ fixedBits: 0x5f0a000,
+ args: Zm_T__Rdn__Pg__Rdn,
+ },
// ZCLASTA <Zm>.<T>, <Zdn>.<T>, <Pg>, <Zdn>.<T>
{
goOp: AZCLASTA,
@@ -936,8 +1293,59 @@ var insts = [][]instEncoder{
args: Zm_T__Zdn_T__Pg__Zdn_T,
},
},
+ // ZCLASTAB
+ {
+ // ZCLASTAB <Zm>.<T>, <V><dn>, <Pg>, <V><dn>
+ {
+ goOp: AZCLASTAB,
+ fixedBits: 0x52a8000,
+ args: Zm_T__Vdn__Pg__Vdn__1,
+ },
+ },
+ // ZCLASTAD
+ {
+ // ZCLASTAD <Zm>.<T>, <V><dn>, <Pg>, <V><dn>
+ {
+ goOp: AZCLASTAD,
+ fixedBits: 0x5ea8000,
+ args: Zm_T__Vdn__Pg__Vdn__1,
+ },
+ },
+ // ZCLASTAH
+ {
+ // ZCLASTAH <Zm>.<T>, <V><dn>, <Pg>, <V><dn>
+ {
+ goOp: AZCLASTAH,
+ fixedBits: 0x56a8000,
+ args: Zm_T__Vdn__Pg__Vdn__1,
+ },
+ },
+ // ZCLASTAS
+ {
+ // ZCLASTAS <Zm>.<T>, <V><dn>, <Pg>, <V><dn>
+ {
+ goOp: AZCLASTAS,
+ fixedBits: 0x5aa8000,
+ args: Zm_T__Vdn__Pg__Vdn__1,
+ },
+ },
+ // ZCLASTAW
+ {
+ // ZCLASTAW <Zm>.<T>, <R><dn>, <Pg>, <R><dn>
+ {
+ goOp: AZCLASTAW,
+ fixedBits: 0x530a000,
+ args: Zm_T__Rdn__Pg__Rdn,
+ },
+ },
// ZCLASTB
{
+ // ZCLASTB <Zm>.<T>, <R><dn>, <Pg>, <R><dn>
+ {
+ goOp: AZCLASTB,
+ fixedBits: 0x5f1a000,
+ args: Zm_T__Rdn__Pg__Rdn,
+ },
// ZCLASTB <Zm>.<T>, <Zdn>.<T>, <Pg>, <Zdn>.<T>
{
goOp: AZCLASTB,
@@ -945,35 +1353,80 @@ var insts = [][]instEncoder{
args: Zm_T__Zdn_T__Pg__Zdn_T,
},
},
- // ZCLS
+ // ZCLASTBB
{
- // ZCLS <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ // ZCLASTBB <Zm>.<T>, <V><dn>, <Pg>, <V><dn>
{
- goOp: AZCLS,
- fixedBits: 0x408a000,
- args: Zn_T__PgZ__Zd_T__2,
+ goOp: AZCLASTBB,
+ fixedBits: 0x52b8000,
+ args: Zm_T__Vdn__Pg__Vdn__1,
+ },
+ },
+ // ZCLASTBD
+ {
+ // ZCLASTBD <Zm>.<T>, <V><dn>, <Pg>, <V><dn>
+ {
+ goOp: AZCLASTBD,
+ fixedBits: 0x5eb8000,
+ args: Zm_T__Vdn__Pg__Vdn__1,
+ },
+ },
+ // ZCLASTBH
+ {
+ // ZCLASTBH <Zm>.<T>, <V><dn>, <Pg>, <V><dn>
+ {
+ goOp: AZCLASTBH,
+ fixedBits: 0x56b8000,
+ args: Zm_T__Vdn__Pg__Vdn__1,
+ },
+ },
+ // ZCLASTBS
+ {
+ // ZCLASTBS <Zm>.<T>, <V><dn>, <Pg>, <V><dn>
+ {
+ goOp: AZCLASTBS,
+ fixedBits: 0x5ab8000,
+ args: Zm_T__Vdn__Pg__Vdn__1,
+ },
+ },
+ // ZCLASTBW
+ {
+ // ZCLASTBW <Zm>.<T>, <R><dn>, <Pg>, <R><dn>
+ {
+ goOp: AZCLASTBW,
+ fixedBits: 0x531a000,
+ args: Zm_T__Rdn__Pg__Rdn,
},
+ },
+ // ZCLS
+ {
// ZCLS <Zn>.<T>, <Pg>/M, <Zd>.<T>
{
goOp: AZCLS,
fixedBits: 0x418a000,
args: Zn_T__PgM__Zd_T__2,
},
- },
- // ZCLZ
- {
- // ZCLZ <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ // ZCLS <Zn>.<T>, <Pg>/Z, <Zd>.<T>
{
- goOp: AZCLZ,
- fixedBits: 0x409a000,
+ goOp: AZCLS,
+ fixedBits: 0x408a000,
args: Zn_T__PgZ__Zd_T__2,
},
+ },
+ // ZCLZ
+ {
// ZCLZ <Zn>.<T>, <Pg>/M, <Zd>.<T>
{
goOp: AZCLZ,
fixedBits: 0x419a000,
args: Zn_T__PgM__Zd_T__2,
},
+ // ZCLZ <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZCLZ,
+ fixedBits: 0x409a000,
+ args: Zn_T__PgZ__Zd_T__2,
+ },
},
// ZCMPEQ
{
@@ -992,48 +1445,48 @@ var insts = [][]instEncoder{
},
// ZCMPGE
{
- // ZCMPGE <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
- {
- goOp: AZCMPGE,
- fixedBits: 0x24008000,
- args: Zm_T__Zn_T__PgZ__Pd_T__2,
- },
// ZCMPGE <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
{
goOp: AZCMPGE,
fixedBits: 0x24004000,
args: Zm_D__Zn_T__PgZ__Pd_T,
},
- },
- // ZCMPGT
- {
- // ZCMPGT <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ // ZCMPGE <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
{
- goOp: AZCMPGT,
- fixedBits: 0x24008010,
+ goOp: AZCMPGE,
+ fixedBits: 0x24008000,
args: Zm_T__Zn_T__PgZ__Pd_T__2,
},
+ },
+ // ZCMPGT
+ {
// ZCMPGT <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
{
goOp: AZCMPGT,
fixedBits: 0x24004010,
args: Zm_D__Zn_T__PgZ__Pd_T,
},
+ // ZCMPGT <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZCMPGT,
+ fixedBits: 0x24008010,
+ args: Zm_T__Zn_T__PgZ__Pd_T__2,
+ },
},
// ZCMPHI
{
- // ZCMPHI <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
- {
- goOp: AZCMPHI,
- fixedBits: 0x2400c010,
- args: Zm_D__Zn_T__PgZ__Pd_T,
- },
// ZCMPHI <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
{
goOp: AZCMPHI,
fixedBits: 0x24000010,
args: Zm_T__Zn_T__PgZ__Pd_T__2,
},
+ // ZCMPHI <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZCMPHI,
+ fixedBits: 0x2400c010,
+ args: Zm_D__Zn_T__PgZ__Pd_T,
+ },
},
// ZCMPHS
{
@@ -1103,33 +1556,33 @@ var insts = [][]instEncoder{
},
// ZCNOT
{
- // ZCNOT <Zn>.<T>, <Pg>/M, <Zd>.<T>
- {
- goOp: AZCNOT,
- fixedBits: 0x41ba000,
- args: Zn_T__PgM__Zd_T__2,
- },
// ZCNOT <Zn>.<T>, <Pg>/Z, <Zd>.<T>
{
goOp: AZCNOT,
fixedBits: 0x40ba000,
args: Zn_T__PgZ__Zd_T__2,
},
- },
- // ZCNT
- {
- // ZCNT <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ // ZCNOT <Zn>.<T>, <Pg>/M, <Zd>.<T>
{
- goOp: AZCNT,
- fixedBits: 0x41aa000,
+ goOp: AZCNOT,
+ fixedBits: 0x41ba000,
args: Zn_T__PgM__Zd_T__2,
},
+ },
+ // ZCNT
+ {
// ZCNT <Zn>.<T>, <Pg>/Z, <Zd>.<T>
{
goOp: AZCNT,
fixedBits: 0x40aa000,
args: Zn_T__PgZ__Zd_T__2,
},
+ // ZCNT <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZCNT,
+ fixedBits: 0x41aa000,
+ args: Zn_T__PgM__Zd_T__2,
+ },
},
// ZCOMPACT
{
@@ -1146,6 +1599,60 @@ var insts = [][]instEncoder{
args: Zn_T__Pg__Zd_T__2,
},
},
+ // ZCPY
+ {
+ // ZCPY <R><n|SP>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZCPY,
+ fixedBits: 0x5e8a000,
+ args: RnSP__PgM__Zd_T,
+ },
+ },
+ // ZCPYB
+ {
+ // ZCPYB <V><n>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZCPYB,
+ fixedBits: 0x5208000,
+ args: Vn__PgM__Zd_T,
+ },
+ },
+ // ZCPYD
+ {
+ // ZCPYD <V><n>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZCPYD,
+ fixedBits: 0x5e08000,
+ args: Vn__PgM__Zd_T,
+ },
+ },
+ // ZCPYH
+ {
+ // ZCPYH <V><n>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZCPYH,
+ fixedBits: 0x5608000,
+ args: Vn__PgM__Zd_T,
+ },
+ },
+ // ZCPYS
+ {
+ // ZCPYS <V><n>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZCPYS,
+ fixedBits: 0x5a08000,
+ args: Vn__PgM__Zd_T,
+ },
+ },
+ // ZCPYW
+ {
+ // ZCPYW <R><n|SP>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZCPYW,
+ fixedBits: 0x528a000,
+ args: RnSP__PgM__Zd_T,
+ },
+ },
// ZDECP
{
// ZDECP <Pm>.<T>, <Zdn>.<T>
@@ -1155,20 +1662,38 @@ var insts = [][]instEncoder{
args: Pm_T__Zdn_T,
},
},
- // ZEOR
+ // ZDUP
{
- // ZEOR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ // ZDUP <R><n|SP>, <Zd>.<T>
{
- goOp: AZEOR,
- fixedBits: 0x4190000,
- args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ goOp: AZDUP,
+ fixedBits: 0x5e03800,
+ args: RnSP__Zd_T,
+ },
+ },
+ // ZDUPW
+ {
+ // ZDUPW <R><n|SP>, <Zd>.<T>
+ {
+ goOp: AZDUPW,
+ fixedBits: 0x5203800,
+ args: RnSP__Zd_T,
},
+ },
+ // ZEOR
+ {
// ZEOR <Zm>.D, <Zn>.D, <Zd>.D
{
goOp: AZEOR,
fixedBits: 0x4a03000,
args: Zm_D__Zn_D__Zd_D,
},
+ // ZEOR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZEOR,
+ fixedBits: 0x4190000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
},
// ZEOR3
{
@@ -1206,6 +1731,42 @@ var insts = [][]instEncoder{
args: Zm_T__Zn_T__Zd_T__1,
},
},
+ // ZEORVB
+ {
+ // ZEORVB <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZEORVB,
+ fixedBits: 0x4192000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZEORVD
+ {
+ // ZEORVD <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZEORVD,
+ fixedBits: 0x4d92000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZEORVH
+ {
+ // ZEORVH <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZEORVH,
+ fixedBits: 0x4592000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZEORVS
+ {
+ // ZEORVS <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZEORVS,
+ fixedBits: 0x4992000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
// ZEXPAND
{
// ZEXPAND <Zn>.<T>, <Pg>, <Zd>.<T>
@@ -1308,6 +1869,33 @@ var insts = [][]instEncoder{
args: Zm_T__Zn_T__Zd_T__2,
},
},
+ // ZFADDAD
+ {
+ // ZFADDAD <Zm>.<T>, <V><dn>, <Pg>, <V><dn>
+ {
+ goOp: AZFADDAD,
+ fixedBits: 0x65d82000,
+ args: Zm_T__Vdn__Pg__Vdn__2,
+ },
+ },
+ // ZFADDAH
+ {
+ // ZFADDAH <Zm>.<T>, <V><dn>, <Pg>, <V><dn>
+ {
+ goOp: AZFADDAH,
+ fixedBits: 0x65582000,
+ args: Zm_T__Vdn__Pg__Vdn__2,
+ },
+ },
+ // ZFADDAS
+ {
+ // ZFADDAS <Zm>.<T>, <V><dn>, <Pg>, <V><dn>
+ {
+ goOp: AZFADDAS,
+ fixedBits: 0x65982000,
+ args: Zm_T__Vdn__Pg__Vdn__2,
+ },
+ },
// ZFADDP
{
// ZFADDP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
@@ -1326,6 +1914,33 @@ var insts = [][]instEncoder{
args: Zn_Tb__Pg__Vd_T__2,
},
},
+ // ZFADDVD
+ {
+ // ZFADDVD <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZFADDVD,
+ fixedBits: 0x65c02000,
+ args: Zn_T__Pg__Vd__2,
+ },
+ },
+ // ZFADDVH
+ {
+ // ZFADDVH <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZFADDVH,
+ fixedBits: 0x65402000,
+ args: Zn_T__Pg__Vd__2,
+ },
+ },
+ // ZFADDVS
+ {
+ // ZFADDVS <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZFADDVS,
+ fixedBits: 0x65802000,
+ args: Zn_T__Pg__Vd__2,
+ },
+ },
// ZFAMAX
{
// ZFAMAX <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
@@ -1400,11 +2015,11 @@ var insts = [][]instEncoder{
},
// ZFCVT
{
- // ZFCVT <Zn>.H, <Pg>/M, <Zd>.S
+ // ZFCVT <Zn>.H, <Pg>/M, <Zd>.D
{
goOp: AZFCVT,
- fixedBits: 0x6589a000,
- args: Zn_H__PgM__Zd_S,
+ fixedBits: 0x65c9a000,
+ args: Zn_H__PgM__Zd_D,
},
// ZFCVT <Zn>.S, <Pg>/M, <Zd>.D
{
@@ -1412,17 +2027,17 @@ var insts = [][]instEncoder{
fixedBits: 0x65cba000,
args: Zn_S__PgM__Zd_D,
},
- // ZFCVT <Zn>.H, <Pg>/Z, <Zd>.S
+ // ZFCVT <Zn>.H, <Pg>/M, <Zd>.S
{
goOp: AZFCVT,
- fixedBits: 0x649aa000,
- args: Zn_H__PgZ__Zd_S,
+ fixedBits: 0x6589a000,
+ args: Zn_H__PgM__Zd_S,
},
- // ZFCVT <Zn>.H, <Pg>/M, <Zd>.D
+ // ZFCVT <Zn>.H, <Pg>/Z, <Zd>.S
{
goOp: AZFCVT,
- fixedBits: 0x65c9a000,
- args: Zn_H__PgM__Zd_D,
+ fixedBits: 0x649aa000,
+ args: Zn_H__PgZ__Zd_S,
},
// ZFCVT <Zn>.H, <Pg>/Z, <Zd>.D
{
@@ -1442,17 +2057,17 @@ var insts = [][]instEncoder{
fixedBits: 0x649a8000,
args: Zn_S__PgZ__Zd_H,
},
- // ZFCVT <Zn>.S, <Pg>/Z, <Zd>.D
+ // ZFCVT <Zn>.D, <Pg>/Z, <Zd>.S
{
goOp: AZFCVT,
- fixedBits: 0x64dae000,
- args: Zn_S__PgZ__Zd_D,
+ fixedBits: 0x64dac000,
+ args: Zn_D__PgZ__Zd_S,
},
- // ZFCVT <Zn>.D, <Pg>/M, <Zd>.H
+ // ZFCVT <Zn>.D, <Pg>/M, <Zd>.S
{
goOp: AZFCVT,
- fixedBits: 0x65c8a000,
- args: Zn_D__PgM__Zd_H,
+ fixedBits: 0x65caa000,
+ args: Zn_D__PgM__Zd_S,
},
// ZFCVT <Zn>.D, <Pg>/Z, <Zd>.H
{
@@ -1460,17 +2075,17 @@ var insts = [][]instEncoder{
fixedBits: 0x64da8000,
args: Zn_D__PgZ__Zd_H,
},
- // ZFCVT <Zn>.D, <Pg>/M, <Zd>.S
+ // ZFCVT <Zn>.D, <Pg>/M, <Zd>.H
{
goOp: AZFCVT,
- fixedBits: 0x65caa000,
- args: Zn_D__PgM__Zd_S,
+ fixedBits: 0x65c8a000,
+ args: Zn_D__PgM__Zd_H,
},
- // ZFCVT <Zn>.D, <Pg>/Z, <Zd>.S
+ // ZFCVT <Zn>.S, <Pg>/Z, <Zd>.D
{
goOp: AZFCVT,
- fixedBits: 0x64dac000,
- args: Zn_D__PgZ__Zd_S,
+ fixedBits: 0x64dae000,
+ args: Zn_S__PgZ__Zd_D,
},
},
// ZFCVTLT
@@ -1502,18 +2117,18 @@ var insts = [][]instEncoder{
},
// ZFCVTNT
{
- // ZFCVTNT <Zn>.S, <Pg>/M, <Zd>.H
- {
- goOp: AZFCVTNT,
- fixedBits: 0x6488a000,
- args: Zn_S__PgM__Zd_H,
- },
// ZFCVTNT <Zn>.S, <Pg>/Z, <Zd>.H
{
goOp: AZFCVTNT,
fixedBits: 0x6480a000,
args: Zn_S__PgZ__Zd_H,
},
+ // ZFCVTNT <Zn>.S, <Pg>/M, <Zd>.H
+ {
+ goOp: AZFCVTNT,
+ fixedBits: 0x6488a000,
+ args: Zn_S__PgM__Zd_H,
+ },
// ZFCVTNT <Zn>.D, <Pg>/M, <Zd>.S
{
goOp: AZFCVTNT,
@@ -1529,33 +2144,33 @@ var insts = [][]instEncoder{
},
// ZFCVTX
{
- // ZFCVTX <Zn>.D, <Pg>/Z, <Zd>.S
- {
- goOp: AZFCVTX,
- fixedBits: 0x641ac000,
- args: Zn_D__PgZ__Zd_S,
- },
// ZFCVTX <Zn>.D, <Pg>/M, <Zd>.S
{
goOp: AZFCVTX,
fixedBits: 0x650aa000,
args: Zn_D__PgM__Zd_S,
},
+ // ZFCVTX <Zn>.D, <Pg>/Z, <Zd>.S
+ {
+ goOp: AZFCVTX,
+ fixedBits: 0x641ac000,
+ args: Zn_D__PgZ__Zd_S,
+ },
},
// ZFCVTXNT
{
- // ZFCVTXNT <Zn>.D, <Pg>/M, <Zd>.S
- {
- goOp: AZFCVTXNT,
- fixedBits: 0x640aa000,
- args: Zn_D__PgM__Zd_S,
- },
// ZFCVTXNT <Zn>.D, <Pg>/Z, <Zd>.S
{
goOp: AZFCVTXNT,
fixedBits: 0x6402a000,
args: Zn_D__PgZ__Zd_S,
},
+ // ZFCVTXNT <Zn>.D, <Pg>/M, <Zd>.S
+ {
+ goOp: AZFCVTXNT,
+ fixedBits: 0x640aa000,
+ args: Zn_D__PgM__Zd_S,
+ },
},
// ZFCVTZS
{
@@ -1565,11 +2180,11 @@ var insts = [][]instEncoder{
fixedBits: 0x655aa000,
args: Zn_H__PgM__Zd_H,
},
- // ZFCVTZS <Zn>.H, <Pg>/Z, <Zd>.H
+ // ZFCVTZS <Zn>.D, <Pg>/Z, <Zd>.D
{
goOp: AZFCVTZS,
- fixedBits: 0x645ec000,
- args: Zn_H__PgZ__Zd_H,
+ fixedBits: 0x64dfc000,
+ args: Zn_D__PgZ__Zd_D,
},
// ZFCVTZS <Zn>.H, <Pg>/M, <Zd>.S
{
@@ -1607,6 +2222,12 @@ var insts = [][]instEncoder{
fixedBits: 0x649f8000,
args: Zn_S__PgZ__Zd_S,
},
+ // ZFCVTZS <Zn>.H, <Pg>/Z, <Zd>.H
+ {
+ goOp: AZFCVTZS,
+ fixedBits: 0x645ec000,
+ args: Zn_H__PgZ__Zd_H,
+ },
// ZFCVTZS <Zn>.S, <Pg>/M, <Zd>.D
{
goOp: AZFCVTZS,
@@ -1637,32 +2258,20 @@ var insts = [][]instEncoder{
fixedBits: 0x65dea000,
args: Zn_D__PgM__Zd_D,
},
- // ZFCVTZS <Zn>.D, <Pg>/Z, <Zd>.D
- {
- goOp: AZFCVTZS,
- fixedBits: 0x64dfc000,
- args: Zn_D__PgZ__Zd_D,
- },
},
// ZFCVTZU
{
- // ZFCVTZU <Zn>.D, <Pg>/Z, <Zd>.S
- {
- goOp: AZFCVTZU,
- fixedBits: 0x64dea000,
- args: Zn_D__PgZ__Zd_S,
- },
- // ZFCVTZU <Zn>.H, <Pg>/M, <Zd>.D
+ // ZFCVTZU <Zn>.S, <Pg>/Z, <Zd>.D
{
goOp: AZFCVTZU,
- fixedBits: 0x655fa000,
- args: Zn_H__PgM__Zd_D,
+ fixedBits: 0x64dfa000,
+ args: Zn_S__PgZ__Zd_D,
},
- // ZFCVTZU <Zn>.H, <Pg>/M, <Zd>.H
+ // ZFCVTZU <Zn>.S, <Pg>/M, <Zd>.S
{
goOp: AZFCVTZU,
- fixedBits: 0x655ba000,
- args: Zn_H__PgM__Zd_H,
+ fixedBits: 0x659da000,
+ args: Zn_S__PgM__Zd_S,
},
// ZFCVTZU <Zn>.H, <Pg>/Z, <Zd>.H
{
@@ -1670,17 +2279,11 @@ var insts = [][]instEncoder{
fixedBits: 0x645ee000,
args: Zn_H__PgZ__Zd_H,
},
- // ZFCVTZU <Zn>.D, <Pg>/Z, <Zd>.D
- {
- goOp: AZFCVTZU,
- fixedBits: 0x64dfe000,
- args: Zn_D__PgZ__Zd_D,
- },
- // ZFCVTZU <Zn>.H, <Pg>/M, <Zd>.S
+ // ZFCVTZU <Zn>.H, <Pg>/M, <Zd>.H
{
goOp: AZFCVTZU,
- fixedBits: 0x655da000,
- args: Zn_H__PgM__Zd_S,
+ fixedBits: 0x655ba000,
+ args: Zn_H__PgM__Zd_H,
},
// ZFCVTZU <Zn>.H, <Pg>/Z, <Zd>.S
{
@@ -1688,23 +2291,35 @@ var insts = [][]instEncoder{
fixedBits: 0x645fa000,
args: Zn_H__PgZ__Zd_S,
},
+ // ZFCVTZU <Zn>.H, <Pg>/M, <Zd>.D
+ {
+ goOp: AZFCVTZU,
+ fixedBits: 0x655fa000,
+ args: Zn_H__PgM__Zd_D,
+ },
// ZFCVTZU <Zn>.H, <Pg>/Z, <Zd>.D
{
goOp: AZFCVTZU,
fixedBits: 0x645fe000,
args: Zn_H__PgZ__Zd_D,
},
- // ZFCVTZU <Zn>.D, <Pg>/M, <Zd>.D
+ // ZFCVTZU <Zn>.H, <Pg>/M, <Zd>.S
{
goOp: AZFCVTZU,
- fixedBits: 0x65dfa000,
- args: Zn_D__PgM__Zd_D,
+ fixedBits: 0x655da000,
+ args: Zn_H__PgM__Zd_S,
},
- // ZFCVTZU <Zn>.S, <Pg>/M, <Zd>.S
+ // ZFCVTZU <Zn>.S, <Pg>/Z, <Zd>.S
{
goOp: AZFCVTZU,
- fixedBits: 0x659da000,
- args: Zn_S__PgM__Zd_S,
+ fixedBits: 0x649fa000,
+ args: Zn_S__PgZ__Zd_S,
+ },
+ // ZFCVTZU <Zn>.S, <Pg>/M, <Zd>.D
+ {
+ goOp: AZFCVTZU,
+ fixedBits: 0x65dda000,
+ args: Zn_S__PgM__Zd_D,
},
// ZFCVTZU <Zn>.D, <Pg>/M, <Zd>.S
{
@@ -1712,23 +2327,23 @@ var insts = [][]instEncoder{
fixedBits: 0x65d9a000,
args: Zn_D__PgM__Zd_S,
},
- // ZFCVTZU <Zn>.S, <Pg>/Z, <Zd>.D
+ // ZFCVTZU <Zn>.D, <Pg>/Z, <Zd>.S
{
goOp: AZFCVTZU,
- fixedBits: 0x64dfa000,
- args: Zn_S__PgZ__Zd_D,
+ fixedBits: 0x64dea000,
+ args: Zn_D__PgZ__Zd_S,
},
- // ZFCVTZU <Zn>.S, <Pg>/M, <Zd>.D
+ // ZFCVTZU <Zn>.D, <Pg>/M, <Zd>.D
{
goOp: AZFCVTZU,
- fixedBits: 0x65dda000,
- args: Zn_S__PgM__Zd_D,
+ fixedBits: 0x65dfa000,
+ args: Zn_D__PgM__Zd_D,
},
- // ZFCVTZU <Zn>.S, <Pg>/Z, <Zd>.S
+ // ZFCVTZU <Zn>.D, <Pg>/Z, <Zd>.D
{
goOp: AZFCVTZU,
- fixedBits: 0x649fa000,
- args: Zn_S__PgZ__Zd_S,
+ fixedBits: 0x64dfe000,
+ args: Zn_D__PgZ__Zd_D,
},
},
// ZFDIV
@@ -1757,18 +2372,18 @@ var insts = [][]instEncoder{
fixedBits: 0x64608400,
args: Zm_B__Zn_B__Zda_S,
},
- // ZFDOT <Zm>.B, <Zn>.B, <Zda>.H
- {
- goOp: AZFDOT,
- fixedBits: 0x64208400,
- args: Zm_B__Zn_B__Zda_H,
- },
// ZFDOT <Zm>.H, <Zn>.H, <Zda>.S
{
goOp: AZFDOT,
fixedBits: 0x64208000,
args: Zm_H__Zn_H__Zda_S,
},
+ // ZFDOT <Zm>.B, <Zn>.B, <Zda>.H
+ {
+ goOp: AZFDOT,
+ fixedBits: 0x64208400,
+ args: Zm_B__Zn_B__Zda_H,
+ },
},
// ZFEXPA
{
@@ -1781,18 +2396,18 @@ var insts = [][]instEncoder{
},
// ZFLOGB
{
- // ZFLOGB <Zn>.<T>, <Pg>/M, <Zd>.<T>
- {
- goOp: AZFLOGB,
- fixedBits: 0x6518a000,
- args: Zn_T__PgM__Zd_T__6,
- },
// ZFLOGB <Zn>.<T>, <Pg>/Z, <Zd>.<T>
{
goOp: AZFLOGB,
fixedBits: 0x641e8000,
args: Zn_T__PgZ__Zd_T__6,
},
+ // ZFLOGB <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZFLOGB,
+ fixedBits: 0x6518a000,
+ args: Zn_T__PgM__Zd_T__6,
+ },
},
// ZFMAD
{
@@ -1839,6 +2454,33 @@ var insts = [][]instEncoder{
args: Zn_Tb__Pg__Vd_T__2,
},
},
+ // ZFMAXNMVD
+ {
+ // ZFMAXNMVD <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZFMAXNMVD,
+ fixedBits: 0x65c42000,
+ args: Zn_T__Pg__Vd__2,
+ },
+ },
+ // ZFMAXNMVH
+ {
+ // ZFMAXNMVH <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZFMAXNMVH,
+ fixedBits: 0x65442000,
+ args: Zn_T__Pg__Vd__2,
+ },
+ },
+ // ZFMAXNMVS
+ {
+ // ZFMAXNMVS <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZFMAXNMVS,
+ fixedBits: 0x65842000,
+ args: Zn_T__Pg__Vd__2,
+ },
+ },
// ZFMAXP
{
// ZFMAXP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
@@ -1857,6 +2499,33 @@ var insts = [][]instEncoder{
args: Zn_Tb__Pg__Vd_T__2,
},
},
+ // ZFMAXVD
+ {
+ // ZFMAXVD <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZFMAXVD,
+ fixedBits: 0x65c62000,
+ args: Zn_T__Pg__Vd__2,
+ },
+ },
+ // ZFMAXVH
+ {
+ // ZFMAXVH <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZFMAXVH,
+ fixedBits: 0x65462000,
+ args: Zn_T__Pg__Vd__2,
+ },
+ },
+ // ZFMAXVS
+ {
+ // ZFMAXVS <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZFMAXVS,
+ fixedBits: 0x65862000,
+ args: Zn_T__Pg__Vd__2,
+ },
+ },
// ZFMIN
{
// ZFMIN <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
@@ -1893,6 +2562,33 @@ var insts = [][]instEncoder{
args: Zn_Tb__Pg__Vd_T__2,
},
},
+ // ZFMINNMVD
+ {
+ // ZFMINNMVD <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZFMINNMVD,
+ fixedBits: 0x65c52000,
+ args: Zn_T__Pg__Vd__2,
+ },
+ },
+ // ZFMINNMVH
+ {
+ // ZFMINNMVH <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZFMINNMVH,
+ fixedBits: 0x65452000,
+ args: Zn_T__Pg__Vd__2,
+ },
+ },
+ // ZFMINNMVS
+ {
+ // ZFMINNMVS <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZFMINNMVS,
+ fixedBits: 0x65852000,
+ args: Zn_T__Pg__Vd__2,
+ },
+ },
// ZFMINP
{
// ZFMINP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
@@ -1911,6 +2607,33 @@ var insts = [][]instEncoder{
args: Zn_Tb__Pg__Vd_T__2,
},
},
+ // ZFMINVD
+ {
+ // ZFMINVD <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZFMINVD,
+ fixedBits: 0x65c72000,
+ args: Zn_T__Pg__Vd__2,
+ },
+ },
+ // ZFMINVH
+ {
+ // ZFMINVH <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZFMINVH,
+ fixedBits: 0x65472000,
+ args: Zn_T__Pg__Vd__2,
+ },
+ },
+ // ZFMINVS
+ {
+ // ZFMINVS <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZFMINVS,
+ fixedBits: 0x65872000,
+ args: Zn_T__Pg__Vd__2,
+ },
+ },
// ZFMLA
{
// ZFMLA <Zm>.<T>, <Zn>.<T>, <Pg>/M, <Zda>.<T>
@@ -1973,18 +2696,18 @@ var insts = [][]instEncoder{
},
// ZFMLALT
{
- // ZFMLALT <Zm>.B, <Zn>.B, <Zda>.H
- {
- goOp: AZFMLALT,
- fixedBits: 0x64a09800,
- args: Zm_B__Zn_B__Zda_H,
- },
// ZFMLALT <Zm>.H, <Zn>.H, <Zda>.S
{
goOp: AZFMLALT,
fixedBits: 0x64a08400,
args: Zm_H__Zn_H__Zda_S,
},
+ // ZFMLALT <Zm>.B, <Zn>.B, <Zda>.H
+ {
+ goOp: AZFMLALT,
+ fixedBits: 0x64a09800,
+ args: Zm_B__Zn_B__Zda_H,
+ },
},
// ZFMLS
{
@@ -2015,11 +2738,11 @@ var insts = [][]instEncoder{
},
// ZFMMLA
{
- // ZFMMLA <Zm>.H, <Zn>.H, <Zda>.H
+ // ZFMMLA <Zm>.D, <Zn>.D, <Zda>.D
{
goOp: AZFMMLA,
- fixedBits: 0x64a0e000,
- args: Zm_H__Zn_H__Zda_H,
+ fixedBits: 0x64e0e400,
+ args: Zm_D__Zn_D__Zda_D,
},
// ZFMMLA <Zm>.S, <Zn>.S, <Zda>.S
{
@@ -2027,11 +2750,11 @@ var insts = [][]instEncoder{
fixedBits: 0x64a0e400,
args: Zm_S__Zn_S__Zda_S,
},
- // ZFMMLA <Zm>.D, <Zn>.D, <Zda>.D
+ // ZFMMLA <Zm>.H, <Zn>.H, <Zda>.H
{
goOp: AZFMMLA,
- fixedBits: 0x64e0e400,
- args: Zm_D__Zn_D__Zda_D,
+ fixedBits: 0x64a0e000,
+ args: Zm_H__Zn_H__Zda_H,
},
// ZFMMLA <Zm>.H, <Zn>.H, <Zda>.S
{
@@ -2156,18 +2879,18 @@ var insts = [][]instEncoder{
},
// ZFRECPX
{
- // ZFRECPX <Zn>.<T>, <Pg>/M, <Zd>.<T>
- {
- goOp: AZFRECPX,
- fixedBits: 0x650ca000,
- args: Zn_T__PgM__Zd_T__1,
- },
// ZFRECPX <Zn>.<T>, <Pg>/Z, <Zd>.<T>
{
goOp: AZFRECPX,
fixedBits: 0x641b8000,
args: Zn_T__PgZ__Zd_T__1,
},
+ // ZFRECPX <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZFRECPX,
+ fixedBits: 0x650ca000,
+ args: Zn_T__PgM__Zd_T__1,
+ },
},
// ZFRINT32X
{
@@ -2186,33 +2909,33 @@ var insts = [][]instEncoder{
},
// ZFRINT32Z
{
- // ZFRINT32Z <Zn>.<T>, <Pg>/Z, <Zd>.<T>
- {
- goOp: AZFRINT32Z,
- fixedBits: 0x641c8000,
- args: Zn_T__PgZ__Zd_T__3,
- },
// ZFRINT32Z <Zn>.<T>, <Pg>/M, <Zd>.<T>
{
goOp: AZFRINT32Z,
fixedBits: 0x6510a000,
args: Zn_T__PgM__Zd_T__3,
},
- },
- // ZFRINT64X
- {
- // ZFRINT64X <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ // ZFRINT32Z <Zn>.<T>, <Pg>/Z, <Zd>.<T>
{
- goOp: AZFRINT64X,
- fixedBits: 0x641da000,
+ goOp: AZFRINT32Z,
+ fixedBits: 0x641c8000,
args: Zn_T__PgZ__Zd_T__3,
},
+ },
+ // ZFRINT64X
+ {
// ZFRINT64X <Zn>.<T>, <Pg>/M, <Zd>.<T>
{
goOp: AZFRINT64X,
fixedBits: 0x6515a000,
args: Zn_T__PgM__Zd_T__3,
},
+ // ZFRINT64X <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZFRINT64X,
+ fixedBits: 0x641da000,
+ args: Zn_T__PgZ__Zd_T__3,
+ },
},
// ZFRINT64Z
{
@@ -2246,33 +2969,33 @@ var insts = [][]instEncoder{
},
// ZFRINTI
{
- // ZFRINTI <Zn>.<T>, <Pg>/Z, <Zd>.<T>
- {
- goOp: AZFRINTI,
- fixedBits: 0x6419e000,
- args: Zn_T__PgZ__Zd_T__1,
- },
// ZFRINTI <Zn>.<T>, <Pg>/M, <Zd>.<T>
{
goOp: AZFRINTI,
fixedBits: 0x6507a000,
args: Zn_T__PgM__Zd_T__1,
},
- },
- // ZFRINTM
- {
- // ZFRINTM <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ // ZFRINTI <Zn>.<T>, <Pg>/Z, <Zd>.<T>
{
- goOp: AZFRINTM,
- fixedBits: 0x6418c000,
+ goOp: AZFRINTI,
+ fixedBits: 0x6419e000,
args: Zn_T__PgZ__Zd_T__1,
},
+ },
+ // ZFRINTM
+ {
// ZFRINTM <Zn>.<T>, <Pg>/M, <Zd>.<T>
{
goOp: AZFRINTM,
fixedBits: 0x6502a000,
args: Zn_T__PgM__Zd_T__1,
},
+ // ZFRINTM <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZFRINTM,
+ fixedBits: 0x6418c000,
+ args: Zn_T__PgZ__Zd_T__1,
+ },
},
// ZFRINTN
{
@@ -2291,48 +3014,48 @@ var insts = [][]instEncoder{
},
// ZFRINTP
{
- // ZFRINTP <Zn>.<T>, <Pg>/M, <Zd>.<T>
- {
- goOp: AZFRINTP,
- fixedBits: 0x6501a000,
- args: Zn_T__PgM__Zd_T__1,
- },
// ZFRINTP <Zn>.<T>, <Pg>/Z, <Zd>.<T>
{
goOp: AZFRINTP,
fixedBits: 0x6418a000,
args: Zn_T__PgZ__Zd_T__1,
},
+ // ZFRINTP <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZFRINTP,
+ fixedBits: 0x6501a000,
+ args: Zn_T__PgM__Zd_T__1,
+ },
},
// ZFRINTX
{
- // ZFRINTX <Zn>.<T>, <Pg>/Z, <Zd>.<T>
- {
- goOp: AZFRINTX,
- fixedBits: 0x6419c000,
- args: Zn_T__PgZ__Zd_T__1,
- },
// ZFRINTX <Zn>.<T>, <Pg>/M, <Zd>.<T>
{
goOp: AZFRINTX,
fixedBits: 0x6506a000,
args: Zn_T__PgM__Zd_T__1,
},
+ // ZFRINTX <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZFRINTX,
+ fixedBits: 0x6419c000,
+ args: Zn_T__PgZ__Zd_T__1,
+ },
},
// ZFRINTZ
{
- // ZFRINTZ <Zn>.<T>, <Pg>/M, <Zd>.<T>
- {
- goOp: AZFRINTZ,
- fixedBits: 0x6503a000,
- args: Zn_T__PgM__Zd_T__1,
- },
// ZFRINTZ <Zn>.<T>, <Pg>/Z, <Zd>.<T>
{
goOp: AZFRINTZ,
fixedBits: 0x6418e000,
args: Zn_T__PgZ__Zd_T__1,
},
+ // ZFRINTZ <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZFRINTZ,
+ fixedBits: 0x6503a000,
+ args: Zn_T__PgM__Zd_T__1,
+ },
},
// ZFRSQRTE
{
@@ -2363,33 +3086,33 @@ var insts = [][]instEncoder{
},
// ZFSQRT
{
- // ZFSQRT <Zn>.<T>, <Pg>/Z, <Zd>.<T>
- {
- goOp: AZFSQRT,
- fixedBits: 0x641ba000,
- args: Zn_T__PgZ__Zd_T__1,
- },
// ZFSQRT <Zn>.<T>, <Pg>/M, <Zd>.<T>
{
goOp: AZFSQRT,
fixedBits: 0x650da000,
args: Zn_T__PgM__Zd_T__1,
},
+ // ZFSQRT <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZFSQRT,
+ fixedBits: 0x641ba000,
+ args: Zn_T__PgZ__Zd_T__1,
+ },
},
// ZFSUB
{
- // ZFSUB <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
- {
- goOp: AZFSUB,
- fixedBits: 0x65000400,
- args: Zm_T__Zn_T__Zd_T__2,
- },
// ZFSUB <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
{
goOp: AZFSUB,
fixedBits: 0x65018000,
args: Zm_T__Zdn_T__PgM__Zdn_T__3,
},
+ // ZFSUB <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZFSUB,
+ fixedBits: 0x65000400,
+ args: Zm_T__Zn_T__Zd_T__2,
+ },
},
// ZFSUBR
{
@@ -2445,6 +3168,186 @@ var insts = [][]instEncoder{
args: Pm_T__Zdn_T,
},
},
+ // ZINDEX
+ {
+ // ZINDEX <R><m>, <R><n>, <Zd>.<T>
+ {
+ goOp: AZINDEX,
+ fixedBits: 0x4e04c00,
+ args: Rm__Rn__Zd_T,
+ },
+ },
+ // ZINDEXW
+ {
+ // ZINDEXW <R><m>, <R><n>, <Zd>.<T>
+ {
+ goOp: AZINDEXW,
+ fixedBits: 0x4204c00,
+ args: Rm__Rn__Zd_T,
+ },
+ },
+ // ZINSR
+ {
+ // ZINSR <R><m>, <Zdn>.<T>
+ {
+ goOp: AZINSR,
+ fixedBits: 0x5e43800,
+ args: Rm__Zdn_T,
+ },
+ },
+ // ZINSRB
+ {
+ // ZINSRB <V><m>, <Zdn>.<T>
+ {
+ goOp: AZINSRB,
+ fixedBits: 0x5343800,
+ args: Vm__Zdn_T,
+ },
+ },
+ // ZINSRD
+ {
+ // ZINSRD <V><m>, <Zdn>.<T>
+ {
+ goOp: AZINSRD,
+ fixedBits: 0x5f43800,
+ args: Vm__Zdn_T,
+ },
+ },
+ // ZINSRH
+ {
+ // ZINSRH <V><m>, <Zdn>.<T>
+ {
+ goOp: AZINSRH,
+ fixedBits: 0x5743800,
+ args: Vm__Zdn_T,
+ },
+ },
+ // ZINSRS
+ {
+ // ZINSRS <V><m>, <Zdn>.<T>
+ {
+ goOp: AZINSRS,
+ fixedBits: 0x5b43800,
+ args: Vm__Zdn_T,
+ },
+ },
+ // ZINSRW
+ {
+ // ZINSRW <R><m>, <Zdn>.<T>
+ {
+ goOp: AZINSRW,
+ fixedBits: 0x5243800,
+ args: Rm__Zdn_T,
+ },
+ },
+ // ZLASTA
+ {
+ // ZLASTA <Zn>.<T>, <Pg>, <R><d>
+ {
+ goOp: AZLASTA,
+ fixedBits: 0x5e0a000,
+ args: Zn_T__Pg__Rd,
+ },
+ },
+ // ZLASTAB
+ {
+ // ZLASTAB <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZLASTAB,
+ fixedBits: 0x5228000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZLASTAD
+ {
+ // ZLASTAD <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZLASTAD,
+ fixedBits: 0x5e28000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZLASTAH
+ {
+ // ZLASTAH <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZLASTAH,
+ fixedBits: 0x5628000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZLASTAS
+ {
+ // ZLASTAS <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZLASTAS,
+ fixedBits: 0x5a28000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZLASTAW
+ {
+ // ZLASTAW <Zn>.<T>, <Pg>, <R><d>
+ {
+ goOp: AZLASTAW,
+ fixedBits: 0x520a000,
+ args: Zn_T__Pg__Rd,
+ },
+ },
+ // ZLASTB
+ {
+ // ZLASTB <Zn>.<T>, <Pg>, <R><d>
+ {
+ goOp: AZLASTB,
+ fixedBits: 0x5e1a000,
+ args: Zn_T__Pg__Rd,
+ },
+ },
+ // ZLASTBB
+ {
+ // ZLASTBB <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZLASTBB,
+ fixedBits: 0x5238000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZLASTBD
+ {
+ // ZLASTBD <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZLASTBD,
+ fixedBits: 0x5e38000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZLASTBH
+ {
+ // ZLASTBH <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZLASTBH,
+ fixedBits: 0x5638000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZLASTBS
+ {
+ // ZLASTBS <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZLASTBS,
+ fixedBits: 0x5a38000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZLASTBW
+ {
+ // ZLASTBW <Zn>.<T>, <Pg>, <R><d>
+ {
+ goOp: AZLASTBW,
+ fixedBits: 0x521a000,
+ args: Zn_T__Pg__Rd,
+ },
+ },
// ZLSL
{
// ZLSL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
@@ -2483,18 +3386,18 @@ var insts = [][]instEncoder{
fixedBits: 0x4118000,
args: Zm_T__Zdn_T__PgM__Zdn_T__1,
},
- // ZLSR <Zm>.D, <Zn>.<T>, <Zd>.<T>
- {
- goOp: AZLSR,
- fixedBits: 0x4208400,
- args: Zm_D__Zn_T__Zd_T,
- },
// ZLSR <Zm>.D, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
{
goOp: AZLSR,
fixedBits: 0x4198000,
args: Zm_D__Zdn_T__PgM__Zdn_T,
},
+ // ZLSR <Zm>.D, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZLSR,
+ fixedBits: 0x4208400,
+ args: Zm_D__Zn_T__Zd_T,
+ },
},
// ZLSRR
{
@@ -2585,18 +3488,18 @@ var insts = [][]instEncoder{
},
// ZMUL
{
- // ZMUL <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
- {
- goOp: AZMUL,
- fixedBits: 0x4206000,
- args: Zm_T__Zn_T__Zd_T__1,
- },
// ZMUL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
{
goOp: AZMUL,
fixedBits: 0x4100000,
args: Zm_T__Zdn_T__PgM__Zdn_T__1,
},
+ // ZMUL <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZMUL,
+ fixedBits: 0x4206000,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
},
// ZNBSL
{
@@ -2633,18 +3536,18 @@ var insts = [][]instEncoder{
},
// ZNOT
{
- // ZNOT <Zn>.<T>, <Pg>/M, <Zd>.<T>
- {
- goOp: AZNOT,
- fixedBits: 0x41ea000,
- args: Zn_T__PgM__Zd_T__2,
- },
// ZNOT <Zn>.<T>, <Pg>/Z, <Zd>.<T>
{
goOp: AZNOT,
fixedBits: 0x40ea000,
args: Zn_T__PgZ__Zd_T__2,
},
+ // ZNOT <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZNOT,
+ fixedBits: 0x41ea000,
+ args: Zn_T__PgM__Zd_T__2,
+ },
},
// ZORQV
{
@@ -2657,33 +3560,69 @@ var insts = [][]instEncoder{
},
// ZORR
{
+ // ZORR <Zm>.D, <Zn>.D, <Zd>.D
+ {
+ goOp: AZORR,
+ fixedBits: 0x4603000,
+ args: Zm_D__Zn_D__Zd_D,
+ },
// ZORR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
{
goOp: AZORR,
fixedBits: 0x4180000,
args: Zm_T__Zdn_T__PgM__Zdn_T__1,
},
- // ZORR <Zm>.D, <Zn>.D, <Zd>.D
+ },
+ // ZORVB
+ {
+ // ZORVB <Zn>.<T>, <Pg>, <V><d>
{
- goOp: AZORR,
- fixedBits: 0x4603000,
- args: Zm_D__Zn_D__Zd_D,
+ goOp: AZORVB,
+ fixedBits: 0x4182000,
+ args: Zn_T__Pg__Vd__1,
},
},
- // ZPMOV
+ // ZORVD
{
- // ZPMOV <Pn>.B, <Zd>
+ // ZORVD <Zn>.<T>, <Pg>, <V><d>
{
- goOp: AZPMOV,
- fixedBits: 0x52b3800,
- args: Pn_B__Zd,
+ goOp: AZORVD,
+ fixedBits: 0x4d82000,
+ args: Zn_T__Pg__Vd__1,
},
+ },
+ // ZORVH
+ {
+ // ZORVH <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZORVH,
+ fixedBits: 0x4582000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZORVS
+ {
+ // ZORVS <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZORVS,
+ fixedBits: 0x4982000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZPMOV
+ {
// ZPMOV <Zn>, <Pd>.B
{
goOp: AZPMOV,
fixedBits: 0x52a3800,
args: Zn__Pd_B,
},
+ // ZPMOV <Pn>.B, <Zd>
+ {
+ goOp: AZPMOV,
+ fixedBits: 0x52b3800,
+ args: Pn_B__Zd,
+ },
},
// ZPMUL
{
@@ -2792,48 +3731,48 @@ var insts = [][]instEncoder{
},
// ZREVD
{
- // ZREVD <Zn>.Q, <Pg>/M, <Zd>.Q
- {
- goOp: AZREVD,
- fixedBits: 0x52e8000,
- args: Zn_Q__PgM__Zd_Q,
- },
// ZREVD <Zn>.Q, <Pg>/Z, <Zd>.Q
{
goOp: AZREVD,
fixedBits: 0x52ea000,
args: Zn_Q__PgZ__Zd_Q,
},
+ // ZREVD <Zn>.Q, <Pg>/M, <Zd>.Q
+ {
+ goOp: AZREVD,
+ fixedBits: 0x52e8000,
+ args: Zn_Q__PgM__Zd_Q,
+ },
},
// ZREVH
{
- // ZREVH <Zn>.<T>, <Pg>/Z, <Zd>.<T>
- {
- goOp: AZREVH,
- fixedBits: 0x5a5a000,
- args: Zn_T__PgZ__Zd_T__5,
- },
// ZREVH <Zn>.<T>, <Pg>/M, <Zd>.<T>
{
goOp: AZREVH,
fixedBits: 0x5a58000,
args: Zn_T__PgM__Zd_T__5,
},
+ // ZREVH <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZREVH,
+ fixedBits: 0x5a5a000,
+ args: Zn_T__PgZ__Zd_T__5,
+ },
},
// ZREVW
{
- // ZREVW <Zn>.D, <Pg>/Z, <Zd>.D
- {
- goOp: AZREVW,
- fixedBits: 0x5e6a000,
- args: Zn_D__PgZ__Zd_D,
- },
// ZREVW <Zn>.D, <Pg>/M, <Zd>.D
{
goOp: AZREVW,
fixedBits: 0x5e68000,
args: Zn_D__PgM__Zd_D,
},
+ // ZREVW <Zn>.D, <Pg>/Z, <Zd>.D
+ {
+ goOp: AZREVW,
+ fixedBits: 0x5e6a000,
+ args: Zn_D__PgZ__Zd_D,
+ },
},
// ZRSUBHNB
{
@@ -2952,6 +3891,15 @@ var insts = [][]instEncoder{
args: Zm_Tb__Zn_Tb__Zd_T__1,
},
},
+ // ZSADDVD
+ {
+ // ZSADDVD <Zn>.<T>, <Pg>, <Dd>
+ {
+ goOp: AZSADDVD,
+ fixedBits: 0x4002000,
+ args: Zn_T__Pg__Dd__1,
+ },
+ },
// ZSADDWB
{
// ZSADDWB <Zm>.<Tb>, <Zn>.<T>, <Zd>.<T>
@@ -2999,35 +3947,23 @@ var insts = [][]instEncoder{
},
// ZSCVTF
{
- // ZSCVTF <Zn>.S, <Pg>/M, <Zd>.D
- {
- goOp: AZSCVTF,
- fixedBits: 0x65d0a000,
- args: Zn_S__PgM__Zd_D,
- },
- // ZSCVTF <Zn>.<Tb>, <Zd>.<T>
- {
- goOp: AZSCVTF,
- fixedBits: 0x650c3000,
- args: Zn_Tb__Zd_T__1,
- },
- // ZSCVTF <Zn>.D, <Pg>/M, <Zd>.S
+ // ZSCVTF <Zn>.H, <Pg>/Z, <Zd>.H
{
goOp: AZSCVTF,
- fixedBits: 0x65d4a000,
- args: Zn_D__PgM__Zd_S,
+ fixedBits: 0x645cc000,
+ args: Zn_H__PgZ__Zd_H,
},
- // ZSCVTF <Zn>.D, <Pg>/Z, <Zd>.S
+ // ZSCVTF <Zn>.S, <Pg>/Z, <Zd>.D
{
goOp: AZSCVTF,
- fixedBits: 0x64dd8000,
- args: Zn_D__PgZ__Zd_S,
+ fixedBits: 0x64dc8000,
+ args: Zn_S__PgZ__Zd_D,
},
- // ZSCVTF <Zn>.D, <Pg>/M, <Zd>.D
+ // ZSCVTF <Zn>.H, <Pg>/M, <Zd>.H
{
goOp: AZSCVTF,
- fixedBits: 0x65d6a000,
- args: Zn_D__PgM__Zd_D,
+ fixedBits: 0x6552a000,
+ args: Zn_H__PgM__Zd_H,
},
// ZSCVTF <Zn>.D, <Pg>/Z, <Zd>.D
{
@@ -3035,12 +3971,6 @@ var insts = [][]instEncoder{
fixedBits: 0x64ddc000,
args: Zn_D__PgZ__Zd_D,
},
- // ZSCVTF <Zn>.H, <Pg>/Z, <Zd>.H
- {
- goOp: AZSCVTF,
- fixedBits: 0x645cc000,
- args: Zn_H__PgZ__Zd_H,
- },
// ZSCVTF <Zn>.S, <Pg>/M, <Zd>.H
{
goOp: AZSCVTF,
@@ -3053,11 +3983,29 @@ var insts = [][]instEncoder{
fixedBits: 0x645d8000,
args: Zn_S__PgZ__Zd_H,
},
- // ZSCVTF <Zn>.D, <Pg>/Z, <Zd>.H
+ // ZSCVTF <Zn>.S, <Pg>/M, <Zd>.S
{
goOp: AZSCVTF,
- fixedBits: 0x645dc000,
- args: Zn_D__PgZ__Zd_H,
+ fixedBits: 0x6594a000,
+ args: Zn_S__PgM__Zd_S,
+ },
+ // ZSCVTF <Zn>.S, <Pg>/Z, <Zd>.S
+ {
+ goOp: AZSCVTF,
+ fixedBits: 0x649d8000,
+ args: Zn_S__PgZ__Zd_S,
+ },
+ // ZSCVTF <Zn>.S, <Pg>/M, <Zd>.D
+ {
+ goOp: AZSCVTF,
+ fixedBits: 0x65d0a000,
+ args: Zn_S__PgM__Zd_D,
+ },
+ // ZSCVTF <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZSCVTF,
+ fixedBits: 0x650c3000,
+ args: Zn_Tb__Zd_T__1,
},
// ZSCVTF <Zn>.D, <Pg>/M, <Zd>.H
{
@@ -3065,29 +4013,29 @@ var insts = [][]instEncoder{
fixedBits: 0x6556a000,
args: Zn_D__PgM__Zd_H,
},
- // ZSCVTF <Zn>.S, <Pg>/Z, <Zd>.D
+ // ZSCVTF <Zn>.D, <Pg>/Z, <Zd>.H
{
goOp: AZSCVTF,
- fixedBits: 0x64dc8000,
- args: Zn_S__PgZ__Zd_D,
+ fixedBits: 0x645dc000,
+ args: Zn_D__PgZ__Zd_H,
},
- // ZSCVTF <Zn>.H, <Pg>/M, <Zd>.H
+ // ZSCVTF <Zn>.D, <Pg>/M, <Zd>.S
{
goOp: AZSCVTF,
- fixedBits: 0x6552a000,
- args: Zn_H__PgM__Zd_H,
+ fixedBits: 0x65d4a000,
+ args: Zn_D__PgM__Zd_S,
},
- // ZSCVTF <Zn>.S, <Pg>/Z, <Zd>.S
+ // ZSCVTF <Zn>.D, <Pg>/Z, <Zd>.S
{
goOp: AZSCVTF,
- fixedBits: 0x649d8000,
- args: Zn_S__PgZ__Zd_S,
+ fixedBits: 0x64dd8000,
+ args: Zn_D__PgZ__Zd_S,
},
- // ZSCVTF <Zn>.S, <Pg>/M, <Zd>.S
+ // ZSCVTF <Zn>.D, <Pg>/M, <Zd>.D
{
goOp: AZSCVTF,
- fixedBits: 0x6594a000,
- args: Zn_S__PgM__Zd_S,
+ fixedBits: 0x65d6a000,
+ args: Zn_D__PgM__Zd_D,
},
},
// ZSCVTFLT
@@ -3119,12 +4067,6 @@ var insts = [][]instEncoder{
},
// ZSDOT
{
- // ZSDOT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
- {
- goOp: AZSDOT,
- fixedBits: 0x44800000,
- args: Zm_Tb__Zn_Tb__Zda_T__2,
- },
// ZSDOT <Zm>.H, <Zn>.H, <Zda>.S
{
goOp: AZSDOT,
@@ -3137,6 +4079,12 @@ var insts = [][]instEncoder{
fixedBits: 0x44400000,
args: Zm_B__Zn_B__Zda_H,
},
+ // ZSDOT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
+ {
+ goOp: AZSDOT,
+ fixedBits: 0x44800000,
+ args: Zm_Tb__Zn_Tb__Zda_T__2,
+ },
},
// ZSEL
{
@@ -3219,6 +4167,42 @@ var insts = [][]instEncoder{
args: Zn_Tb__Pg__Vd_T__1,
},
},
+ // ZSMAXVB
+ {
+ // ZSMAXVB <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZSMAXVB,
+ fixedBits: 0x4082000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZSMAXVD
+ {
+ // ZSMAXVD <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZSMAXVD,
+ fixedBits: 0x4c82000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZSMAXVH
+ {
+ // ZSMAXVH <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZSMAXVH,
+ fixedBits: 0x4482000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZSMAXVS
+ {
+ // ZSMAXVS <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZSMAXVS,
+ fixedBits: 0x4882000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
// ZSMIN
{
// ZSMIN <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
@@ -3246,6 +4230,42 @@ var insts = [][]instEncoder{
args: Zn_Tb__Pg__Vd_T__1,
},
},
+ // ZSMINVB
+ {
+ // ZSMINVB <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZSMINVB,
+ fixedBits: 0x40a2000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZSMINVD
+ {
+ // ZSMINVD <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZSMINVD,
+ fixedBits: 0x4ca2000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZSMINVH
+ {
+ // ZSMINVH <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZSMINVH,
+ fixedBits: 0x44a2000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZSMINVS
+ {
+ // ZSMINVS <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZSMINVS,
+ fixedBits: 0x48a2000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
// ZSMLALB
{
// ZSMLALB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
@@ -3293,18 +4313,18 @@ var insts = [][]instEncoder{
},
// ZSMULH
{
- // ZSMULH <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
- {
- goOp: AZSMULH,
- fixedBits: 0x4206800,
- args: Zm_T__Zn_T__Zd_T__1,
- },
// ZSMULH <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
{
goOp: AZSMULH,
fixedBits: 0x4120000,
args: Zm_T__Zdn_T__PgM__Zdn_T__1,
},
+ // ZSMULH <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZSMULH,
+ fixedBits: 0x4206800,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
},
// ZSMULLB
{
@@ -3335,33 +4355,33 @@ var insts = [][]instEncoder{
},
// ZSQABS
{
- // ZSQABS <Zn>.<T>, <Pg>/M, <Zd>.<T>
- {
- goOp: AZSQABS,
- fixedBits: 0x4408a000,
- args: Zn_T__PgM__Zd_T__2,
- },
// ZSQABS <Zn>.<T>, <Pg>/Z, <Zd>.<T>
{
goOp: AZSQABS,
fixedBits: 0x440aa000,
args: Zn_T__PgZ__Zd_T__2,
},
+ // ZSQABS <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZSQABS,
+ fixedBits: 0x4408a000,
+ args: Zn_T__PgM__Zd_T__2,
+ },
},
// ZSQADD
{
- // ZSQADD <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
- {
- goOp: AZSQADD,
- fixedBits: 0x4201000,
- args: Zm_T__Zn_T__Zd_T__1,
- },
// ZSQADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
{
goOp: AZSQADD,
fixedBits: 0x44188000,
args: Zm_T__Zdn_T__PgM__Zdn_T__1,
},
+ // ZSQADD <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZSQADD,
+ fixedBits: 0x4201000,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
},
// ZSQDECP
{
@@ -3542,18 +4562,18 @@ var insts = [][]instEncoder{
},
// ZSQSUB
{
- // ZSQSUB <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
- {
- goOp: AZSQSUB,
- fixedBits: 0x4201800,
- args: Zm_T__Zn_T__Zd_T__1,
- },
// ZSQSUB <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
{
goOp: AZSQSUB,
fixedBits: 0x441a8000,
args: Zm_T__Zdn_T__PgM__Zdn_T__1,
},
+ // ZSQSUB <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZSQSUB,
+ fixedBits: 0x4201800,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
},
// ZSQSUBR
{
@@ -3683,18 +4703,18 @@ var insts = [][]instEncoder{
},
// ZSUB
{
- // ZSUB <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
- {
- goOp: AZSUB,
- fixedBits: 0x4200400,
- args: Zm_T__Zn_T__Zd_T__1,
- },
// ZSUB <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
{
goOp: AZSUB,
fixedBits: 0x4010000,
args: Zm_T__Zdn_T__PgM__Zdn_T__1,
},
+ // ZSUB <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZSUB,
+ fixedBits: 0x4200400,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
},
// ZSUBHNB
{
@@ -3725,18 +4745,18 @@ var insts = [][]instEncoder{
},
// ZSUBPT
{
- // ZSUBPT <Zm>.D, <Zn>.D, <Zd>.D
- {
- goOp: AZSUBPT,
- fixedBits: 0x4e00c00,
- args: Zm_D__Zn_D__Zd_D,
- },
// ZSUBPT <Zm>.D, <Zdn>.D, <Pg>/M, <Zdn>.D
{
goOp: AZSUBPT,
fixedBits: 0x4c50000,
args: Zm_D__Zdn_D__PgM__Zdn_D,
},
+ // ZSUBPT <Zm>.D, <Zn>.D, <Zd>.D
+ {
+ goOp: AZSUBPT,
+ fixedBits: 0x4e00c00,
+ args: Zm_D__Zn_D__Zd_D,
+ },
},
// ZSUBR
{
@@ -3776,18 +4796,18 @@ var insts = [][]instEncoder{
},
// ZSXTB
{
- // ZSXTB <Zn>.<T>, <Pg>/Z, <Zd>.<T>
- {
- goOp: AZSXTB,
- fixedBits: 0x400a000,
- args: Zn_T__PgZ__Zd_T__4,
- },
// ZSXTB <Zn>.<T>, <Pg>/M, <Zd>.<T>
{
goOp: AZSXTB,
fixedBits: 0x410a000,
args: Zn_T__PgM__Zd_T__4,
},
+ // ZSXTB <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZSXTB,
+ fixedBits: 0x400a000,
+ args: Zn_T__PgZ__Zd_T__4,
+ },
},
// ZSXTH
{
@@ -3839,18 +4859,18 @@ var insts = [][]instEncoder{
},
// ZTRN1
{
- // ZTRN1 <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
- {
- goOp: AZTRN1,
- fixedBits: 0x5207000,
- args: Zm_T__Zn_T__Zd_T__1,
- },
// ZTRN1 <Zm>.Q, <Zn>.Q, <Zd>.Q
{
goOp: AZTRN1,
fixedBits: 0x5a01800,
args: Zm_Q__Zn_Q__Zd_Q,
},
+ // ZTRN1 <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZTRN1,
+ fixedBits: 0x5207000,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
},
// ZTRN2
{
@@ -3957,6 +4977,15 @@ var insts = [][]instEncoder{
args: Zm_Tb__Zn_Tb__Zd_T__1,
},
},
+ // ZUADDVD
+ {
+ // ZUADDVD <Zn>.<T>, <Pg>, <Dd>
+ {
+ goOp: AZUADDVD,
+ fixedBits: 0x4012000,
+ args: Zn_T__Pg__Dd__2,
+ },
+ },
// ZUADDWB
{
// ZUADDWB <Zm>.<Tb>, <Zn>.<T>, <Zd>.<T>
@@ -3986,11 +5015,11 @@ var insts = [][]instEncoder{
},
// ZUCVTF
{
- // ZUCVTF <Zn>.D, <Pg>/Z, <Zd>.S
+ // ZUCVTF <Zn>.D, <Pg>/Z, <Zd>.H
{
goOp: AZUCVTF,
- fixedBits: 0x64dda000,
- args: Zn_D__PgZ__Zd_S,
+ fixedBits: 0x645de000,
+ args: Zn_D__PgZ__Zd_H,
},
// ZUCVTF <Zn>.D, <Pg>/M, <Zd>.H
{
@@ -3998,47 +5027,35 @@ var insts = [][]instEncoder{
fixedBits: 0x6557a000,
args: Zn_D__PgM__Zd_H,
},
- // ZUCVTF <Zn>.S, <Pg>/Z, <Zd>.H
- {
- goOp: AZUCVTF,
- fixedBits: 0x645da000,
- args: Zn_S__PgZ__Zd_H,
- },
- // ZUCVTF <Zn>.S, <Pg>/M, <Zd>.S
- {
- goOp: AZUCVTF,
- fixedBits: 0x6595a000,
- args: Zn_S__PgM__Zd_S,
- },
- // ZUCVTF <Zn>.S, <Pg>/Z, <Zd>.S
+ // ZUCVTF <Zn>.<Tb>, <Zd>.<T>
{
goOp: AZUCVTF,
- fixedBits: 0x649da000,
- args: Zn_S__PgZ__Zd_S,
+ fixedBits: 0x650c3400,
+ args: Zn_Tb__Zd_T__1,
},
- // ZUCVTF <Zn>.S, <Pg>/M, <Zd>.D
+ // ZUCVTF <Zn>.H, <Pg>/M, <Zd>.H
{
goOp: AZUCVTF,
- fixedBits: 0x65d1a000,
- args: Zn_S__PgM__Zd_D,
+ fixedBits: 0x6553a000,
+ args: Zn_H__PgM__Zd_H,
},
- // ZUCVTF <Zn>.S, <Pg>/Z, <Zd>.D
+ // ZUCVTF <Zn>.D, <Pg>/Z, <Zd>.D
{
goOp: AZUCVTF,
- fixedBits: 0x64dca000,
- args: Zn_S__PgZ__Zd_D,
+ fixedBits: 0x64dde000,
+ args: Zn_D__PgZ__Zd_D,
},
- // ZUCVTF <Zn>.H, <Pg>/M, <Zd>.H
+ // ZUCVTF <Zn>.D, <Pg>/M, <Zd>.D
{
goOp: AZUCVTF,
- fixedBits: 0x6553a000,
- args: Zn_H__PgM__Zd_H,
+ fixedBits: 0x65d7a000,
+ args: Zn_D__PgM__Zd_D,
},
- // ZUCVTF <Zn>.D, <Pg>/Z, <Zd>.H
+ // ZUCVTF <Zn>.D, <Pg>/Z, <Zd>.S
{
goOp: AZUCVTF,
- fixedBits: 0x645de000,
- args: Zn_D__PgZ__Zd_H,
+ fixedBits: 0x64dda000,
+ args: Zn_D__PgZ__Zd_S,
},
// ZUCVTF <Zn>.D, <Pg>/M, <Zd>.S
{
@@ -4052,29 +5069,41 @@ var insts = [][]instEncoder{
fixedBits: 0x645ce000,
args: Zn_H__PgZ__Zd_H,
},
- // ZUCVTF <Zn>.D, <Pg>/M, <Zd>.D
+ // ZUCVTF <Zn>.S, <Pg>/M, <Zd>.H
{
goOp: AZUCVTF,
- fixedBits: 0x65d7a000,
- args: Zn_D__PgM__Zd_D,
+ fixedBits: 0x6555a000,
+ args: Zn_S__PgM__Zd_H,
},
- // ZUCVTF <Zn>.D, <Pg>/Z, <Zd>.D
+ // ZUCVTF <Zn>.S, <Pg>/Z, <Zd>.D
{
goOp: AZUCVTF,
- fixedBits: 0x64dde000,
- args: Zn_D__PgZ__Zd_D,
+ fixedBits: 0x64dca000,
+ args: Zn_S__PgZ__Zd_D,
},
- // ZUCVTF <Zn>.S, <Pg>/M, <Zd>.H
+ // ZUCVTF <Zn>.S, <Pg>/M, <Zd>.D
{
goOp: AZUCVTF,
- fixedBits: 0x6555a000,
- args: Zn_S__PgM__Zd_H,
+ fixedBits: 0x65d1a000,
+ args: Zn_S__PgM__Zd_D,
},
- // ZUCVTF <Zn>.<Tb>, <Zd>.<T>
+ // ZUCVTF <Zn>.S, <Pg>/Z, <Zd>.S
{
goOp: AZUCVTF,
- fixedBits: 0x650c3400,
- args: Zn_Tb__Zd_T__1,
+ fixedBits: 0x649da000,
+ args: Zn_S__PgZ__Zd_S,
+ },
+ // ZUCVTF <Zn>.S, <Pg>/M, <Zd>.S
+ {
+ goOp: AZUCVTF,
+ fixedBits: 0x6595a000,
+ args: Zn_S__PgM__Zd_S,
+ },
+ // ZUCVTF <Zn>.S, <Pg>/Z, <Zd>.H
+ {
+ goOp: AZUCVTF,
+ fixedBits: 0x645da000,
+ args: Zn_S__PgZ__Zd_H,
},
},
// ZUCVTFLT
@@ -4106,18 +5135,18 @@ var insts = [][]instEncoder{
},
// ZUDOT
{
- // ZUDOT <Zm>.B, <Zn>.B, <Zda>.H
- {
- goOp: AZUDOT,
- fixedBits: 0x44400400,
- args: Zm_B__Zn_B__Zda_H,
- },
// ZUDOT <Zm>.H, <Zn>.H, <Zda>.S
{
goOp: AZUDOT,
fixedBits: 0x4400cc00,
args: Zm_H__Zn_H__Zda_S,
},
+ // ZUDOT <Zm>.B, <Zn>.B, <Zda>.H
+ {
+ goOp: AZUDOT,
+ fixedBits: 0x44400400,
+ args: Zm_B__Zn_B__Zda_H,
+ },
// ZUDOT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
{
goOp: AZUDOT,
@@ -4179,6 +5208,42 @@ var insts = [][]instEncoder{
args: Zn_Tb__Pg__Vd_T__1,
},
},
+ // ZUMAXVB
+ {
+ // ZUMAXVB <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZUMAXVB,
+ fixedBits: 0x4092000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZUMAXVD
+ {
+ // ZUMAXVD <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZUMAXVD,
+ fixedBits: 0x4c92000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZUMAXVH
+ {
+ // ZUMAXVH <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZUMAXVH,
+ fixedBits: 0x4492000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZUMAXVS
+ {
+ // ZUMAXVS <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZUMAXVS,
+ fixedBits: 0x4892000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
// ZUMIN
{
// ZUMIN <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
@@ -4206,6 +5271,42 @@ var insts = [][]instEncoder{
args: Zn_Tb__Pg__Vd_T__1,
},
},
+ // ZUMINVB
+ {
+ // ZUMINVB <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZUMINVB,
+ fixedBits: 0x40b2000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZUMINVD
+ {
+ // ZUMINVD <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZUMINVD,
+ fixedBits: 0x4cb2000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZUMINVH
+ {
+ // ZUMINVH <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZUMINVH,
+ fixedBits: 0x44b2000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
+ // ZUMINVS
+ {
+ // ZUMINVS <Zn>.<T>, <Pg>, <V><d>
+ {
+ goOp: AZUMINVS,
+ fixedBits: 0x48b2000,
+ args: Zn_T__Pg__Vd__1,
+ },
+ },
// ZUMLALB
{
// ZUMLALB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
@@ -4286,18 +5387,18 @@ var insts = [][]instEncoder{
},
// ZUQADD
{
- // ZUQADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
- {
- goOp: AZUQADD,
- fixedBits: 0x44198000,
- args: Zm_T__Zdn_T__PgM__Zdn_T__1,
- },
// ZUQADD <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
{
goOp: AZUQADD,
fixedBits: 0x4201400,
args: Zm_T__Zn_T__Zd_T__1,
},
+ // ZUQADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZUQADD,
+ fixedBits: 0x44198000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
},
// ZUQDECP
{
@@ -4355,18 +5456,18 @@ var insts = [][]instEncoder{
},
// ZUQSUB
{
- // ZUQSUB <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
- {
- goOp: AZUQSUB,
- fixedBits: 0x441b8000,
- args: Zm_T__Zdn_T__PgM__Zdn_T__1,
- },
// ZUQSUB <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
{
goOp: AZUQSUB,
fixedBits: 0x4201c00,
args: Zm_T__Zn_T__Zd_T__1,
},
+ // ZUQSUB <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZUQSUB,
+ fixedBits: 0x441b8000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
},
// ZUQSUBR
{
@@ -4397,18 +5498,18 @@ var insts = [][]instEncoder{
},
// ZURECPE
{
- // ZURECPE <Zn>.S, <Pg>/M, <Zd>.S
- {
- goOp: AZURECPE,
- fixedBits: 0x4480a000,
- args: Zn_S__PgM__Zd_S,
- },
// ZURECPE <Zn>.S, <Pg>/Z, <Zd>.S
{
goOp: AZURECPE,
fixedBits: 0x4482a000,
args: Zn_S__PgZ__Zd_S,
},
+ // ZURECPE <Zn>.S, <Pg>/M, <Zd>.S
+ {
+ goOp: AZURECPE,
+ fixedBits: 0x4480a000,
+ args: Zn_S__PgM__Zd_S,
+ },
},
// ZURHADD
{
@@ -4550,18 +5651,18 @@ var insts = [][]instEncoder{
},
// ZUXTH
{
- // ZUXTH <Zn>.<T>, <Pg>/M, <Zd>.<T>
- {
- goOp: AZUXTH,
- fixedBits: 0x493a000,
- args: Zn_T__PgM__Zd_T__5,
- },
// ZUXTH <Zn>.<T>, <Pg>/Z, <Zd>.<T>
{
goOp: AZUXTH,
fixedBits: 0x483a000,
args: Zn_T__PgZ__Zd_T__5,
},
+ // ZUXTH <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZUXTH,
+ fixedBits: 0x493a000,
+ args: Zn_T__PgM__Zd_T__5,
+ },
},
// ZUXTW
{
@@ -4580,18 +5681,18 @@ var insts = [][]instEncoder{
},
// ZUZP1
{
- // ZUZP1 <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
- {
- goOp: AZUZP1,
- fixedBits: 0x5206800,
- args: Zm_T__Zn_T__Zd_T__1,
- },
// ZUZP1 <Zm>.Q, <Zn>.Q, <Zd>.Q
{
goOp: AZUZP1,
fixedBits: 0x5a00800,
args: Zm_Q__Zn_Q__Zd_Q,
},
+ // ZUZP1 <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZUZP1,
+ fixedBits: 0x5206800,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
},
// ZUZP2
{
@@ -4760,6 +5861,13 @@ var a_ARNG_Pm1620_SizeBHSD2224 = operand{
},
}
+var a_ARNG_Pm59v1_SizeBHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodePm59v1, enc_Pm},
+ {encodeSizeBHSD2224, enc_size},
+ },
+}
+
var a_ARNG_Pm59v1_SizeHSD2224 = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
{encodePm59v1, enc_Pm},
@@ -5110,6 +6218,13 @@ var a_ARNG_ZdnSrcDst_ArngBCheck = operand{
},
}
+var a_ARNG_ZdnSrcDst_SizeBHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZdnSrcDst, enc_Zdn},
+ {encodeSizeBHSD2224, enc_size},
+ },
+}
+
var a_ARNG_ZdnSrcDst_SizeHSD2224 = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
{encodeZdnSrcDst, enc_Zdn},
@@ -5229,62 +6344,76 @@ var a_ARNG_Zm1621_SzSD2223 = operand{
},
}
-var a_ARNG_Zm510_ArngBCheck = operand{
+var a_ARNG_Zm510V1_ArngBCheck = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
- {encodeZm510, enc_Zm},
+ {encodeZm510V1, enc_Zm},
{encodeArngBCheck, enc_NIL},
},
}
-var a_ARNG_Zm510_ArngDCheck = operand{
+var a_ARNG_Zm510V1_ArngDCheck = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
- {encodeZm510, enc_Zm},
+ {encodeZm510V1, enc_Zm},
{encodeArngDCheck, enc_NIL},
},
}
-var a_ARNG_Zm510_ArngHCheck = operand{
+var a_ARNG_Zm510V1_ArngHCheck = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
- {encodeZm510, enc_Zm},
+ {encodeZm510V1, enc_Zm},
{encodeArngHCheck, enc_NIL},
},
}
-var a_ARNG_Zm510_ArngSCheck = operand{
+var a_ARNG_Zm510V1_ArngSCheck = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
- {encodeZm510, enc_Zm},
+ {encodeZm510V1, enc_Zm},
{encodeArngSCheck, enc_NIL},
},
}
-var a_ARNG_Zm510_Size0SD2223 = operand{
+var a_ARNG_Zm510V1_Size0SD2223 = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
- {encodeZm510, enc_Zm},
+ {encodeZm510V1, enc_Zm},
{encodeSize0SD2223, enc_size0},
},
}
-var a_ARNG_Zm510_SizeBHSD2224 = operand{
+var a_ARNG_Zm510V1_SizeBHSD2224 = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
- {encodeZm510, enc_Zm},
+ {encodeZm510V1, enc_Zm},
{encodeSizeBHSD2224, enc_size},
},
}
-var a_ARNG_Zm510_SizeHSD2224 = operand{
+var a_ARNG_Zm510V1_SizeHSD2224 = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
- {encodeZm510, enc_Zm},
+ {encodeZm510V1, enc_Zm},
{encodeSizeHSD2224, enc_size},
},
}
-var a_ARNG_Zm510_SizeHSD2224No00 = operand{
+var a_ARNG_Zm510V1_SizeHSD2224No00 = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
- {encodeZm510, enc_Zm},
+ {encodeZm510V1, enc_Zm},
{encodeSizeHSD2224No00, enc_size},
},
}
+var a_ARNG_Zm510V2_SizeBHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm510V2, enc_Zm},
+ {encodeSizeBHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_Zm510V2_SizeHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm510V2, enc_Zm},
+ {encodeSizeHSD2224, enc_size},
+ },
+}
+
var a_ARNG_Zn510Src_ArngBCheck = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
{encodeZn510Src, enc_Zn},
@@ -5327,6 +6456,13 @@ var a_ARNG_Zn510Src_Size0HalfwordMergeZero = operand{
},
}
+var a_ARNG_Zn510Src_SizeBHS2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510Src, enc_Zn},
+ {encodeSizeBHS2224, enc_size},
+ },
+}
+
var a_ARNG_Zn510Src_SizeBHSD2224 = operand{
class: AC_ARNG, elemEncoders: []elemEncoder{
{encodeZn510Src, enc_Zn},
@@ -5614,6 +6750,118 @@ var a_PREG_Pv59_Noop = operand{
},
}
+var a_SPZGREG_Noop_Rd05 = operand{
+ class: AC_SPZGREG, elemEncoders: []elemEncoder{
+ {encodeNoop, enc_NIL},
+ {encodeRd05, enc_Rd},
+ },
+}
+
+var a_SPZGREG_Noop_Rd05ZR = operand{
+ class: AC_SPZGREG, elemEncoders: []elemEncoder{
+ {encodeNoop, enc_NIL},
+ {encodeRd05ZR, enc_Rd},
+ },
+}
+
+var a_SPZGREG_Noop_Rdn05ZR = operand{
+ class: AC_SPZGREG, elemEncoders: []elemEncoder{
+ {encodeNoop, enc_NIL},
+ {encodeRdn05ZR, enc_Rdn},
+ },
+}
+
+var a_SPZGREG_Noop_Rm1621 = operand{
+ class: AC_SPZGREG, elemEncoders: []elemEncoder{
+ {encodeNoop, enc_NIL},
+ {encodeRm1621, enc_Rm},
+ },
+}
+
+var a_SPZGREG_Noop_Rm1621ZR = operand{
+ class: AC_SPZGREG, elemEncoders: []elemEncoder{
+ {encodeNoop, enc_NIL},
+ {encodeRm1621ZR, enc_Rm},
+ },
+}
+
+var a_SPZGREG_Noop_Rm510ZR = operand{
+ class: AC_SPZGREG, elemEncoders: []elemEncoder{
+ {encodeNoop, enc_NIL},
+ {encodeRm510ZR, enc_Rm},
+ },
+}
+
+var a_SPZGREG_Noop_Rn510 = operand{
+ class: AC_SPZGREG, elemEncoders: []elemEncoder{
+ {encodeNoop, enc_NIL},
+ {encodeRn510, enc_Rn},
+ },
+}
+
+var a_SPZGREG_Noop_Rn510SP = operand{
+ class: AC_SPZGREG, elemEncoders: []elemEncoder{
+ {encodeNoop, enc_NIL},
+ {encodeRn510SP, enc_Rn},
+ },
+}
+
+var a_SPZGREG_Noop_Rn510ZR = operand{
+ class: AC_SPZGREG, elemEncoders: []elemEncoder{
+ {encodeNoop, enc_NIL},
+ {encodeRn510ZR, enc_Rn},
+ },
+}
+
+var a_SPZGREG_Noop_Wdn05 = operand{
+ class: AC_SPZGREG, elemEncoders: []elemEncoder{
+ {encodeNoop, enc_NIL},
+ {encodeWdn05, enc_Rdn},
+ },
+}
+
+var a_SPZGREG_Noop_Xdn05 = operand{
+ class: AC_SPZGREG, elemEncoders: []elemEncoder{
+ {encodeNoop, enc_NIL},
+ {encodeXdn05, enc_Rdn},
+ },
+}
+
+var a_VREG_Noop_Vd05 = operand{
+ class: AC_VREG, elemEncoders: []elemEncoder{
+ {encodeNoop, enc_NIL},
+ {encodeVd05, enc_Vd},
+ },
+}
+
+var a_VREG_Noop_Vd0564 = operand{
+ class: AC_VREG, elemEncoders: []elemEncoder{
+ {encodeNoop, enc_NIL},
+ {encodeVd0564, enc_Vd},
+ },
+}
+
+var a_VREG_Noop_Vdn05 = operand{
+ class: AC_VREG, elemEncoders: []elemEncoder{
+ {encodeNoop, enc_NIL},
+ {encodeVdn05, enc_Vdn},
+ },
+}
+
+var a_VREG_Noop_Vm510 = operand{
+ class: AC_VREG, elemEncoders: []elemEncoder{
+ {encodeNoop, enc_NIL},
+ {encodeVm510, enc_Vm},
+ },
+}
+
+var a_VREG_Noop_Vn510 = operand{
+ class: AC_VREG, elemEncoders: []elemEncoder{
+ {encodeNoop, enc_NIL},
+ {encodeVn510, enc_Vn},
+ },
+}
+
var a_ZREG_Zd_Noop = operand{
class: AC_ZREG, elemEncoders: []elemEncoder{
{encodeZd, enc_Zd},
@@ -5680,6 +6928,16 @@ var Pm_T__Pn_T__Pd_T = []operand{
a_ARNG_Pd_SizeBHSD2224,
}
+var Pm_T__Wdn = []operand{
+ a_ARNG_Pm59v1_SizeBHSD2224,
+ a_SPZGREG_Noop_Wdn05,
+}
+
+var Pm_T__Xdn = []operand{
+ a_ARNG_Pm59v1_SizeBHSD2224,
+ a_SPZGREG_Noop_Xdn05,
+}
+
var Pm_T__Zdn_T = []operand{
a_ARNG_Pm59v1_SizeHSD2224,
a_ARNG_ZdnSrcDst_SizeHSD2224,
@@ -5721,6 +6979,68 @@ var Pn_T__Pd_T = []operand{
a_ARNG_Pd_SizeBHSD2224,
}
+var Pn_T__Pg__Xd = []operand{
+ a_ARNG_Pn59v2_SizeBHSD2224,
+ a_PREG_Pg1014_Noop,
+ a_SPZGREG_Noop_Rd05,
+}
+
+var Rm__Rn = []operand{
+ a_SPZGREG_Noop_Rm1621ZR,
+ a_SPZGREG_Noop_Rn510ZR,
+}
+
+var Rm__Rn__Pd_T = []operand{
+ a_SPZGREG_Noop_Rm1621ZR,
+ a_SPZGREG_Noop_Rn510ZR,
+ a_ARNG_Pd_SizeBHSD2224,
+}
+
+var Rm__Rn__Zd_T = []operand{
+ a_SPZGREG_Noop_Rm1621ZR,
+ a_SPZGREG_Noop_Rn510ZR,
+ a_ARNG_Zd_SizeBHSD2224,
+}
+
+var Rm__Zdn_T = []operand{
+ a_SPZGREG_Noop_Rm510ZR,
+ a_ARNG_ZdnSrcDst_SizeBHSD2224,
+}
+
+var RnSP__PgM__Zd_T = []operand{
+ a_SPZGREG_Noop_Rn510SP,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_Zd_SizeBHSD2224,
+}
+
+var RnSP__Zd_T = []operand{
+ a_SPZGREG_Noop_Rn510SP,
+ a_ARNG_Zd_SizeBHSD2224,
+}
+
+var Vm__Zdn_T = []operand{
+ a_VREG_Noop_Vm510,
+ a_ARNG_ZdnSrcDst_SizeBHSD2224,
+}
+
+var Vn__PgM__Zd_T = []operand{
+ a_VREG_Noop_Vn510,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_Zd_SizeBHSD2224,
+}
+
+var Wdn__Pm_T__Xdn = []operand{
+ a_SPZGREG_Noop_Wdn05,
+ a_ARNG_Pm59v1_SizeBHSD2224,
+ a_SPZGREG_Noop_Xdn05,
+}
+
+var Xm__Xn__Pd_T = []operand{
+ a_SPZGREG_Noop_Rm1621,
+ a_SPZGREG_Noop_Rn510,
+ a_ARNG_Pd_SizeBHSD2224,
+}
+
var Za_D__Zm_D__Zdn_D = []operand{
a_ARNG_Za5103Rd_ArngDCheck,
a_ARNG_Zm1621_ArngDCheck,
@@ -5729,7 +7049,7 @@ var Za_D__Zm_D__Zdn_D = []operand{
var Za_T__Zm_T__PgM__Zdn_T__1 = []operand{
a_ARNG_Za16213Rd_SizeHSD2224,
- a_ARNG_Zm510_SizeHSD2224,
+ a_ARNG_Zm510V1_SizeHSD2224,
a_PREGZM_Pg1013_MergePredCheck,
a_ARNG_ZdnDest_SizeHSD2224,
}
@@ -5754,7 +7074,7 @@ var Zk_D__Zm_D__Zdn_D__Zdn_D = []operand{
}
var Zm_B__Zdn_B__Zdn_B = []operand{
- a_ARNG_Zm510_ArngBCheck,
+ a_ARNG_Zm510V1_ArngBCheck,
a_ARNG_ZdnDest_ArngBCheck,
a_ARNG_ZdnDest_ArngBCheck,
}
@@ -5778,14 +7098,14 @@ var Zm_B__Zn_B__Zda_S = []operand{
}
var Zm_D__Zdn_D__PgM__Zdn_D = []operand{
- a_ARNG_Zm510_ArngDCheck,
+ a_ARNG_Zm510V1_ArngDCheck,
a_ARNG_ZdnDest_ArngDCheck,
a_PREGZM_Pg1013_MergePredCheck,
a_ARNG_ZdnDest_ArngDCheck,
}
var Zm_D__Zdn_T__PgM__Zdn_T = []operand{
- a_ARNG_Zm510_ArngDCheck,
+ a_ARNG_Zm510V1_ArngDCheck,
a_ARNG_ZdnDest_SizeBHS2224,
a_PREGZM_Pg1013_MergePredCheck,
a_ARNG_ZdnDest_SizeBHS2224,
@@ -5823,7 +7143,7 @@ var Zm_D__Zn_T__Zd_T = []operand{
}
var Zm_H__Zdn_H__PgM__Zdn_H = []operand{
- a_ARNG_Zm510_ArngHCheck,
+ a_ARNG_Zm510V1_ArngHCheck,
a_ARNG_ZdnDest_ArngHCheck,
a_PREGZM_Pg1013_MergePredCheck,
a_ARNG_ZdnDest_ArngHCheck,
@@ -5861,7 +7181,7 @@ var Zm_Q__Zn_Q__Zd_Q = []operand{
}
var Zm_S__Zdn_S__Zdn_S = []operand{
- a_ARNG_Zm510_ArngSCheck,
+ a_ARNG_Zm510V1_ArngSCheck,
a_ARNG_ZdnDest_ArngSCheck,
a_ARNG_ZdnDest_ArngSCheck,
}
@@ -5878,43 +7198,64 @@ var Zm_S__Zn_S__Zda_S = []operand{
a_ARNG_Zda3RdSrcDst_ArngSCheck,
}
+var Zm_T__Rdn__Pg__Rdn = []operand{
+ a_ARNG_Zm510V2_SizeBHSD2224,
+ a_SPZGREG_Noop_Rdn05ZR,
+ a_PREG_Pg1013_Noop,
+ a_SPZGREG_Noop_Rdn05ZR,
+}
+
+var Zm_T__Vdn__Pg__Vdn__1 = []operand{
+ a_ARNG_Zm510V2_SizeBHSD2224,
+ a_VREG_Noop_Vdn05,
+ a_PREG_Pg1013_Noop,
+ a_VREG_Noop_Vdn05,
+}
+
+var Zm_T__Vdn__Pg__Vdn__2 = []operand{
+ a_ARNG_Zm510V2_SizeHSD2224,
+ a_VREG_Noop_Vdn05,
+ a_PREG_Pg1013_Noop,
+ a_VREG_Noop_Vdn05,
+}
+
var Zm_T__Zdn_T__PgM__Zdn_T__1 = []operand{
- a_ARNG_Zm510_SizeBHSD2224,
+ a_ARNG_Zm510V1_SizeBHSD2224,
a_ARNG_ZdnDest_SizeBHSD2224,
a_PREGZM_Pg1013_MergePredCheck,
a_ARNG_ZdnDest_SizeBHSD2224,
}
var Zm_T__Zdn_T__PgM__Zdn_T__2 = []operand{
- a_ARNG_Zm510_SizeHSD2224,
+ a_ARNG_Zm510V1_SizeHSD2224,
a_ARNG_ZdnDest_SizeHSD2224,
a_PREGZM_Pg1013_MergePredCheck,
a_ARNG_ZdnDest_SizeHSD2224,
}
var Zm_T__Zdn_T__PgM__Zdn_T__3 = []operand{
- a_ARNG_Zm510_SizeHSD2224No00,
+ a_ARNG_Zm510V1_SizeHSD2224No00,
a_ARNG_ZdnDest_SizeHSD2224No00,
a_PREGZM_Pg1013_MergePredCheck,
a_ARNG_ZdnDest_SizeHSD2224No00,
}
var Zm_T__Zdn_T__PgM__Zdn_T__4 = []operand{
- a_ARNG_Zm510_Size0SD2223,
+ a_ARNG_Zm510V1_Size0SD2223,
a_ARNG_ZdnDest_Size0SD2223,
a_PREGZM_Pg1013_MergePredCheck,
a_ARNG_ZdnDest_Size0SD2223,
}
var Zm_T__Zdn_T__Pg__Zdn_T = []operand{
- a_ARNG_Zm510_SizeBHSD2224,
+ a_ARNG_Zm510V1_SizeBHSD2224,
a_ARNG_ZdnDest_SizeBHSD2224,
a_PREG_Pg1013_Noop,
a_ARNG_ZdnDest_SizeBHSD2224,
}
var Zm_T__Zdn_T__Pv__Zdn_T = []operand{
- a_ARNG_Zm510_SizeBHSD2224,
+ a_ARNG_Zm510V1_SizeBHSD2224,
a_ARNG_ZdnDest_SizeBHSD2224,
a_PREG_Pv1013_Noop,
a_ARNG_ZdnDest_SizeBHSD2224,
@@ -6238,6 +7579,36 @@ var Zn_T__PgZ__Zd_T__6 = []operand{
a_ARNG_Zd_SizeHSD1315,
}
+var Zn_T__Pg__Dd__1 = []operand{
+ a_ARNG_Zn510Src_SizeBHS2224,
+ a_PREG_Pg1013_Noop,
+ a_VREG_Noop_Vd0564,
+}
+
+var Zn_T__Pg__Dd__2 = []operand{
+ a_ARNG_Zn510Src_SizeBHSD2224,
+ a_PREG_Pg1013_Noop,
+ a_VREG_Noop_Vd0564,
+}
+
+var Zn_T__Pg__Rd = []operand{
+ a_ARNG_Zn510Src_SizeBHSD2224,
+ a_PREG_Pg1013_Noop,
+ a_SPZGREG_Noop_Rd05ZR,
+}
+
+var Zn_T__Pg__Vd__1 = []operand{
+ a_ARNG_Zn510Src_SizeBHSD2224,
+ a_PREG_Pg1013_Noop,
+ a_VREG_Noop_Vd05,
+}
+
+var Zn_T__Pg__Vd__2 = []operand{
+ a_ARNG_Zn510Src_SizeHSD2224,
+ a_PREG_Pg1013_Noop,
+ a_VREG_Noop_Vd05,
+}
+
var Zn_T__Pg__Zd_T__1 = []operand{
a_ARNG_Zn510Src_SzByteHalfword,
a_PREG_Pg1013_Noop,
generated by cgit v1.3 (git 2.53.0) at 2026-04-15 06:52:39 +0000