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-rw-r--r--src/cmd/asm/internal/asm/parse.go24
-rw-r--r--src/cmd/asm/internal/asm/testdata/arm64sveenc.s77
-rw-r--r--src/cmd/asm/internal/asm/testdata/arm64sveerror.s77
-rw-r--r--src/cmd/internal/obj/arm64/anames_gen.go11
-rw-r--r--src/cmd/internal/obj/arm64/encoding_gen.go101
-rw-r--r--src/cmd/internal/obj/arm64/goops_gen.go11
-rw-r--r--src/cmd/internal/obj/arm64/inst.go7
-rw-r--r--src/cmd/internal/obj/arm64/inst_gen.go825
-rw-r--r--src/cmd/internal/obj/util.go42
9 files changed, 1156 insertions, 19 deletions
diff --git a/src/cmd/asm/internal/asm/parse.go b/src/cmd/asm/internal/asm/parse.go
index 935be172cc..0094e305b0 100644
--- a/src/cmd/asm/internal/asm/parse.go
+++ b/src/cmd/asm/internal/asm/parse.go
@@ -472,6 +472,30 @@ func (p *Parser) operand(a *obj.Addr) {
return
}
+ // Detect (VL*imm) or (-VL*imm) pattern in ARM64
+ if p.arch.Family == sys.ARM64 && len(p.input) >= 5 && p.input[0].ScanToken == '(' {
+ pos := 1
+ sign := int64(1)
+ if p.input[pos].ScanToken == '-' {
+ sign = -1
+ pos++
+ } else if p.input[pos].ScanToken == '+' {
+ pos++
+ }
+ if pos+3 < len(p.input) && p.input[pos].String() == "VL" && p.input[pos+1].ScanToken == '*' && p.input[pos+2].ScanToken == scanner.Int && p.input[pos+3].ScanToken == ')' {
+ imm := int64(p.atoi(p.input[pos+2].String()))
+ imm *= sign
+ a.Offset = imm
+ a.Scale = -32768 // bit 15 signals multiple of Vector Length
+
+ // Remove the (VL*imm) tokens and let operand parse the remaining sequence (reg.T)
+ p.input = p.input[pos+4:]
+ p.inputPos = 0
+ p.operand(a)
+ return
+ }
+ }
+
// Constant.
haveConstant := false
switch tok.ScanToken {
diff --git a/src/cmd/asm/internal/asm/testdata/arm64sveenc.s b/src/cmd/asm/internal/asm/testdata/arm64sveenc.s
index 04a1eb9b98..8fa3cc9c78 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64sveenc.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64sveenc.s
@@ -1209,4 +1209,81 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZST1H 6(Z7.D), P4, [Z13.D] // edb0c3e4
ZST1W 12(Z0.S), P6, [Z25.S] // 19b863e5
ZST1W 12(Z0.D), P6, [Z25.D] // 19b843e5
+ PLDR (-VL*2)(RSP), P5 // e51bbf85
+ PPRFB (VL*1)(RSP), P3, PSTL3KEEP // ec0fc185
+ PPRFD (VL*1)(RSP), P3, PSTL3KEEP // ec6fc185
+ PPRFH (VL*1)(RSP), P3, PSTL3KEEP // ec2fc185
+ PPRFW (VL*1)(RSP), P3, PSTL3KEEP // ec4fc185
+ PSTR (-VL*2)(RSP), P5 // e51bbfe5
+ ZLD1B (-VL*2)(R14), P4.Z, [Z13.B] // cdb10ea4
+ ZLD1B (-VL*2)(R14), P4.Z, [Z13.H] // cdb12ea4
+ ZLD1B (-VL*2)(R14), P4.Z, [Z13.S] // cdb14ea4
+ ZLD1B (-VL*2)(R14), P4.Z, [Z13.D] // cdb16ea4
+ ZLD1H (-VL*2)(R14), P4.Z, [Z13.H] // cdb1aea4
+ ZLD1H (-VL*2)(R14), P4.Z, [Z13.S] // cdb1cea4
+ ZLD1H (-VL*2)(R14), P4.Z, [Z13.D] // cdb1eea4
+ ZLD1SB (-VL*2)(R14), P4.Z, [Z13.H] // cdb1cea5
+ ZLD1SB (-VL*2)(R14), P4.Z, [Z13.S] // cdb1aea5
+ ZLD1SB (-VL*2)(R14), P4.Z, [Z13.D] // cdb18ea5
+ ZLD1SH (-VL*2)(R14), P4.Z, [Z13.S] // cdb12ea5
+ ZLD1SH (-VL*2)(R14), P4.Z, [Z13.D] // cdb10ea5
+ ZLD1SW (-VL*2)(R14), P4.Z, [Z13.D] // cdb18ea4
+ ZLD2B (-VL*2)(R14), P4.Z, [Z13.B, Z14.B] // cdf12fa4
+ ZLD2D (-VL*2)(R14), P4.Z, [Z13.D, Z14.D] // cdf1afa5
+ ZLD2H (-VL*2)(R14), P4.Z, [Z13.H, Z14.H] // cdf1afa4
+ ZLD2Q (-VL*2)(R14), P4.Z, [Z13.Q, Z14.Q] // cdf19fa4
+ ZLD2W (-VL*2)(R14), P4.Z, [Z13.S, Z14.S] // cdf12fa5
+ ZLD3B (-VL*3)(R10), P4.Z, [Z21.B, Z22.B, Z23.B] // 55f14fa4
+ ZLD3D (-VL*3)(R10), P4.Z, [Z21.D, Z22.D, Z23.D] // 55f1cfa5
+ ZLD3H (-VL*3)(R10), P4.Z, [Z21.H, Z22.H, Z23.H] // 55f1cfa4
+ ZLD3Q (-VL*3)(R10), P4.Z, [Z21.Q, Z22.Q, Z23.Q] // 55f11fa5
+ ZLD3W (-VL*3)(R10), P4.Z, [Z21.S, Z22.S, Z23.S] // 55f14fa5
+ ZLD4B (VL*4)(R4), P6.Z, [Z25.B, Z26.B, Z27.B, Z28.B]// 99f861a4
+ ZLD4D (VL*4)(R4), P6.Z, [Z25.D, Z26.D, Z27.D, Z28.D]// 99f8e1a5
+ ZLD4H (VL*4)(R4), P6.Z, [Z25.H, Z26.H, Z27.H, Z28.H]// 99f8e1a4
+ ZLD4Q (VL*4)(R4), P6.Z, [Z25.Q, Z26.Q, Z27.Q, Z28.Q]// 99f891a5
+ ZLD4W (VL*4)(R4), P6.Z, [Z25.S, Z26.S, Z27.S, Z28.S]// 99f861a5
+ ZLDNF1B (-VL*2)(R14), P4.Z, [Z13.B] // cdb11ea4
+ ZLDNF1B (-VL*2)(R14), P4.Z, [Z13.H] // cdb13ea4
+ ZLDNF1B (-VL*2)(R14), P4.Z, [Z13.S] // cdb15ea4
+ ZLDNF1B (-VL*2)(R14), P4.Z, [Z13.D] // cdb17ea4
+ ZLDNF1D (-VL*2)(R14), P4.Z, [Z13.D] // cdb1fea5
+ ZLDNF1H (-VL*2)(R14), P4.Z, [Z13.H] // cdb1bea4
+ ZLDNF1H (-VL*2)(R14), P4.Z, [Z13.S] // cdb1dea4
+ ZLDNF1H (-VL*2)(R14), P4.Z, [Z13.D] // cdb1fea4
+ ZLDNF1SB (-VL*2)(R14), P4.Z, [Z13.H] // cdb1dea5
+ ZLDNF1SB (-VL*2)(R14), P4.Z, [Z13.S] // cdb1bea5
+ ZLDNF1SB (-VL*2)(R14), P4.Z, [Z13.D] // cdb19ea5
+ ZLDNF1SH (-VL*2)(R14), P4.Z, [Z13.S] // cdb13ea5
+ ZLDNF1SH (-VL*2)(R14), P4.Z, [Z13.D] // cdb11ea5
+ ZLDNF1SW (-VL*2)(R14), P4.Z, [Z13.D] // cdb19ea4
+ ZLDNF1W (-VL*2)(R14), P4.Z, [Z13.S] // cdb15ea5
+ ZLDNF1W (-VL*2)(R14), P4.Z, [Z13.D] // cdb17ea5
+ ZLDNT1B (-VL*2)(R14), P4.Z, [Z13.B] // cdf10ea4
+ ZLDNT1D (-VL*2)(R14), P4.Z, [Z13.D] // cdf18ea5
+ ZLDNT1H (-VL*2)(R14), P4.Z, [Z13.H] // cdf18ea4
+ ZLDNT1W (-VL*2)(R14), P4.Z, [Z13.S] // cdf10ea5
+ ZLDR (-VL*2)(RSP), Z7 // e75bbf85
+ ZST1B (-VL*2)(R14), P4, [Z13.B] // cdf10ee4
+ ZST1H (-VL*2)(RSP), P1, [Z12.S] // ece7cee4
+ ZST2B (-VL*2)(R14), P4, [Z13.B, Z14.B] // cdf13fe4
+ ZST2D (-VL*2)(R14), P4, [Z13.D, Z14.D] // cdf1bfe5
+ ZST2H (-VL*2)(R14), P4, [Z13.H, Z14.H] // cdf1bfe4
+ ZST2Q (-VL*2)(R14), P4, [Z13.Q, Z14.Q] // cd114fe4
+ ZST2W (-VL*2)(R14), P4, [Z13.S, Z14.S] // cdf13fe5
+ ZST3B (-VL*3)(R10), P4, [Z21.B, Z22.B, Z23.B] // 55f15fe4
+ ZST3D (-VL*3)(R10), P4, [Z21.D, Z22.D, Z23.D] // 55f1dfe5
+ ZST3H (-VL*3)(R10), P4, [Z21.H, Z22.H, Z23.H] // 55f1dfe4
+ ZST3Q (-VL*3)(R10), P4, [Z21.Q, Z22.Q, Z23.Q] // 55118fe4
+ ZST3W (-VL*3)(R10), P4, [Z21.S, Z22.S, Z23.S] // 55f15fe5
+ ZST4B (VL*4)(R4), P6, [Z25.B, Z26.B, Z27.B, Z28.B]// 99f871e4
+ ZST4D (VL*4)(R4), P6, [Z25.D, Z26.D, Z27.D, Z28.D]// 99f8f1e5
+ ZST4H (VL*4)(R4), P6, [Z25.H, Z26.H, Z27.H, Z28.H]// 99f8f1e4
+ ZST4Q (VL*4)(R4), P6, [Z25.Q, Z26.Q, Z27.Q, Z28.Q]// 9918c1e4
+ ZST4W (VL*4)(R4), P6, [Z25.S, Z26.S, Z27.S, Z28.S]// 99f871e5
+ ZSTNT1B (-VL*2)(R14), P4, [Z13.B] // cdf11ee4
+ ZSTNT1D (-VL*2)(R14), P4, [Z13.D] // cdf19ee5
+ ZSTNT1H (-VL*2)(R14), P4, [Z13.H] // cdf19ee4
+ ZSTNT1W (-VL*2)(R14), P4, [Z13.S] // cdf11ee5
+ ZSTR (-VL*2)(RSP), Z7 // e75bbfe5
RET
diff --git a/src/cmd/asm/internal/asm/testdata/arm64sveerror.s b/src/cmd/asm/internal/asm/testdata/arm64sveerror.s
index ea33010739..4f06883bff 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64sveerror.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64sveerror.s
@@ -1208,4 +1208,81 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
ZST1H 11(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
ZST1W 11(Z1.S), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
ZST1W 11(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ PLDR (VL*3)(RSP), P13.Z // ERROR "illegal combination from SVE"
+ PPRFB (VL*3)(RSP), P13.Z, PSTL3STRM // ERROR "illegal combination from SVE"
+ PPRFD (VL*3)(RSP), P13.Z, PSTL3STRM // ERROR "illegal combination from SVE"
+ PPRFH (VL*3)(RSP), P13.Z, PSTL3STRM // ERROR "illegal combination from SVE"
+ PPRFW (VL*3)(RSP), P13.Z, PSTL3STRM // ERROR "illegal combination from SVE"
+ PSTR (VL*3)(RSP), P13.Z // ERROR "illegal combination from SVE"
+ ZLD1B (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLD1B (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLD1B (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLD1B (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLD1H (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLD1H (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLD1H (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLD1SB (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLD1SB (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLD1SB (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLD1SH (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLD1SH (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLD1SW (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLD2B (VL*3)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE"
+ ZLD2D (VL*3)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE"
+ ZLD2H (VL*3)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE"
+ ZLD2Q (VL*3)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE"
+ ZLD2W (VL*3)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE"
+ ZLD3B (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE"
+ ZLD3D (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE"
+ ZLD3H (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE"
+ ZLD3Q (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE"
+ ZLD3W (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE"
+ ZLD4B (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE"
+ ZLD4D (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE"
+ ZLD4H (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE"
+ ZLD4Q (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE"
+ ZLD4W (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE"
+ ZLDNF1B (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLDNF1B (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLDNF1B (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLDNF1B (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLDNF1D (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLDNF1H (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLDNF1H (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLDNF1H (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLDNF1SB (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLDNF1SB (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLDNF1SB (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLDNF1SH (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLDNF1SH (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLDNF1SW (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLDNF1W (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLDNF1W (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLDNT1B (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLDNT1D (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLDNT1H (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLDNT1W (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZLDR (VL*3)(RSP), Z26.S // ERROR "illegal combination from SVE"
+ ZST1B (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZST1H (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZST2B (VL*3)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE"
+ ZST2D (VL*3)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE"
+ ZST2H (VL*3)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE"
+ ZST2Q (VL*3)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE"
+ ZST2W (VL*3)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE"
+ ZST3B (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE"
+ ZST3D (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE"
+ ZST3H (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE"
+ ZST3Q (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE"
+ ZST3W (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE"
+ ZST4B (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE"
+ ZST4D (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE"
+ ZST4H (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE"
+ ZST4Q (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE"
+ ZST4W (VL*3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE"
+ ZSTNT1B (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZSTNT1D (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZSTNT1H (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZSTNT1W (VL*3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE"
+ ZSTR (VL*3)(RSP), Z26.S // ERROR "illegal combination from SVE"
RET
diff --git a/src/cmd/internal/obj/arm64/anames_gen.go b/src/cmd/internal/obj/arm64/anames_gen.go
index 5ca4524997..e33b696a15 100644
--- a/src/cmd/internal/obj/arm64/anames_gen.go
+++ b/src/cmd/internal/obj/arm64/anames_gen.go
@@ -31,6 +31,7 @@ var sveAnames = []string{
"PFIRSTP",
"PINCP",
"PLASTP",
+ "PLDR",
"PNAND",
"PNANDS",
"PNOR",
@@ -59,6 +60,7 @@ var sveAnames = []string{
"PSQDECPW",
"PSQINCP",
"PSQINCPW",
+ "PSTR",
"PTRN1",
"PTRN2",
"PUQDECP",
@@ -377,6 +379,13 @@ var sveAnames = []string{
"ZLDFF1SH",
"ZLDFF1SW",
"ZLDFF1W",
+ "ZLDNF1B",
+ "ZLDNF1D",
+ "ZLDNF1H",
+ "ZLDNF1SB",
+ "ZLDNF1SH",
+ "ZLDNF1SW",
+ "ZLDNF1W",
"ZLDNT1B",
"ZLDNT1D",
"ZLDNT1H",
@@ -384,6 +393,7 @@ var sveAnames = []string{
"ZLDNT1SH",
"ZLDNT1SW",
"ZLDNT1W",
+ "ZLDR",
"ZLSL",
"ZLSLR",
"ZLSR",
@@ -562,6 +572,7 @@ var sveAnames = []string{
"ZSTNT1D",
"ZSTNT1H",
"ZSTNT1W",
+ "ZSTR",
"ZSUB",
"ZSUBHNB",
"ZSUBHNT",
diff --git a/src/cmd/internal/obj/arm64/encoding_gen.go b/src/cmd/internal/obj/arm64/encoding_gen.go
index ef2fe64286..5af77d570c 100644
--- a/src/cmd/internal/obj/arm64/encoding_gen.go
+++ b/src/cmd/internal/obj/arm64/encoding_gen.go
@@ -38,6 +38,7 @@ const (
enc_i4h_i4l
enc_imm2_tsz
enc_imm8h_imm8l
+ enc_imm9h_imm9l
enc_tszh_tszl_imm3
enc_tszh_tszl
enc_M
@@ -49,6 +50,7 @@ const (
enc_Pg
enc_Pm
enc_Pn
+ enc_Pt
enc_Pv
enc_Rd
enc_Rdn
@@ -1405,6 +1407,17 @@ func encodePd(v uint32) (uint32, bool) {
return v, true
}
+// encodePt04V1 is the implementation of the following encoding logic:
+// Is the name of the destination scalable predicate register, encoded in the "Pt" field.
+// bit range mappings:
+// Pt: [0:4)
+func encodePt04V1(v uint32) (uint32, bool) {
+ if v > 15 {
+ return 0, false
+ }
+ return v, true
+}
+
// encodeZd is the implementation of the following encoding logic:
// Is the name of the destination scalable vector register, encoded in the "Zd" field.
// bit range mappings:
@@ -1575,6 +1588,17 @@ func encodeZm1621V3(v uint32) (uint32, bool) {
return v << 16, true
}
+// encodePt04V2 is the implementation of the following encoding logic:
+// Is the name of the scalable predicate transfer register, encoded in the "Pt" field.
+// bit range mappings:
+// Pt: [0:4)
+func encodePt04V2(v uint32) (uint32, bool) {
+ if v > 15 {
+ return 0, false
+ }
+ return v, true
+}
+
// encodeZt05 is the implementation of the following encoding logic:
// Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.
// bit range mappings:
@@ -2021,6 +2045,83 @@ func encodeImm41620V2(v uint32) (uint32, bool) {
return 0, false
}
+// encodeImm41620V6 is the implementation of the following encoding logic:
+// Is the optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.
+// bit range mappings:
+// imm4: [16:20)
+func encodeImm41620V6(v uint32) (uint32, bool) {
+ if v&1 != 0 {
+ return 0, false
+ }
+ vi := int32(v)
+ if vi >= -16 && vi <= 14 {
+ return (uint32(vi/2) & 15) << 16, true
+ }
+ return 0, false
+}
+
+// encodeImm41620V3 is the implementation of the following encoding logic:
+// Is the optional signed immediate vector offset, a multiple of 3 in the range -24 to 21, defaulting to 0, encoded in the "imm4" field.
+// bit range mappings:
+// imm4: [16:20)
+func encodeImm41620V3(v uint32) (uint32, bool) {
+ vi := int32(v)
+ if vi >= -24 && vi <= 21 && vi%3 == 0 {
+ return uint32((vi/3)&15) << 16, true
+ }
+ return 0, false
+}
+
+// encodeImm41620V4 is the implementation of the following encoding logic:
+// Is the optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.
+// bit range mappings:
+// imm4: [16:20)
+func encodeImm41620V4(v uint32) (uint32, bool) {
+ vi := int32(v)
+ if vi >= -32 && vi <= 28 && vi%4 == 0 {
+ return uint32((vi/4)&15) << 16, true
+ }
+ return 0, false
+}
+
+// encodeImm9h1622L1013 is the implementation of the following encoding logic:
+// Is the optional signed immediate vector offset, in the range -256 to 255, defaulting to 0, encoded in the "imm9h:imm9l" fields.
+// bit range mappings:
+// imm9h: [16:22)
+// imm9l: [10:13)
+func encodeImm9h1622L1013(v uint32) (uint32, bool) {
+ vi := int32(v)
+ if vi >= -256 && vi <= 255 {
+ val := uint32(vi) & 0x1FF
+ return ((val & 7) << 10) | ((val >> 3) << 16), true
+ }
+ return 0, false
+}
+
+// encodeImm61622V5 is the implementation of the following encoding logic:
+// Is the optional signed immediate vector offset, in the range -32 to 31, defaulting to 0, encoded in the "imm6" field.
+// bit range mappings:
+// imm6: [16:22)
+func encodeImm61622V5(v uint32) (uint32, bool) {
+ vi := int32(v)
+ if vi >= -32 && vi <= 31 {
+ return (uint32(vi) & 0x3F) << 16, true
+ }
+ return 0, false
+}
+
+// encodeImm41620V5 is the implementation of the following encoding logic:
+// Is the optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.
+// bit range mappings:
+// imm4: [16:20)
+func encodeImm41620V5(v uint32) (uint32, bool) {
+ vi := int32(v)
+ if vi >= -8 && vi <= 7 {
+ return (uint32(vi) & 0xF) << 16, true
+ }
+ return 0, false
+}
+
// encodeImm61622V1 is the implementation of the following encoding logic:
// Is the optional unsigned immediate byte offset, a multiple of 2 in the range 0 to 126, defaulting to 0, encoded in the "imm6" field.
// bit range mappings:
diff --git a/src/cmd/internal/obj/arm64/goops_gen.go b/src/cmd/internal/obj/arm64/goops_gen.go
index 77ecfff4a9..dbf46257a2 100644
--- a/src/cmd/internal/obj/arm64/goops_gen.go
+++ b/src/cmd/internal/obj/arm64/goops_gen.go
@@ -32,6 +32,7 @@ const (
APFIRSTP
APINCP
APLASTP
+ APLDR
APNAND
APNANDS
APNOR
@@ -60,6 +61,7 @@ const (
APSQDECPW
APSQINCP
APSQINCPW
+ APSTR
APTRN1
APTRN2
APUQDECP
@@ -378,6 +380,13 @@ const (
AZLDFF1SH
AZLDFF1SW
AZLDFF1W
+ AZLDNF1B
+ AZLDNF1D
+ AZLDNF1H
+ AZLDNF1SB
+ AZLDNF1SH
+ AZLDNF1SW
+ AZLDNF1W
AZLDNT1B
AZLDNT1D
AZLDNT1H
@@ -385,6 +394,7 @@ const (
AZLDNT1SH
AZLDNT1SW
AZLDNT1W
+ AZLDR
AZLSL
AZLSLR
AZLSR
@@ -563,6 +573,7 @@ const (
AZSTNT1D
AZSTNT1H
AZSTNT1W
+ AZSTR
AZSUB
AZSUBHNB
AZSUBHNT
diff --git a/src/cmd/internal/obj/arm64/inst.go b/src/cmd/internal/obj/arm64/inst.go
index 111f707bdd..e1f4e46595 100644
--- a/src/cmd/internal/obj/arm64/inst.go
+++ b/src/cmd/internal/obj/arm64/inst.go
@@ -145,6 +145,9 @@ func aclass(a *obj.Addr) AClass {
}
if a.Type == obj.TYPE_MEM {
if a.Index == 0 {
+ if a.Scale&-32768 != 0 {
+ return AC_MEMOFFMULVL
+ }
return AC_MEMOFF
}
return AC_MEMEXT
@@ -352,7 +355,7 @@ func addrComponent(a *obj.Addr, acl AClass, index int) uint32 {
default:
panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl))
}
- // AClass: AC_MEMOFF
+ // AClass: AC_MEMOFF, AC_MEMOFFMULVL
// GNU mnemonic: [<reg>.<T>, #<imm>]
// Go mnemonic:
// imm(reg.T)
@@ -360,7 +363,7 @@ func addrComponent(a *obj.Addr, acl AClass, index int) uint32 {
// Type = TYPE_MEM
// Reg = Base register (with arrangement if applicable)
// Offset = Immediate offset
- case AC_MEMOFF:
+ case AC_MEMOFF, AC_MEMOFFMULVL:
switch index {
case 0:
return uint32(a.Reg & 31)
diff --git a/src/cmd/internal/obj/arm64/inst_gen.go b/src/cmd/internal/obj/arm64/inst_gen.go
index 577ebf3657..7543384ee9 100644
--- a/src/cmd/internal/obj/arm64/inst_gen.go
+++ b/src/cmd/internal/obj/arm64/inst_gen.go
@@ -255,6 +255,15 @@ var insts = [][]instEncoder{
args: Pn_T__Pg__Xd,
},
},
+ // PLDR
+ {
+ // PLDR [<Xn|SP>{, #<imm>, MUL VL}], <Pt>
+ {
+ goOp: APLDR,
+ fixedBits: 0x85800000,
+ args: XnSP__cimm__MUL_VL___Pt__1,
+ },
+ },
// PNAND
{
// PNAND <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
@@ -377,6 +386,12 @@ var insts = [][]instEncoder{
fixedBits: 0x8400c000,
args: XnSP__Xm___Pg__prfop,
},
+ // PPRFB [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, <prfop>
+ {
+ goOp: APPRFB,
+ fixedBits: 0x85c00000,
+ args: XnSP__cimm__MUL_VL___Pg__prfop,
+ },
},
// PPRFD
{
@@ -386,6 +401,12 @@ var insts = [][]instEncoder{
fixedBits: 0x8580c000,
args: XnSP__Xm__LSL_c3___Pg__prfop,
},
+ // PPRFD [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, <prfop>
+ {
+ goOp: APPRFD,
+ fixedBits: 0x85c06000,
+ args: XnSP__cimm__MUL_VL___Pg__prfop,
+ },
},
// PPRFH
{
@@ -395,6 +416,12 @@ var insts = [][]instEncoder{
fixedBits: 0x8480c000,
args: XnSP__Xm__LSL_c1___Pg__prfop,
},
+ // PPRFH [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, <prfop>
+ {
+ goOp: APPRFH,
+ fixedBits: 0x85c02000,
+ args: XnSP__cimm__MUL_VL___Pg__prfop,
+ },
},
// PPRFW
{
@@ -404,6 +431,12 @@ var insts = [][]instEncoder{
fixedBits: 0x8500c000,
args: XnSP__Xm__LSL_c2___Pg__prfop,
},
+ // PPRFW [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, <prfop>
+ {
+ goOp: APPRFW,
+ fixedBits: 0x85c04000,
+ args: XnSP__cimm__MUL_VL___Pg__prfop,
+ },
},
// PPTEST
{
@@ -519,6 +552,15 @@ var insts = [][]instEncoder{
args: Wdn__Pm_T__Xdn,
},
},
+ // PSTR
+ {
+ // PSTR [<Xn|SP>{, #<imm>, MUL VL}], <Pt>
+ {
+ goOp: APSTR,
+ fixedBits: 0xe5800000,
+ args: XnSP__cimm__MUL_VL___Pt__2,
+ },
+ },
// PTRN1
{
// PTRN1 <Pm>.<T>, <Pn>.<T>, <Pd>.<T>
@@ -4178,6 +4220,30 @@ var insts = [][]instEncoder{
fixedBits: 0x8420c000,
args: Zn_S__cimm___PgZ___Zt_S___1,
},
+ // ZLD1B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.B }
+ {
+ goOp: AZLD1B,
+ fixedBits: 0xa400a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_B_,
+ },
+ // ZLD1B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
+ {
+ goOp: AZLD1B,
+ fixedBits: 0xa460a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_D_,
+ },
+ // ZLD1B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.H }
+ {
+ goOp: AZLD1B,
+ fixedBits: 0xa420a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_H_,
+ },
+ // ZLD1B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.S }
+ {
+ goOp: AZLD1B,
+ fixedBits: 0xa440a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_S_,
+ },
},
// ZLD1D
{
@@ -4280,6 +4346,24 @@ var insts = [][]instEncoder{
fixedBits: 0x84a0c000,
args: Zn_S__cimm___PgZ___Zt_S___2,
},
+ // ZLD1H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
+ {
+ goOp: AZLD1H,
+ fixedBits: 0xa4e0a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_D_,
+ },
+ // ZLD1H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.H }
+ {
+ goOp: AZLD1H,
+ fixedBits: 0xa4a0a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_H_,
+ },
+ // ZLD1H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.S }
+ {
+ goOp: AZLD1H,
+ fixedBits: 0xa4c0a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_S_,
+ },
},
// ZLD1Q
{
@@ -4577,6 +4661,24 @@ var insts = [][]instEncoder{
fixedBits: 0x84208000,
args: Zn_S__cimm___PgZ___Zt_S___1,
},
+ // ZLD1SB [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
+ {
+ goOp: AZLD1SB,
+ fixedBits: 0xa580a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_D_,
+ },
+ // ZLD1SB [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.H }
+ {
+ goOp: AZLD1SB,
+ fixedBits: 0xa5c0a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_H_,
+ },
+ // ZLD1SB [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.S }
+ {
+ goOp: AZLD1SB,
+ fixedBits: 0xa5a0a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_S_,
+ },
},
// ZLD1SH
{
@@ -4640,6 +4742,18 @@ var insts = [][]instEncoder{
fixedBits: 0x84a08000,
args: Zn_S__cimm___PgZ___Zt_S___2,
},
+ // ZLD1SH [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
+ {
+ goOp: AZLD1SH,
+ fixedBits: 0xa500a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_D_,
+ },
+ // ZLD1SH [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.S }
+ {
+ goOp: AZLD1SH,
+ fixedBits: 0xa520a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_S_,
+ },
},
// ZLD1SW
{
@@ -4679,6 +4793,12 @@ var insts = [][]instEncoder{
fixedBits: 0xc5208000,
args: Zn_D__cimm___PgZ___Zt_D___3,
},
+ // ZLD1SW [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
+ {
+ goOp: AZLD1SW,
+ fixedBits: 0xa480a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_D_,
+ },
},
// ZLD1W
{
@@ -4739,6 +4859,12 @@ var insts = [][]instEncoder{
fixedBits: 0xa420c000,
args: XnSP__Xm___PgZ___Zt1_B__Zt2_B_,
},
+ // ZLD2B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.B, <Zt2>.B }
+ {
+ goOp: AZLD2B,
+ fixedBits: 0xa420e000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt1_B__Zt2_B_,
+ },
},
// ZLD2D
{
@@ -4748,6 +4874,12 @@ var insts = [][]instEncoder{
fixedBits: 0xa5a0c000,
args: XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D_,
},
+ // ZLD2D [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.D, <Zt2>.D }
+ {
+ goOp: AZLD2D,
+ fixedBits: 0xa5a0e000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt1_D__Zt2_D_,
+ },
},
// ZLD2H
{
@@ -4757,6 +4889,12 @@ var insts = [][]instEncoder{
fixedBits: 0xa4a0c000,
args: XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H_,
},
+ // ZLD2H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.H, <Zt2>.H }
+ {
+ goOp: AZLD2H,
+ fixedBits: 0xa4a0e000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt1_H__Zt2_H_,
+ },
},
// ZLD2Q
{
@@ -4766,6 +4904,12 @@ var insts = [][]instEncoder{
fixedBits: 0xa4a08000,
args: XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q_,
},
+ // ZLD2Q [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.Q, <Zt2>.Q }
+ {
+ goOp: AZLD2Q,
+ fixedBits: 0xa490e000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt1_Q__Zt2_Q_,
+ },
},
// ZLD2W
{
@@ -4775,6 +4919,12 @@ var insts = [][]instEncoder{
fixedBits: 0xa520c000,
args: XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S_,
},
+ // ZLD2W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.S, <Zt2>.S }
+ {
+ goOp: AZLD2W,
+ fixedBits: 0xa520e000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt1_S__Zt2_S_,
+ },
},
// ZLD3B
{
@@ -4784,6 +4934,12 @@ var insts = [][]instEncoder{
fixedBits: 0xa440c000,
args: XnSP__Xm___PgZ___Zt1_B__Zt2_B__Zt3_B_,
},
+ // ZLD3B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.B, <Zt2>.B, <Zt3>.B }
+ {
+ goOp: AZLD3B,
+ fixedBits: 0xa440e000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt1_B__Zt2_B__Zt3_B_,
+ },
},
// ZLD3D
{
@@ -4793,6 +4949,12 @@ var insts = [][]instEncoder{
fixedBits: 0xa5c0c000,
args: XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D__Zt3_D_,
},
+ // ZLD3D [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.D, <Zt2>.D, <Zt3>.D }
+ {
+ goOp: AZLD3D,
+ fixedBits: 0xa5c0e000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt1_D__Zt2_D__Zt3_D_,
+ },
},
// ZLD3H
{
@@ -4802,6 +4964,12 @@ var insts = [][]instEncoder{
fixedBits: 0xa4c0c000,
args: XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H__Zt3_H_,
},
+ // ZLD3H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.H, <Zt2>.H, <Zt3>.H }
+ {
+ goOp: AZLD3H,
+ fixedBits: 0xa4c0e000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt1_H__Zt2_H__Zt3_H_,
+ },
},
// ZLD3Q
{
@@ -4811,6 +4979,12 @@ var insts = [][]instEncoder{
fixedBits: 0xa5208000,
args: XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q__Zt3_Q_,
},
+ // ZLD3Q [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q }
+ {
+ goOp: AZLD3Q,
+ fixedBits: 0xa510e000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt1_Q__Zt2_Q__Zt3_Q_,
+ },
},
// ZLD3W
{
@@ -4820,6 +4994,12 @@ var insts = [][]instEncoder{
fixedBits: 0xa540c000,
args: XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S__Zt3_S_,
},
+ // ZLD3W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.S, <Zt2>.S, <Zt3>.S }
+ {
+ goOp: AZLD3W,
+ fixedBits: 0xa540e000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt1_S__Zt2_S__Zt3_S_,
+ },
},
// ZLD4B
{
@@ -4829,6 +5009,12 @@ var insts = [][]instEncoder{
fixedBits: 0xa460c000,
args: XnSP__Xm___PgZ___Zt1_B__Zt2_B__Zt3_B__Zt4_B_,
},
+ // ZLD4B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }
+ {
+ goOp: AZLD4B,
+ fixedBits: 0xa460e000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt1_B__Zt2_B__Zt3_B__Zt4_B_,
+ },
},
// ZLD4D
{
@@ -4838,6 +5024,12 @@ var insts = [][]instEncoder{
fixedBits: 0xa5e0c000,
args: XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D__Zt3_D__Zt4_D_,
},
+ // ZLD4D [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }
+ {
+ goOp: AZLD4D,
+ fixedBits: 0xa5e0e000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt1_D__Zt2_D__Zt3_D__Zt4_D_,
+ },
},
// ZLD4H
{
@@ -4847,6 +5039,12 @@ var insts = [][]instEncoder{
fixedBits: 0xa4e0c000,
args: XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H__Zt3_H__Zt4_H_,
},
+ // ZLD4H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }
+ {
+ goOp: AZLD4H,
+ fixedBits: 0xa4e0e000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt1_H__Zt2_H__Zt3_H__Zt4_H_,
+ },
},
// ZLD4Q
{
@@ -4856,6 +5054,12 @@ var insts = [][]instEncoder{
fixedBits: 0xa5a08000,
args: XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_,
},
+ // ZLD4Q [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q, <Zt4>.Q }
+ {
+ goOp: AZLD4Q,
+ fixedBits: 0xa590e000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_,
+ },
},
// ZLD4W
{
@@ -4865,6 +5069,12 @@ var insts = [][]instEncoder{
fixedBits: 0xa560c000,
args: XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S__Zt3_S__Zt4_S_,
},
+ // ZLD4W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }
+ {
+ goOp: AZLD4W,
+ fixedBits: 0xa560e000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt1_S__Zt2_S__Zt3_S__Zt4_S_,
+ },
},
// ZLDFF1B
{
@@ -5247,6 +5457,123 @@ var insts = [][]instEncoder{
args: Zn_S__cimm___PgZ___Zt_S___3,
},
},
+ // ZLDNF1B
+ {
+ // ZLDNF1B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.B }
+ {
+ goOp: AZLDNF1B,
+ fixedBits: 0xa410a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_B_,
+ },
+ // ZLDNF1B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
+ {
+ goOp: AZLDNF1B,
+ fixedBits: 0xa470a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_D_,
+ },
+ // ZLDNF1B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.H }
+ {
+ goOp: AZLDNF1B,
+ fixedBits: 0xa430a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_H_,
+ },
+ // ZLDNF1B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.S }
+ {
+ goOp: AZLDNF1B,
+ fixedBits: 0xa450a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_S_,
+ },
+ },
+ // ZLDNF1D
+ {
+ // ZLDNF1D [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
+ {
+ goOp: AZLDNF1D,
+ fixedBits: 0xa5f0a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_D_,
+ },
+ },
+ // ZLDNF1H
+ {
+ // ZLDNF1H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
+ {
+ goOp: AZLDNF1H,
+ fixedBits: 0xa4f0a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_D_,
+ },
+ // ZLDNF1H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.H }
+ {
+ goOp: AZLDNF1H,
+ fixedBits: 0xa4b0a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_H_,
+ },
+ // ZLDNF1H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.S }
+ {
+ goOp: AZLDNF1H,
+ fixedBits: 0xa4d0a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_S_,
+ },
+ },
+ // ZLDNF1SB
+ {
+ // ZLDNF1SB [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
+ {
+ goOp: AZLDNF1SB,
+ fixedBits: 0xa590a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_D_,
+ },
+ // ZLDNF1SB [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.H }
+ {
+ goOp: AZLDNF1SB,
+ fixedBits: 0xa5d0a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_H_,
+ },
+ // ZLDNF1SB [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.S }
+ {
+ goOp: AZLDNF1SB,
+ fixedBits: 0xa5b0a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_S_,
+ },
+ },
+ // ZLDNF1SH
+ {
+ // ZLDNF1SH [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
+ {
+ goOp: AZLDNF1SH,
+ fixedBits: 0xa510a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_D_,
+ },
+ // ZLDNF1SH [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.S }
+ {
+ goOp: AZLDNF1SH,
+ fixedBits: 0xa530a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_S_,
+ },
+ },
+ // ZLDNF1SW
+ {
+ // ZLDNF1SW [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
+ {
+ goOp: AZLDNF1SW,
+ fixedBits: 0xa490a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_D_,
+ },
+ },
+ // ZLDNF1W
+ {
+ // ZLDNF1W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
+ {
+ goOp: AZLDNF1W,
+ fixedBits: 0xa570a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_D_,
+ },
+ // ZLDNF1W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.S }
+ {
+ goOp: AZLDNF1W,
+ fixedBits: 0xa550a000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_S_,
+ },
+ },
// ZLDNT1B
{
// ZLDNT1B [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt>.B }
@@ -5267,6 +5594,12 @@ var insts = [][]instEncoder{
fixedBits: 0x8400a000,
args: Zn_S__Xm___PgZ___Zt_S_,
},
+ // ZLDNT1B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.B }
+ {
+ goOp: AZLDNT1B,
+ fixedBits: 0xa400e000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_B_,
+ },
},
// ZLDNT1D
{
@@ -5282,6 +5615,12 @@ var insts = [][]instEncoder{
fixedBits: 0xc580c000,
args: Zn_D__Xm___PgZ___Zt_D_,
},
+ // ZLDNT1D [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
+ {
+ goOp: AZLDNT1D,
+ fixedBits: 0xa580e000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_D_,
+ },
},
// ZLDNT1H
{
@@ -5303,6 +5642,12 @@ var insts = [][]instEncoder{
fixedBits: 0x8480a000,
args: Zn_S__Xm___PgZ___Zt_S_,
},
+ // ZLDNT1H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.H }
+ {
+ goOp: AZLDNT1H,
+ fixedBits: 0xa480e000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_H_,
+ },
},
// ZLDNT1SB
{
@@ -5363,6 +5708,21 @@ var insts = [][]instEncoder{
fixedBits: 0x8500a000,
args: Zn_S__Xm___PgZ___Zt_S_,
},
+ // ZLDNT1W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.S }
+ {
+ goOp: AZLDNT1W,
+ fixedBits: 0xa500e000,
+ args: XnSP__cimm__MUL_VL___PgZ___Zt_S_,
+ },
+ },
+ // ZLDR
+ {
+ // ZLDR [<Xn|SP>{, #<imm>, MUL VL}], <Zt>
+ {
+ goOp: AZLDR,
+ fixedBits: 0x85804000,
+ args: XnSP__cimm__MUL_VL___Zt,
+ },
},
// ZLSL
{
@@ -7550,6 +7910,12 @@ var insts = [][]instEncoder{
fixedBits: 0xe460a000,
args: Zn_S__cimm___Pg___Zt_S___1,
},
+ // ZST1B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt>.<T> }
+ {
+ goOp: AZST1B,
+ fixedBits: 0xe400e000,
+ args: XnSP__cimm__MUL_VL___Pg___Zt_T___1,
+ },
},
// ZST1D
{
@@ -7640,6 +8006,12 @@ var insts = [][]instEncoder{
fixedBits: 0xe4e0a000,
args: Zn_S__cimm___Pg___Zt_S___2,
},
+ // ZST1H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt>.<T> }
+ {
+ goOp: AZST1H,
+ fixedBits: 0xe480e000,
+ args: XnSP__cimm__MUL_VL___Pg___Zt_T___2,
+ },
},
// ZST1Q
{
@@ -7709,6 +8081,12 @@ var insts = [][]instEncoder{
fixedBits: 0xe4206000,
args: XnSP__Xm___Pg___Zt1_B__Zt2_B_,
},
+ // ZST2B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.B, <Zt2>.B }
+ {
+ goOp: AZST2B,
+ fixedBits: 0xe430e000,
+ args: XnSP__cimm__MUL_VL___Pg___Zt1_B__Zt2_B_,
+ },
},
// ZST2D
{
@@ -7718,6 +8096,12 @@ var insts = [][]instEncoder{
fixedBits: 0xe5a06000,
args: XnSP__Xm__LSL_c3___Pg___Zt1_D__Zt2_D_,
},
+ // ZST2D [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.D, <Zt2>.D }
+ {
+ goOp: AZST2D,
+ fixedBits: 0xe5b0e000,
+ args: XnSP__cimm__MUL_VL___Pg___Zt1_D__Zt2_D_,
+ },
},
// ZST2H
{
@@ -7727,6 +8111,12 @@ var insts = [][]instEncoder{
fixedBits: 0xe4a06000,
args: XnSP__Xm__LSL_c1___Pg___Zt1_H__Zt2_H_,
},
+ // ZST2H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.H, <Zt2>.H }
+ {
+ goOp: AZST2H,
+ fixedBits: 0xe4b0e000,
+ args: XnSP__cimm__MUL_VL___Pg___Zt1_H__Zt2_H_,
+ },
},
// ZST2Q
{
@@ -7736,6 +8126,12 @@ var insts = [][]instEncoder{
fixedBits: 0xe4600000,
args: XnSP__Xm__LSL_c4___Pg___Zt1_Q__Zt2_Q_,
},
+ // ZST2Q [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.Q, <Zt2>.Q }
+ {
+ goOp: AZST2Q,
+ fixedBits: 0xe4400000,
+ args: XnSP__cimm__MUL_VL___Pg___Zt1_Q__Zt2_Q_,
+ },
},
// ZST2W
{
@@ -7745,6 +8141,12 @@ var insts = [][]instEncoder{
fixedBits: 0xe5206000,
args: XnSP__Xm__LSL_c2___Pg___Zt1_S__Zt2_S_,
},
+ // ZST2W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.S, <Zt2>.S }
+ {
+ goOp: AZST2W,
+ fixedBits: 0xe530e000,
+ args: XnSP__cimm__MUL_VL___Pg___Zt1_S__Zt2_S_,
+ },
},
// ZST3B
{
@@ -7754,6 +8156,12 @@ var insts = [][]instEncoder{
fixedBits: 0xe4406000,
args: XnSP__Xm___Pg___Zt1_B__Zt2_B__Zt3_B_,
},
+ // ZST3B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.B, <Zt2>.B, <Zt3>.B }
+ {
+ goOp: AZST3B,
+ fixedBits: 0xe450e000,
+ args: XnSP__cimm__MUL_VL___Pg___Zt1_B__Zt2_B__Zt3_B_,
+ },
},
// ZST3D
{
@@ -7763,6 +8171,12 @@ var insts = [][]instEncoder{
fixedBits: 0xe5c06000,
args: XnSP__Xm__LSL_c3___Pg___Zt1_D__Zt2_D__Zt3_D_,
},
+ // ZST3D [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.D, <Zt2>.D, <Zt3>.D }
+ {
+ goOp: AZST3D,
+ fixedBits: 0xe5d0e000,
+ args: XnSP__cimm__MUL_VL___Pg___Zt1_D__Zt2_D__Zt3_D_,
+ },
},
// ZST3H
{
@@ -7772,6 +8186,12 @@ var insts = [][]instEncoder{
fixedBits: 0xe4c06000,
args: XnSP__Xm__LSL_c1___Pg___Zt1_H__Zt2_H__Zt3_H_,
},
+ // ZST3H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.H, <Zt2>.H, <Zt3>.H }
+ {
+ goOp: AZST3H,
+ fixedBits: 0xe4d0e000,
+ args: XnSP__cimm__MUL_VL___Pg___Zt1_H__Zt2_H__Zt3_H_,
+ },
},
// ZST3Q
{
@@ -7781,6 +8201,12 @@ var insts = [][]instEncoder{
fixedBits: 0xe4a00000,
args: XnSP__Xm__LSL_c4___Pg___Zt1_Q__Zt2_Q__Zt3_Q_,
},
+ // ZST3Q [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q }
+ {
+ goOp: AZST3Q,
+ fixedBits: 0xe4800000,
+ args: XnSP__cimm__MUL_VL___Pg___Zt1_Q__Zt2_Q__Zt3_Q_,
+ },
},
// ZST3W
{
@@ -7790,6 +8216,12 @@ var insts = [][]instEncoder{
fixedBits: 0xe5406000,
args: XnSP__Xm__LSL_c2___Pg___Zt1_S__Zt2_S__Zt3_S_,
},
+ // ZST3W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.S, <Zt2>.S, <Zt3>.S }
+ {
+ goOp: AZST3W,
+ fixedBits: 0xe550e000,
+ args: XnSP__cimm__MUL_VL___Pg___Zt1_S__Zt2_S__Zt3_S_,
+ },
},
// ZST4B
{
@@ -7799,6 +8231,12 @@ var insts = [][]instEncoder{
fixedBits: 0xe4606000,
args: XnSP__Xm___Pg___Zt1_B__Zt2_B__Zt3_B__Zt4_B_,
},
+ // ZST4B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }
+ {
+ goOp: AZST4B,
+ fixedBits: 0xe470e000,
+ args: XnSP__cimm__MUL_VL___Pg___Zt1_B__Zt2_B__Zt3_B__Zt4_B_,
+ },
},
// ZST4D
{
@@ -7808,6 +8246,12 @@ var insts = [][]instEncoder{
fixedBits: 0xe5e06000,
args: XnSP__Xm__LSL_c3___Pg___Zt1_D__Zt2_D__Zt3_D__Zt4_D_,
},
+ // ZST4D [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }
+ {
+ goOp: AZST4D,
+ fixedBits: 0xe5f0e000,
+ args: XnSP__cimm__MUL_VL___Pg___Zt1_D__Zt2_D__Zt3_D__Zt4_D_,
+ },
},
// ZST4H
{
@@ -7817,6 +8261,12 @@ var insts = [][]instEncoder{
fixedBits: 0xe4e06000,
args: XnSP__Xm__LSL_c1___Pg___Zt1_H__Zt2_H__Zt3_H__Zt4_H_,
},
+ // ZST4H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }
+ {
+ goOp: AZST4H,
+ fixedBits: 0xe4f0e000,
+ args: XnSP__cimm__MUL_VL___Pg___Zt1_H__Zt2_H__Zt3_H__Zt4_H_,
+ },
},
// ZST4Q
{
@@ -7826,6 +8276,12 @@ var insts = [][]instEncoder{
fixedBits: 0xe4e00000,
args: XnSP__Xm__LSL_c4___Pg___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_,
},
+ // ZST4Q [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q, <Zt4>.Q }
+ {
+ goOp: AZST4Q,
+ fixedBits: 0xe4c00000,
+ args: XnSP__cimm__MUL_VL___Pg___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_,
+ },
},
// ZST4W
{
@@ -7835,6 +8291,12 @@ var insts = [][]instEncoder{
fixedBits: 0xe5606000,
args: XnSP__Xm__LSL_c2___Pg___Zt1_S__Zt2_S__Zt3_S__Zt4_S_,
},
+ // ZST4W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }
+ {
+ goOp: AZST4W,
+ fixedBits: 0xe570e000,
+ args: XnSP__cimm__MUL_VL___Pg___Zt1_S__Zt2_S__Zt3_S__Zt4_S_,
+ },
},
// ZSTNT1B
{
@@ -7856,6 +8318,12 @@ var insts = [][]instEncoder{
fixedBits: 0xe4402000,
args: Zn_S__Xm___Pg___Zt_S_,
},
+ // ZSTNT1B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt>.B }
+ {
+ goOp: AZSTNT1B,
+ fixedBits: 0xe410e000,
+ args: XnSP__cimm__MUL_VL___Pg___Zt_B_,
+ },
},
// ZSTNT1D
{
@@ -7871,6 +8339,12 @@ var insts = [][]instEncoder{
fixedBits: 0xe5802000,
args: Zn_D__Xm___Pg___Zt_D_,
},
+ // ZSTNT1D [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt>.D }
+ {
+ goOp: AZSTNT1D,
+ fixedBits: 0xe590e000,
+ args: XnSP__cimm__MUL_VL___Pg___Zt_D_,
+ },
},
// ZSTNT1H
{
@@ -7892,6 +8366,12 @@ var insts = [][]instEncoder{
fixedBits: 0xe4c02000,
args: Zn_S__Xm___Pg___Zt_S_,
},
+ // ZSTNT1H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt>.H }
+ {
+ goOp: AZSTNT1H,
+ fixedBits: 0xe490e000,
+ args: XnSP__cimm__MUL_VL___Pg___Zt_H_,
+ },
},
// ZSTNT1W
{
@@ -7913,6 +8393,21 @@ var insts = [][]instEncoder{
fixedBits: 0xe5402000,
args: Zn_S__Xm___Pg___Zt_S_,
},
+ // ZSTNT1W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt>.S }
+ {
+ goOp: AZSTNT1W,
+ fixedBits: 0xe510e000,
+ args: XnSP__cimm__MUL_VL___Pg___Zt_S_,
+ },
+ },
+ // ZSTR
+ {
+ // ZSTR [<Xn|SP>{, #<imm>, MUL VL}], <Zt>
+ {
+ goOp: AZSTR,
+ fixedBits: 0xe5804000,
+ args: XnSP__cimm__MUL_VL___Zt,
+ },
},
// ZSUB
{
@@ -11020,6 +11515,54 @@ var a_MEMEXT_Zn510V2_SzSD2223_Zm1621V3_SzSD2223_Msz1012_Msz1012Amount = operand{
},
}
+var a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3 = operand{
+ class: AC_MEMOFFMULVL, elemEncoders: []elemEncoder{
+ {encodeRn510SPV2, enc_Rn},
+ {encodeNoop, enc_NIL},
+ {encodeImm41620V3, enc_imm4},
+ },
+}
+
+var a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4 = operand{
+ class: AC_MEMOFFMULVL, elemEncoders: []elemEncoder{
+ {encodeRn510SPV2, enc_Rn},
+ {encodeNoop, enc_NIL},
+ {encodeImm41620V4, enc_imm4},
+ },
+}
+
+var a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5 = operand{
+ class: AC_MEMOFFMULVL, elemEncoders: []elemEncoder{
+ {encodeRn510SPV2, enc_Rn},
+ {encodeNoop, enc_NIL},
+ {encodeImm41620V5, enc_imm4},
+ },
+}
+
+var a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6 = operand{
+ class: AC_MEMOFFMULVL, elemEncoders: []elemEncoder{
+ {encodeRn510SPV2, enc_Rn},
+ {encodeNoop, enc_NIL},
+ {encodeImm41620V6, enc_imm4},
+ },
+}
+
+var a_MEMOFFMULVL_Rn510SPV2_Noop_Imm61622V5 = operand{
+ class: AC_MEMOFFMULVL, elemEncoders: []elemEncoder{
+ {encodeRn510SPV2, enc_Rn},
+ {encodeNoop, enc_NIL},
+ {encodeImm61622V5, enc_imm6},
+ },
+}
+
+var a_MEMOFFMULVL_Rn510SPV2_Noop_Imm9h1622L1013 = operand{
+ class: AC_MEMOFFMULVL, elemEncoders: []elemEncoder{
+ {encodeRn510SPV2, enc_Rn},
+ {encodeNoop, enc_NIL},
+ {encodeImm9h1622L1013, enc_imm9h_imm9l},
+ },
+}
+
var a_MEMOFF_Rn510SPV2_Noop_Imm41620V1 = operand{
class: AC_MEMOFF, elemEncoders: []elemEncoder{
{encodeRn510SPV2, enc_Rn},
@@ -11225,6 +11768,20 @@ var a_PREG_Pg59_Noop = operand{
},
}
+var a_PREG_Pt04V1_Noop = operand{
+ class: AC_PREG, elemEncoders: []elemEncoder{
+ {encodePt04V1, enc_Pt},
+ {encodeNoop, enc_NIL},
+ },
+}
+
+var a_PREG_Pt04V2_Noop = operand{
+ class: AC_PREG, elemEncoders: []elemEncoder{
+ {encodePt04V2, enc_Pt},
+ {encodeNoop, enc_NIL},
+ },
+}
+
var a_PREG_Pv1013_Noop = operand{
class: AC_PREG, elemEncoders: []elemEncoder{
{encodePv1013, enc_Pv},
@@ -11788,6 +12345,13 @@ var a_ZREG_Zn510Src_Noop = operand{
},
}
+var a_ZREG_Zt05_Noop = operand{
+ class: AC_ZREG, elemEncoders: []elemEncoder{
+ {encodeZt05, enc_Zt},
+ {encodeNoop, enc_NIL},
+ },
+}
+
var PNd_T = []operand{
a_ARNG_PNd_SizeBHSD2224,
}
@@ -12554,6 +13118,267 @@ var XnSP__Zm_S__mod_c3___Pg__prfop = []operand{
a_SPECIAL_Prfop04,
}
+var XnSP__cimm__MUL_VL___PgZ___Zt1_B__Zt2_B_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_REGLIST2_Zt051_ArngBCheck_Zt052_ArngBCheck,
+}
+
+var XnSP__cimm__MUL_VL___PgZ___Zt1_B__Zt2_B__Zt3_B_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_REGLIST3_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck,
+}
+
+var XnSP__cimm__MUL_VL___PgZ___Zt1_B__Zt2_B__Zt3_B__Zt4_B_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_REGLIST4_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck_Zt054_ArngBCheck,
+}
+
+var XnSP__cimm__MUL_VL___PgZ___Zt1_D__Zt2_D_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_REGLIST2_Zt051_ArngDCheck_Zt052_ArngDCheck,
+}
+
+var XnSP__cimm__MUL_VL___PgZ___Zt1_D__Zt2_D__Zt3_D_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_REGLIST3_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck,
+}
+
+var XnSP__cimm__MUL_VL___PgZ___Zt1_D__Zt2_D__Zt3_D__Zt4_D_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_REGLIST4_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck_Zt054_ArngDCheck,
+}
+
+var XnSP__cimm__MUL_VL___PgZ___Zt1_H__Zt2_H_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_REGLIST2_Zt051_ArngHCheck_Zt052_ArngHCheck,
+}
+
+var XnSP__cimm__MUL_VL___PgZ___Zt1_H__Zt2_H__Zt3_H_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_REGLIST3_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck,
+}
+
+var XnSP__cimm__MUL_VL___PgZ___Zt1_H__Zt2_H__Zt3_H__Zt4_H_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_REGLIST4_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck_Zt054_ArngHCheck,
+}
+
+var XnSP__cimm__MUL_VL___PgZ___Zt1_Q__Zt2_Q_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_REGLIST2_Zt051_ArngQCheck_Zt052_ArngQCheck,
+}
+
+var XnSP__cimm__MUL_VL___PgZ___Zt1_Q__Zt2_Q__Zt3_Q_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_REGLIST3_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck,
+}
+
+var XnSP__cimm__MUL_VL___PgZ___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_REGLIST4_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck_Zt054_ArngQCheck,
+}
+
+var XnSP__cimm__MUL_VL___PgZ___Zt1_S__Zt2_S_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_REGLIST2_Zt051_ArngSCheck_Zt052_ArngSCheck,
+}
+
+var XnSP__cimm__MUL_VL___PgZ___Zt1_S__Zt2_S__Zt3_S_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_REGLIST3_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck,
+}
+
+var XnSP__cimm__MUL_VL___PgZ___Zt1_S__Zt2_S__Zt3_S__Zt4_S_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_REGLIST4_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck_Zt054_ArngSCheck,
+}
+
+var XnSP__cimm__MUL_VL___PgZ___Zt_B_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_REGLIST1_Zt05_ArngBCheck,
+}
+
+var XnSP__cimm__MUL_VL___PgZ___Zt_D_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__cimm__MUL_VL___PgZ___Zt_H_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_REGLIST1_Zt05_ArngHCheck,
+}
+
+var XnSP__cimm__MUL_VL___PgZ___Zt_S_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var XnSP__cimm__MUL_VL___Pg___Zt1_B__Zt2_B_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6,
+ a_PREG_Pg1013_Noop,
+ a_REGLIST2_Zt051_ArngBCheck_Zt052_ArngBCheck,
+}
+
+var XnSP__cimm__MUL_VL___Pg___Zt1_B__Zt2_B__Zt3_B_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3,
+ a_PREG_Pg1013_Noop,
+ a_REGLIST3_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck,
+}
+
+var XnSP__cimm__MUL_VL___Pg___Zt1_B__Zt2_B__Zt3_B__Zt4_B_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4,
+ a_PREG_Pg1013_Noop,
+ a_REGLIST4_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck_Zt054_ArngBCheck,
+}
+
+var XnSP__cimm__MUL_VL___Pg___Zt1_D__Zt2_D_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6,
+ a_PREG_Pg1013_Noop,
+ a_REGLIST2_Zt051_ArngDCheck_Zt052_ArngDCheck,
+}
+
+var XnSP__cimm__MUL_VL___Pg___Zt1_D__Zt2_D__Zt3_D_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3,
+ a_PREG_Pg1013_Noop,
+ a_REGLIST3_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck,
+}
+
+var XnSP__cimm__MUL_VL___Pg___Zt1_D__Zt2_D__Zt3_D__Zt4_D_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4,
+ a_PREG_Pg1013_Noop,
+ a_REGLIST4_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck_Zt054_ArngDCheck,
+}
+
+var XnSP__cimm__MUL_VL___Pg___Zt1_H__Zt2_H_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6,
+ a_PREG_Pg1013_Noop,
+ a_REGLIST2_Zt051_ArngHCheck_Zt052_ArngHCheck,
+}
+
+var XnSP__cimm__MUL_VL___Pg___Zt1_H__Zt2_H__Zt3_H_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3,
+ a_PREG_Pg1013_Noop,
+ a_REGLIST3_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck,
+}
+
+var XnSP__cimm__MUL_VL___Pg___Zt1_H__Zt2_H__Zt3_H__Zt4_H_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4,
+ a_PREG_Pg1013_Noop,
+ a_REGLIST4_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck_Zt054_ArngHCheck,
+}
+
+var XnSP__cimm__MUL_VL___Pg___Zt1_Q__Zt2_Q_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6,
+ a_PREG_Pg1013_Noop,
+ a_REGLIST2_Zt051_ArngQCheck_Zt052_ArngQCheck,
+}
+
+var XnSP__cimm__MUL_VL___Pg___Zt1_Q__Zt2_Q__Zt3_Q_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3,
+ a_PREG_Pg1013_Noop,
+ a_REGLIST3_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck,
+}
+
+var XnSP__cimm__MUL_VL___Pg___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4,
+ a_PREG_Pg1013_Noop,
+ a_REGLIST4_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck_Zt054_ArngQCheck,
+}
+
+var XnSP__cimm__MUL_VL___Pg___Zt1_S__Zt2_S_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6,
+ a_PREG_Pg1013_Noop,
+ a_REGLIST2_Zt051_ArngSCheck_Zt052_ArngSCheck,
+}
+
+var XnSP__cimm__MUL_VL___Pg___Zt1_S__Zt2_S__Zt3_S_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3,
+ a_PREG_Pg1013_Noop,
+ a_REGLIST3_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck,
+}
+
+var XnSP__cimm__MUL_VL___Pg___Zt1_S__Zt2_S__Zt3_S__Zt4_S_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4,
+ a_PREG_Pg1013_Noop,
+ a_REGLIST4_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck_Zt054_ArngSCheck,
+}
+
+var XnSP__cimm__MUL_VL___Pg___Zt_B_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5,
+ a_PREG_Pg1013_Noop,
+ a_REGLIST1_Zt05_ArngBCheck,
+}
+
+var XnSP__cimm__MUL_VL___Pg___Zt_D_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5,
+ a_PREG_Pg1013_Noop,
+ a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__cimm__MUL_VL___Pg___Zt_H_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5,
+ a_PREG_Pg1013_Noop,
+ a_REGLIST1_Zt05_ArngHCheck,
+}
+
+var XnSP__cimm__MUL_VL___Pg___Zt_S_ = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5,
+ a_PREG_Pg1013_Noop,
+ a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var XnSP__cimm__MUL_VL___Pg___Zt_T___1 = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5,
+ a_PREG_Pg1013_Noop,
+ a_REGLIST1_Zt05_Size2123V1,
+}
+
+var XnSP__cimm__MUL_VL___Pg___Zt_T___2 = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5,
+ a_PREG_Pg1013_Noop,
+ a_REGLIST1_Zt05_Size2123V2,
+}
+
+var XnSP__cimm__MUL_VL___Pg__prfop = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm61622V5,
+ a_PREG_Pg1013_Noop,
+ a_SPECIAL_Prfop04,
+}
+
+var XnSP__cimm__MUL_VL___Pt__1 = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm9h1622L1013,
+ a_PREG_Pt04V1_Noop,
+}
+
+var XnSP__cimm__MUL_VL___Pt__2 = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm9h1622L1013,
+ a_PREG_Pt04V2_Noop,
+}
+
+var XnSP__cimm__MUL_VL___Zt = []operand{
+ a_MEMOFFMULVL_Rn510SPV2_Noop_Imm9h1622L1013,
+ a_ZREG_Zt05_Noop,
+}
+
var XnSP__cimm___PgZ___Zt_B___1 = []operand{
a_MEMOFF_Rn510SPV2_Noop_Imm61622V4,
a_PREGZM_Pg1013_ZeroPredCheck,
diff --git a/src/cmd/internal/obj/util.go b/src/cmd/internal/obj/util.go
index fffafeba05..2b7c1f99a8 100644
--- a/src/cmd/internal/obj/util.go
+++ b/src/cmd/internal/obj/util.go
@@ -304,24 +304,32 @@ func writeDconv(w io.Writer, p *Prog, a *Addr, abiDetail bool) {
case TYPE_MEM:
if buildcfg.GOARCH == "arm64" && (a.Scale < 0 || (a.Index != REG_NONE && (isZReg(int(a.Reg)) || isZReg(int(a.Index))))) {
// SVE extended addressing pattern
- amount := 0
- mod := 0
- if a.Scale < 0 {
- amount = int((a.Scale >> 12) & 0x7)
- mod = int((a.Scale >> 9) & 0x7)
- }
- modStr := ""
- switch mod {
- case 1:
- modStr = ".UXTW"
- case 2:
- modStr = ".SXTW"
- }
- amountStr := ""
- if amount != 0 {
- amountStr = fmt.Sprintf("<<%d", amount)
+ if a.Index == REG_NONE {
+ if a.Offset < 0 {
+ fmt.Fprintf(w, "(-VL*%d)(%v)", -a.Offset, Rconv(int(a.Reg)))
+ } else {
+ fmt.Fprintf(w, "(VL*%d)(%v)", a.Offset, Rconv(int(a.Reg)))
+ }
+ } else {
+ amount := 0
+ mod := 0
+ if a.Scale < 0 {
+ amount = int((a.Scale >> 12) & 0x7)
+ mod = int((a.Scale >> 9) & 0x7)
+ }
+ modStr := ""
+ switch mod {
+ case 1:
+ modStr = ".UXTW"
+ case 2:
+ modStr = ".SXTW"
+ }
+ amountStr := ""
+ if amount != 0 {
+ amountStr = fmt.Sprintf("<<%d", amount)
+ }
+ fmt.Fprintf(w, "(%v%s%s)(%v)", Rconv(int(a.Reg)), modStr, amountStr, Rconv(int(a.Index)))
}
- fmt.Fprintf(w, "(%v%s%s)(%v)", Rconv(int(a.Reg)), modStr, amountStr, Rconv(int(a.Index)))
} else {
a.WriteNameTo(w)
if a.Index != REG_NONE {
generated by cgit v1.3 (git 2.53.0) at 2026-04-15 07:40:50 +0000