diff options
Diffstat (limited to 'src/cmd')
| -rw-r--r-- | src/cmd/compile/internal/ppc64/ssa.go | 20 | ||||
| -rw-r--r-- | src/cmd/go/internal/modfetch/pseudo.go | 2 | ||||
| -rw-r--r-- | src/cmd/internal/obj/s390x/asmz.go | 484 | ||||
| -rw-r--r-- | src/cmd/link/internal/ld/dwarf_test.go | 6 | ||||
| -rw-r--r-- | src/cmd/link/internal/wasm/asm.go | 34 | ||||
| -rw-r--r-- | src/cmd/trace/pprof.go | 2 |
6 files changed, 274 insertions, 274 deletions
diff --git a/src/cmd/compile/internal/ppc64/ssa.go b/src/cmd/compile/internal/ppc64/ssa.go index f3a49643f1..cbe233f054 100644 --- a/src/cmd/compile/internal/ppc64/ssa.go +++ b/src/cmd/compile/internal/ppc64/ssa.go @@ -25,16 +25,16 @@ type iselOp struct { var iselRegs = [2]int16{ppc64.REG_R0, ppc64.REGTMP} var iselOps = map[ssa.Op]iselOp{ - ssa.OpPPC64Equal: iselOp{cond: ppc64.C_COND_EQ, valueIfCond: 1}, - ssa.OpPPC64NotEqual: iselOp{cond: ppc64.C_COND_EQ, valueIfCond: 0}, - ssa.OpPPC64LessThan: iselOp{cond: ppc64.C_COND_LT, valueIfCond: 1}, - ssa.OpPPC64GreaterEqual: iselOp{cond: ppc64.C_COND_LT, valueIfCond: 0}, - ssa.OpPPC64GreaterThan: iselOp{cond: ppc64.C_COND_GT, valueIfCond: 1}, - ssa.OpPPC64LessEqual: iselOp{cond: ppc64.C_COND_GT, valueIfCond: 0}, - ssa.OpPPC64FLessThan: iselOp{cond: ppc64.C_COND_LT, valueIfCond: 1}, - ssa.OpPPC64FGreaterThan: iselOp{cond: ppc64.C_COND_GT, valueIfCond: 1}, - ssa.OpPPC64FLessEqual: iselOp{cond: ppc64.C_COND_LT, valueIfCond: 1}, // 2 comparisons, 2nd is EQ - ssa.OpPPC64FGreaterEqual: iselOp{cond: ppc64.C_COND_GT, valueIfCond: 1}, // 2 comparisons, 2nd is EQ + ssa.OpPPC64Equal: {cond: ppc64.C_COND_EQ, valueIfCond: 1}, + ssa.OpPPC64NotEqual: {cond: ppc64.C_COND_EQ, valueIfCond: 0}, + ssa.OpPPC64LessThan: {cond: ppc64.C_COND_LT, valueIfCond: 1}, + ssa.OpPPC64GreaterEqual: {cond: ppc64.C_COND_LT, valueIfCond: 0}, + ssa.OpPPC64GreaterThan: {cond: ppc64.C_COND_GT, valueIfCond: 1}, + ssa.OpPPC64LessEqual: {cond: ppc64.C_COND_GT, valueIfCond: 0}, + ssa.OpPPC64FLessThan: {cond: ppc64.C_COND_LT, valueIfCond: 1}, + ssa.OpPPC64FGreaterThan: {cond: ppc64.C_COND_GT, valueIfCond: 1}, + ssa.OpPPC64FLessEqual: {cond: ppc64.C_COND_LT, valueIfCond: 1}, // 2 comparisons, 2nd is EQ + ssa.OpPPC64FGreaterEqual: {cond: ppc64.C_COND_GT, valueIfCond: 1}, // 2 comparisons, 2nd is EQ } // markMoves marks any MOVXconst ops that need to avoid clobbering flags. diff --git a/src/cmd/go/internal/modfetch/pseudo.go b/src/cmd/go/internal/modfetch/pseudo.go index 88c3d3a527..0d3be10491 100644 --- a/src/cmd/go/internal/modfetch/pseudo.go +++ b/src/cmd/go/internal/modfetch/pseudo.go @@ -62,7 +62,7 @@ func PseudoVersion(major, older string, t time.Time, rev string) string { // Form (2), (3). // Extract patch from vMAJOR.MINOR.PATCH - v := older[:len(older)] + v := older[:] i := strings.LastIndex(v, ".") + 1 v, patch := v[:i], v[i:] diff --git a/src/cmd/internal/obj/s390x/asmz.go b/src/cmd/internal/obj/s390x/asmz.go index d043b2878e..2b187edca5 100644 --- a/src/cmd/internal/obj/s390x/asmz.go +++ b/src/cmd/internal/obj/s390x/asmz.go @@ -68,351 +68,351 @@ type Optab struct { var optab = []Optab{ // zero-length instructions - Optab{i: 0, as: obj.ATEXT, a1: C_ADDR, a6: C_TEXTSIZE}, - Optab{i: 0, as: obj.ATEXT, a1: C_ADDR, a3: C_LCON, a6: C_TEXTSIZE}, - Optab{i: 0, as: obj.APCDATA, a1: C_LCON, a6: C_LCON}, - Optab{i: 0, as: obj.AFUNCDATA, a1: C_SCON, a6: C_ADDR}, - Optab{i: 0, as: obj.ANOP}, - Optab{i: 0, as: obj.ANOP, a1: C_SAUTO}, + {i: 0, as: obj.ATEXT, a1: C_ADDR, a6: C_TEXTSIZE}, + {i: 0, as: obj.ATEXT, a1: C_ADDR, a3: C_LCON, a6: C_TEXTSIZE}, + {i: 0, as: obj.APCDATA, a1: C_LCON, a6: C_LCON}, + {i: 0, as: obj.AFUNCDATA, a1: C_SCON, a6: C_ADDR}, + {i: 0, as: obj.ANOP}, + {i: 0, as: obj.ANOP, a1: C_SAUTO}, // move register - Optab{i: 1, as: AMOVD, a1: C_REG, a6: C_REG}, - Optab{i: 1, as: AMOVB, a1: C_REG, a6: C_REG}, - Optab{i: 1, as: AMOVBZ, a1: C_REG, a6: C_REG}, - Optab{i: 1, as: AMOVW, a1: C_REG, a6: C_REG}, - Optab{i: 1, as: AMOVWZ, a1: C_REG, a6: C_REG}, - Optab{i: 1, as: AFMOVD, a1: C_FREG, a6: C_FREG}, - Optab{i: 1, as: AMOVDBR, a1: C_REG, a6: C_REG}, + {i: 1, as: AMOVD, a1: C_REG, a6: C_REG}, + {i: 1, as: AMOVB, a1: C_REG, a6: C_REG}, + {i: 1, as: AMOVBZ, a1: C_REG, a6: C_REG}, + {i: 1, as: AMOVW, a1: C_REG, a6: C_REG}, + {i: 1, as: AMOVWZ, a1: C_REG, a6: C_REG}, + {i: 1, as: AFMOVD, a1: C_FREG, a6: C_FREG}, + {i: 1, as: AMOVDBR, a1: C_REG, a6: C_REG}, // load constant - Optab{i: 26, as: AMOVD, a1: C_LACON, a6: C_REG}, - Optab{i: 26, as: AMOVW, a1: C_LACON, a6: C_REG}, - Optab{i: 26, as: AMOVWZ, a1: C_LACON, a6: C_REG}, - Optab{i: 3, as: AMOVD, a1: C_DCON, a6: C_REG}, - Optab{i: 3, as: AMOVW, a1: C_DCON, a6: C_REG}, - Optab{i: 3, as: AMOVWZ, a1: C_DCON, a6: C_REG}, - Optab{i: 3, as: AMOVB, a1: C_DCON, a6: C_REG}, - Optab{i: 3, as: AMOVBZ, a1: C_DCON, a6: C_REG}, + {i: 26, as: AMOVD, a1: C_LACON, a6: C_REG}, + {i: 26, as: AMOVW, a1: C_LACON, a6: C_REG}, + {i: 26, as: AMOVWZ, a1: C_LACON, a6: C_REG}, + {i: 3, as: AMOVD, a1: C_DCON, a6: C_REG}, + {i: 3, as: AMOVW, a1: C_DCON, a6: C_REG}, + {i: 3, as: AMOVWZ, a1: C_DCON, a6: C_REG}, + {i: 3, as: AMOVB, a1: C_DCON, a6: C_REG}, + {i: 3, as: AMOVBZ, a1: C_DCON, a6: C_REG}, // store constant - Optab{i: 72, as: AMOVD, a1: C_SCON, a6: C_LAUTO}, - Optab{i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LAUTO}, - Optab{i: 72, as: AMOVW, a1: C_SCON, a6: C_LAUTO}, - Optab{i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LAUTO}, - Optab{i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LAUTO}, - Optab{i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LAUTO}, - Optab{i: 72, as: AMOVB, a1: C_SCON, a6: C_LAUTO}, - Optab{i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LAUTO}, - Optab{i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LAUTO}, - Optab{i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LAUTO}, - Optab{i: 72, as: AMOVD, a1: C_SCON, a6: C_LOREG}, - Optab{i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LOREG}, - Optab{i: 72, as: AMOVW, a1: C_SCON, a6: C_LOREG}, - Optab{i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LOREG}, - Optab{i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LOREG}, - Optab{i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LOREG}, - Optab{i: 72, as: AMOVB, a1: C_SCON, a6: C_LOREG}, - Optab{i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LOREG}, - Optab{i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LOREG}, - Optab{i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LOREG}, + {i: 72, as: AMOVD, a1: C_SCON, a6: C_LAUTO}, + {i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LAUTO}, + {i: 72, as: AMOVW, a1: C_SCON, a6: C_LAUTO}, + {i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LAUTO}, + {i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LAUTO}, + {i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LAUTO}, + {i: 72, as: AMOVB, a1: C_SCON, a6: C_LAUTO}, + {i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LAUTO}, + {i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LAUTO}, + {i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LAUTO}, + {i: 72, as: AMOVD, a1: C_SCON, a6: C_LOREG}, + {i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LOREG}, + {i: 72, as: AMOVW, a1: C_SCON, a6: C_LOREG}, + {i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LOREG}, + {i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LOREG}, + {i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LOREG}, + {i: 72, as: AMOVB, a1: C_SCON, a6: C_LOREG}, + {i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LOREG}, + {i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LOREG}, + {i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LOREG}, // store - Optab{i: 35, as: AMOVD, a1: C_REG, a6: C_LAUTO}, - Optab{i: 35, as: AMOVW, a1: C_REG, a6: C_LAUTO}, - Optab{i: 35, as: AMOVWZ, a1: C_REG, a6: C_LAUTO}, - Optab{i: 35, as: AMOVBZ, a1: C_REG, a6: C_LAUTO}, - Optab{i: 35, as: AMOVB, a1: C_REG, a6: C_LAUTO}, - Optab{i: 35, as: AMOVDBR, a1: C_REG, a6: C_LAUTO}, - Optab{i: 35, as: AMOVHBR, a1: C_REG, a6: C_LAUTO}, - Optab{i: 35, as: AMOVD, a1: C_REG, a6: C_LOREG}, - Optab{i: 35, as: AMOVW, a1: C_REG, a6: C_LOREG}, - Optab{i: 35, as: AMOVWZ, a1: C_REG, a6: C_LOREG}, - Optab{i: 35, as: AMOVBZ, a1: C_REG, a6: C_LOREG}, - Optab{i: 35, as: AMOVB, a1: C_REG, a6: C_LOREG}, - Optab{i: 35, as: AMOVDBR, a1: C_REG, a6: C_LOREG}, - Optab{i: 35, as: AMOVHBR, a1: C_REG, a6: C_LOREG}, - Optab{i: 74, as: AMOVD, a1: C_REG, a6: C_ADDR}, - Optab{i: 74, as: AMOVW, a1: C_REG, a6: C_ADDR}, - Optab{i: 74, as: AMOVWZ, a1: C_REG, a6: C_ADDR}, - Optab{i: 74, as: AMOVBZ, a1: C_REG, a6: C_ADDR}, - Optab{i: 74, as: AMOVB, a1: C_REG, a6: C_ADDR}, + {i: 35, as: AMOVD, a1: C_REG, a6: C_LAUTO}, + {i: 35, as: AMOVW, a1: C_REG, a6: C_LAUTO}, + {i: 35, as: AMOVWZ, a1: C_REG, a6: C_LAUTO}, + {i: 35, as: AMOVBZ, a1: C_REG, a6: C_LAUTO}, + {i: 35, as: AMOVB, a1: C_REG, a6: C_LAUTO}, + {i: 35, as: AMOVDBR, a1: C_REG, a6: C_LAUTO}, + {i: 35, as: AMOVHBR, a1: C_REG, a6: C_LAUTO}, + {i: 35, as: AMOVD, a1: C_REG, a6: C_LOREG}, + {i: 35, as: AMOVW, a1: C_REG, a6: C_LOREG}, + {i: 35, as: AMOVWZ, a1: C_REG, a6: C_LOREG}, + {i: 35, as: AMOVBZ, a1: C_REG, a6: C_LOREG}, + {i: 35, as: AMOVB, a1: C_REG, a6: C_LOREG}, + {i: 35, as: AMOVDBR, a1: C_REG, a6: C_LOREG}, + {i: 35, as: AMOVHBR, a1: C_REG, a6: C_LOREG}, + {i: 74, as: AMOVD, a1: C_REG, a6: C_ADDR}, + {i: 74, as: AMOVW, a1: C_REG, a6: C_ADDR}, + {i: 74, as: AMOVWZ, a1: C_REG, a6: C_ADDR}, + {i: 74, as: AMOVBZ, a1: C_REG, a6: C_ADDR}, + {i: 74, as: AMOVB, a1: C_REG, a6: C_ADDR}, // load - Optab{i: 36, as: AMOVD, a1: C_LAUTO, a6: C_REG}, - Optab{i: 36, as: AMOVW, a1: C_LAUTO, a6: C_REG}, - Optab{i: 36, as: AMOVWZ, a1: C_LAUTO, a6: C_REG}, - Optab{i: 36, as: AMOVBZ, a1: C_LAUTO, a6: C_REG}, - Optab{i: 36, as: AMOVB, a1: C_LAUTO, a6: C_REG}, - Optab{i: 36, as: AMOVDBR, a1: C_LAUTO, a6: C_REG}, - Optab{i: 36, as: AMOVHBR, a1: C_LAUTO, a6: C_REG}, - Optab{i: 36, as: AMOVD, a1: C_LOREG, a6: C_REG}, - Optab{i: 36, as: AMOVW, a1: C_LOREG, a6: C_REG}, - Optab{i: 36, as: AMOVWZ, a1: C_LOREG, a6: C_REG}, - Optab{i: 36, as: AMOVBZ, a1: C_LOREG, a6: C_REG}, - Optab{i: 36, as: AMOVB, a1: C_LOREG, a6: C_REG}, - Optab{i: 36, as: AMOVDBR, a1: C_LOREG, a6: C_REG}, - Optab{i: 36, as: AMOVHBR, a1: C_LOREG, a6: C_REG}, - Optab{i: 75, as: AMOVD, a1: C_ADDR, a6: C_REG}, - Optab{i: 75, as: AMOVW, a1: C_ADDR, a6: C_REG}, - Optab{i: 75, as: AMOVWZ, a1: C_ADDR, a6: C_REG}, - Optab{i: 75, as: AMOVBZ, a1: C_ADDR, a6: C_REG}, - Optab{i: 75, as: AMOVB, a1: C_ADDR, a6: C_REG}, + {i: 36, as: AMOVD, a1: C_LAUTO, a6: C_REG}, + {i: 36, as: AMOVW, a1: C_LAUTO, a6: C_REG}, + {i: 36, as: AMOVWZ, a1: C_LAUTO, a6: C_REG}, + {i: 36, as: AMOVBZ, a1: C_LAUTO, a6: C_REG}, + {i: 36, as: AMOVB, a1: C_LAUTO, a6: C_REG}, + {i: 36, as: AMOVDBR, a1: C_LAUTO, a6: C_REG}, + {i: 36, as: AMOVHBR, a1: C_LAUTO, a6: C_REG}, + {i: 36, as: AMOVD, a1: C_LOREG, a6: C_REG}, + {i: 36, as: AMOVW, a1: C_LOREG, a6: C_REG}, + {i: 36, as: AMOVWZ, a1: C_LOREG, a6: C_REG}, + {i: 36, as: AMOVBZ, a1: C_LOREG, a6: C_REG}, + {i: 36, as: AMOVB, a1: C_LOREG, a6: C_REG}, + {i: 36, as: AMOVDBR, a1: C_LOREG, a6: C_REG}, + {i: 36, as: AMOVHBR, a1: C_LOREG, a6: C_REG}, + {i: 75, as: AMOVD, a1: C_ADDR, a6: C_REG}, + {i: 75, as: AMOVW, a1: C_ADDR, a6: C_REG}, + {i: 75, as: AMOVWZ, a1: C_ADDR, a6: C_REG}, + {i: 75, as: AMOVBZ, a1: C_ADDR, a6: C_REG}, + {i: 75, as: AMOVB, a1: C_ADDR, a6: C_REG}, // interlocked load and op - Optab{i: 99, as: ALAAG, a1: C_REG, a2: C_REG, a6: C_LOREG}, + {i: 99, as: ALAAG, a1: C_REG, a2: C_REG, a6: C_LOREG}, // integer arithmetic - Optab{i: 2, as: AADD, a1: C_REG, a2: C_REG, a6: C_REG}, - Optab{i: 2, as: AADD, a1: C_REG, a6: C_REG}, - Optab{i: 22, as: AADD, a1: C_LCON, a2: C_REG, a6: C_REG}, - Optab{i: 22, as: AADD, a1: C_LCON, a6: C_REG}, - Optab{i: 12, as: AADD, a1: C_LOREG, a6: C_REG}, - Optab{i: 12, as: AADD, a1: C_LAUTO, a6: C_REG}, - Optab{i: 21, as: ASUB, a1: C_LCON, a2: C_REG, a6: C_REG}, - Optab{i: 21, as: ASUB, a1: C_LCON, a6: C_REG}, - Optab{i: 12, as: ASUB, a1: C_LOREG, a6: C_REG}, - Optab{i: 12, as: ASUB, a1: C_LAUTO, a6: C_REG}, - Optab{i: 4, as: AMULHD, a1: C_REG, a6: C_REG}, - Optab{i: 4, as: AMULHD, a1: C_REG, a2: C_REG, a6: C_REG}, - Optab{i: 2, as: ADIVW, a1: C_REG, a2: C_REG, a6: C_REG}, - Optab{i: 2, as: ADIVW, a1: C_REG, a6: C_REG}, - Optab{i: 10, as: ASUB, a1: C_REG, a2: C_REG, a6: C_REG}, - Optab{i: 10, as: ASUB, a1: C_REG, a6: C_REG}, - Optab{i: 47, as: ANEG, a1: C_REG, a6: C_REG}, - Optab{i: 47, as: ANEG, a6: C_REG}, + {i: 2, as: AADD, a1: C_REG, a2: C_REG, a6: C_REG}, + {i: 2, as: AADD, a1: C_REG, a6: C_REG}, + {i: 22, as: AADD, a1: C_LCON, a2: C_REG, a6: C_REG}, + {i: 22, as: AADD, a1: C_LCON, a6: C_REG}, + {i: 12, as: AADD, a1: C_LOREG, a6: C_REG}, + {i: 12, as: AADD, a1: C_LAUTO, a6: C_REG}, + {i: 21, as: ASUB, a1: C_LCON, a2: C_REG, a6: C_REG}, + {i: 21, as: ASUB, a1: C_LCON, a6: C_REG}, + {i: 12, as: ASUB, a1: C_LOREG, a6: C_REG}, + {i: 12, as: ASUB, a1: C_LAUTO, a6: C_REG}, + {i: 4, as: AMULHD, a1: C_REG, a6: C_REG}, + {i: 4, as: AMULHD, a1: C_REG, a2: C_REG, a6: C_REG}, + {i: 2, as: ADIVW, a1: C_REG, a2: C_REG, a6: C_REG}, + {i: 2, as: ADIVW, a1: C_REG, a6: C_REG}, + {i: 10, as: ASUB, a1: C_REG, a2: C_REG, a6: C_REG}, + {i: 10, as: ASUB, a1: C_REG, a6: C_REG}, + {i: 47, as: ANEG, a1: C_REG, a6: C_REG}, + {i: 47, as: ANEG, a6: C_REG}, // integer logical - Optab{i: 6, as: AAND, a1: C_REG, a2: C_REG, a6: C_REG}, - Optab{i: 6, as: AAND, a1: C_REG, a6: C_REG}, - Optab{i: 23, as: AAND, a1: C_LCON, a6: C_REG}, - Optab{i: 12, as: AAND, a1: C_LOREG, a6: C_REG}, - Optab{i: 12, as: AAND, a1: C_LAUTO, a6: C_REG}, - Optab{i: 6, as: AANDW, a1: C_REG, a2: C_REG, a6: C_REG}, - Optab{i: 6, as: AANDW, a1: C_REG, a6: C_REG}, - Optab{i: 24, as: AANDW, a1: C_LCON, a6: C_REG}, - Optab{i: 12, as: AANDW, a1: C_LOREG, a6: C_REG}, - Optab{i: 12, as: AANDW, a1: C_LAUTO, a6: C_REG}, - Optab{i: 7, as: ASLD, a1: C_REG, a6: C_REG}, - Optab{i: 7, as: ASLD, a1: C_REG, a2: C_REG, a6: C_REG}, - Optab{i: 7, as: ASLD, a1: C_SCON, a2: C_REG, a6: C_REG}, - Optab{i: 7, as: ASLD, a1: C_SCON, a6: C_REG}, - Optab{i: 13, as: ARNSBG, a1: C_SCON, a3: C_SCON, a4: C_SCON, a5: C_REG, a6: C_REG}, + {i: 6, as: AAND, a1: C_REG, a2: C_REG, a6: C_REG}, + {i: 6, as: AAND, a1: C_REG, a6: C_REG}, + {i: 23, as: AAND, a1: C_LCON, a6: C_REG}, + {i: 12, as: AAND, a1: C_LOREG, a6: C_REG}, + {i: 12, as: AAND, a1: C_LAUTO, a6: C_REG}, + {i: 6, as: AANDW, a1: C_REG, a2: C_REG, a6: C_REG}, + {i: 6, as: AANDW, a1: C_REG, a6: C_REG}, + {i: 24, as: AANDW, a1: C_LCON, a6: C_REG}, + {i: 12, as: AANDW, a1: C_LOREG, a6: C_REG}, + {i: 12, as: AANDW, a1: C_LAUTO, a6: C_REG}, + {i: 7, as: ASLD, a1: C_REG, a6: C_REG}, + {i: 7, as: ASLD, a1: C_REG, a2: C_REG, a6: C_REG}, + {i: 7, as: ASLD, a1: C_SCON, a2: C_REG, a6: C_REG}, + {i: 7, as: ASLD, a1: C_SCON, a6: C_REG}, + {i: 13, as: ARNSBG, a1: C_SCON, a3: C_SCON, a4: C_SCON, a5: C_REG, a6: C_REG}, // compare and swap - Optab{i: 79, as: ACSG, a1: C_REG, a2: C_REG, a6: C_SOREG}, + {i: 79, as: ACSG, a1: C_REG, a2: C_REG, a6: C_SOREG}, // floating point - Optab{i: 32, as: AFADD, a1: C_FREG, a6: C_FREG}, - Optab{i: 33, as: AFABS, a1: C_FREG, a6: C_FREG}, - Optab{i: 33, as: AFABS, a6: C_FREG}, - Optab{i: 34, as: AFMADD, a1: C_FREG, a2: C_FREG, a6: C_FREG}, - Optab{i: 32, as: AFMUL, a1: C_FREG, a6: C_FREG}, - Optab{i: 36, as: AFMOVD, a1: C_LAUTO, a6: C_FREG}, - Optab{i: 36, as: AFMOVD, a1: C_LOREG, a6: C_FREG}, - Optab{i: 75, as: AFMOVD, a1: C_ADDR, a6: C_FREG}, - Optab{i: 35, as: AFMOVD, a1: C_FREG, a6: C_LAUTO}, - Optab{i: 35, as: AFMOVD, a1: C_FREG, a6: C_LOREG}, - Optab{i: 74, as: AFMOVD, a1: C_FREG, a6: C_ADDR}, - Optab{i: 67, as: AFMOVD, a1: C_ZCON, a6: C_FREG}, - Optab{i: 81, as: ALDGR, a1: C_REG, a6: C_FREG}, - Optab{i: 81, as: ALGDR, a1: C_FREG, a6: C_REG}, - Optab{i: 82, as: ACEFBRA, a1: C_REG, a6: C_FREG}, - Optab{i: 83, as: ACFEBRA, a1: C_FREG, a6: C_REG}, - Optab{i: 48, as: AFIEBR, a1: C_SCON, a2: C_FREG, a6: C_FREG}, - Optab{i: 49, as: ACPSDR, a1: C_FREG, a2: C_FREG, a6: C_FREG}, - Optab{i: 50, as: ALTDBR, a1: C_FREG, a6: C_FREG}, - Optab{i: 51, as: ATCDB, a1: C_FREG, a6: C_SCON}, + {i: 32, as: AFADD, a1: C_FREG, a6: C_FREG}, + {i: 33, as: AFABS, a1: C_FREG, a6: C_FREG}, + {i: 33, as: AFABS, a6: C_FREG}, + {i: 34, as: AFMADD, a1: C_FREG, a2: C_FREG, a6: C_FREG}, + {i: 32, as: AFMUL, a1: C_FREG, a6: C_FREG}, + {i: 36, as: AFMOVD, a1: C_LAUTO, a6: C_FREG}, + {i: 36, as: AFMOVD, a1: C_LOREG, a6: C_FREG}, + {i: 75, as: AFMOVD, a1: C_ADDR, a6: C_FREG}, + {i: 35, as: AFMOVD, a1: C_FREG, a6: C_LAUTO}, + {i: 35, as: AFMOVD, a1: C_FREG, a6: C_LOREG}, + {i: 74, as: AFMOVD, a1: C_FREG, a6: C_ADDR}, + {i: 67, as: AFMOVD, a1: C_ZCON, a6: C_FREG}, + {i: 81, as: ALDGR, a1: C_REG, a6: C_FREG}, + {i: 81, as: ALGDR, a1: C_FREG, a6: C_REG}, + {i: 82, as: ACEFBRA, a1: C_REG, a6: C_FREG}, + {i: 83, as: ACFEBRA, a1: C_FREG, a6: C_REG}, + {i: 48, as: AFIEBR, a1: C_SCON, a2: C_FREG, a6: C_FREG}, + {i: 49, as: ACPSDR, a1: C_FREG, a2: C_FREG, a6: C_FREG}, + {i: 50, as: ALTDBR, a1: C_FREG, a6: C_FREG}, + {i: 51, as: ATCDB, a1: C_FREG, a6: C_SCON}, // load symbol address (plus offset) - Optab{i: 19, as: AMOVD, a1: C_SYMADDR, a6: C_REG}, - Optab{i: 93, as: AMOVD, a1: C_GOTADDR, a6: C_REG}, - Optab{i: 94, as: AMOVD, a1: C_TLS_LE, a6: C_REG}, - Optab{i: 95, as: AMOVD, a1: C_TLS_IE, a6: C_REG}, + {i: 19, as: AMOVD, a1: C_SYMADDR, a6: C_REG}, + {i: 93, as: AMOVD, a1: C_GOTADDR, a6: C_REG}, + {i: 94, as: AMOVD, a1: C_TLS_LE, a6: C_REG}, + {i: 95, as: AMOVD, a1: C_TLS_IE, a6: C_REG}, // system call - Optab{i: 5, as: ASYSCALL}, - Optab{i: 77, as: ASYSCALL, a1: C_SCON}, + {i: 5, as: ASYSCALL}, + {i: 77, as: ASYSCALL, a1: C_SCON}, // branch - Optab{i: 16, as: ABEQ, a6: C_SBRA}, - Optab{i: 11, as: ABR, a6: C_LBRA}, - Optab{i: 16, as: ABC, a1: C_SCON, a2: C_REG, a6: C_LBRA}, - Optab{i: 18, as: ABR, a6: C_REG}, - Optab{i: 18, as: ABR, a1: C_REG, a6: C_REG}, - Optab{i: 15, as: ABR, a6: C_ZOREG}, - Optab{i: 15, as: ABC, a6: C_ZOREG}, - Optab{i: 89, as: ACMPBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA}, - Optab{i: 90, as: ACMPBEQ, a1: C_REG, a3: C_ADDCON, a6: C_SBRA}, - Optab{i: 90, as: ACMPBEQ, a1: C_REG, a3: C_SCON, a6: C_SBRA}, - Optab{i: 89, as: ACMPUBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA}, - Optab{i: 90, as: ACMPUBEQ, a1: C_REG, a3: C_ANDCON, a6: C_SBRA}, + {i: 16, as: ABEQ, a6: C_SBRA}, + {i: 11, as: ABR, a6: C_LBRA}, + {i: 16, as: ABC, a1: C_SCON, a2: C_REG, a6: C_LBRA}, + {i: 18, as: ABR, a6: C_REG}, + {i: 18, as: ABR, a1: C_REG, a6: C_REG}, + {i: 15, as: ABR, a6: C_ZOREG}, + {i: 15, as: ABC, a6: C_ZOREG}, + {i: 89, as: ACMPBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA}, + {i: 90, as: ACMPBEQ, a1: C_REG, a3: C_ADDCON, a6: C_SBRA}, + {i: 90, as: ACMPBEQ, a1: C_REG, a3: C_SCON, a6: C_SBRA}, + {i: 89, as: ACMPUBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA}, + {i: 90, as: ACMPUBEQ, a1: C_REG, a3: C_ANDCON, a6: C_SBRA}, // move on condition - Optab{i: 17, as: AMOVDEQ, a1: C_REG, a6: C_REG}, + {i: 17, as: AMOVDEQ, a1: C_REG, a6: C_REG}, // find leftmost one - Optab{i: 8, as: AFLOGR, a1: C_REG, a6: C_REG}, + {i: 8, as: AFLOGR, a1: C_REG, a6: C_REG}, // population count - Optab{i: 9, as: APOPCNT, a1: C_REG, a6: C_REG}, + {i: 9, as: APOPCNT, a1: C_REG, a6: C_REG}, // compare - Optab{i: 70, as: ACMP, a1: C_REG, a6: C_REG}, - Optab{i: 71, as: ACMP, a1: C_REG, a6: C_LCON}, - Optab{i: 70, as: ACMPU, a1: C_REG, a6: C_REG}, - Optab{i: 71, as: ACMPU, a1: C_REG, a6: C_LCON}, - Optab{i: 70, as: AFCMPO, a1: C_FREG, a6: C_FREG}, - Optab{i: 70, as: AFCMPO, a1: C_FREG, a2: C_REG, a6: C_FREG}, + {i: 70, as: ACMP, a1: C_REG, a6: C_REG}, + {i: 71, as: ACMP, a1: C_REG, a6: C_LCON}, + {i: 70, as: ACMPU, a1: C_REG, a6: C_REG}, + {i: 71, as: ACMPU, a1: C_REG, a6: C_LCON}, + {i: 70, as: AFCMPO, a1: C_FREG, a6: C_FREG}, + {i: 70, as: AFCMPO, a1: C_FREG, a2: C_REG, a6: C_FREG}, // test under mask - Optab{i: 91, as: ATMHH, a1: C_REG, a6: C_ANDCON}, + {i: 91, as: ATMHH, a1: C_REG, a6: C_ANDCON}, // insert program mask - Optab{i: 92, as: AIPM, a1: C_REG}, + {i: 92, as: AIPM, a1: C_REG}, // 32-bit access registers - Optab{i: 68, as: AMOVW, a1: C_AREG, a6: C_REG}, - Optab{i: 68, as: AMOVWZ, a1: C_AREG, a6: C_REG}, - Optab{i: 69, as: AMOVW, a1: C_REG, a6: C_AREG}, - Optab{i: 69, as: AMOVWZ, a1: C_REG, a6: C_AREG}, + {i: 68, as: AMOVW, a1: C_AREG, a6: C_REG}, + {i: 68, as: AMOVWZ, a1: C_AREG, a6: C_REG}, + {i: 69, as: AMOVW, a1: C_REG, a6: C_AREG}, + {i: 69, as: AMOVWZ, a1: C_REG, a6: C_AREG}, // macros - Optab{i: 96, as: ACLEAR, a1: C_LCON, a6: C_LOREG}, - Optab{i: 96, as: ACLEAR, a1: C_LCON, a6: C_LAUTO}, + {i: 96, as: ACLEAR, a1: C_LCON, a6: C_LOREG}, + {i: 96, as: ACLEAR, a1: C_LCON, a6: C_LAUTO}, // load/store multiple - Optab{i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LOREG}, - Optab{i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LAUTO}, - Optab{i: 98, as: ALMG, a1: C_LOREG, a2: C_REG, a6: C_REG}, - Optab{i: 98, as: ALMG, a1: C_LAUTO, a2: C_REG, a6: C_REG}, + {i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LOREG}, + {i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LAUTO}, + {i: 98, as: ALMG, a1: C_LOREG, a2: C_REG, a6: C_REG}, + {i: 98, as: ALMG, a1: C_LAUTO, a2: C_REG, a6: C_REG}, // bytes - Optab{i: 40, as: ABYTE, a1: C_SCON}, - Optab{i: 40, as: AWORD, a1: C_LCON}, - Optab{i: 31, as: ADWORD, a1: C_LCON}, - Optab{i: 31, as: ADWORD, a1: C_DCON}, + {i: 40, as: ABYTE, a1: C_SCON}, + {i: 40, as: AWORD, a1: C_LCON}, + {i: 31, as: ADWORD, a1: C_LCON}, + {i: 31, as: ADWORD, a1: C_DCON}, // fast synchronization - Optab{i: 80, as: ASYNC}, + {i: 80, as: ASYNC}, // store clock - Optab{i: 88, as: ASTCK, a6: C_SAUTO}, - Optab{i: 88, as: ASTCK, a6: C_SOREG}, + {i: 88, as: ASTCK, a6: C_SAUTO}, + {i: 88, as: ASTCK, a6: C_SOREG}, // storage and storage - Optab{i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LOREG}, - Optab{i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LAUTO}, - Optab{i: 84, as: AMVC, a1: C_SCON, a3: C_LAUTO, a6: C_LAUTO}, + {i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LOREG}, + {i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LAUTO}, + {i: 84, as: AMVC, a1: C_SCON, a3: C_LAUTO, a6: C_LAUTO}, // address - Optab{i: 85, as: ALARL, a1: C_LCON, a6: C_REG}, - Optab{i: 85, as: ALARL, a1: C_SYMADDR, a6: C_REG}, - Optab{i: 86, as: ALA, a1: C_SOREG, a6: C_REG}, - Optab{i: 86, as: ALA, a1: C_SAUTO, a6: C_REG}, - Optab{i: 87, as: AEXRL, a1: C_SYMADDR, a6: C_REG}, + {i: 85, as: ALARL, a1: C_LCON, a6: C_REG}, + {i: 85, as: ALARL, a1: C_SYMADDR, a6: C_REG}, + {i: 86, as: ALA, a1: C_SOREG, a6: C_REG}, + {i: 86, as: ALA, a1: C_SAUTO, a6: C_REG}, + {i: 87, as: AEXRL, a1: C_SYMADDR, a6: C_REG}, // undefined (deliberate illegal instruction) - Optab{i: 78, as: obj.AUNDEF}, + {i: 78, as: obj.AUNDEF}, // vector instructions // VRX store - Optab{i: 100, as: AVST, a1: C_VREG, a6: C_SOREG}, - Optab{i: 100, as: AVST, a1: C_VREG, a6: C_SAUTO}, - Optab{i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG}, - Optab{i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO}, + {i: 100, as: AVST, a1: C_VREG, a6: C_SOREG}, + {i: 100, as: AVST, a1: C_VREG, a6: C_SAUTO}, + {i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG}, + {i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO}, // VRX load - Optab{i: 101, as: AVL, a1: C_SOREG, a6: C_VREG}, - Optab{i: 101, as: AVL, a1: C_SAUTO, a6: C_VREG}, - Optab{i: 101, as: AVLEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG}, - Optab{i: 101, as: AVLEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG}, + {i: 101, as: AVL, a1: C_SOREG, a6: C_VREG}, + {i: 101, as: AVL, a1: C_SAUTO, a6: C_VREG}, + {i: 101, as: AVLEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG}, + {i: 101, as: AVLEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG}, // VRV scatter - Optab{i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG}, - Optab{i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO}, + {i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG}, + {i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO}, // VRV gather - Optab{i: 103, as: AVGEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG}, - Optab{i: 103, as: AVGEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG}, + {i: 103, as: AVGEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG}, + {i: 103, as: AVGEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG}, // VRS element shift/rotate and load gr to/from vr element - Optab{i: 104, as: AVESLG, a1: C_SCON, a2: C_VREG, a6: C_VREG}, - Optab{i: 104, as: AVESLG, a1: C_REG, a2: C_VREG, a6: C_VREG}, - Optab{i: 104, as: AVESLG, a1: C_SCON, a6: C_VREG}, - Optab{i: 104, as: AVESLG, a1: C_REG, a6: C_VREG}, - Optab{i: 104, as: AVLGVG, a1: C_SCON, a2: C_VREG, a6: C_REG}, - Optab{i: 104, as: AVLGVG, a1: C_REG, a2: C_VREG, a6: C_REG}, - Optab{i: 104, as: AVLVGG, a1: C_SCON, a2: C_REG, a6: C_VREG}, - Optab{i: 104, as: AVLVGG, a1: C_REG, a2: C_REG, a6: C_VREG}, + {i: 104, as: AVESLG, a1: C_SCON, a2: C_VREG, a6: C_VREG}, + {i: 104, as: AVESLG, a1: C_REG, a2: C_VREG, a6: C_VREG}, + {i: 104, as: AVESLG, a1: C_SCON, a6: C_VREG}, + {i: 104, as: AVESLG, a1: C_REG, a6: C_VREG}, + {i: 104, as: AVLGVG, a1: C_SCON, a2: C_VREG, a6: C_REG}, + {i: 104, as: AVLGVG, a1: C_REG, a2: C_VREG, a6: C_REG}, + {i: 104, as: AVLVGG, a1: C_SCON, a2: C_REG, a6: C_VREG}, + {i: 104, as: AVLVGG, a1: C_REG, a2: C_REG, a6: C_VREG}, // VRS store multiple - Optab{i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SOREG}, - Optab{i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SAUTO}, + {i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SOREG}, + {i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SAUTO}, // VRS load multiple - Optab{i: 106, as: AVLM, a1: C_SOREG, a2: C_VREG, a6: C_VREG}, - Optab{i: 106, as: AVLM, a1: C_SAUTO, a2: C_VREG, a6: C_VREG}, + {i: 106, as: AVLM, a1: C_SOREG, a2: C_VREG, a6: C_VREG}, + {i: 106, as: AVLM, a1: C_SAUTO, a2: C_VREG, a6: C_VREG}, // VRS store with length - Optab{i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SOREG}, - Optab{i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SAUTO}, + {i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SOREG}, + {i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SAUTO}, // VRS load with length - Optab{i: 108, as: AVLL, a1: C_REG, a3: C_SOREG, a6: C_VREG}, - Optab{i: 108, as: AVLL, a1: C_REG, a3: C_SAUTO, a6: C_VREG}, + {i: 108, as: AVLL, a1: C_REG, a3: C_SOREG, a6: C_VREG}, + {i: 108, as: AVLL, a1: C_REG, a3: C_SAUTO, a6: C_VREG}, // VRI-a - Optab{i: 109, as: AVGBM, a1: C_ANDCON, a6: C_VREG}, - Optab{i: 109, as: AVZERO, a6: C_VREG}, - Optab{i: 109, as: AVREPIG, a1: C_ADDCON, a6: C_VREG}, - Optab{i: 109, as: AVREPIG, a1: C_SCON, a6: C_VREG}, - Optab{i: 109, as: AVLEIG, a1: C_SCON, a3: C_ADDCON, a6: C_VREG}, - Optab{i: 109, as: AVLEIG, a1: C_SCON, a3: C_SCON, a6: C_VREG}, + {i: 109, as: AVGBM, a1: C_ANDCON, a6: C_VREG}, + {i: 109, as: AVZERO, a6: C_VREG}, + {i: 109, as: AVREPIG, a1: C_ADDCON, a6: C_VREG}, + {i: 109, as: AVREPIG, a1: C_SCON, a6: C_VREG}, + {i: 109, as: AVLEIG, a1: C_SCON, a3: C_ADDCON, a6: C_VREG}, + {i: 109, as: AVLEIG, a1: C_SCON, a3: C_SCON, a6: C_VREG}, // VRI-b generate mask - Optab{i: 110, as: AVGMG, a1: C_SCON, a3: C_SCON, a6: C_VREG}, + {i: 110, as: AVGMG, a1: C_SCON, a3: C_SCON, a6: C_VREG}, // VRI-c replicate - Optab{i: 111, as: AVREPG, a1: C_UCON, a2: C_VREG, a6: C_VREG}, + {i: 111, as: AVREPG, a1: C_UCON, a2: C_VREG, a6: C_VREG}, // VRI-d element rotate and insert under mask and // shift left double by byte - Optab{i: 112, as: AVERIMG, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG}, - Optab{i: 112, as: AVSLDB, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG}, + {i: 112, as: AVERIMG, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG}, + {i: 112, as: AVSLDB, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG}, // VRI-d fp test data class immediate - Optab{i: 113, as: AVFTCIDB, a1: C_SCON, a2: C_VREG, a6: C_VREG}, + {i: 113, as: AVFTCIDB, a1: C_SCON, a2: C_VREG, a6: C_VREG}, // VRR-a load reg - Optab{i: 114, as: AVLR, a1: C_VREG, a6: C_VREG}, + {i: 114, as: AVLR, a1: C_VREG, a6: C_VREG}, // VRR-a compare - Optab{i: 115, as: AVECG, a1: C_VREG, a6: C_VREG}, + {i: 115, as: AVECG, a1: C_VREG, a6: C_VREG}, // VRR-b - Optab{i: 117, as: AVCEQG, a1: C_VREG, a2: C_VREG, a6: C_VREG}, - Optab{i: 117, as: AVFAEF, a1: C_VREG, a2: C_VREG, a6: C_VREG}, - Optab{i: 117, as: AVPKSG, a1: C_VREG, a2: C_VREG, a6: C_VREG}, + {i: 117, as: AVCEQG, a1: C_VREG, a2: C_VREG, a6: C_VREG}, + {i: 117, as: AVFAEF, a1: C_VREG, a2: C_VREG, a6: C_VREG}, + {i: 117, as: AVPKSG, a1: C_VREG, a2: C_VREG, a6: C_VREG}, // VRR-c - Optab{i: 118, as: AVAQ, a1: C_VREG, a2: C_VREG, a6: C_VREG}, - Optab{i: 118, as: AVAQ, a1: C_VREG, a6: C_VREG}, - Optab{i: 118, as: AVNOT, a1: C_VREG, a6: C_VREG}, - Optab{i: 123, as: AVPDI, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG}, + {i: 118, as: AVAQ, a1: C_VREG, a2: C_VREG, a6: C_VREG}, + {i: 118, as: AVAQ, a1: C_VREG, a6: C_VREG}, + {i: 118, as: AVNOT, a1: C_VREG, a6: C_VREG}, + {i: 123, as: AVPDI, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG}, // VRR-c shifts - Optab{i: 119, as: AVERLLVG, a1: C_VREG, a2: C_VREG, a6: C_VREG}, - Optab{i: 119, as: AVERLLVG, a1: C_VREG, a6: C_VREG}, + {i: 119, as: AVERLLVG, a1: C_VREG, a2: C_VREG, a6: C_VREG}, + {i: 119, as: AVERLLVG, a1: C_VREG, a6: C_VREG}, // VRR-d - Optab{i: 120, as: AVACQ, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG}, + {i: 120, as: AVACQ, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG}, // VRR-e - Optab{i: 121, as: AVSEL, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG}, + {i: 121, as: AVSEL, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG}, // VRR-f - Optab{i: 122, as: AVLVGP, a1: C_REG, a2: C_REG, a6: C_VREG}, + {i: 122, as: AVLVGP, a1: C_REG, a2: C_REG, a6: C_VREG}, } var oprange [ALAST & obj.AMask][]Optab diff --git a/src/cmd/link/internal/ld/dwarf_test.go b/src/cmd/link/internal/ld/dwarf_test.go index f6ed8d3401..190a54c4c3 100644 --- a/src/cmd/link/internal/ld/dwarf_test.go +++ b/src/cmd/link/internal/ld/dwarf_test.go @@ -164,9 +164,9 @@ func main() { }` want := map[string]map[string]bool{ - "main.Foo": map[string]bool{"v": false}, - "main.Bar": map[string]bool{"Foo": true, "name": false}, - "main.Baz": map[string]bool{"Foo": true, "name": false}, + "main.Foo": {"v": false}, + "main.Bar": {"Foo": true, "name": false}, + "main.Baz": {"Foo": true, "name": false}, } dir, err := ioutil.TempDir("", "TestEmbeddedStructMarker") diff --git a/src/cmd/link/internal/wasm/asm.go b/src/cmd/link/internal/wasm/asm.go index 8ab58b200f..c80e81e5b3 100644 --- a/src/cmd/link/internal/wasm/asm.go +++ b/src/cmd/link/internal/wasm/asm.go @@ -54,21 +54,21 @@ type wasmFuncType struct { } var wasmFuncTypes = map[string]*wasmFuncType{ - "_rt0_wasm_js": &wasmFuncType{Params: []byte{}}, // - "wasm_export_run": &wasmFuncType{Params: []byte{I32, I32}}, // argc, argv - "wasm_export_resume": &wasmFuncType{Params: []byte{}}, // - "wasm_export_getsp": &wasmFuncType{Results: []byte{I32}}, // sp - "wasm_pc_f_loop": &wasmFuncType{Params: []byte{}}, // - "runtime.wasmMove": &wasmFuncType{Params: []byte{I32, I32, I32}}, // dst, src, len - "runtime.wasmZero": &wasmFuncType{Params: []byte{I32, I32}}, // ptr, len - "runtime.wasmDiv": &wasmFuncType{Params: []byte{I64, I64}, Results: []byte{I64}}, // x, y -> x/y - "runtime.wasmTruncS": &wasmFuncType{Params: []byte{F64}, Results: []byte{I64}}, // x -> int(x) - "runtime.wasmTruncU": &wasmFuncType{Params: []byte{F64}, Results: []byte{I64}}, // x -> uint(x) - "runtime.gcWriteBarrier": &wasmFuncType{Params: []byte{I64, I64}}, // ptr, val - "cmpbody": &wasmFuncType{Params: []byte{I64, I64, I64, I64}, Results: []byte{I64}}, // a, alen, b, blen -> -1/0/1 - "memeqbody": &wasmFuncType{Params: []byte{I64, I64, I64}, Results: []byte{I64}}, // a, b, len -> 0/1 - "memcmp": &wasmFuncType{Params: []byte{I32, I32, I32}, Results: []byte{I32}}, // a, b, len -> <0/0/>0 - "memchr": &wasmFuncType{Params: []byte{I32, I32, I32}, Results: []byte{I32}}, // s, c, len -> index + "_rt0_wasm_js": {Params: []byte{}}, // + "wasm_export_run": {Params: []byte{I32, I32}}, // argc, argv + "wasm_export_resume": {Params: []byte{}}, // + "wasm_export_getsp": {Results: []byte{I32}}, // sp + "wasm_pc_f_loop": {Params: []byte{}}, // + "runtime.wasmMove": {Params: []byte{I32, I32, I32}}, // dst, src, len + "runtime.wasmZero": {Params: []byte{I32, I32}}, // ptr, len + "runtime.wasmDiv": {Params: []byte{I64, I64}, Results: []byte{I64}}, // x, y -> x/y + "runtime.wasmTruncS": {Params: []byte{F64}, Results: []byte{I64}}, // x -> int(x) + "runtime.wasmTruncU": {Params: []byte{F64}, Results: []byte{I64}}, // x -> uint(x) + "runtime.gcWriteBarrier": {Params: []byte{I64, I64}}, // ptr, val + "cmpbody": {Params: []byte{I64, I64, I64, I64}, Results: []byte{I64}}, // a, alen, b, blen -> -1/0/1 + "memeqbody": {Params: []byte{I64, I64, I64}, Results: []byte{I64}}, // a, b, len -> 0/1 + "memcmp": {Params: []byte{I32, I32, I32}, Results: []byte{I32}}, // a, b, len -> <0/0/>0 + "memchr": {Params: []byte{I32, I32, I32}, Results: []byte{I32}}, // s, c, len -> index } func assignAddress(ctxt *ld.Link, sect *sym.Section, n int, s *sym.Symbol, va uint64, isTramp bool) (*sym.Section, int, uint64) { @@ -105,12 +105,12 @@ func asmb2(ctxt *ld.Link) { // For normal Go functions the return value is // 0 if the function returned normally or // 1 if the stack needs to be unwound. - &wasmFuncType{Results: []byte{I32}}, + {Results: []byte{I32}}, } // collect host imports (functions that get imported from the WebAssembly host, usually JavaScript) hostImports := []*wasmFunc{ - &wasmFunc{ + { Name: "debug", Type: lookupType(&wasmFuncType{Params: []byte{I32}}, &types), }, diff --git a/src/cmd/trace/pprof.go b/src/cmd/trace/pprof.go index 3389d2799b..a31d71b013 100644 --- a/src/cmd/trace/pprof.go +++ b/src/cmd/trace/pprof.go @@ -358,7 +358,7 @@ func buildProfile(prof map[uint64]Record) *profile.Profile { ID: uint64(len(p.Location) + 1), Address: frame.PC, Line: []profile.Line{ - profile.Line{ + { Function: fn, Line: int64(frame.Line), }, |