3 files changed, 24 insertions, 0 deletions
diff --git a/src/cmd/internal/obj/s390x/a.out.go b/src/cmd/internal/obj/s390x/a.out.go
index 3eed4624b1..1a64370efa 100644
--- a/src/cmd/internal/obj/s390x/a.out.go
+++ b/src/cmd/internal/obj/s390x/a.out.go
@@ -444,6 +444,7 @@ const (
 	// storage-and-storage
 	AMVC
 	AMVCIN
+	AMVCLE
 	ACLC
 	AXC
 	AOC
diff --git a/src/cmd/internal/obj/s390x/anames.go b/src/cmd/internal/obj/s390x/anames.go
index ae86d2092b..c0a0c401fa 100644
--- a/src/cmd/internal/obj/s390x/anames.go
+++ b/src/cmd/internal/obj/s390x/anames.go
@@ -181,6 +181,7 @@ var Anames = []string{
 	"CMPUBNE",
 	"MVC",
 	"MVCIN",
+	"MVCLE",
 	"CLC",
 	"XC",
 	"OC",
diff --git a/src/cmd/internal/obj/s390x/asmz.go b/src/cmd/internal/obj/s390x/asmz.go
index 6511549eeb..72d92abbaf 100644
--- a/src/cmd/internal/obj/s390x/asmz.go
+++ b/src/cmd/internal/obj/s390x/asmz.go
@@ -449,6 +449,10 @@ var optab = []Optab{
 
 	// VRR-f
 	{i: 122, as: AVLVGP, a1: C_REG, a2: C_REG, a6: C_VREG},
+
+	// MVC storage and storage
+	{i: 127, as: AMVCLE, a1: C_LOREG, a2: C_REG, a6: C_REG},
+	{i: 127, as: AMVCLE, a1: C_SCON, a2: C_REG, a6: C_REG},
 }
 
 var oprange [ALAST & obj.AMask][]Optab
@@ -4453,6 +4457,24 @@ func (c *ctxtz) asmout(p *obj.Prog, asm *[]byte) {
 			}
 		}
 		zRRF(opcode, uint32(p.Reg), 0, uint32(p.From.Reg), uint32(p.To.Reg), asm)
+
+	case 127:
+		// NOTE: Mapping MVCLE operands is as follows:
+		// Instruction Format: MVCLE R1,R3,D2(B2)
+		// R1 - prog.To (for Destination)
+		// R3 - prog.Reg (for Source)
+		// B2 - prog.From (for Padding Byte)
+		d2 := c.regoff(&p.From)
+		if p.To.Reg&1 != 0 {
+			c.ctxt.Diag("output argument must be even register in %v", p)
+		}
+		if p.Reg&1 != 0 {
+			c.ctxt.Diag("input argument must be an even register in %v", p)
+		}
+		if (p.From.Reg == p.To.Reg) || (p.From.Reg == p.Reg) {
+			c.ctxt.Diag("padding byte register cannot be same as input or output register %v", p)
+		}
+		zRS(op_MVCLE, uint32(p.To.Reg), uint32(p.Reg), uint32(p.From.Reg), uint32(d2), asm)
 	}
 }