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-rw-r--r--src/cmd/internal/obj/arm/5.out.go120
-rw-r--r--src/cmd/internal/obj/arm/asm5.go7
-rw-r--r--src/cmd/internal/obj/objfile.go96
-rw-r--r--src/cmd/internal/obj/ppc64/9.out.go102
-rw-r--r--src/cmd/internal/obj/ppc64/asm9.go1
-rw-r--r--src/cmd/internal/obj/x86/6.out.go61
-rw-r--r--src/cmd/internal/obj/x86/asm6.go64
7 files changed, 336 insertions, 115 deletions
diff --git a/src/cmd/internal/obj/arm/5.out.go b/src/cmd/internal/obj/arm/5.out.go
index 424dd3d58e..d187367e46 100644
--- a/src/cmd/internal/obj/arm/5.out.go
+++ b/src/cmd/internal/obj/arm/5.out.go
@@ -44,7 +44,7 @@ const (
)
const (
- REG_R0 = obj.RBaseARM + iota
+ REG_R0 = obj.RBaseARM + iota // must be 16-aligned
REG_R1
REG_R2
REG_R3
@@ -60,7 +60,8 @@ const (
REG_R13
REG_R14
REG_R15
- REG_F0
+
+ REG_F0 // must be 16-aligned
REG_F1
REG_F2
REG_F3
@@ -76,28 +77,37 @@ const (
REG_F13
REG_F14
REG_F15
- REG_FPSR
+
+ REG_FPSR // must be 2-aligned
REG_FPCR
- REG_CPSR
+
+ REG_CPSR // must be 2-aligned
REG_SPSR
+
MAXREG
- REGRET = REG_R0
- REGEXT = REG_R10
- REGG = REGEXT - 0
- REGM = REGEXT - 1
+ REGRET = REG_R0
+ /* compiler allocates R1 up as temps */
+ /* compiler allocates register variables R3 up */
+ /* compiler allocates external registers R10 down */
+ REGEXT = REG_R10
+ /* these two registers are declared in runtime.h */
+ REGG = REGEXT - 0
+ REGM = REGEXT - 1
+
REGCTXT = REG_R7
REGTMP = REG_R11
REGSP = REG_R13
REGLINK = REG_R14
REGPC = REG_R15
- NFREG = 16
+
+ NFREG = 16
+ /* compiler allocates register variables F0 up */
+ /* compiler allocates external registers F7 down */
FREGRET = REG_F0
FREGEXT = REG_F7
FREGTMP = REG_F15
)
-/* compiler allocates register variables F0 up */
-/* compiler allocates external registers F7 down */
const (
C_NONE = iota
C_REG
@@ -108,37 +118,46 @@ const (
C_FREG
C_PSR
C_FCR
- C_RCON
- C_NCON
- C_SCON
+
+ C_RCON /* 0xff rotated */
+ C_NCON /* ~RCON */
+ C_SCON /* 0xffff */
C_LCON
C_LCONADDR
C_ZFCON
C_SFCON
C_LFCON
+
C_RACON
C_LACON
+
C_SBRA
C_LBRA
- C_HAUTO
- C_FAUTO
- C_HFAUTO
- C_SAUTO
+
+ C_HAUTO /* halfword insn offset (-0xff to 0xff) */
+ C_FAUTO /* float insn offset (0 to 0x3fc, word aligned) */
+ C_HFAUTO /* both H and F */
+ C_SAUTO /* -0xfff to 0xfff */
C_LAUTO
+
C_HOREG
C_FOREG
C_HFOREG
C_SOREG
C_ROREG
- C_SROREG
+ C_SROREG /* both nil and R */
C_LOREG
+
C_PC
C_SP
C_HREG
- C_ADDR
+
+ C_ADDR /* reference to relocatable address */
C_TEXTSIZE
+
C_GOK
- C_NCLASS
+
+ C_NCLASS /* must be the last */
)
const (
@@ -156,7 +175,13 @@ const (
ACMN
AORR
ABIC
+
AMVN
+
+ /*
+ * Do not reorder or fragment the conditional branch
+ * opcodes, or the predication code will break
+ */
ABEQ
ABNE
ABCS
@@ -173,6 +198,7 @@ const (
ABLT
ABGT
ABLE
+
AMOVWD
AMOVWF
AMOVDW
@@ -181,6 +207,7 @@ const (
AMOVDF
AMOVF
AMOVD
+
ACMPF
ACMPD
AADDF
@@ -195,6 +222,7 @@ const (
ASQRTD
AABSF
AABSD
+
ASRL
ASRA
ASLL
@@ -204,6 +232,7 @@ const (
ADIV
AMOD
AMODU
+
AMOVB
AMOVBS
AMOVBU
@@ -214,46 +243,64 @@ const (
AMOVM
ASWPBU
ASWPW
+
ARFE
ASWI
AMULA
+
AWORD
ABCASE
ACASE
+
AMULL
AMULAL
AMULLU
AMULALU
+
ABX
ABXRET
ADWORD
+
ALDREX
ASTREX
ALDREXD
ASTREXD
+
APLD
+
ACLZ
+
AMULWT
AMULWB
AMULAWT
AMULAWB
+
ADATABUNDLE
ADATABUNDLEEND
- AMRC
+
+ AMRC // MRC/MCR
+
ALAST
+
+ // aliases
AB = obj.AJMP
ABL = obj.ACALL
)
/* scond byte */
const (
- C_SCOND = (1 << 4) - 1
- C_SBIT = 1 << 4
- C_PBIT = 1 << 5
- C_WBIT = 1 << 6
- C_FBIT = 1 << 7
- C_UBIT = 1 << 7
- C_SCOND_XOR = 14
+ C_SCOND = (1 << 4) - 1
+ C_SBIT = 1 << 4
+ C_PBIT = 1 << 5
+ C_WBIT = 1 << 6
+ C_FBIT = 1 << 7 /* psr flags-only */
+ C_UBIT = 1 << 7 /* up bit, unsigned bit */
+
+ // These constants are the ARM condition codes encodings,
+ // XORed with 14 so that C_SCOND_NONE has value 0,
+ // so that a zeroed Prog.scond means "always execute".
+ C_SCOND_XOR = 14
+
C_SCOND_EQ = 0 ^ C_SCOND_XOR
C_SCOND_NE = 1 ^ C_SCOND_XOR
C_SCOND_HS = 2 ^ C_SCOND_XOR
@@ -270,13 +317,10 @@ const (
C_SCOND_LE = 13 ^ C_SCOND_XOR
C_SCOND_NONE = 14 ^ C_SCOND_XOR
C_SCOND_NV = 15 ^ C_SCOND_XOR
- SHIFT_LL = 0 << 5
- SHIFT_LR = 1 << 5
- SHIFT_AR = 2 << 5
- SHIFT_RR = 3 << 5
-)
-/*
- * this is the ranlib header
- */
-var SYMDEF string
+ /* D_SHIFT type */
+ SHIFT_LL = 0 << 5
+ SHIFT_LR = 1 << 5
+ SHIFT_AR = 2 << 5
+ SHIFT_RR = 3 << 5
+)
diff --git a/src/cmd/internal/obj/arm/asm5.go b/src/cmd/internal/obj/arm/asm5.go
index 980bbebca6..b801bd7e41 100644
--- a/src/cmd/internal/obj/arm/asm5.go
+++ b/src/cmd/internal/obj/arm/asm5.go
@@ -350,8 +350,8 @@ func asmoutnacl(ctxt *obj.Link, origPC int32, p *obj.Prog, o *Optab, out []uint3
if out != nil {
out[0] = ((uint32(p.Scond)&C_SCOND)^C_SCOND_XOR)<<28 | 0x03c0013f | (uint32(p.To.Reg)&15)<<12 | (uint32(p.To.Reg)&15)<<16 // BIC $0xc000000f, Rx
if p.As == AB {
- out[1] = ((uint32(p.Scond)&C_SCOND)^C_SCOND_XOR)<<28 | 0x012fff10 | (uint32(p.To.Reg)&15)<<0 // BX Rx // ABL
- } else {
+ out[1] = ((uint32(p.Scond)&C_SCOND)^C_SCOND_XOR)<<28 | 0x012fff10 | (uint32(p.To.Reg)&15)<<0 // BX Rx
+ } else { // ABL
out[1] = ((uint32(p.Scond)&C_SCOND)^C_SCOND_XOR)<<28 | 0x012fff30 | (uint32(p.To.Reg)&15)<<0 // BLX Rx
}
}
@@ -473,7 +473,8 @@ func asmoutnacl(ctxt *obj.Link, origPC int32, p *obj.Prog, o *Optab, out []uint3
break
}
- if (p.To.Type == obj.TYPE_MEM && p.To.Reg != REG_R13 && p.To.Reg != REG_R9) || (p.From.Type == obj.TYPE_MEM && p.From.Reg != REG_R13 && p.From.Reg != REG_R9) { // MOVW Rx, X(Ry), y != 13 && y != 9 // MOVW X(Rx), Ry, x != 13 && x != 9
+ if (p.To.Type == obj.TYPE_MEM && p.To.Reg != REG_R13 && p.To.Reg != REG_R9) || // MOVW Rx, X(Ry), y != 13 && y != 9
+ (p.From.Type == obj.TYPE_MEM && p.From.Reg != REG_R13 && p.From.Reg != REG_R9) { // MOVW X(Rx), Ry, x != 13 && x != 9
var a *obj.Addr
if p.To.Type == obj.TYPE_MEM {
a = &p.To
diff --git a/src/cmd/internal/obj/objfile.go b/src/cmd/internal/obj/objfile.go
index ef17d721f7..e69e246e2c 100644
--- a/src/cmd/internal/obj/objfile.go
+++ b/src/cmd/internal/obj/objfile.go
@@ -2,6 +2,102 @@
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
+// Writing of Go object files.
+//
+// Originally, Go object files were Plan 9 object files, but no longer.
+// Now they are more like standard object files, in that each symbol is defined
+// by an associated memory image (bytes) and a list of relocations to apply
+// during linking. We do not (yet?) use a standard file format, however.
+// For now, the format is chosen to be as simple as possible to read and write.
+// It may change for reasons of efficiency, or we may even switch to a
+// standard file format if there are compelling benefits to doing so.
+// See golang.org/s/go13linker for more background.
+//
+// The file format is:
+//
+// - magic header: "\x00\x00go13ld"
+// - byte 1 - version number
+// - sequence of strings giving dependencies (imported packages)
+// - empty string (marks end of sequence)
+// - sequence of defined symbols
+// - byte 0xff (marks end of sequence)
+// - magic footer: "\xff\xffgo13ld"
+//
+// All integers are stored in a zigzag varint format.
+// See golang.org/s/go12symtab for a definition.
+//
+// Data blocks and strings are both stored as an integer
+// followed by that many bytes.
+//
+// A symbol reference is a string name followed by a version.
+// An empty name corresponds to a nil LSym* pointer.
+//
+// Each symbol is laid out as the following fields (taken from LSym*):
+//
+// - byte 0xfe (sanity check for synchronization)
+// - type [int]
+// - name [string]
+// - version [int]
+// - flags [int]
+// 1 dupok
+// - size [int]
+// - gotype [symbol reference]
+// - p [data block]
+// - nr [int]
+// - r [nr relocations, sorted by off]
+//
+// If type == STEXT, there are a few more fields:
+//
+// - args [int]
+// - locals [int]
+// - nosplit [int]
+// - flags [int]
+// 1 leaf
+// 2 C function
+// - nlocal [int]
+// - local [nlocal automatics]
+// - pcln [pcln table]
+//
+// Each relocation has the encoding:
+//
+// - off [int]
+// - siz [int]
+// - type [int]
+// - add [int]
+// - xadd [int]
+// - sym [symbol reference]
+// - xsym [symbol reference]
+//
+// Each local has the encoding:
+//
+// - asym [symbol reference]
+// - offset [int]
+// - type [int]
+// - gotype [symbol reference]
+//
+// The pcln table has the encoding:
+//
+// - pcsp [data block]
+// - pcfile [data block]
+// - pcline [data block]
+// - npcdata [int]
+// - pcdata [npcdata data blocks]
+// - nfuncdata [int]
+// - funcdata [nfuncdata symbol references]
+// - funcdatasym [nfuncdata ints]
+// - nfile [int]
+// - file [nfile symbol references]
+//
+// The file layout and meaning of type integers are architecture-independent.
+//
+// TODO(rsc): The file format is good for a first pass but needs work.
+// - There are SymID in the object file that should really just be strings.
+// - The actual symbol memory images are interlaced with the symbol
+// metadata. They should be separated, to reduce the I/O required to
+// load just the metadata.
+// - The symbol references should be shortened, either with a symbol
+// table or by using a simple backward index to an earlier mentioned symbol.
+
package obj
import (
diff --git a/src/cmd/internal/obj/ppc64/9.out.go b/src/cmd/internal/obj/ppc64/9.out.go
index d3d54fda79..90377ff07a 100644
--- a/src/cmd/internal/obj/ppc64/9.out.go
+++ b/src/cmd/internal/obj/ppc64/9.out.go
@@ -39,11 +39,10 @@ import "cmd/internal/obj"
const (
NSNAME = 8
NSYM = 50
- NREG = 32
- NFREG = 32
+ NREG = 32 /* number of general registers */
+ NFREG = 32 /* number of floating point registers */
)
-// avoid conflict with ucontext.h. sigh.
const (
REG_R0 = obj.RBasePPC64 + iota
REG_R1
@@ -77,6 +76,7 @@ const (
REG_R29
REG_R30
REG_R31
+
REG_F0 = obj.RBasePPC64 + 32 + iota - 32
REG_F1
REG_F2
@@ -109,8 +109,10 @@ const (
REG_F29
REG_F30
REG_F31
+
REG_SPECIAL = obj.RBasePPC64 + 64
- REG_CR0 = obj.RBasePPC64 + 64 + iota - 65
+
+ REG_CR0 = obj.RBasePPC64 + 64 + iota - 65
REG_CR1
REG_CR2
REG_CR3
@@ -118,37 +120,41 @@ const (
REG_CR5
REG_CR6
REG_CR7
+
REG_MSR = obj.RBasePPC64 + 72 + iota - 73
REG_FPSCR
REG_CR
- REG_SPR0 = obj.RBasePPC64 + 1024
- REG_DCR0 = obj.RBasePPC64 + 2048
- REG_XER = REG_SPR0 + 1
- REG_LR = REG_SPR0 + 8
- REG_CTR = REG_SPR0 + 9
- REGZERO = REG_R0
+
+ REG_SPR0 = obj.RBasePPC64 + 1024 // first of 1024 registers
+ REG_DCR0 = obj.RBasePPC64 + 2048 // first of 1024 registers
+
+ REG_XER = REG_SPR0 + 1
+ REG_LR = REG_SPR0 + 8
+ REG_CTR = REG_SPR0 + 9
+
+ REGZERO = REG_R0 /* set to zero */
REGSP = REG_R1
REGSB = REG_R2
REGRET = REG_R3
- REGARG = -1
- REGRT1 = REG_R3
- REGRT2 = REG_R4
- REGMIN = REG_R7
- REGCTXT = REG_R11
- REGTLS = REG_R13
+ REGARG = -1 /* -1 disables passing the first argument in register */
+ REGRT1 = REG_R3 /* reserved for runtime, duffzero and duffcopy */
+ REGRT2 = REG_R4 /* reserved for runtime, duffcopy */
+ REGMIN = REG_R7 /* register variables allocated from here to REGMAX */
+ REGCTXT = REG_R11 /* context for closures */
+ REGTLS = REG_R13 /* C ABI TLS base pointer */
REGMAX = REG_R27
- REGEXT = REG_R30
- REGG = REG_R30
- REGTMP = REG_R31
+ REGEXT = REG_R30 /* external registers allocated from here down */
+ REGG = REG_R30 /* G */
+ REGTMP = REG_R31 /* used by the linker */
FREGRET = REG_F0
- FREGMIN = REG_F17
- FREGMAX = REG_F26
- FREGEXT = REG_F26
- FREGCVI = REG_F27
- FREGZERO = REG_F28
- FREGHALF = REG_F29
- FREGONE = REG_F30
- FREGTWO = REG_F31
+ FREGMIN = REG_F17 /* first register variable */
+ FREGMAX = REG_F26 /* last register variable for 9g only */
+ FREGEXT = REG_F26 /* first external register */
+ FREGCVI = REG_F27 /* floating conversion constant */
+ FREGZERO = REG_F28 /* both float and double */
+ FREGHALF = REG_F29 /* double */
+ FREGONE = REG_F30 /* double */
+ FREGTWO = REG_F31 /* double */
)
/*
@@ -166,6 +172,7 @@ const (
)
const (
+ /* mark flags */
LABEL = 1 << 0
LEAF = 1 << 1
FLOAT = 1 << 2
@@ -183,19 +190,19 @@ const (
C_REG
C_FREG
C_CREG
- C_SPR
+ C_SPR /* special processor register */
C_ZCON
- C_SCON
- C_UCON
- C_ADDCON
- C_ANDCON
- C_LCON
- C_DCON
- C_SACON
+ C_SCON /* 16 bit signed */
+ C_UCON /* 32 bit signed, low 16 bits 0 */
+ C_ADDCON /* -0x8000 <= v < 0 */
+ C_ANDCON /* 0 < v <= 0xFFFF */
+ C_LCON /* other 32 */
+ C_DCON /* other 64 (could subdivide further) */
+ C_SACON /* $n(REG) where n <= int16 */
C_SECON
- C_LACON
+ C_LACON /* $n(REG) where int16 < n <= int32 */
C_LECON
- C_DACON
+ C_DACON /* $n(REG) where int32 < n */
C_SBRA
C_LBRA
C_SAUTO
@@ -214,7 +221,8 @@ const (
C_GOK
C_ADDR
C_TEXTSIZE
- C_NCLASS
+
+ C_NCLASS /* must be the last */
)
const (
@@ -414,6 +422,7 @@ const (
ASYNC
AXOR
AXORCC
+
ADCBF
ADCBI
ADCBST
@@ -430,9 +439,13 @@ const (
ATLBIEL
ATLBSYNC
ATW
+
ASYSCALL
AWORD
+
ARFCI
+
+ /* optional on 32-bit */
AFRES
AFRESCC
AFRSQRTE
@@ -443,9 +456,12 @@ const (
AFSQRTCC
AFSQRTS
AFSQRTSCC
+
+ /* 64-bit */
+
ACNTLZD
ACNTLZDCC
- ACMPW
+ ACMPW /* CMP with L=0 */
ACMPWU
ADIVD
ADIVDCC
@@ -457,6 +473,7 @@ const (
ADIVDUV
AEXTSW
AEXTSWCC
+ /* AFCFIW; AFCFIWCC */
AFCFID
AFCFIDCC
AFCTID
@@ -498,6 +515,8 @@ const (
ASRDCC
ASTDCCC
ATD
+
+ /* 64-bit pseudo operation */
ADWORD
AREMD
AREMDCC
@@ -507,8 +526,13 @@ const (
AREMDUCC
AREMDUV
AREMDUVCC
+
+ /* more 64-bit operations */
AHRFID
+
ALAST
+
+ // aliases
ABR = obj.AJMP
ABL = obj.ACALL
ARETURN = obj.ARET
diff --git a/src/cmd/internal/obj/ppc64/asm9.go b/src/cmd/internal/obj/ppc64/asm9.go
index 9e227c427d..470f6f9ff2 100644
--- a/src/cmd/internal/obj/ppc64/asm9.go
+++ b/src/cmd/internal/obj/ppc64/asm9.go
@@ -1331,6 +1331,7 @@ func OP_RLW(op uint32, a uint32, s uint32, sh uint32, mb uint32, me uint32) uint
}
const (
+ /* each rhs is OPVCC(_, _, _, _) */
OP_ADD = 31<<26 | 266<<1 | 0<<10 | 0
OP_ADDI = 14<<26 | 0<<1 | 0<<10 | 0
OP_ADDIS = 15<<26 | 0<<1 | 0<<10 | 0
diff --git a/src/cmd/internal/obj/x86/6.out.go b/src/cmd/internal/obj/x86/6.out.go
index 0e136985df..495ecd2707 100644
--- a/src/cmd/internal/obj/x86/6.out.go
+++ b/src/cmd/internal/obj/x86/6.out.go
@@ -264,6 +264,7 @@ const (
AXORB
AXORL
AXORW
+
AFMOVB
AFMOVBP
AFMOVD
@@ -278,6 +279,7 @@ const (
AFMOVWP
AFMOVX
AFMOVXP
+
AFCOMB
AFCOMBP
AFCOMD
@@ -292,38 +294,46 @@ const (
AFUCOM
AFUCOMP
AFUCOMPP
+
AFADDDP
AFADDW
AFADDL
AFADDF
AFADDD
+
AFMULDP
AFMULW
AFMULL
AFMULF
AFMULD
+
AFSUBDP
AFSUBW
AFSUBL
AFSUBF
AFSUBD
+
AFSUBRDP
AFSUBRW
AFSUBRL
AFSUBRF
AFSUBRD
+
AFDIVDP
AFDIVW
AFDIVL
AFDIVF
AFDIVD
+
AFDIVRDP
AFDIVRW
AFDIVRL
AFDIVRF
AFDIVRD
+
AFXCHD
AFFREE
+
AFLDCW
AFLDENV
AFRSTOR
@@ -331,6 +341,7 @@ const (
AFSTCW
AFSTENV
AFSTSW
+
AF2XM1
AFABS
AFCHS
@@ -361,6 +372,8 @@ const (
AFXTRACT
AFYL2X
AFYL2XP1
+
+ // extra 32-bit operations
ACMPXCHGB
ACMPXCHGL
ACMPXCHGW
@@ -382,6 +395,8 @@ const (
AXADDB
AXADDL
AXADDW
+
+ // conditional move
ACMOVLCC
ACMOVLCS
ACMOVLEQ
@@ -430,6 +445,8 @@ const (
ACMOVWPC
ACMOVWPL
ACMOVWPS
+
+ // 64-bit
AADCQ
AADDQ
AANDQ
@@ -481,6 +498,8 @@ const (
AXADDQ
AXCHGQ
AXORQ
+
+ // media
AADDPD
AADDPS
AADDSD
@@ -682,6 +701,7 @@ const (
AUNPCKLPS
AXORPD
AXORPS
+
APF2IW
APF2IL
API2FW
@@ -690,25 +710,32 @@ const (
ARETFL
ARETFQ
ASWAPGS
+
AMODE
ACRC32B
ACRC32Q
AIMUL3Q
+
APREFETCHT0
APREFETCHT1
APREFETCHT2
APREFETCHNTA
+
AMOVQL
ABSWAPL
ABSWAPQ
+
AAESENC
AAESENCLAST
AAESDEC
AAESDECLAST
AAESIMC
AAESKEYGENASSIST
+
APSHUFD
APCLMULQDQ
+
+ // from 386
AJCXZW
AFCMOVCC
AFCMOVCS
@@ -722,6 +749,7 @@ const (
AFCOMIP
AFUCOMI
AFUCOMIP
+
ALAST
)
@@ -743,6 +771,7 @@ const (
REG_R13B
REG_R14B
REG_R15B
+
REG_AX = obj.RBaseAMD64 + 16 + iota - 17
REG_CX
REG_DX
@@ -759,12 +788,16 @@ const (
REG_R13
REG_R14
REG_R15
+
REG_AH = obj.RBaseAMD64 + 32 + iota - 33
REG_CH
REG_DH
REG_BH
+
REG_F0 = obj.RBaseAMD64 + 36
+
REG_M0 = obj.RBaseAMD64 + 44
+
REG_X0 = obj.RBaseAMD64 + 52 + iota - 39
REG_X1
REG_X2
@@ -781,31 +814,37 @@ const (
REG_X13
REG_X14
REG_X15
+
REG_CS = obj.RBaseAMD64 + 68 + iota - 55
REG_SS
REG_DS
REG_ES
REG_FS
REG_GS
- REG_GDTR
- REG_IDTR
- REG_LDTR
- REG_MSW
- REG_TASK
- REG_CR = obj.RBaseAMD64 + 79
- REG_DR = obj.RBaseAMD64 + 95
- REG_TR = obj.RBaseAMD64 + 103
+
+ REG_GDTR /* global descriptor table register */
+ REG_IDTR /* interrupt descriptor table register */
+ REG_LDTR /* local descriptor table register */
+ REG_MSW /* machine status word */
+ REG_TASK /* task register */
+
+ REG_CR = obj.RBaseAMD64 + 79
+ REG_DR = obj.RBaseAMD64 + 95
+ REG_TR = obj.RBaseAMD64 + 103
+
REG_TLS = obj.RBaseAMD64 + 111 + iota - 69
+
MAXREG
+
REGARG = -1
REGRET = REG_AX
FREGRET = REG_X0
REGSP = REG_SP
REGTMP = REG_DI
REGCTXT = REG_DX
- REGEXT = REG_R15
- FREGMIN = REG_X0 + 5
- FREGEXT = REG_X0 + 15
+ REGEXT = REG_R15 /* compiler allocates external registers R15 down */
+ FREGMIN = REG_X0 + 5 /* first register variable */
+ FREGEXT = REG_X0 + 15 /* first external register */
T_TYPE = 1 << 0
T_INDEX = 1 << 1
T_OFFSET = 1 << 2
diff --git a/src/cmd/internal/obj/x86/asm6.go b/src/cmd/internal/obj/x86/asm6.go
index 4ec4b2537d..ae47801249 100644
--- a/src/cmd/internal/obj/x86/asm6.go
+++ b/src/cmd/internal/obj/x86/asm6.go
@@ -40,7 +40,21 @@ import (
// Instruction layout.
const (
- MaxAlign = 32
+ MaxAlign = 32 // max data alignment
+
+ // Loop alignment constants:
+ // want to align loop entry to LoopAlign-byte boundary,
+ // and willing to insert at most MaxLoopPad bytes of NOP to do so.
+ // We define a loop entry as the target of a backward jump.
+ //
+ // gcc uses MaxLoopPad = 10 for its 'generic x86-64' config,
+ // and it aligns all jump targets, not just backward jump targets.
+ //
+ // As of 6/1/2012, the effect of setting MaxLoopPad = 10 here
+ // is very slight but negative, so the alignment is disabled by
+ // setting MaxLoopPad = 0. The code is here for reference and
+ // for future experiments.
+ //
LoopAlign = 16
MaxLoopPad = 0
FuncAlign = 16
@@ -173,7 +187,7 @@ const (
Zm_r_3d
Zm_r_xm_nr
Zr_m_xm_nr
- Zibm_r
+ Zibm_r /* mmx1,mmx2/mem64,imm8 */
Zmb_r
Zaut_r
Zo_m
@@ -194,28 +208,30 @@ const (
)
const (
- Px = 0
- Px1 = 1 // symbolic; exact value doesn't matter
- P32 = 0x32
- Pe = 0x66
- Pm = 0x0f
- Pq = 0xff
- Pb = 0xfe
- Pf2 = 0xf2
- Pf3 = 0xf3
- Pq3 = 0x67
- Pw = 0x48
- Pw8 = 0x90 // symbolic; exact value doesn't matter
- Py = 0x80
- Py1 = 0x81 // symbolic; exact value doesn't matter
- Py3 = 0x83 // symbolic; exact value doesn't matter
- Rxf = 1 << 9
- Rxt = 1 << 8
- Rxw = 1 << 3
- Rxr = 1 << 2
- Rxx = 1 << 1
- Rxb = 1 << 0
- Maxand = 10
+ Px = 0
+ Px1 = 1 // symbolic; exact value doesn't matter
+ P32 = 0x32 /* 32-bit only */
+ Pe = 0x66 /* operand escape */
+ Pm = 0x0f /* 2byte opcode escape */
+ Pq = 0xff /* both escapes: 66 0f */
+ Pb = 0xfe /* byte operands */
+ Pf2 = 0xf2 /* xmm escape 1: f2 0f */
+ Pf3 = 0xf3 /* xmm escape 2: f3 0f */
+ Pq3 = 0x67 /* xmm escape 3: 66 48 0f */
+ Pw = 0x48 /* Rex.w */
+ Pw8 = 0x90 // symbolic; exact value doesn't matter
+ Py = 0x80 /* defaults to 64-bit mode */
+ Py1 = 0x81 // symbolic; exact value doesn't matter
+ Py3 = 0x83 // symbolic; exact value doesn't matter
+
+ Rxf = 1 << 9 /* internal flag for Rxr on from */
+ Rxt = 1 << 8 /* internal flag for Rxr on to */
+ Rxw = 1 << 3 /* =1, 64-bit operand size */
+ Rxr = 1 << 2 /* extend modrm reg */
+ Rxx = 1 << 1 /* extend sib index */
+ Rxb = 1 << 0 /* extend modrm r/m, sib base, or opcode reg */
+
+ Maxand = 10 /* in -a output width of the byte codes */
)
var ycover [Ymax * Ymax]uint8
generated by cgit v1.3 (git 2.53.0) at 2026-04-16 07:37:42 +0000