diff options
Diffstat (limited to 'src/cmd/asm/internal')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/riscv64.s | 10 | ||||
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/riscv64error.s | 1 | ||||
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/riscv64validation.s | 2 |
3 files changed, 13 insertions, 0 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/riscv64.s b/src/cmd/asm/internal/asm/testdata/riscv64.s index 07a898465f..702b82223b 100644 --- a/src/cmd/asm/internal/asm/testdata/riscv64.s +++ b/src/cmd/asm/internal/asm/testdata/riscv64.s @@ -549,6 +549,16 @@ start: VSOXEI64V V3, V2, (X10) // a771250e VSOXEI64V V3, V2, V0, (X10) // a771250c + // 31.7.7: Unit-stride Fault-Only-First Loads + VLE8FFV (X10), V8 // 07040503 + VLE16FFV (X10), V8 // 07540503 + VLE32FFV (X10), V8 // 07640503 + VLE64FFV (X10), V8 // 07740503 + VLE8FFV (X10), V0, V8 // 07040501 + VLE16FFV (X10), V0, V8 // 07540501 + VLE32FFV (X10), V0, V8 // 07640501 + VLE64FFV (X10), V0, V8 // 07740501 + // 31.7.8: Vector Load/Store Segment Instructions // 31.7.8.1: Vector Unit-Stride Segment Loads and Stores diff --git a/src/cmd/asm/internal/asm/testdata/riscv64error.s b/src/cmd/asm/internal/asm/testdata/riscv64error.s index 113b4ad2d6..3c09770d2a 100644 --- a/src/cmd/asm/internal/asm/testdata/riscv64error.s +++ b/src/cmd/asm/internal/asm/testdata/riscv64error.s @@ -73,6 +73,7 @@ TEXT errors(SB),$0 // VSETIVLI X10, E32, M2, TA, MA, X12 // ERROR "expected immediate value" VLE8V (X10), V1, V3 // ERROR "invalid vector mask register" + VLE8FFV (X10), V1, V3 // ERROR "invalid vector mask register" VSE8V V3, V1, (X10) // ERROR "invalid vector mask register" VLSE8V (X10), X10, V1, V3 // ERROR "invalid vector mask register" VSSE8V V3, X11, V1, (X10) // ERROR "invalid vector mask register" diff --git a/src/cmd/asm/internal/asm/testdata/riscv64validation.s b/src/cmd/asm/internal/asm/testdata/riscv64validation.s index eac1a992c3..6549765916 100644 --- a/src/cmd/asm/internal/asm/testdata/riscv64validation.s +++ b/src/cmd/asm/internal/asm/testdata/riscv64validation.s @@ -20,6 +20,8 @@ TEXT validation(SB),$0 VSETVL X10, X11 // ERROR "expected integer register in rs1 position" VLE8V (X10), X10 // ERROR "expected vector register in vd position" VLE8V (V1), V3 // ERROR "expected integer register in rs1 position" + VLE8FFV (X10), X10 // ERROR "expected vector register in vd position" + VLE8FFV (V1), V3 // ERROR "expected integer register in rs1 position" VSE8V X10, (X10) // ERROR "expected vector register in vs1 position" VSE8V V3, (V1) // ERROR "expected integer register in rd position" VLSE8V (X10), V3 // ERROR "expected integer register in rs2 position" |