diff options
| -rw-r--r-- | src/cmd/7g/galign.go | 1 | ||||
| -rw-r--r-- | src/cmd/internal/gc/gen.go | 16 | ||||
| -rw-r--r-- | src/cmd/internal/gc/go.go | 1 |
3 files changed, 13 insertions, 5 deletions
diff --git a/src/cmd/7g/galign.go b/src/cmd/7g/galign.go index c21cb67fab..3ad786a8fd 100644 --- a/src/cmd/7g/galign.go +++ b/src/cmd/7g/galign.go @@ -49,6 +49,7 @@ func main() { gc.Thearch.REGRETURN = arm64.REG_R0 gc.Thearch.REGMIN = arm64.REG_R0 gc.Thearch.REGMAX = arm64.REG_R31 + gc.Thearch.REGZERO = arm64.REGZERO gc.Thearch.FREGMIN = arm64.REG_F0 gc.Thearch.FREGMAX = arm64.REG_F31 gc.Thearch.MAXWIDTH = MAXWIDTH diff --git a/src/cmd/internal/gc/gen.go b/src/cmd/internal/gc/gen.go index fde0a196b7..e95ddeb29f 100644 --- a/src/cmd/internal/gc/gen.go +++ b/src/cmd/internal/gc/gen.go @@ -1183,12 +1183,18 @@ func Componentgen(nr *Node, nl *Node) bool { } } else { // When zeroing, prepare a register containing zero. - var tmp Node - Nodconst(&tmp, nl.Type, 0) + if Thearch.REGZERO != 0 { + // cpu has a dedicated zero register + Nodreg(&nodr, Types[TUINT], Thearch.REGZERO) + } else { + // no dedicated zero register + var tmp Node + Nodconst(&tmp, nl.Type, 0) - Regalloc(&nodr, Types[TUINT], nil) - Thearch.Gmove(&tmp, &nodr) - defer Regfree(&nodr) + Regalloc(&nodr, Types[TUINT], nil) + Thearch.Gmove(&tmp, &nodr) + defer Regfree(&nodr) + } } // nl and nr are 'cadable' which basically means they are names (variables) now. diff --git a/src/cmd/internal/gc/go.go b/src/cmd/internal/gc/go.go index 5803f39ec2..25ada5524d 100644 --- a/src/cmd/internal/gc/go.go +++ b/src/cmd/internal/gc/go.go @@ -769,6 +769,7 @@ type Arch struct { REGRETURN int // AX REGMIN int REGMAX int + REGZERO int // architectural zero register, if available FREGMIN int FREGMAX int MAXWIDTH int64 |