diff options
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/arm64sveenc.s | 110 | ||||
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/arm64sveerror.s | 110 | ||||
| -rw-r--r-- | src/cmd/internal/obj/arm64/anames_gen.go | 49 | ||||
| -rw-r--r-- | src/cmd/internal/obj/arm64/encoding_gen.go | 704 | ||||
| -rw-r--r-- | src/cmd/internal/obj/arm64/goops_gen.go | 51 | ||||
| -rw-r--r-- | src/cmd/internal/obj/arm64/inst.go | 260 | ||||
| -rw-r--r-- | src/cmd/internal/obj/arm64/inst_gen.go | 2903 |
7 files changed, 3441 insertions, 746 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/arm64sveenc.s b/src/cmd/asm/internal/asm/testdata/arm64sveenc.s index f5467164ab..369c047dfa 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64sveenc.s +++ b/src/cmd/asm/internal/asm/testdata/arm64sveenc.s @@ -808,4 +808,114 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 ZUMULLT Z6.H[3], Z23.H, Z13.S // eddeae44 ZUMULLT Z6.S[3], Z23.S, Z13.D // eddef644 ZUSDOT Z6.B[3], Z23.B, Z13.S // ed1abe44 + ADDPL $9, R11, RSP // 3f516b04 + ADDVL $9, R11, RSP // 3f512b04 + RDVL $1, R27 // 3b50bf04 + ZADD $6, Z7.D, Z7.D // c7c0e025 + ZAND $6, Z7.D, Z7.D // 27f88305 + ZASR $6, Z23.B, P1.M, Z23.B // 57850004 + ZASR $6, Z7.D, Z23.D // f790fa04 + ZASRD $6, Z23.B, P1.M, Z23.B // 57850404 + ZCADD $270, Z25.S, Z22.S, Z22.S // 36df8045 + ZCDOT $0, Z5.B[3], Z16.B, Z26.S // 1a42bd44 + ZCDOT $270, Z3.H[0], Z2.H, Z23.D // 574ce344 + ZCDOT $270, Z28.B, Z1.B, Z9.S // 291c9c44 + ZCMLA $0, Z5.H[3], Z16.H, Z26.H // 1a62bd44 + ZCMLA $270, Z3.S[0], Z2.S, Z23.S // 576ce344 + ZCMLA $180, Z19.S, Z20.S, Z9.S // 892a9344 + ZCMPEQ $6, Z23.B, P1.Z, P14.B // ee860625 + ZCMPGE $6, Z23.B, P1.Z, P14.B // ee060625 + ZCMPGT $6, Z23.B, P1.Z, P14.B // fe060625 + ZCMPHI $6, Z23.B, P1.Z, P14.B // fe862124 + ZCMPHS $6, Z23.B, P1.Z, P14.B // ee862124 + // TODO: CMPLE + // TODO: CMPLO + // TODO: CMPLS + // TODO: CMPLT + ZCMPNE $6, Z23.B, P1.Z, P14.B // fe860625 + ZCPY $6, P5.M, Z6.H // c6405505 + ZCPY $6, P5.Z, Z6.H // c6005505 + ZDUP $9, Z11.B // 2bc13825 + ZDUPM $7, Z6.H // 4604c005 + ZEOR $6, Z7.D, Z7.D // 27f84305 + ZEXT $6, Z23.B, Z13.B, Z13.B // ed1a2005 + ZEXTQ $6, Z23.B, Z13.B, Z13.B // ed266605 + ZFADD $(1.0), Z5.D, P5.M, Z5.D // 2594d865 + ZFCADD $90, Z13.S, Z4.S, P4.M, Z4.S // a4918064 + ZFCMEQ $(0.0), Z7.D, P4.Z, P2.D // e230d265 + ZFCMGE $(0.0), Z7.D, P4.Z, P2.D // e230d065 + ZFCMGT $(0.0), Z7.D, P4.Z, P2.D // f230d065 + ZFCMLA $0, Z5.H[3], Z16.H, Z26.H // 1a12bd64 + ZFCMLA $270, Z3.S[0], Z2.S, Z23.S // 571ce364 + ZFCMLA $180, Z30.D, Z29.D, P7.M, Z25.D // b95fde64 + ZFCMLE $(0.0), Z7.D, P4.Z, P2.D // f230d165 + ZFCMLT $(0.0), Z7.D, P4.Z, P2.D // e230d165 + ZFCMNE $(0.0), Z7.D, P4.Z, P2.D // e230d365 + ZFCPY $(2.0), P6.M, Z23.H // 17c05605 + ZFDUP $(2.0), Z4.S // 04c0b925 + ZFMAX $(0.0), Z3.D, P1.M, Z3.D // 0384de65 + ZFMAXNM $(0.0), Z3.D, P1.M, Z3.D // 0384dc65 + ZFMIN $(0.0), Z3.D, P1.M, Z3.D // 0384df65 + ZFMINNM $(0.0), Z3.D, P1.M, Z3.D // 0384dd65 + ZFMUL $(2.0), Z16.S, P1.M, Z16.S // 30849a65 + ZFSUB $(1.0), Z5.D, P5.M, Z5.D // 2594d965 + ZFSUBR $(1.0), Z5.D, P5.M, Z5.D // 2594db65 + ZFTMAD $3, Z13.S, Z9.S, Z9.S // a9819365 + ZINDEX R11, $6, Z7.D // c748eb04 + ZINDEX $1, $11, Z26.S // 7a41a104 + ZINDEX $8, R24, Z14.D // 0e47e804 + ZINDEXW R2, $10, Z8.H // 48496204 + ZINDEXW $1, R27, Z26.S // 7a47a104 + ZLSL $6, Z23.B, P1.M, Z23.B // d7850304 + ZLSL $6, Z7.D, Z23.D // f79ca604 + ZLSR $6, Z23.B, P1.M, Z23.B // 57850104 + ZLSR $6, Z7.D, Z23.D // f794fa04 + ZMUL $6, Z7.D, Z7.D // c7c0f025 + ZORR $6, Z7.D, Z7.D // 27f80305 + ZRSHRNB $9, Z7.S, Z23.H // f7183745 + ZRSHRNT $9, Z7.S, Z23.H // f71c3745 + ZSHRNB $9, Z7.S, Z23.H // f7103745 + ZSHRNT $9, Z7.S, Z23.H // f7143745 + ZSLI $6, Z7.D, Z23.D // f7f48645 + ZSMAX $6, Z7.D, Z7.D // c7c0e825 + ZSMIN $6, Z7.D, Z7.D // c7c0ea25 + ZSQADD $6, Z7.D, Z7.D // c7c0e425 + ZSQCADD $270, Z25.S, Z22.S, Z22.S // 36df8145 + ZSQRDCMLAH $0, Z5.H[3], Z16.H, Z26.H // 1a72bd44 + ZSQRDCMLAH $270, Z3.S[0], Z2.S, Z23.S // 577ce344 + ZSQRDCMLAH $180, Z19.S, Z20.S, Z9.S // 893a9344 + ZSQRSHRNB $9, Z7.S, Z23.H // f7283745 + ZSQRSHRNT $9, Z7.S, Z23.H // f72c3745 + ZSQRSHRUNB $9, Z7.S, Z23.H // f7083745 + ZSQRSHRUNT $9, Z7.S, Z23.H // f70c3745 + ZSQSHL $6, Z23.B, P1.M, Z23.B // d7850604 + ZSQSHLU $6, Z23.B, P1.M, Z23.B // d7850f04 + ZSQSHRNB $9, Z7.S, Z23.H // f7203745 + ZSQSHRNT $9, Z7.S, Z23.H // f7243745 + ZSQSHRUNB $9, Z7.S, Z23.H // f7003745 + ZSQSHRUNT $9, Z7.S, Z23.H // f7043745 + ZSQSUB $6, Z7.D, Z7.D // c7c0e625 + ZSRI $6, Z7.D, Z23.D // f7f0da45 + ZSRSHR $6, Z23.B, P1.M, Z23.B // 57850c04 + ZSRSRA $6, Z7.D, Z23.D // f7e8da45 + ZSSHLLB $5, Z22.S, Z10.D // caa24545 + ZSSHLLT $5, Z22.S, Z10.D // caa64545 + ZSSRA $6, Z7.D, Z23.D // f7e0da45 + ZSUB $6, Z7.D, Z7.D // c7c0e125 + ZSUBR $6, Z7.D, Z7.D // c7c0e325 + ZUMAX $6, Z7.D, Z7.D // c7c0e925 + ZUMIN $6, Z7.D, Z7.D // c7c0eb25 + ZUQADD $6, Z7.D, Z7.D // c7c0e525 + ZUQRSHRNB $9, Z7.S, Z23.H // f7383745 + ZUQRSHRNT $9, Z7.S, Z23.H // f73c3745 + ZUQSHL $6, Z23.B, P1.M, Z23.B // d7850704 + ZUQSHRNB $9, Z7.S, Z23.H // f7303745 + ZUQSHRNT $9, Z7.S, Z23.H // f7343745 + ZUQSUB $6, Z7.D, Z7.D // c7c0e725 + ZURSHR $6, Z23.B, P1.M, Z23.B // 57850d04 + ZURSRA $6, Z7.D, Z23.D // f7ecda45 + ZUSHLLB $5, Z22.S, Z10.D // caaa4545 + ZUSHLLT $5, Z22.S, Z10.D // caae4545 + ZUSRA $6, Z7.D, Z23.D // f7e4da45 + ZXAR $6, Z23.B, Z21.B, Z21.B // f5362a04 RET diff --git a/src/cmd/asm/internal/asm/testdata/arm64sveerror.s b/src/cmd/asm/internal/asm/testdata/arm64sveerror.s index 52798e8336..ade1c64ddc 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64sveerror.s +++ b/src/cmd/asm/internal/asm/testdata/arm64sveerror.s @@ -807,4 +807,114 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 ZUMULLT Z27.H[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" ZUMULLT Z27.S[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" ZUSDOT Z27.B[1], Z26.S, Z11.B // ERROR "illegal combination from SVE" + ADDPL $1, R27, ZR // ERROR "illegal combination from SVE" + ADDVL $1, R27, ZR // ERROR "illegal combination from SVE" + RDVL $11, RSP // ERROR "illegal combination from SVE" + ZADD $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZAND $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZASR $1, Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZASR $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZASRD $1, Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZCADD $1, Z27.Q, Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZCDOT $1, Z26.B[3], Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZCDOT $1, Z26.H[3], Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZCDOT $1, Z27.Q, Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZCMLA $1, Z26.H[3], Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZCMLA $1, Z26.S[3], Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZCMLA $1, Z27.Q, Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZCMPEQ $1, Z27.Q, P7.Z, P0.H // ERROR "illegal combination from SVE" + ZCMPGE $1, Z27.Q, P7.Z, P0.H // ERROR "illegal combination from SVE" + ZCMPGT $1, Z27.Q, P7.Z, P0.H // ERROR "illegal combination from SVE" + ZCMPHI $1, Z27.Q, P7.Z, P0.H // ERROR "illegal combination from SVE" + ZCMPHS $1, Z27.Q, P7.Z, P0.H // ERROR "illegal combination from SVE" + ZCMPLE $1, Z27.Q, P7.Z, P0.H // ERROR "illegal combination from SVE" + ZCMPLO $1, Z27.Q, P7.Z, P0.H // ERROR "illegal combination from SVE" + ZCMPLS $1, Z27.Q, P7.Z, P0.H // ERROR "illegal combination from SVE" + ZCMPLT $1, Z27.Q, P7.Z, P0.H // ERROR "illegal combination from SVE" + ZCMPNE $1, Z27.Q, P7.Z, P0.H // ERROR "illegal combination from SVE" + ZCPY $1, P7.M, Z25.Q // ERROR "illegal combination from SVE" + ZCPY $1, P7.M, Z25.Q // ERROR "illegal combination from SVE" + ZDUP $1, Z27.Q // ERROR "illegal combination from SVE" + ZDUPM $1, Z27.Q // ERROR "illegal combination from SVE" + ZEOR $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZEXT $1, Z27.Q, Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZEXTQ $1, Z27.Q, Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZFADD $(3.6), Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZFCADD $1, Z27.Q, Z25.Q, P0.Z, Z6.H // ERROR "illegal combination from SVE" + ZFCMEQ $(0.0), Z1.S, P13.Z, P14.B // ERROR "illegal combination from SVE" + ZFCMGE $(0.0), Z1.S, P13.Z, P14.B // ERROR "illegal combination from SVE" + ZFCMGT $(0.0), Z1.S, P13.Z, P14.B // ERROR "illegal combination from SVE" + ZFCMLA $1, Z26.H[3], Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZFCMLA $1, Z26.S[3], Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZFCMLA $1, Z27.Q, Z25.Q, P0.Z, Z6.H // ERROR "illegal combination from SVE" + ZFCMLE $(0.0), Z1.S, P13.Z, P14.B // ERROR "illegal combination from SVE" + ZFCMLT $(0.0), Z1.S, P13.Z, P14.B // ERROR "illegal combination from SVE" + ZFCMNE $(0.0), Z1.S, P13.Z, P14.B // ERROR "illegal combination from SVE" + ZFCPY $(3.6), P7.M, Z25.Q // ERROR "illegal combination from SVE" + ZFDUP $(3.6), Z27.Q // ERROR "illegal combination from SVE" + ZFMAX $(3.6), Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZFMAXNM $(3.6), Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZFMIN $(3.6), Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZFMINNM $(3.6), Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZFMUL $(3.6), Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZFSUB $(3.6), Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZFSUBR $(3.6), Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZFTMAD $1, Z27.Q, Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZINDEX RSP, $11, Z26.S // ERROR "illegal combination from SVE" + ZINDEX $7, $90, Z21.Q // ERROR "illegal combination from SVE" + // TODO: INDEX + ZINDEXW RSP, $11, Z26.S // ERROR "illegal combination from SVE" + // TODO: INDEX + ZLSL $1, Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZLSL $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZLSR $1, Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZLSR $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZMUL $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZORR $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZRSHRNB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZRSHRNT $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSHRNB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSHRNT $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSLI $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSMAX $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSMIN $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSQADD $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSQCADD $1, Z27.Q, Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZSQRDCMLAH $1, Z26.H[3], Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZSQRDCMLAH $1, Z26.S[3], Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZSQRDCMLAH $1, Z27.Q, Z25.Q, Z6.H // ERROR "illegal combination from SVE" + ZSQRSHRNB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSQRSHRNT $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSQRSHRUNB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSQRSHRUNT $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSQSHL $1, Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZSQSHLU $1, Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZSQSHRNB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSQSHRNT $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSQSHRUNB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSQSHRUNT $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSQSUB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSRI $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSRSHR $1, Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZSRSRA $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSSHLLB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSSHLLT $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSSRA $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSUB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZSUBR $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZUMAX $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZUMIN $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZUQADD $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZUQRSHRNB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZUQRSHRNT $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZUQSHL $1, Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZUQSHRNB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZUQSHRNT $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZUQSUB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZURSHR $1, Z27.Q, P7.Z, Z6.H // ERROR "illegal combination from SVE" + ZURSRA $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZUSHLLB $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZUSHLLT $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZUSRA $1, Z27.Q, Z25.Q // ERROR "illegal combination from SVE" + ZXAR $1, Z27.Q, Z25.Q, Z6.H // ERROR "illegal combination from SVE" RET diff --git a/src/cmd/internal/obj/arm64/anames_gen.go b/src/cmd/internal/obj/arm64/anames_gen.go index 498d227772..9d15f9f801 100644 --- a/src/cmd/internal/obj/arm64/anames_gen.go +++ b/src/cmd/internal/obj/arm64/anames_gen.go @@ -4,6 +4,8 @@ package arm64 var sveAnames = []string{ "SVESTART", + "ADDPL", + "ADDVL", "CTERMEQ", "CTERMEQW", "CTERMNE", @@ -82,6 +84,7 @@ var sveAnames = []string{ "PWRFFR", "PZIP1", "PZIP2", + "RDVL", "SETFFR", "ZABS", "ZADCLB", @@ -105,6 +108,7 @@ var sveAnames = []string{ "ZANDVH", "ZANDVS", "ZASR", + "ZASRD", "ZASRR", "ZBCAX", "ZBDEP", @@ -137,6 +141,8 @@ var sveAnames = []string{ "ZBSL", "ZBSL1N", "ZBSL2N", + "ZCADD", + "ZCDOT", "ZCLASTA", "ZCLASTAB", "ZCLASTAD", @@ -151,6 +157,7 @@ var sveAnames = []string{ "ZCLASTBW", "ZCLS", "ZCLZ", + "ZCMLA", "ZCMPEQ", "ZCMPGE", "ZCMPGT", @@ -172,6 +179,7 @@ var sveAnames = []string{ "ZCPYW", "ZDECP", "ZDUP", + "ZDUPM", "ZDUPQ", "ZDUPW", "ZEOR", @@ -184,6 +192,8 @@ var sveAnames = []string{ "ZEORVH", "ZEORVS", "ZEXPAND", + "ZEXT", + "ZEXTQ", "ZF1CVT", "ZF1CVTLT", "ZF2CVT", @@ -203,12 +213,17 @@ var sveAnames = []string{ "ZFADDVS", "ZFAMAX", "ZFAMIN", + "ZFCADD", "ZFCLAMP", "ZFCMEQ", "ZFCMGE", "ZFCMGT", + "ZFCMLA", + "ZFCMLE", + "ZFCMLT", "ZFCMNE", "ZFCMUO", + "ZFCPY", "ZFCVT", "ZFCVTLT", "ZFCVTNT", @@ -219,6 +234,7 @@ var sveAnames = []string{ "ZFDIV", "ZFDIVR", "ZFDOT", + "ZFDUP", "ZFEXPA", "ZFLOGB", "ZFMAD", @@ -285,6 +301,7 @@ var sveAnames = []string{ "ZFSQRT", "ZFSUB", "ZFSUBR", + "ZFTMAD", "ZFTSMUL", "ZFTSSEL", "ZHISTCNT", @@ -346,6 +363,8 @@ var sveAnames = []string{ "ZREVD", "ZREVH", "ZREVW", + "ZRSHRNB", + "ZRSHRNT", "ZRSUBHNB", "ZRSUBHNT", "ZSABA", @@ -372,8 +391,11 @@ var sveAnames = []string{ "ZSDOT", "ZSEL", "ZSHADD", + "ZSHRNB", + "ZSHRNT", "ZSHSUB", "ZSHSUBR", + "ZSLI", "ZSM4E", "ZSM4EKEY", "ZSMAX", @@ -401,6 +423,7 @@ var sveAnames = []string{ "ZSPLICE", "ZSQABS", "ZSQADD", + "ZSQCADD", "ZSQDECP", "ZSQDMLALB", "ZSQDMLALBT", @@ -413,13 +436,23 @@ var sveAnames = []string{ "ZSQDMULLT", "ZSQINCP", "ZSQNEG", + "ZSQRDCMLAH", "ZSQRDMLAH", "ZSQRDMLSH", "ZSQRDMULH", "ZSQRSHL", "ZSQRSHLR", + "ZSQRSHRNB", + "ZSQRSHRNT", + "ZSQRSHRUNB", + "ZSQRSHRUNT", "ZSQSHL", "ZSQSHLR", + "ZSQSHLU", + "ZSQSHRNB", + "ZSQSHRNT", + "ZSQSHRUNB", + "ZSQSHRUNT", "ZSQSUB", "ZSQSUBR", "ZSQXTNB", @@ -427,8 +460,14 @@ var sveAnames = []string{ "ZSQXTUNB", "ZSQXTUNT", "ZSRHADD", + "ZSRI", "ZSRSHL", "ZSRSHLR", + "ZSRSHR", + "ZSRSRA", + "ZSSHLLB", + "ZSSHLLT", + "ZSSRA", "ZSSUBLB", "ZSSUBLBT", "ZSSUBLT", @@ -501,8 +540,12 @@ var sveAnames = []string{ "ZUQINCP", "ZUQRSHL", "ZUQRSHLR", + "ZUQRSHRNB", + "ZUQRSHRNT", "ZUQSHL", "ZUQSHLR", + "ZUQSHRNB", + "ZUQSHRNT", "ZUQSUB", "ZUQSUBR", "ZUQXTNB", @@ -511,10 +554,15 @@ var sveAnames = []string{ "ZURHADD", "ZURSHL", "ZURSHLR", + "ZURSHR", "ZURSQRTE", + "ZURSRA", "ZUSDOT", + "ZUSHLLB", + "ZUSHLLT", "ZUSMMLA", "ZUSQADD", + "ZUSRA", "ZUSUBLB", "ZUSUBLT", "ZUSUBWB", @@ -528,6 +576,7 @@ var sveAnames = []string{ "ZUZP2", "ZUZPQ1", "ZUZPQ2", + "ZXAR", "ZZIP1", "ZZIP2", "ZZIPQ1", diff --git a/src/cmd/internal/obj/arm64/encoding_gen.go b/src/cmd/internal/obj/arm64/encoding_gen.go index 6fd3b93476..da5e6fea67 100644 --- a/src/cmd/internal/obj/arm64/encoding_gen.go +++ b/src/cmd/internal/obj/arm64/encoding_gen.go @@ -9,6 +9,8 @@ const ( enc_i3h_i3l enc_i4h_i4l enc_imm2_tsz + enc_imm8h_imm8l + enc_tszh_tszl_imm3 enc_tszh_tszl enc_M enc_PNd @@ -37,13 +39,28 @@ const ( enc_Zn enc_i1 enc_i2 + enc_imm13 enc_imm2 + enc_imm3 + enc_imm4 + enc_imm5 + enc_imm5b + enc_imm6 + enc_imm7 + enc_imm8 + enc_rot enc_size enc_size0 enc_sz enc_tsz ) +// encodeXCheck is the implementation of the following encoding logic: +// Check this is a 64-bit scalar register +func encodeXCheck(v uint32) (uint32, bool) { + return 0, true +} + // encodeArngBCheck is the implementation of the following encoding logic: // Check this is a B arrangement func encodeArngBCheck(v uint32) (uint32, bool) { @@ -107,6 +124,15 @@ func encodeZeroPredCheck(v uint32) (uint32, bool) { return 0, false } +// encodeFimm0_0_56 is the implementation of the following encoding logic: +// Check this is immediate 0.0 +func encodeFimm0_0_56(v uint32) (uint32, bool) { + if (v & 0x7FFFFFFF) != 0 { + return 0, false + } + return 0, true +} + // encodeI2_1921_16To32Bit is the implementation of the following encoding logic: // For the "16-bit to 32-bit" variant: is the immediate index of a pair of 16-bit elements within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field. // bit range mappings: @@ -151,6 +177,17 @@ func encodeZm1619_16Bit32Bit(v uint32) (uint32, bool) { return v << 16, true } +// encodeI2_1921_16bit is the implementation of the following encoding logic: +// For the "16-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2" field. +// bit range mappings: +// i2: [19:21) +func encodeI2_1921_16bit(v uint32) (uint32, bool) { + if v > 3 { + return 0, false + } + return v << 19, true +} + // encodeI3hI3l_1923_16Bit is the implementation of the following encoding logic: // For the "16-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields. // bit range mappings: @@ -163,6 +200,28 @@ func encodeI3hI3l_1923_16Bit(v uint32) (uint32, bool) { return (v&3)<<19 | (v>>2)<<22, true } +// encodeZm_1619_Range0_7V1 is the implementation of the following encoding logic: +// For the "16-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field. +// bit range mappings: +// Zm: [16:19) +func encodeZm_1619_Range0_7V1(v uint32) (uint32, bool) { + if v <= 7 { + return v << 16, true + } + return 0, false +} + +// encodeI1_2021_32bit is the implementation of the following encoding logic: +// For the "32-bit" variant: is the element index, in the range 0 to 1, encoded in the "i1" field. +// bit range mappings: +// i1: [20:21) +func encodeI1_2021_32bit(v uint32) (uint32, bool) { + if v > 1 { + return 0, false + } + return v << 20, true +} + // encodeI2_1921_32Bit is the implementation of the following encoding logic: // For the "32-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2" field. // bit range mappings: @@ -186,6 +245,17 @@ func encodeI3hI3l_1119_32Bit(v uint32) (uint32, bool) { return (v&1)<<11 | (v>>1)<<19, true } +// encodeZm_1620_Range0_15 is the implementation of the following encoding logic: +// For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field. +// bit range mappings: +// Zm: [16:20) +func encodeZm_1620_Range0_15(v uint32) (uint32, bool) { + if v <= 15 { + return v << 16, true + } + return 0, false +} + // encodeZm1619_32Bit is the implementation of the following encoding logic: // For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field. // bit range mappings: @@ -337,6 +407,17 @@ func encodeI3hI3l_1722_Doubleword(v uint32) (uint32, bool) { return (v&3)<<17 | (v>>2)<<22, true } +// encodeImm5Signed_1621V2 is the implementation of the following encoding logic: +// For the "Equal", "Greater than or equal", "Greater than", "Less than or equal", "Less than", and "Not equal" variants: is the signed immediate operand, in the range -16 to 15, encoded in the "imm5" field. +// bit range mappings: +// imm5: [16:21) +func encodeImm5Signed_1621V2(v uint32) (uint32, bool) { + if int32(v) >= -16 && int32(v) <= 15 { + return (v & 31) << 16, true + } + return 0, false +} + // encodeZm1619_HalfSinglePrecision is the implementation of the following encoding logic: // For the "Half-precision" and "Single-precision" variants: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field. // bit range mappings: @@ -360,6 +441,28 @@ func encodeI3hI3l_1923_HalfPrecision(v uint32) (uint32, bool) { return (v&3)<<19 | (v>>2)<<22, true } +// encodeI2_1921_Half is the implementation of the following encoding logic: +// For the "Half-precision" variant: is the index of a Real and Imaginary pair, in the range 0 to 3, encoded in the "i2" field. +// bit range mappings: +// i2: [19:21) +func encodeI2_1921_Half(v uint32) (uint32, bool) { + if v > 3 { + return 0, false + } + return v << 19, true +} + +// encodeZm_1619_Half is the implementation of the following encoding logic: +// For the "Half-precision" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field. +// bit range mappings: +// Zm: [16:19) +func encodeZm_1619_Half(v uint32) (uint32, bool) { + if v <= 7 { + return v << 16, true + } + return 0, false +} + // encodeI1_1718_Halfword is the implementation of the following encoding logic: // For the "Halfword" variant: is the optional portion index, in the range 0 to 1, defaulting to 0, encoded in the "i1" field. // bit range mappings: @@ -388,6 +491,17 @@ func encodeSize0HalfwordMergeZero(v uint32) (uint32, bool) { return 0, false } +// encodeImm7Unsigned_1421 is the implementation of the following encoding logic: +// For the "Higher or same", "Higher", "Lower or same", and "Lower" variants: is the unsigned immediate operand, in the range 0 to 127, encoded in the "imm7" field. +// bit range mappings: +// imm7: [14:21) +func encodeImm7Unsigned_1421(v uint32) (uint32, bool) { + if v <= 127 { + return v << 14, true + } + return 0, false +} + // encodeI2_1921_SinglePrecision is the implementation of the following encoding logic: // For the "Single-precision" variant: is the immediate index, in the range 0 to 3, encoded in the "i2" field. // bit range mappings: @@ -399,6 +513,28 @@ func encodeI2_1921_SinglePrecision(v uint32) (uint32, bool) { return v << 19, true } +// encodeI1_2021_Single is the implementation of the following encoding logic: +// For the "Single-precision" variant: is the index of a Real and Imaginary pair, in the range 0 to 1, encoded in the "i1" field. +// bit range mappings: +// i1: [20:21) +func encodeI1_2021_Single(v uint32) (uint32, bool) { + if v > 1 { + return 0, false + } + return v << 20, true +} + +// encodeZm_1620_Single is the implementation of the following encoding logic: +// For the "Single-precision" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field. +// bit range mappings: +// Zm: [16:20) +func encodeZm_1620_Single(v uint32) (uint32, bool) { + if v <= 15 { + return v << 16, true + } + return 0, false +} + // encodeSzWordDoubleword is the implementation of the following encoding logic: // For the "Word and doubleword" variant: is the size specifier, // sz <T> @@ -427,6 +563,52 @@ func encodeI2_1719_Word(v uint32) (uint32, bool) { return v << 17, true } +// encodeImm13_518 is the implementation of the following encoding logic: +// Is a 64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits, encoded in the "imm13" field. +// bit range mappings: +// imm13: [5:18) +func encodeImm13_518(v uint32) (uint32, bool) { + return codeLogicalImmArrEncoding, false +} + +// encodeImm8_513_Fimm is the implementation of the following encoding logic: +// Is a floating-point immediate value expressible as ±n÷16×2^r, where n and r are integers such that 16 ≤ n ≤ 31 and -3 ≤ r ≤ 4, i.e. a normalized binary floating-point encoding with 1 sign bit, 3-bit exponent, and 4-bit fractional part, encoded in the "imm8" field. +// bit range mappings: +// imm8: [5:13) +func encodeImm8_513_Fimm(v uint32) (uint32, bool) { + if v <= 255 { + return v << 5, true + } + return 0, false +} + +// encodeImm8SignedLsl8 is the implementation of the following encoding logic: +// Is a signed immediate in the range -128 to 127, encoded in the "imm8" field. +// bit range mappings: +// imm8: [5:13) +// +// Is the optional left shift to apply to the immediate, defaulting to LSL #0 and +// sh <shift> +// 0 LSL #0 +// 1 LSL #8 +// bit range mappings: +// sh: [13:14) +func encodeImm8SignedLsl8(v uint32) (uint32, bool) { + vi := int32(v) + if vi >= -128 && vi <= 127 { + imm8 := uint32(uint8(int8(vi))) + return (imm8 << 5), true + } + if vi&255 == 0 { + unshifted := vi >> 8 + if unshifted >= -128 && unshifted <= 127 { + imm8 := uint32(uint8(int8(unshifted))) + return (imm8 << 5) | (1 << 13), true + } + } + return 0, false +} + // encodeSize16B8H4S2D is the implementation of the following encoding logic: // Is an arrangement specifier, // size <T> @@ -471,6 +653,30 @@ func encodeSize8H4S2D(v uint32) (uint32, bool) { return 0, false } +// encodeImm8UnsignedLsl8 is the implementation of the following encoding logic: +// Is an unsigned immediate in the range 0 to 255, encoded in the "imm8" field. +// bit range mappings: +// imm8: [5:13) +// +// Is the optional left shift to apply to the immediate, defaulting to LSL #0 and +// sh <shift> +// 0 LSL #0 +// 1 LSL #8 +// bit range mappings: +// sh: [13:14) +func encodeImm8UnsignedLsl8(v uint32) (uint32, bool) { + if v <= 255 { + return v << 5, true + } + if v&255 == 0 { + unshifted := v >> 8 + if unshifted <= 255 { + return (unshifted << 5) | (1 << 13), true + } + } + return 0, false +} + // encodeWdn05 is the implementation of the following encoding logic: // Is the 32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field. // bit range mappings: @@ -490,6 +696,20 @@ func encodeVd0564(v uint32) (uint32, bool) { return v & 31, true } +// encodeRd05_SPAllowed is the implementation of the following encoding logic: +// Is the 64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field. +// bit range mappings: +// Rd: [0:5) +func encodeRd05_SPAllowed(v uint32) (uint32, bool) { + if v == REG_R31 { + return 0, false + } + if v == REG_RSP { + return 31, true + } + return v & 31, true +} + // encodeRd05 is the implementation of the following encoding logic: // Is the 64-bit name of the destination general-purpose register, encoded in the "Rd" field. // bit range mappings: @@ -534,6 +754,162 @@ func encodeXdn05(v uint32) (uint32, bool) { return v & 31, true } +// encodeRn1621_SPAllowed is the implementation of the following encoding logic: +// Is the 64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field. +// bit range mappings: +// Rn: [16:21) +func encodeRn1621_SPAllowed(v uint32) (uint32, bool) { + if v == REG_R31 { + return 0, false + } + if v == REG_RSP { + return 31 << 16, true + } + return (v & 31) << 16, true +} + +// encodeRot90_270_1011 is the implementation of the following encoding logic: +// Is the const specifier, +// rot <const> +// 0 #90 +// 1 #270 +// bit range mappings: +// rot: [10:11) +func encodeRot90_270_1011(v uint32) (uint32, bool) { + switch v { + case 90: + return 0, true + case 270: + return 1 << 10, true + } + return 0, false +} + +// encodeRot90_270_1617 is the implementation of the following encoding logic: +// Is the const specifier, +// rot <const> +// 0 #90 +// 1 #270 +// bit range mappings: +// rot: [16:17) +func encodeRot90_270_1617(v uint32) (uint32, bool) { + switch v { + case 90: + return 0, true + case 270: + return 1 << 16, true + } + return 0, false +} + +// encodeRot0_90_180_270_1012 is the implementation of the following encoding logic: +// Is the const specifier, +// rot <const> +// 00 #0 +// 01 #90 +// 10 #180 +// 11 #270 +// bit range mappings: +// rot: [10:12) +func encodeRot0_90_180_270_1012(v uint32) (uint32, bool) { + switch v { + case 0: + return 0, true + case 90: + return 1 << 10, true + case 180: + return 2 << 10, true + case 270: + return 3 << 10, true + } + return 0, false +} + +// encodeRot0_90_180_270_1315 is the implementation of the following encoding logic: +// Is the const specifier, +// rot <const> +// 00 #0 +// 01 #90 +// 10 #180 +// 11 #270 +// bit range mappings: +// rot: [13:15) +func encodeRot0_90_180_270_1315(v uint32) (uint32, bool) { + switch v { + case 0: + return 0, true + case 90: + return 1 << 13, true + case 180: + return 2 << 13, true + case 270: + return 3 << 13, true + } + return 0, false +} + +// encodeImm5Signed_510 is the implementation of the following encoding logic: +// Is the first signed immediate operand, in the range -16 to 15, encoded in the "imm5" field. +// bit range mappings: +// imm5: [5:10) +func encodeImm5Signed_510(v uint32) (uint32, bool) { + if int32(v) >= -16 && int32(v) <= 15 { + return (v & 31) << 5, true + } + return 0, false +} + +// encodeFimm0_0_1_0_56 is the implementation of the following encoding logic: +// Is the floating-point immediate value, +// i1 <const> +// 0 #0.0 +// 1 #1.0 +// bit range mappings: +// i1: [5:6) +func encodeFimm0_0_1_0_56(v uint32) (uint32, bool) { + switch v { + case 0: + return 0, true + case 0x3F800000: // 1.0 + return 1 << 5, true + } + return 0, false +} + +// encodeFimm0_5_1_0_56 is the implementation of the following encoding logic: +// Is the floating-point immediate value, +// i1 <const> +// 0 #0.5 +// 1 #1.0 +// bit range mappings: +// i1: [5:6) +func encodeFimm0_5_1_0_56(v uint32) (uint32, bool) { + switch v { + case 0x3F000000: // 0.5 + return 0, true + case 0x3F800000: // 1.0 + return 1 << 5, true + } + return 0, false +} + +// encodeFimm0_5_2_0_56 is the implementation of the following encoding logic: +// Is the floating-point immediate value, +// i1 <const> +// 0 #0.5 +// 1 #2.0 +// bit range mappings: +// i1: [5:6) +func encodeFimm0_5_2_0_56(v uint32) (uint32, bool) { + switch v { + case 0x3F000000: // 0.5 + return 0, true + case 0x40000000: // 2.0 + return 1 << 5, true + } + return 0, false +} + // encodeI2_1921_8BitGroup is the implementation of the following encoding logic: // Is the immediate index of a 32-bit group of four 8-bit values within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field. // bit range mappings: @@ -626,6 +1002,66 @@ func encodeImm2Tsz_Delegate(v uint32) (uint32, bool) { return codeImm2Tsz, false } +// encodeShiftTsz1619Range0V1 is the implementation of the following encoding logic: +// Is the immediate shift amount, in the range 0 to number of bits per element minus 1, encoded in "tszh:tszl:imm3". +// bit range mappings: +// imm3: [16:19) +// tszh: [22:23) +// tszl: [19:21) +func encodeShiftTsz1619Range0V1(v uint32) (uint32, bool) { + return codeShift161919212223, false +} + +// encodeShiftTsz1619Range0V2 is the implementation of the following encoding logic: +// Is the immediate shift amount, in the range 0 to number of bits per element minus 1, encoded in "tszh:tszl:imm3". +// bit range mappings: +// imm3: [16:19) +// tszh: [22:24) +// tszl: [19:21) +func encodeShiftTsz1619Range0V2(v uint32) (uint32, bool) { + return codeShift161919212224, false +} + +// encodeShiftTsz58Range0 is the implementation of the following encoding logic: +// Is the immediate shift amount, in the range 0 to number of bits per element minus 1, encoded in "tszh:tszl:imm3". +// bit range mappings: +// imm3: [5:8) +// tszh: [22:24) +// tszl: [8:10) +func encodeShiftTsz58Range0(v uint32) (uint32, bool) { + return codeShift588102224, false +} + +// encodeShiftTsz1619Range1V1 is the implementation of the following encoding logic: +// Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3". +// bit range mappings: +// imm3: [16:19) +// tszh: [22:23) +// tszl: [19:21) +func encodeShiftTsz1619Range1V1(v uint32) (uint32, bool) { + return codeShift161919212223, false +} + +// encodeShiftTsz1619Range1V2 is the implementation of the following encoding logic: +// Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3". +// bit range mappings: +// imm3: [16:19) +// tszh: [22:24) +// tszl: [19:21) +func encodeShiftTsz1619Range1V2(v uint32) (uint32, bool) { + return codeShift161919212224, false +} + +// encodeShiftTsz58Range1 is the implementation of the following encoding logic: +// Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3". +// bit range mappings: +// imm3: [5:8) +// tszh: [22:24) +// tszl: [8:10) +func encodeShiftTsz58Range1(v uint32) (uint32, bool) { + return codeShift588102224, false +} + // encodeVd is the implementation of the following encoding logic: // Is the name of the destination SIMD&FP register, encoded in the "Vd" field. // bit range mappings: @@ -725,6 +1161,14 @@ func encodePg1014(v uint32) (uint32, bool) { return v << 10, true } +// encodePg1620 is the implementation of the following encoding logic: +// Is the name of the governing scalable predicate register, encoded in the "Pg" field. +// bit range mappings: +// Pg: [16:20) +func encodePg1620(v uint32) (uint32, bool) { + return v << 16, true +} + // encodePg59 is the implementation of the following encoding logic: // Is the name of the governing scalable predicate register, encoded in the "Pg" field. // bit range mappings: @@ -757,11 +1201,11 @@ func encodePm1620(v uint32) (uint32, bool) { return v << 16, true } -// encodeZm_1619_Range0_7 is the implementation of the following encoding logic: +// encodeZm_1619_Range0_7V2 is the implementation of the following encoding logic: // Is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field. // bit range mappings: // Zm: [16:19) -func encodeZm_1619_Range0_7(v uint32) (uint32, bool) { +func encodeZm_1619_Range0_7V2(v uint32) (uint32, bool) { if v <= 7 { return v << 16, true } @@ -1035,6 +1479,77 @@ func encodePredQualM45(v uint32) (uint32, bool) { return 0, false } +// encodeImm5bSigned_1621 is the implementation of the following encoding logic: +// Is the second signed immediate operand, in the range -16 to 15, encoded in the "imm5b" field. +// bit range mappings: +// imm5b: [16:21) +func encodeImm5bSigned_1621(v uint32) (uint32, bool) { + if int32(v) >= -16 && int32(v) <= 15 { + return (v & 31) << 16, true + } + return 0, false +} + +// encodeImm8Signed_513 is the implementation of the following encoding logic: +// Is the signed immediate operand, in the range -128 to 127, encoded in the "imm8" field. +// bit range mappings: +// imm8: [5:13) +func encodeImm8Signed_513(v uint32) (uint32, bool) { + if int32(v) >= -128 && int32(v) <= 127 { + return (v & 255) << 5, true + } + return 0, false +} + +// encodeImm5Signed_1621V1 is the implementation of the following encoding logic: +// Is the signed immediate operand, in the range -16 to 15, encoded in the "imm5" field. +// bit range mappings: +// imm5: [16:21) +func encodeImm5Signed_1621V1(v uint32) (uint32, bool) { + if int32(v) >= -16 && int32(v) <= 15 { + return (v & 31) << 16, true + } + return 0, false +} + +// encodeImm5Signed510Unique is the implementation of the following encoding logic: +// Is the signed immediate operand, in the range -16 to 15, encoded in the "imm5" field. +// bit range mappings: +// imm5: [5:10) +func encodeImm5Signed510Unique(v uint32) (uint32, bool) { + if int32(v) >= -16 && int32(v) <= 15 { + return (v & 31) << 5, true + } + return 0, false +} + +// encodeImm6Signed_511 is the implementation of the following encoding logic: +// Is the signed immediate operand, in the range -32 to 31, encoded in the "imm6" field. +// bit range mappings: +// imm6: [5:11) +func encodeImm6Signed_511(v uint32) (uint32, bool) { + if int32(v) >= -32 && int32(v) <= 31 { + return (v & 63) << 5, true + } + return 0, false +} + +// encodeSizeImm13NoOp is the implementation of the following encoding logic: +// Is the size specifier, +// imm13 <T> +// 0xxxxxx0xxxxx S +// 0xxxxxx10xxxx H +// 0xxxxxx110xxx B +// 0xxxxxx1110xx B +// 0xxxxxx11110x B +// 0xxxxxx11111x RESERVED +// 1xxxxxxxxxxxx D +// bit range mappings: +// imm13: [5:18) +func encodeSizeImm13NoOp(v uint32) (uint32, bool) { + return codeNoOp, false +} + // encodeSizeBHSD2224 is the implementation of the following encoding logic: // Is the size specifier, // size <T> @@ -1460,6 +1975,122 @@ func encodeTszhTszlBHS(v uint32) (uint32, bool) { return 0, false } +// encodeSizeBhsTsz1921 is the implementation of the following encoding logic: +// Is the size specifier, +// tszh tszl <T> +// 0 00 RESERVED +// 0 01 B +// 0 1x H +// 1 xx S +// bit range mappings: +// tszh: [22:23) +// tszl: [19:21) +func encodeSizeBhsTsz1921(v uint32) (uint32, bool) { + switch v { + case ARNG_B: + return 1 << 19, true + case ARNG_H: + return 2 << 19, true + case ARNG_S: + return 1 << 22, true + } + return 0, false +} + +// encodeSizeHsdTsz1921 is the implementation of the following encoding logic: +// Is the size specifier, +// tszh tszl <T> +// 0 00 RESERVED +// 0 01 H +// 0 1x S +// 1 xx D +// bit range mappings: +// tszh: [22:23) +// tszl: [19:21) +func encodeSizeHsdTsz1921(v uint32) (uint32, bool) { + switch v { + case ARNG_H: + return 1 << 19, true + case ARNG_S: + return 2 << 19, true + case ARNG_D: + return 1 << 22, true + } + return 0, false +} + +// encodeSizeBhsdTsz1921 is the implementation of the following encoding logic: +// Is the size specifier, +// tszh tszl <T> +// 00 00 RESERVED +// 00 01 B +// 00 1x H +// 01 xx S +// 1x xx D +// bit range mappings: +// tszh: [22:24) +// tszl: [19:21) +func encodeSizeBhsdTsz1921(v uint32) (uint32, bool) { + switch v { + case ARNG_B: + return 1 << 19, true + case ARNG_H: + return 2 << 19, true + case ARNG_S: + return 1 << 22, true + case ARNG_D: + return 1 << 23, true + } + return 0, false +} + +// encodeSizeBhsdTsz810 is the implementation of the following encoding logic: +// Is the size specifier, +// tszh tszl <T> +// 00 00 RESERVED +// 00 01 B +// 00 1x H +// 01 xx S +// 1x xx D +// bit range mappings: +// tszh: [22:24) +// tszl: [8:10) +func encodeSizeBhsdTsz810(v uint32) (uint32, bool) { + switch v { + case ARNG_B: + return 1 << 8, true + case ARNG_H: + return 2 << 8, true + case ARNG_S: + return 1 << 22, true + case ARNG_D: + return 1 << 23, true + } + return 0, false +} + +// encodeSizeBhsTsz1921Unique is the implementation of the following encoding logic: +// Is the size specifier, +// tszh tszl <Tb> +// 0 00 RESERVED +// 0 01 B +// 0 1x H +// 1 xx S +// bit range mappings: +// tszh: [22:23) +// tszl: [19:21) +func encodeSizeBhsTsz1921Unique(v uint32) (uint32, bool) { + switch v { + case ARNG_B: + return 1 << 19, true + case ARNG_H: + return 2 << 19, true + case ARNG_S: + return 1 << 22, true + } + return 0, false +} + // encodeTszhTszlTbHSD is the implementation of the following encoding logic: // Is the size specifier, // tszh tszl <Tb> @@ -1485,6 +2116,75 @@ func encodeTszhTszlTbHSD(v uint32) (uint32, bool) { return 0, false } +// encodeSizeHsdTsz1921Unique is the implementation of the following encoding logic: +// Is the size specifier, +// tszh tszl <Tb> +// 0 00 RESERVED +// 0 01 H +// 0 1x S +// 1 xx D +// bit range mappings: +// tszh: [22:23) +// tszl: [19:21) +func encodeSizeHsdTsz1921Unique(v uint32) (uint32, bool) { + switch v { + case ARNG_H: + return 1 << 19, true + case ARNG_S: + return 2 << 19, true + case ARNG_D: + return 1 << 22, true + } + return 0, false +} + +// encodeImm4Unsigned_1620 is the implementation of the following encoding logic: +// Is the unsigned immediate operand, in the range 0 to 15, encoded in the "imm4" field. +// bit range mappings: +// imm4: [16:20) +func encodeImm4Unsigned_1620(v uint32) (uint32, bool) { + if v <= 15 { + return v << 16, true + } + return 0, false +} + +// encodeImm8Unsigned_513 is the implementation of the following encoding logic: +// Is the unsigned immediate operand, in the range 0 to 255, encoded in the "imm8" field. +// bit range mappings: +// imm8: [5:13) +func encodeImm8Unsigned_513(v uint32) (uint32, bool) { + if v <= 255 { + return v << 5, true + } + return 0, false +} + +// encodeImm8hImm8l_Unsigned is the implementation of the following encoding logic: +// Is the unsigned immediate operand, in the range 0 to 255, encoded in the "imm8h:imm8l" fields. +// bit range mappings: +// imm8h: [16:21) +// imm8l: [10:13) +func encodeImm8hImm8l_Unsigned(v uint32) (uint32, bool) { + if v <= 255 { + l := v & 7 + h := v >> 3 + return (l << 10) | (h << 16), true + } + return 0, false +} + +// encodeImm3Unsigned_1619 is the implementation of the following encoding logic: +// Is the unsigned immediate operand, in the range 0 to 7, encoded in the "imm3" field. +// bit range mappings: +// imm3: [16:19) +func encodeImm3Unsigned_1619(v uint32) (uint32, bool) { + if v <= 7 { + return v << 16, true + } + return 0, false +} + // encodeNoop is the implementation of the following encoding logic: // No-op check, returns true func encodeNoop(v uint32) (uint32, bool) { diff --git a/src/cmd/internal/obj/arm64/goops_gen.go b/src/cmd/internal/obj/arm64/goops_gen.go index ba800712ca..f479bbd7df 100644 --- a/src/cmd/internal/obj/arm64/goops_gen.go +++ b/src/cmd/internal/obj/arm64/goops_gen.go @@ -5,7 +5,9 @@ package arm64 import "cmd/internal/obj" const ( - ACTERMEQ obj.As = ASVESTART + 1 + iota + AADDPL obj.As = ASVESTART + 1 + iota + AADDVL + ACTERMEQ ACTERMEQW ACTERMNE ACTERMNEW @@ -83,6 +85,7 @@ const ( APWRFFR APZIP1 APZIP2 + ARDVL ASETFFR AZABS AZADCLB @@ -106,6 +109,7 @@ const ( AZANDVH AZANDVS AZASR + AZASRD AZASRR AZBCAX AZBDEP @@ -138,6 +142,8 @@ const ( AZBSL AZBSL1N AZBSL2N + AZCADD + AZCDOT AZCLASTA AZCLASTAB AZCLASTAD @@ -152,6 +158,7 @@ const ( AZCLASTBW AZCLS AZCLZ + AZCMLA AZCMPEQ AZCMPGE AZCMPGT @@ -173,6 +180,7 @@ const ( AZCPYW AZDECP AZDUP + AZDUPM AZDUPQ AZDUPW AZEOR @@ -185,6 +193,8 @@ const ( AZEORVH AZEORVS AZEXPAND + AZEXT + AZEXTQ AZF1CVT AZF1CVTLT AZF2CVT @@ -204,12 +214,17 @@ const ( AZFADDVS AZFAMAX AZFAMIN + AZFCADD AZFCLAMP AZFCMEQ AZFCMGE AZFCMGT + AZFCMLA + AZFCMLE + AZFCMLT AZFCMNE AZFCMUO + AZFCPY AZFCVT AZFCVTLT AZFCVTNT @@ -220,6 +235,7 @@ const ( AZFDIV AZFDIVR AZFDOT + AZFDUP AZFEXPA AZFLOGB AZFMAD @@ -286,6 +302,7 @@ const ( AZFSQRT AZFSUB AZFSUBR + AZFTMAD AZFTSMUL AZFTSSEL AZHISTCNT @@ -347,6 +364,8 @@ const ( AZREVD AZREVH AZREVW + AZRSHRNB + AZRSHRNT AZRSUBHNB AZRSUBHNT AZSABA @@ -373,8 +392,11 @@ const ( AZSDOT AZSEL AZSHADD + AZSHRNB + AZSHRNT AZSHSUB AZSHSUBR + AZSLI AZSM4E AZSM4EKEY AZSMAX @@ -402,6 +424,7 @@ const ( AZSPLICE AZSQABS AZSQADD + AZSQCADD AZSQDECP AZSQDMLALB AZSQDMLALBT @@ -414,13 +437,23 @@ const ( AZSQDMULLT AZSQINCP AZSQNEG + AZSQRDCMLAH AZSQRDMLAH AZSQRDMLSH AZSQRDMULH AZSQRSHL AZSQRSHLR + AZSQRSHRNB + AZSQRSHRNT + AZSQRSHRUNB + AZSQRSHRUNT AZSQSHL AZSQSHLR + AZSQSHLU + AZSQSHRNB + AZSQSHRNT + AZSQSHRUNB + AZSQSHRUNT AZSQSUB AZSQSUBR AZSQXTNB @@ -428,8 +461,14 @@ const ( AZSQXTUNB AZSQXTUNT AZSRHADD + AZSRI AZSRSHL AZSRSHLR + AZSRSHR + AZSRSRA + AZSSHLLB + AZSSHLLT + AZSSRA AZSSUBLB AZSSUBLBT AZSSUBLT @@ -502,8 +541,12 @@ const ( AZUQINCP AZUQRSHL AZUQRSHLR + AZUQRSHRNB + AZUQRSHRNT AZUQSHL AZUQSHLR + AZUQSHRNB + AZUQSHRNT AZUQSUB AZUQSUBR AZUQXTNB @@ -512,10 +555,15 @@ const ( AZURHADD AZURSHL AZURSHLR + AZURSHR AZURSQRTE + AZURSRA AZUSDOT + AZUSHLLB + AZUSHLLT AZUSMMLA AZUSQADD + AZUSRA AZUSUBLB AZUSUBLT AZUSUBWB @@ -529,6 +577,7 @@ const ( AZUZP2 AZUZPQ1 AZUZPQ2 + AZXAR AZZIP1 AZZIP2 AZZIPQ1 diff --git a/src/cmd/internal/obj/arm64/inst.go b/src/cmd/internal/obj/arm64/inst.go index dd9c802aab..131d0211af 100644 --- a/src/cmd/internal/obj/arm64/inst.go +++ b/src/cmd/internal/obj/arm64/inst.go @@ -8,6 +8,8 @@ import ( "cmd/internal/obj" "fmt" "iter" + "math" + "math/bits" ) // instEncoder represents an instruction encoder. @@ -126,6 +128,9 @@ func aclass(a *obj.Addr) AClass { return AC_SPZGREG } } + if a.Type == obj.TYPE_CONST || a.Type == obj.TYPE_FCONST { + return AC_IMM + } panic("unknown AClass") } @@ -197,6 +202,28 @@ func addrComponent(a *obj.Addr, acl AClass, index int) uint32 { default: panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl)) } + // AClass: AC_IMM + // GNU mnemonic: <imm>, <shift> + // Go mnemonic: + // $imm<<shift + // Encoding: + // Type = TYPE_CONST or TYPE_FCONST + // Offset = imm (shift already applied) + case AC_IMM: + switch index { + case 0: + if a.Type == obj.TYPE_FCONST { + switch v := a.Val.(type) { + case float64: + return math.Float32bits(float32(v)) + default: + panic(fmt.Errorf("unknown float immediate value %v", a.Val)) + } + } + return uint32(a.Offset) + default: + panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl)) + } } // TODO: handle more AClasses. panic(fmt.Errorf("unknown AClass %d", acl)) @@ -204,6 +231,11 @@ func addrComponent(a *obj.Addr, acl AClass, index int) uint32 { var codeI1Tsz uint32 = 0xffffffff var codeImm2Tsz uint32 = 0xfffffffe +var codeShift161919212223 uint32 = 0xfffffffd +var codeShift161919212224 uint32 = 0xfffffffc +var codeShift588102224 uint32 = 0xfffffffb +var codeLogicalImmArrEncoding uint32 = 0xfffffffa +var codeNoOp uint32 = 0xfffffff9 // encodeI1Tsz is the implementation of the following encoding logic: // Is the immediate index, in the range 0 to one less than the number of elements in 128 bits, encoded in "i1:tsz". @@ -292,6 +324,203 @@ func encodeImm2Tsz(v, arr uint32) (uint32, bool) { } } +type arrAlignType int + +const ( + arrAlignBHSD arrAlignType = iota + arrAlignHSD + arrAlignBHS +) + +// encodeShiftTriple encodes an shift immediate value in "tszh:tszl:imm3". +// tszh, tszl, imm3 are in ranges, sorted by bit position. +// These shifts are also bounded by arrangement element size. +func encodeShiftTriple(v uint32, r [6]int, prevAddr *obj.Addr, op obj.As) (uint32, bool) { + // The previous op must be a scalable vector, and we need its arrangement. + acl := aclass(prevAddr) + if acl != AC_ARNG { + return 0, false + } + arr := addrComponent(prevAddr, acl, 1) // Get arrangement + elemBits := uint32(0) + switch arr { + case ARNG_B: + elemBits = 8 + case ARNG_H: + elemBits = 16 + case ARNG_S: + elemBits = 32 + case ARNG_D: + elemBits = 64 + default: + return 0, false + } + if v >= elemBits { + return 0, false + } + var C uint32 + // Unfortunately these information are in the decoding ASL. + // For these instructions, the esize (see comment in the switch below) + // is derived from the destination arrangement, however how this function is called is deriving + // the esize from one of the source. + // We need to address this discrepancy. + effectiveEsize := elemBits + switch op { + case AZRSHRNB, AZRSHRNT, AZSHRNB, AZSHRNT, AZSQRSHRNB, AZSQRSHRNT, AZSQRSHRUNB, AZSQRSHRUNT, + AZSQSHRNB, AZSQSHRNT, AZSQSHRUNB, AZSQSHRUNT, AZUQRSHRNB, AZUQRSHRNT, AZUQSHRNB, AZUQSHRNT: + effectiveEsize = elemBits / 2 + } + switch op { + case AZASR, AZLSR, AZURSHR, AZASRD, + AZRSHRNB, AZRSHRNT, AZSHRNB, AZSHRNT, AZSQRSHRNB, AZSQRSHRNT, AZSQRSHRUNB, AZSQRSHRUNT, + AZSQSHRNB, AZSQSHRNT, AZSQSHRUNB, AZSQSHRUNT, AZSRSHR, AZUQRSHRNB, AZUQRSHRNT, AZUQSHRNB, AZUQSHRNT, + AZURSRA, AZUSRA, AZXAR, AZSRI, AZSRSRA, AZSSRA: + // ASL: let shift : integer = (2 * esize) - UInt(tsize::imm3); + if v == 0 { + return 0, false + } + C = (2 * effectiveEsize) - v + default: + // ASL: let shift : integer = UInt(tsize::imm3) - esize; + C = effectiveEsize + v + } + var chunks [3]uint32 + for i := 0; i < 6; i += 2 { + chunks[i/2] = C & ((1 << (r[i+1] - r[i])) - 1) + C >>= (r[i+1] - r[i]) + } + return uint32((chunks[0] << r[0]) | + (chunks[1] << r[2]) | + (chunks[2] << r[4])), true +} + +// encodeLogicalImmEncoding is the implementation of the following encoding logic: +// Is the size specifier, +// imm13 <T> +// 0xxxxxx0xxxxx S +// 0xxxxxx10xxxx H +// 0xxxxxx110xxx B +// 0xxxxxx1110xx B +// 0xxxxxx11110x B +// 0xxxxxx11111x RESERVED +// 1xxxxxxxxxxxx D +// At the meantime: +// Is a 64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, +// each field containing a rotated run of non-zero bits, encoded in the "imm13" field. +// +// bit range mappings: +// imm13: [5:18) +// +// ARM created a "clever" recipe that can generate useful repeating 8-64 bit bitmasks. +// Instead of storing the literal binary number, the processor reads a 13-bit recipe +// using three fields (bits from high to low): +// N (1 bit), immr (6 bits), and imms (6 bits). +// +// How the recipe works: +// Every logical immediate represents a repeating pattern (like repeating tiles). The processor +// uses the three fields to figure out the size of the tile, how many 1s are in the tile, and +// how far to rotate it. +// The N bit combined with the upper bits of imms determines the width of the repeating block. +// Depending on these bits, the fundamental block can be 2, 4, 8, 16, 32, or 64 bits wide. +// The lower bits of imms dictate exactly how many contiguous 1s exist inside that block. +// The immr value tells the processor how many bits to rotate that block to the right. +// Finally, the resulting block is duplicated to fill a standard 64-bit lane. +func encodeLogicalImmArrEncoding(v uint32, adjacentAddr *obj.Addr) (uint32, bool) { + acl := aclass(adjacentAddr) + if acl != AC_ARNG { + return 0, false + } + arr := addrComponent(adjacentAddr, acl, 1) + + // Replicate the given immediate to fill a full 64-bit lane. + // This ensures our pattern-shrinking logic naturally respects the vector lane bounds. + var val uint64 + switch arr { + case ARNG_B: // 8-bit lane + v8 := uint64(v & 0xFF) + val = v8 * 0x0101010101010101 + case ARNG_H: // 16-bit lane + v16 := uint64(v & 0xFFFF) + val = v16 * 0x0001000100010001 + case ARNG_S: // 32-bit lane + v32 := uint64(v) + val = v32 | (v32 << 32) + case ARNG_D: // 64-bit lane + val = uint64(v) // Top 32 bits are implicitly 0 + default: + return 0, false + } + + // Reject all zeros or all ones (handled by MOV/EOR, invalid for AND/ORR immediates) + if val == 0 || val == ^uint64(0) { + return 0, false + } + + // Find the absolute smallest repeating pattern size (64 down to 2) + size := uint64(64) + for size > 2 { + half := size / 2 + mask := (uint64(1) << half) - 1 + lower := val & mask + upper := (val >> half) & mask + + // If the top half matches the bottom half, shrink our window + if lower == upper { + size = half + val = lower + } else { + break + } + } + + // Count the contiguous ones in this minimal pattern + mask := (uint64(1) << size) - 1 + val &= mask + ones := bits.OnesCount64(val) + + // Find the right-rotation (rot) needed to align the 1s at the bottom + expected := (uint64(1) << ones) - 1 + rot := -1 + for r := 0; r < int(size); r++ { + // Right rotate 'val' by 'r' bits within a 'size'-bit window + rotated := ((val >> r) | (val << (int(size) - r))) & mask + if rotated == expected { + rot = r + break + } + } + + if rot == -1 { + return 0, false + } + + // immr is the amount the hardware must right-rotate the base pattern. + // Since 'rot' is how much we right-rotated the target to find the base, + // the hardware needs the inverse rotation. + immr := uint32((int(size) - rot) % int(size)) + + // If we couldn't find a rotation that forms a perfect contiguous block of 1s, it's invalid. + if rot == -1 { + return 0, false + } + + // Encode N, immr, and imms + n := uint32(0) + if size == 64 { + n = 1 + } + + // The imms prefix is mathematically generated by (~(size*2 - 1) & 0x3F). + // We then OR it with the number of ones (minus 1). + imms := (uint32(^(size*2 - 1)) & 0x3F) | uint32(ones-1) + + // Construct the final 13-bit field: N (1) | immr (6) | imms (6) + imm13 := (n << 12) | (immr << 6) | imms + + // Shift by 5 to place imm13 into instruction bits [5:17] + return imm13 << 5, true +} + // tryEncode tries to encode p with i, it returns the encoded binary and ok signal. func (i *instEncoder) tryEncode(p *obj.Prog) (uint32, bool) { bin := i.fixedBits @@ -300,7 +529,11 @@ func (i *instEncoder) tryEncode(p *obj.Prog) (uint32, bool) { // The 2 instances of <Tb> must encode to the same value. encoded := map[component]uint32{} opIdx := 0 + var addrs []*obj.Addr for addr := range opsInProg(p) { + addrs = append(addrs, addr) + } + for ii, addr := range addrs { if opIdx >= len(i.args) { return 0, false } @@ -312,13 +545,36 @@ func (i *instEncoder) tryEncode(p *obj.Prog) (uint32, bool) { } for i, enc := range op.elemEncoders { val := addrComponent(addr, acl, i) + if (p.As == AZFCPY || p.As == AZFDUP) && acl == AC_IMM { + // These instructions expects ARM's 8-bit float encoding. + // Reinterpret the uint32 bits back as a float32, then convert to float64 for chipfloat7 + fval := float64(math.Float32frombits(val)) + encode := (&ctxt7{}).chipfloat7(fval) + if encode == -1 { + // Handle error or return false to indicate mismatch + return 0, false + } + val = uint32(encode) + } if b, ok := enc.fn(val); ok || b != 0 { + specialB := uint32(b) if !ok { + specialB = b switch b { case codeI1Tsz: b, ok = encodeI1Tsz(val, addrComponent(addr, acl, i-1)) case codeImm2Tsz: b, ok = encodeImm2Tsz(val, addrComponent(addr, acl, i-1)) + case codeShift161919212223: + b, ok = encodeShiftTriple(val, [6]int{16, 19, 19, 21, 22, 23}, addrs[ii+1], p.As) + case codeShift161919212224: + b, ok = encodeShiftTriple(val, [6]int{16, 19, 19, 21, 22, 24}, addrs[ii+1], p.As) + case codeShift588102224: + b, ok = encodeShiftTriple(val, [6]int{5, 8, 8, 10, 22, 24}, addrs[ii+1], p.As) + case codeLogicalImmArrEncoding: + b, ok = encodeLogicalImmArrEncoding(val, addrs[ii+1]) + case codeNoOp: + b, ok = 0, true default: panic(fmt.Errorf("unknown encoding function code %d", b)) } @@ -328,6 +584,10 @@ func (i *instEncoder) tryEncode(p *obj.Prog) (uint32, bool) { } bin |= b if _, ok := encoded[enc.comp]; ok && b != encoded[enc.comp] { + if specialB == codeNoOp { + // NoOp encodings don't need checks. + continue + } return 0, false } if enc.comp != enc_NIL { diff --git a/src/cmd/internal/obj/arm64/inst_gen.go b/src/cmd/internal/obj/arm64/inst_gen.go index b1370c531f..cd13e3e022 100644 --- a/src/cmd/internal/obj/arm64/inst_gen.go +++ b/src/cmd/internal/obj/arm64/inst_gen.go @@ -6,6 +6,24 @@ package arm64 // insts are grouped by [goOp]. var insts = [][]instEncoder{ + // ADDPL + { + // ADDPL #<imm>, <Xn|SP>, <Xd|SP> + { + goOp: AADDPL, + fixedBits: 0x4605000, + args: cimm__XnSP__XdSP, + }, + }, + // ADDVL + { + // ADDVL #<imm>, <Xn|SP>, <Xd|SP> + { + goOp: AADDVL, + fixedBits: 0x4205000, + args: cimm__XnSP__XdSP, + }, + }, // CTERMEQ { // CTERMEQ <R><m>, <R><n> @@ -714,6 +732,15 @@ var insts = [][]instEncoder{ args: Pm_T__Pn_T__Pd_T, }, }, + // RDVL + { + // RDVL #<imm>, <Xd> + { + goOp: ARDVL, + fixedBits: 0x4bf5000, + args: cimm__Xd, + }, + }, // SETFFR { // SETFFR @@ -770,6 +797,12 @@ var insts = [][]instEncoder{ fixedBits: 0x4200000, args: Zm_T__Zn_T__Zd_T__1, }, + // ZADD #<imm>{, <shift>}, <Zdn>.<T>, <Zdn>.<T> + { + goOp: AZADD, + fixedBits: 0x2520c000, + args: cimm__shift__Zdn_T__Zdn_T, + }, }, // ZADDHNB { @@ -878,17 +911,23 @@ var insts = [][]instEncoder{ }, // ZAND { + // ZAND <Zm>.D, <Zn>.D, <Zd>.D + { + goOp: AZAND, + fixedBits: 0x4203000, + args: Zm_D__Zn_D__Zd_D, + }, // ZAND <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> { goOp: AZAND, fixedBits: 0x41a0000, args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, - // ZAND <Zm>.D, <Zn>.D, <Zd>.D + // ZAND #<const>, <Zdn>.<T>, <Zdn>.<T> { goOp: AZAND, - fixedBits: 0x4203000, - args: Zm_D__Zn_D__Zd_D, + fixedBits: 0x5800000, + args: cconst__Zdn_T__Zdn_T, }, }, // ZANDQV @@ -938,12 +977,6 @@ var insts = [][]instEncoder{ }, // ZASR { - // ZASR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> - { - goOp: AZASR, - fixedBits: 0x4108000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, - }, // ZASR <Zm>.D, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> { goOp: AZASR, @@ -956,6 +989,33 @@ var insts = [][]instEncoder{ fixedBits: 0x4208000, args: Zm_D__Zn_T__Zd_T, }, + // ZASR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> + { + goOp: AZASR, + fixedBits: 0x4108000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZASR #<const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> + { + goOp: AZASR, + fixedBits: 0x4008000, + args: cconst__Zdn_T__PgM__Zdn_T__1, + }, + // ZASR #<const>, <Zn>.<T>, <Zd>.<T> + { + goOp: AZASR, + fixedBits: 0x4209000, + args: cconst__Zn_T__Zd_T__1, + }, + }, + // ZASRD + { + // ZASRD #<const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> + { + goOp: AZASRD, + fixedBits: 0x4048000, + args: cconst__Zdn_T__PgM__Zdn_T__1, + }, }, // ZASRR { @@ -1085,18 +1145,18 @@ var insts = [][]instEncoder{ }, // ZBFDOT { - // ZBFDOT <Zm>.H[<imm>], <Zn>.H, <Zda>.S - { - goOp: AZBFDOT, - fixedBits: 0x64604000, - args: Zm_H_imm___Zn_H__Zda_S__3, - }, // ZBFDOT <Zm>.H, <Zn>.H, <Zda>.S { goOp: AZBFDOT, fixedBits: 0x64608000, args: Zm_H__Zn_H__Zda_S, }, + // ZBFDOT <Zm>.H[<imm>], <Zn>.H, <Zda>.S + { + goOp: AZBFDOT, + fixedBits: 0x64604000, + args: Zm_H_imm___Zn_H__Zda_S__3, + }, }, // ZBFMAX { @@ -1136,93 +1196,93 @@ var insts = [][]instEncoder{ }, // ZBFMLA { - // ZBFMLA <Zm>.H[<imm>], <Zn>.H, <Zda>.H - { - goOp: AZBFMLA, - fixedBits: 0x64200800, - args: Zm_H_imm___Zn_H__Zda_H__2, - }, // ZBFMLA <Zm>.H, <Zn>.H, <Pg>/M, <Zda>.H { goOp: AZBFMLA, fixedBits: 0x65200000, args: Zm_H__Zn_H__PgM__Zda_H, }, + // ZBFMLA <Zm>.H[<imm>], <Zn>.H, <Zda>.H + { + goOp: AZBFMLA, + fixedBits: 0x64200800, + args: Zm_H_imm___Zn_H__Zda_H__2, + }, }, // ZBFMLALB { - // ZBFMLALB <Zm>.H[<imm>], <Zn>.H, <Zda>.S - { - goOp: AZBFMLALB, - fixedBits: 0x64e04000, - args: Zm_H_imm___Zn_H__Zda_S__2, - }, // ZBFMLALB <Zm>.H, <Zn>.H, <Zda>.S { goOp: AZBFMLALB, fixedBits: 0x64e08000, args: Zm_H__Zn_H__Zda_S, }, - }, - // ZBFMLALT - { - // ZBFMLALT <Zm>.H[<imm>], <Zn>.H, <Zda>.S + // ZBFMLALB <Zm>.H[<imm>], <Zn>.H, <Zda>.S { - goOp: AZBFMLALT, - fixedBits: 0x64e04400, + goOp: AZBFMLALB, + fixedBits: 0x64e04000, args: Zm_H_imm___Zn_H__Zda_S__2, }, + }, + // ZBFMLALT + { // ZBFMLALT <Zm>.H, <Zn>.H, <Zda>.S { goOp: AZBFMLALT, fixedBits: 0x64e08400, args: Zm_H__Zn_H__Zda_S, }, + // ZBFMLALT <Zm>.H[<imm>], <Zn>.H, <Zda>.S + { + goOp: AZBFMLALT, + fixedBits: 0x64e04400, + args: Zm_H_imm___Zn_H__Zda_S__2, + }, }, // ZBFMLS { - // ZBFMLS <Zm>.H[<imm>], <Zn>.H, <Zda>.H - { - goOp: AZBFMLS, - fixedBits: 0x64200c00, - args: Zm_H_imm___Zn_H__Zda_H__2, - }, // ZBFMLS <Zm>.H, <Zn>.H, <Pg>/M, <Zda>.H { goOp: AZBFMLS, fixedBits: 0x65202000, args: Zm_H__Zn_H__PgM__Zda_H, }, + // ZBFMLS <Zm>.H[<imm>], <Zn>.H, <Zda>.H + { + goOp: AZBFMLS, + fixedBits: 0x64200c00, + args: Zm_H_imm___Zn_H__Zda_H__2, + }, }, // ZBFMLSLB { - // ZBFMLSLB <Zm>.H[<imm>], <Zn>.H, <Zda>.S - { - goOp: AZBFMLSLB, - fixedBits: 0x64e06000, - args: Zm_H_imm___Zn_H__Zda_S__2, - }, // ZBFMLSLB <Zm>.H, <Zn>.H, <Zda>.S { goOp: AZBFMLSLB, fixedBits: 0x64e0a000, args: Zm_H__Zn_H__Zda_S, }, - }, - // ZBFMLSLT - { - // ZBFMLSLT <Zm>.H[<imm>], <Zn>.H, <Zda>.S + // ZBFMLSLB <Zm>.H[<imm>], <Zn>.H, <Zda>.S { - goOp: AZBFMLSLT, - fixedBits: 0x64e06400, + goOp: AZBFMLSLB, + fixedBits: 0x64e06000, args: Zm_H_imm___Zn_H__Zda_S__2, }, + }, + // ZBFMLSLT + { // ZBFMLSLT <Zm>.H, <Zn>.H, <Zda>.S { goOp: AZBFMLSLT, fixedBits: 0x64e0a400, args: Zm_H__Zn_H__Zda_S, }, + // ZBFMLSLT <Zm>.H[<imm>], <Zn>.H, <Zda>.S + { + goOp: AZBFMLSLT, + fixedBits: 0x64e06400, + args: Zm_H_imm___Zn_H__Zda_S__2, + }, }, // ZBFMMLA { @@ -1241,12 +1301,6 @@ var insts = [][]instEncoder{ }, // ZBFMUL { - // ZBFMUL <Zm>.H[<imm>], <Zn>.H, <Zd>.H - { - goOp: AZBFMUL, - fixedBits: 0x64202800, - args: Zm_H_imm___Zn_H__Zd_H__2, - }, // ZBFMUL <Zm>.H, <Zdn>.H, <Pg>/M, <Zdn>.H { goOp: AZBFMUL, @@ -1259,6 +1313,12 @@ var insts = [][]instEncoder{ fixedBits: 0x65000800, args: Zm_H__Zn_H__Zd_H, }, + // ZBFMUL <Zm>.H[<imm>], <Zn>.H, <Zd>.H + { + goOp: AZBFMUL, + fixedBits: 0x64202800, + args: Zm_H_imm___Zn_H__Zd_H__2, + }, }, // ZBFSCALE { @@ -1295,18 +1355,18 @@ var insts = [][]instEncoder{ }, // ZBIC { - // ZBIC <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> - { - goOp: AZBIC, - fixedBits: 0x41b0000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, - }, // ZBIC <Zm>.D, <Zn>.D, <Zd>.D { goOp: AZBIC, fixedBits: 0x4e03000, args: Zm_D__Zn_D__Zd_D, }, + // ZBIC <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> + { + goOp: AZBIC, + fixedBits: 0x41b0000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, }, // ZBSL { @@ -1335,20 +1395,50 @@ var insts = [][]instEncoder{ args: Zk_D__Zm_D__Zdn_D__Zdn_D, }, }, - // ZCLASTA + // ZCADD { - // ZCLASTA <Zm>.<T>, <R><dn>, <Pg>, <R><dn> + // ZCADD <const>, <Zm>.<T>, <Zdn>.<T>, <Zdn>.<T> { - goOp: AZCLASTA, - fixedBits: 0x5f0a000, - args: Zm_T__Rdn__Pg__Rdn, + goOp: AZCADD, + fixedBits: 0x4500d800, + args: const__Zm_T__Zdn_T__Zdn_T, }, + }, + // ZCDOT + { + // ZCDOT <const>, <Zm>.B[<imm>], <Zn>.B, <Zda>.S + { + goOp: AZCDOT, + fixedBits: 0x44a04000, + args: const__Zm_B_imm___Zn_B__Zda_S, + }, + // ZCDOT <const>, <Zm>.H[<imm>], <Zn>.H, <Zda>.D + { + goOp: AZCDOT, + fixedBits: 0x44e04000, + args: const__Zm_H_imm___Zn_H__Zda_D, + }, + // ZCDOT <const>, <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T> + { + goOp: AZCDOT, + fixedBits: 0x44801000, + args: const__Zm_Tb__Zn_Tb__Zda_T, + }, + }, + // ZCLASTA + { // ZCLASTA <Zm>.<T>, <Zdn>.<T>, <Pg>, <Zdn>.<T> { goOp: AZCLASTA, fixedBits: 0x5288000, args: Zm_T__Zdn_T__Pg__Zdn_T, }, + // ZCLASTA <Zm>.<T>, <R><dn>, <Pg>, <R><dn> + { + goOp: AZCLASTA, + fixedBits: 0x5f0a000, + args: Zm_T__Rdn__Pg__Rdn, + }, }, // ZCLASTAB { @@ -1397,18 +1487,18 @@ var insts = [][]instEncoder{ }, // ZCLASTB { - // ZCLASTB <Zm>.<T>, <R><dn>, <Pg>, <R><dn> - { - goOp: AZCLASTB, - fixedBits: 0x5f1a000, - args: Zm_T__Rdn__Pg__Rdn, - }, // ZCLASTB <Zm>.<T>, <Zdn>.<T>, <Pg>, <Zdn>.<T> { goOp: AZCLASTB, fixedBits: 0x5298000, args: Zm_T__Zdn_T__Pg__Zdn_T, }, + // ZCLASTB <Zm>.<T>, <R><dn>, <Pg>, <R><dn> + { + goOp: AZCLASTB, + fixedBits: 0x5f1a000, + args: Zm_T__Rdn__Pg__Rdn, + }, }, // ZCLASTBB { @@ -1485,19 +1575,46 @@ var insts = [][]instEncoder{ args: Zn_T__PgZ__Zd_T__2, }, }, + // ZCMLA + { + // ZCMLA <const>, <Zm>.H[<imm>], <Zn>.H, <Zda>.H + { + goOp: AZCMLA, + fixedBits: 0x44a06000, + args: const__Zm_H_imm___Zn_H__Zda_H__1, + }, + // ZCMLA <const>, <Zm>.S[<imm>], <Zn>.S, <Zda>.S + { + goOp: AZCMLA, + fixedBits: 0x44e06000, + args: const__Zm_S_imm___Zn_S__Zda_S__1, + }, + // ZCMLA <const>, <Zm>.<T>, <Zn>.<T>, <Zda>.<T> + { + goOp: AZCMLA, + fixedBits: 0x44002000, + args: const__Zm_T__Zn_T__Zda_T, + }, + }, // ZCMPEQ { + // ZCMPEQ <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T> + { + goOp: AZCMPEQ, + fixedBits: 0x24002000, + args: Zm_D__Zn_T__PgZ__Pd_T, + }, // ZCMPEQ <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T> { goOp: AZCMPEQ, fixedBits: 0x2400a000, args: Zm_T__Zn_T__PgZ__Pd_T__2, }, - // ZCMPEQ <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T> + // ZCMPEQ #<imm>, <Zn>.<T>, <Pg>/Z, <Pd>.<T> { goOp: AZCMPEQ, - fixedBits: 0x24002000, - args: Zm_D__Zn_T__PgZ__Pd_T, + fixedBits: 0x25008000, + args: cimm__Zn_T__PgZ__Pd_T__1, }, }, // ZCMPGE @@ -1514,50 +1631,74 @@ var insts = [][]instEncoder{ fixedBits: 0x24008000, args: Zm_T__Zn_T__PgZ__Pd_T__2, }, + // ZCMPGE #<imm>, <Zn>.<T>, <Pg>/Z, <Pd>.<T> + { + goOp: AZCMPGE, + fixedBits: 0x25000000, + args: cimm__Zn_T__PgZ__Pd_T__1, + }, }, // ZCMPGT { + // ZCMPGT <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T> + { + goOp: AZCMPGT, + fixedBits: 0x24004010, + args: Zm_D__Zn_T__PgZ__Pd_T, + }, // ZCMPGT <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T> { goOp: AZCMPGT, fixedBits: 0x24008010, args: Zm_T__Zn_T__PgZ__Pd_T__2, }, - // ZCMPGT <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T> + // ZCMPGT #<imm>, <Zn>.<T>, <Pg>/Z, <Pd>.<T> { goOp: AZCMPGT, - fixedBits: 0x24004010, - args: Zm_D__Zn_T__PgZ__Pd_T, + fixedBits: 0x25000010, + args: cimm__Zn_T__PgZ__Pd_T__1, }, }, // ZCMPHI { + // ZCMPHI <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T> + { + goOp: AZCMPHI, + fixedBits: 0x2400c010, + args: Zm_D__Zn_T__PgZ__Pd_T, + }, // ZCMPHI <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T> { goOp: AZCMPHI, fixedBits: 0x24000010, args: Zm_T__Zn_T__PgZ__Pd_T__2, }, - // ZCMPHI <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T> + // ZCMPHI #<imm>, <Zn>.<T>, <Pg>/Z, <Pd>.<T> { goOp: AZCMPHI, - fixedBits: 0x2400c010, - args: Zm_D__Zn_T__PgZ__Pd_T, + fixedBits: 0x24200010, + args: cimm__Zn_T__PgZ__Pd_T__2, }, }, // ZCMPHS { + // ZCMPHS <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T> + { + goOp: AZCMPHS, + fixedBits: 0x2400c000, + args: Zm_D__Zn_T__PgZ__Pd_T, + }, // ZCMPHS <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T> { goOp: AZCMPHS, fixedBits: 0x24000000, args: Zm_T__Zn_T__PgZ__Pd_T__2, }, - // ZCMPHS <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T> + // ZCMPHS #<imm>, <Zn>.<T>, <Pg>/Z, <Pd>.<T> { goOp: AZCMPHS, - fixedBits: 0x2400c000, - args: Zm_D__Zn_T__PgZ__Pd_T, + fixedBits: 0x24200000, + args: cimm__Zn_T__PgZ__Pd_T__2, }, }, // ZCMPLE @@ -1568,6 +1709,12 @@ var insts = [][]instEncoder{ fixedBits: 0x24006010, args: Zm_D__Zn_T__PgZ__Pd_T, }, + // ZCMPLE #<imm>, <Zn>.<T>, <Pg>/Z, <Pd>.<T> + { + goOp: AZCMPLE, + fixedBits: 0x25002010, + args: cimm__Zn_T__PgZ__Pd_T__1, + }, }, // ZCMPLO { @@ -1577,6 +1724,12 @@ var insts = [][]instEncoder{ fixedBits: 0x2400e000, args: Zm_D__Zn_T__PgZ__Pd_T, }, + // ZCMPLO #<imm>, <Zn>.<T>, <Pg>/Z, <Pd>.<T> + { + goOp: AZCMPLO, + fixedBits: 0x24202000, + args: cimm__Zn_T__PgZ__Pd_T__2, + }, }, // ZCMPLS { @@ -1586,6 +1739,12 @@ var insts = [][]instEncoder{ fixedBits: 0x2400e010, args: Zm_D__Zn_T__PgZ__Pd_T, }, + // ZCMPLS #<imm>, <Zn>.<T>, <Pg>/Z, <Pd>.<T> + { + goOp: AZCMPLS, + fixedBits: 0x24202010, + args: cimm__Zn_T__PgZ__Pd_T__2, + }, }, // ZCMPLT { @@ -1595,6 +1754,12 @@ var insts = [][]instEncoder{ fixedBits: 0x24006000, args: Zm_D__Zn_T__PgZ__Pd_T, }, + // ZCMPLT #<imm>, <Zn>.<T>, <Pg>/Z, <Pd>.<T> + { + goOp: AZCMPLT, + fixedBits: 0x25002000, + args: cimm__Zn_T__PgZ__Pd_T__1, + }, }, // ZCMPNE { @@ -1610,21 +1775,27 @@ var insts = [][]instEncoder{ fixedBits: 0x2400a010, args: Zm_T__Zn_T__PgZ__Pd_T__2, }, + // ZCMPNE #<imm>, <Zn>.<T>, <Pg>/Z, <Pd>.<T> + { + goOp: AZCMPNE, + fixedBits: 0x25008010, + args: cimm__Zn_T__PgZ__Pd_T__1, + }, }, // ZCNOT { - // ZCNOT <Zn>.<T>, <Pg>/Z, <Zd>.<T> - { - goOp: AZCNOT, - fixedBits: 0x40ba000, - args: Zn_T__PgZ__Zd_T__2, - }, // ZCNOT <Zn>.<T>, <Pg>/M, <Zd>.<T> { goOp: AZCNOT, fixedBits: 0x41ba000, args: Zn_T__PgM__Zd_T__2, }, + // ZCNOT <Zn>.<T>, <Pg>/Z, <Zd>.<T> + { + goOp: AZCNOT, + fixedBits: 0x40ba000, + args: Zn_T__PgZ__Zd_T__2, + }, }, // ZCNT { @@ -1646,14 +1817,14 @@ var insts = [][]instEncoder{ // ZCOMPACT <Zn>.<T>, <Pg>, <Zd>.<T> { goOp: AZCOMPACT, - fixedBits: 0x5a18000, - args: Zn_T__Pg__Zd_T__2, + fixedBits: 0x5218000, + args: Zn_T__Pg__Zd_T__1, }, // ZCOMPACT <Zn>.<T>, <Pg>, <Zd>.<T> { goOp: AZCOMPACT, - fixedBits: 0x5218000, - args: Zn_T__Pg__Zd_T__1, + fixedBits: 0x5a18000, + args: Zn_T__Pg__Zd_T__2, }, }, // ZCPY @@ -1664,6 +1835,18 @@ var insts = [][]instEncoder{ fixedBits: 0x5e8a000, args: RnSP__PgM__Zd_T, }, + // ZCPY #<imm>{, <shift>}, <Pg>/M, <Zd>.<T> + { + goOp: AZCPY, + fixedBits: 0x5104000, + args: cimm__shift__PgM__Zd_T, + }, + // ZCPY #<imm>{, <shift>}, <Pg>/Z, <Zd>.<T> + { + goOp: AZCPY, + fixedBits: 0x5100000, + args: cimm__shift__PgZ__Zd_T, + }, }, // ZCPYB { @@ -1733,6 +1916,21 @@ var insts = [][]instEncoder{ fixedBits: 0x5202000, args: Zn_T_imm___Zd_T__1, }, + // ZDUP #<imm>{, <shift>}, <Zd>.<T> + { + goOp: AZDUP, + fixedBits: 0x2538c000, + args: cimm__shift__Zd_T, + }, + }, + // ZDUPM + { + // ZDUPM #<const>, <Zd>.<T> + { + goOp: AZDUPM, + fixedBits: 0x5c00000, + args: cconst__Zd_T__1, + }, }, // ZDUPQ { @@ -1754,17 +1952,23 @@ var insts = [][]instEncoder{ }, // ZEOR { + // ZEOR <Zm>.D, <Zn>.D, <Zd>.D + { + goOp: AZEOR, + fixedBits: 0x4a03000, + args: Zm_D__Zn_D__Zd_D, + }, // ZEOR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> { goOp: AZEOR, fixedBits: 0x4190000, args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, - // ZEOR <Zm>.D, <Zn>.D, <Zd>.D + // ZEOR #<const>, <Zdn>.<T>, <Zdn>.<T> { goOp: AZEOR, - fixedBits: 0x4a03000, - args: Zm_D__Zn_D__Zd_D, + fixedBits: 0x5400000, + args: cconst__Zdn_T__Zdn_T, }, }, // ZEOR3 @@ -1848,6 +2052,24 @@ var insts = [][]instEncoder{ args: Zn_T__Pg__Zd_T__3, }, }, + // ZEXT + { + // ZEXT #<imm>, <Zm>.B, <Zdn>.B, <Zdn>.B + { + goOp: AZEXT, + fixedBits: 0x5200000, + args: cimm__Zm_B__Zdn_B__Zdn_B__1, + }, + }, + // ZEXTQ + { + // ZEXTQ #<imm>, <Zm>.B, <Zdn>.B, <Zdn>.B + { + goOp: AZEXTQ, + fixedBits: 0x5602400, + args: cimm__Zm_B__Zdn_B__Zdn_B__2, + }, + }, // ZF1CVT { // ZF1CVT <Zn>.B, <Zd>.H @@ -1895,18 +2117,18 @@ var insts = [][]instEncoder{ }, // ZFABS { - // ZFABS <Zn>.<T>, <Pg>/Z, <Zd>.<T> - { - goOp: AZFABS, - fixedBits: 0x40ca000, - args: Zn_T__PgZ__Zd_T__1, - }, // ZFABS <Zn>.<T>, <Pg>/M, <Zd>.<T> { goOp: AZFABS, fixedBits: 0x41ca000, args: Zn_T__PgM__Zd_T__1, }, + // ZFABS <Zn>.<T>, <Pg>/Z, <Zd>.<T> + { + goOp: AZFABS, + fixedBits: 0x40ca000, + args: Zn_T__PgZ__Zd_T__1, + }, }, // ZFACGE { @@ -1928,17 +2150,23 @@ var insts = [][]instEncoder{ }, // ZFADD { + // ZFADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> + { + goOp: AZFADD, + fixedBits: 0x65008000, + args: Zm_T__Zdn_T__PgM__Zdn_T__3, + }, // ZFADD <Zm>.<T>, <Zn>.<T>, <Zd>.<T> { goOp: AZFADD, fixedBits: 0x65000000, args: Zm_T__Zn_T__Zd_T__2, }, - // ZFADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> + // ZFADD <const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> { goOp: AZFADD, - fixedBits: 0x65008000, - args: Zm_T__Zdn_T__PgM__Zdn_T__3, + fixedBits: 0x65188000, + args: const__Zdn_T__PgM__Zdn_T__2, }, }, // ZFADDAD @@ -2031,6 +2259,15 @@ var insts = [][]instEncoder{ args: Zm_T__Zdn_T__PgM__Zdn_T__2, }, }, + // ZFCADD + { + // ZFCADD <const>, <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> + { + goOp: AZFCADD, + fixedBits: 0x64008000, + args: const__Zm_T__Zdn_T__PgM__Zdn_T, + }, + }, // ZFCLAMP { // ZFCLAMP <Zm>.<T>, <Zn>.<T>, <Zd>.<T> @@ -2048,6 +2285,12 @@ var insts = [][]instEncoder{ fixedBits: 0x65006000, args: Zm_T__Zn_T__PgZ__Pd_T__1, }, + // ZFCMEQ #0.0, <Zn>.<T>, <Pg>/Z, <Pd>.<T> + { + goOp: AZFCMEQ, + fixedBits: 0x65122000, + args: c0_0__Zn_T__PgZ__Pd_T, + }, }, // ZFCMGE { @@ -2057,6 +2300,12 @@ var insts = [][]instEncoder{ fixedBits: 0x65004000, args: Zm_T__Zn_T__PgZ__Pd_T__1, }, + // ZFCMGE #0.0, <Zn>.<T>, <Pg>/Z, <Pd>.<T> + { + goOp: AZFCMGE, + fixedBits: 0x65102000, + args: c0_0__Zn_T__PgZ__Pd_T, + }, }, // ZFCMGT { @@ -2066,6 +2315,51 @@ var insts = [][]instEncoder{ fixedBits: 0x65004010, args: Zm_T__Zn_T__PgZ__Pd_T__1, }, + // ZFCMGT #0.0, <Zn>.<T>, <Pg>/Z, <Pd>.<T> + { + goOp: AZFCMGT, + fixedBits: 0x65102010, + args: c0_0__Zn_T__PgZ__Pd_T, + }, + }, + // ZFCMLA + { + // ZFCMLA <const>, <Zm>.H[<imm>], <Zn>.H, <Zda>.H + { + goOp: AZFCMLA, + fixedBits: 0x64a01000, + args: const__Zm_H_imm___Zn_H__Zda_H__2, + }, + // ZFCMLA <const>, <Zm>.S[<imm>], <Zn>.S, <Zda>.S + { + goOp: AZFCMLA, + fixedBits: 0x64e01000, + args: const__Zm_S_imm___Zn_S__Zda_S__2, + }, + // ZFCMLA <const>, <Zm>.<T>, <Zn>.<T>, <Pg>/M, <Zda>.<T> + { + goOp: AZFCMLA, + fixedBits: 0x64000000, + args: const__Zm_T__Zn_T__PgM__Zda_T, + }, + }, + // ZFCMLE + { + // ZFCMLE #0.0, <Zn>.<T>, <Pg>/Z, <Pd>.<T> + { + goOp: AZFCMLE, + fixedBits: 0x65112010, + args: c0_0__Zn_T__PgZ__Pd_T, + }, + }, + // ZFCMLT + { + // ZFCMLT #0.0, <Zn>.<T>, <Pg>/Z, <Pd>.<T> + { + goOp: AZFCMLT, + fixedBits: 0x65112000, + args: c0_0__Zn_T__PgZ__Pd_T, + }, }, // ZFCMNE { @@ -2075,6 +2369,12 @@ var insts = [][]instEncoder{ fixedBits: 0x65006010, args: Zm_T__Zn_T__PgZ__Pd_T__1, }, + // ZFCMNE #0.0, <Zn>.<T>, <Pg>/Z, <Pd>.<T> + { + goOp: AZFCMNE, + fixedBits: 0x65132000, + args: c0_0__Zn_T__PgZ__Pd_T, + }, }, // ZFCMUO { @@ -2085,25 +2385,40 @@ var insts = [][]instEncoder{ args: Zm_T__Zn_T__PgZ__Pd_T__1, }, }, + // ZFCPY + { + // ZFCPY #<const>, <Pg>/M, <Zd>.<T> + { + goOp: AZFCPY, + fixedBits: 0x510c000, + args: cconst__PgM__Zd_T, + }, + }, // ZFCVT { - // ZFCVT <Zn>.S, <Pg>/Z, <Zd>.H + // ZFCVT <Zn>.D, <Pg>/M, <Zd>.H { goOp: AZFCVT, - fixedBits: 0x649a8000, - args: Zn_S__PgZ__Zd_H, + fixedBits: 0x65c8a000, + args: Zn_D__PgM__Zd_H, }, - // ZFCVT <Zn>.S, <Pg>/M, <Zd>.D + // ZFCVT <Zn>.D, <Pg>/M, <Zd>.S { goOp: AZFCVT, - fixedBits: 0x65cba000, - args: Zn_S__PgM__Zd_D, + fixedBits: 0x65caa000, + args: Zn_D__PgM__Zd_S, }, - // ZFCVT <Zn>.H, <Pg>/Z, <Zd>.S + // ZFCVT <Zn>.D, <Pg>/Z, <Zd>.H { goOp: AZFCVT, - fixedBits: 0x649aa000, - args: Zn_H__PgZ__Zd_S, + fixedBits: 0x64da8000, + args: Zn_D__PgZ__Zd_H, + }, + // ZFCVT <Zn>.D, <Pg>/Z, <Zd>.S + { + goOp: AZFCVT, + fixedBits: 0x64dac000, + args: Zn_D__PgZ__Zd_S, }, // ZFCVT <Zn>.H, <Pg>/M, <Zd>.D { @@ -2111,29 +2426,35 @@ var insts = [][]instEncoder{ fixedBits: 0x65c9a000, args: Zn_H__PgM__Zd_D, }, + // ZFCVT <Zn>.H, <Pg>/M, <Zd>.S + { + goOp: AZFCVT, + fixedBits: 0x6589a000, + args: Zn_H__PgM__Zd_S, + }, // ZFCVT <Zn>.H, <Pg>/Z, <Zd>.D { goOp: AZFCVT, fixedBits: 0x64daa000, args: Zn_H__PgZ__Zd_D, }, - // ZFCVT <Zn>.S, <Pg>/M, <Zd>.H + // ZFCVT <Zn>.H, <Pg>/Z, <Zd>.S { goOp: AZFCVT, - fixedBits: 0x6588a000, - args: Zn_S__PgM__Zd_H, + fixedBits: 0x649aa000, + args: Zn_H__PgZ__Zd_S, }, - // ZFCVT <Zn>.D, <Pg>/Z, <Zd>.S + // ZFCVT <Zn>.S, <Pg>/M, <Zd>.D { goOp: AZFCVT, - fixedBits: 0x64dac000, - args: Zn_D__PgZ__Zd_S, + fixedBits: 0x65cba000, + args: Zn_S__PgM__Zd_D, }, - // ZFCVT <Zn>.H, <Pg>/M, <Zd>.S + // ZFCVT <Zn>.S, <Pg>/M, <Zd>.H { goOp: AZFCVT, - fixedBits: 0x6589a000, - args: Zn_H__PgM__Zd_S, + fixedBits: 0x6588a000, + args: Zn_S__PgM__Zd_H, }, // ZFCVT <Zn>.S, <Pg>/Z, <Zd>.D { @@ -2141,33 +2462,15 @@ var insts = [][]instEncoder{ fixedBits: 0x64dae000, args: Zn_S__PgZ__Zd_D, }, - // ZFCVT <Zn>.D, <Pg>/M, <Zd>.H - { - goOp: AZFCVT, - fixedBits: 0x65c8a000, - args: Zn_D__PgM__Zd_H, - }, - // ZFCVT <Zn>.D, <Pg>/Z, <Zd>.H - { - goOp: AZFCVT, - fixedBits: 0x64da8000, - args: Zn_D__PgZ__Zd_H, - }, - // ZFCVT <Zn>.D, <Pg>/M, <Zd>.S + // ZFCVT <Zn>.S, <Pg>/Z, <Zd>.H { goOp: AZFCVT, - fixedBits: 0x65caa000, - args: Zn_D__PgM__Zd_S, + fixedBits: 0x649a8000, + args: Zn_S__PgZ__Zd_H, }, }, // ZFCVTLT { - // ZFCVTLT <Zn>.S, <Pg>/Z, <Zd>.D - { - goOp: AZFCVTLT, - fixedBits: 0x64c3a000, - args: Zn_S__PgZ__Zd_D, - }, // ZFCVTLT <Zn>.H, <Pg>/M, <Zd>.S { goOp: AZFCVTLT, @@ -2186,21 +2489,15 @@ var insts = [][]instEncoder{ fixedBits: 0x64cba000, args: Zn_S__PgM__Zd_D, }, + // ZFCVTLT <Zn>.S, <Pg>/Z, <Zd>.D + { + goOp: AZFCVTLT, + fixedBits: 0x64c3a000, + args: Zn_S__PgZ__Zd_D, + }, }, // ZFCVTNT { - // ZFCVTNT <Zn>.S, <Pg>/Z, <Zd>.H - { - goOp: AZFCVTNT, - fixedBits: 0x6480a000, - args: Zn_S__PgZ__Zd_H, - }, - // ZFCVTNT <Zn>.S, <Pg>/M, <Zd>.H - { - goOp: AZFCVTNT, - fixedBits: 0x6488a000, - args: Zn_S__PgM__Zd_H, - }, // ZFCVTNT <Zn>.D, <Pg>/M, <Zd>.S { goOp: AZFCVTNT, @@ -2213,6 +2510,18 @@ var insts = [][]instEncoder{ fixedBits: 0x64c2a000, args: Zn_D__PgZ__Zd_S, }, + // ZFCVTNT <Zn>.S, <Pg>/M, <Zd>.H + { + goOp: AZFCVTNT, + fixedBits: 0x6488a000, + args: Zn_S__PgM__Zd_H, + }, + // ZFCVTNT <Zn>.S, <Pg>/Z, <Zd>.H + { + goOp: AZFCVTNT, + fixedBits: 0x6480a000, + args: Zn_S__PgZ__Zd_H, + }, }, // ZFCVTX { @@ -2231,38 +2540,32 @@ var insts = [][]instEncoder{ }, // ZFCVTXNT { - // ZFCVTXNT <Zn>.D, <Pg>/Z, <Zd>.S - { - goOp: AZFCVTXNT, - fixedBits: 0x6402a000, - args: Zn_D__PgZ__Zd_S, - }, // ZFCVTXNT <Zn>.D, <Pg>/M, <Zd>.S { goOp: AZFCVTXNT, fixedBits: 0x640aa000, args: Zn_D__PgM__Zd_S, }, + // ZFCVTXNT <Zn>.D, <Pg>/Z, <Zd>.S + { + goOp: AZFCVTXNT, + fixedBits: 0x6402a000, + args: Zn_D__PgZ__Zd_S, + }, }, // ZFCVTZS { - // ZFCVTZS <Zn>.H, <Pg>/M, <Zd>.S - { - goOp: AZFCVTZS, - fixedBits: 0x655ca000, - args: Zn_H__PgM__Zd_S, - }, - // ZFCVTZS <Zn>.S, <Pg>/M, <Zd>.S + // ZFCVTZS <Zn>.D, <Pg>/M, <Zd>.D { goOp: AZFCVTZS, - fixedBits: 0x659ca000, - args: Zn_S__PgM__Zd_S, + fixedBits: 0x65dea000, + args: Zn_D__PgM__Zd_D, }, - // ZFCVTZS <Zn>.H, <Pg>/Z, <Zd>.H + // ZFCVTZS <Zn>.D, <Pg>/M, <Zd>.S { goOp: AZFCVTZS, - fixedBits: 0x645ec000, - args: Zn_H__PgZ__Zd_H, + fixedBits: 0x65d8a000, + args: Zn_D__PgM__Zd_S, }, // ZFCVTZS <Zn>.D, <Pg>/Z, <Zd>.D { @@ -2270,11 +2573,11 @@ var insts = [][]instEncoder{ fixedBits: 0x64dfc000, args: Zn_D__PgZ__Zd_D, }, - // ZFCVTZS <Zn>.H, <Pg>/Z, <Zd>.S + // ZFCVTZS <Zn>.D, <Pg>/Z, <Zd>.S { goOp: AZFCVTZS, - fixedBits: 0x645f8000, - args: Zn_H__PgZ__Zd_S, + fixedBits: 0x64de8000, + args: Zn_D__PgZ__Zd_S, }, // ZFCVTZS <Zn>.H, <Pg>/M, <Zd>.D { @@ -2282,23 +2585,35 @@ var insts = [][]instEncoder{ fixedBits: 0x655ea000, args: Zn_H__PgM__Zd_D, }, + // ZFCVTZS <Zn>.H, <Pg>/M, <Zd>.H + { + goOp: AZFCVTZS, + fixedBits: 0x655aa000, + args: Zn_H__PgM__Zd_H, + }, + // ZFCVTZS <Zn>.H, <Pg>/M, <Zd>.S + { + goOp: AZFCVTZS, + fixedBits: 0x655ca000, + args: Zn_H__PgM__Zd_S, + }, // ZFCVTZS <Zn>.H, <Pg>/Z, <Zd>.D { goOp: AZFCVTZS, fixedBits: 0x645fc000, args: Zn_H__PgZ__Zd_D, }, - // ZFCVTZS <Zn>.H, <Pg>/M, <Zd>.H + // ZFCVTZS <Zn>.H, <Pg>/Z, <Zd>.H { goOp: AZFCVTZS, - fixedBits: 0x655aa000, - args: Zn_H__PgM__Zd_H, + fixedBits: 0x645ec000, + args: Zn_H__PgZ__Zd_H, }, - // ZFCVTZS <Zn>.S, <Pg>/Z, <Zd>.S + // ZFCVTZS <Zn>.H, <Pg>/Z, <Zd>.S { goOp: AZFCVTZS, - fixedBits: 0x649f8000, - args: Zn_S__PgZ__Zd_S, + fixedBits: 0x645f8000, + args: Zn_H__PgZ__Zd_S, }, // ZFCVTZS <Zn>.S, <Pg>/M, <Zd>.D { @@ -2306,56 +2621,50 @@ var insts = [][]instEncoder{ fixedBits: 0x65dca000, args: Zn_S__PgM__Zd_D, }, - // ZFCVTZS <Zn>.S, <Pg>/Z, <Zd>.D - { - goOp: AZFCVTZS, - fixedBits: 0x64df8000, - args: Zn_S__PgZ__Zd_D, - }, - // ZFCVTZS <Zn>.D, <Pg>/M, <Zd>.S + // ZFCVTZS <Zn>.S, <Pg>/M, <Zd>.S { goOp: AZFCVTZS, - fixedBits: 0x65d8a000, - args: Zn_D__PgM__Zd_S, + fixedBits: 0x659ca000, + args: Zn_S__PgM__Zd_S, }, - // ZFCVTZS <Zn>.D, <Pg>/Z, <Zd>.S + // ZFCVTZS <Zn>.S, <Pg>/Z, <Zd>.D { goOp: AZFCVTZS, - fixedBits: 0x64de8000, - args: Zn_D__PgZ__Zd_S, + fixedBits: 0x64df8000, + args: Zn_S__PgZ__Zd_D, }, - // ZFCVTZS <Zn>.D, <Pg>/M, <Zd>.D + // ZFCVTZS <Zn>.S, <Pg>/Z, <Zd>.S { goOp: AZFCVTZS, - fixedBits: 0x65dea000, - args: Zn_D__PgM__Zd_D, + fixedBits: 0x649f8000, + args: Zn_S__PgZ__Zd_S, }, }, // ZFCVTZU { - // ZFCVTZU <Zn>.H, <Pg>/M, <Zd>.S + // ZFCVTZU <Zn>.D, <Pg>/M, <Zd>.D { goOp: AZFCVTZU, - fixedBits: 0x655da000, - args: Zn_H__PgM__Zd_S, + fixedBits: 0x65dfa000, + args: Zn_D__PgM__Zd_D, }, - // ZFCVTZU <Zn>.S, <Pg>/Z, <Zd>.S + // ZFCVTZU <Zn>.D, <Pg>/M, <Zd>.S { goOp: AZFCVTZU, - fixedBits: 0x649fa000, - args: Zn_S__PgZ__Zd_S, + fixedBits: 0x65d9a000, + args: Zn_D__PgM__Zd_S, }, - // ZFCVTZU <Zn>.H, <Pg>/Z, <Zd>.H + // ZFCVTZU <Zn>.D, <Pg>/Z, <Zd>.D { goOp: AZFCVTZU, - fixedBits: 0x645ee000, - args: Zn_H__PgZ__Zd_H, + fixedBits: 0x64dfe000, + args: Zn_D__PgZ__Zd_D, }, - // ZFCVTZU <Zn>.H, <Pg>/Z, <Zd>.S + // ZFCVTZU <Zn>.D, <Pg>/Z, <Zd>.S { goOp: AZFCVTZU, - fixedBits: 0x645fa000, - args: Zn_H__PgZ__Zd_S, + fixedBits: 0x64dea000, + args: Zn_D__PgZ__Zd_S, }, // ZFCVTZU <Zn>.H, <Pg>/M, <Zd>.D { @@ -2363,59 +2672,59 @@ var insts = [][]instEncoder{ fixedBits: 0x655fa000, args: Zn_H__PgM__Zd_D, }, - // ZFCVTZU <Zn>.H, <Pg>/Z, <Zd>.D + // ZFCVTZU <Zn>.H, <Pg>/M, <Zd>.H { goOp: AZFCVTZU, - fixedBits: 0x645fe000, - args: Zn_H__PgZ__Zd_D, + fixedBits: 0x655ba000, + args: Zn_H__PgM__Zd_H, }, - // ZFCVTZU <Zn>.S, <Pg>/M, <Zd>.S + // ZFCVTZU <Zn>.H, <Pg>/M, <Zd>.S { goOp: AZFCVTZU, - fixedBits: 0x659da000, - args: Zn_S__PgM__Zd_S, + fixedBits: 0x655da000, + args: Zn_H__PgM__Zd_S, }, - // ZFCVTZU <Zn>.H, <Pg>/M, <Zd>.H + // ZFCVTZU <Zn>.H, <Pg>/Z, <Zd>.D { goOp: AZFCVTZU, - fixedBits: 0x655ba000, - args: Zn_H__PgM__Zd_H, + fixedBits: 0x645fe000, + args: Zn_H__PgZ__Zd_D, }, - // ZFCVTZU <Zn>.S, <Pg>/M, <Zd>.D + // ZFCVTZU <Zn>.H, <Pg>/Z, <Zd>.H { goOp: AZFCVTZU, - fixedBits: 0x65dda000, - args: Zn_S__PgM__Zd_D, + fixedBits: 0x645ee000, + args: Zn_H__PgZ__Zd_H, }, - // ZFCVTZU <Zn>.S, <Pg>/Z, <Zd>.D + // ZFCVTZU <Zn>.H, <Pg>/Z, <Zd>.S { goOp: AZFCVTZU, - fixedBits: 0x64dfa000, - args: Zn_S__PgZ__Zd_D, + fixedBits: 0x645fa000, + args: Zn_H__PgZ__Zd_S, }, - // ZFCVTZU <Zn>.D, <Pg>/M, <Zd>.S + // ZFCVTZU <Zn>.S, <Pg>/M, <Zd>.D { goOp: AZFCVTZU, - fixedBits: 0x65d9a000, - args: Zn_D__PgM__Zd_S, + fixedBits: 0x65dda000, + args: Zn_S__PgM__Zd_D, }, - // ZFCVTZU <Zn>.D, <Pg>/Z, <Zd>.S + // ZFCVTZU <Zn>.S, <Pg>/M, <Zd>.S { goOp: AZFCVTZU, - fixedBits: 0x64dea000, - args: Zn_D__PgZ__Zd_S, + fixedBits: 0x659da000, + args: Zn_S__PgM__Zd_S, }, - // ZFCVTZU <Zn>.D, <Pg>/M, <Zd>.D + // ZFCVTZU <Zn>.S, <Pg>/Z, <Zd>.D { goOp: AZFCVTZU, - fixedBits: 0x65dfa000, - args: Zn_D__PgM__Zd_D, + fixedBits: 0x64dfa000, + args: Zn_S__PgZ__Zd_D, }, - // ZFCVTZU <Zn>.D, <Pg>/Z, <Zd>.D + // ZFCVTZU <Zn>.S, <Pg>/Z, <Zd>.S { goOp: AZFCVTZU, - fixedBits: 0x64dfe000, - args: Zn_D__PgZ__Zd_D, + fixedBits: 0x649fa000, + args: Zn_S__PgZ__Zd_S, }, }, // ZFDIV @@ -2438,17 +2747,17 @@ var insts = [][]instEncoder{ }, // ZFDOT { - // ZFDOT <Zm>.B[<imm>], <Zn>.B, <Zda>.H + // ZFDOT <Zm>.B, <Zn>.B, <Zda>.H { goOp: AZFDOT, - fixedBits: 0x64204400, - args: Zm_B_imm___Zn_B__Zda_H__3, + fixedBits: 0x64208400, + args: Zm_B__Zn_B__Zda_H, }, - // ZFDOT <Zm>.H[<imm>], <Zn>.H, <Zda>.S + // ZFDOT <Zm>.B, <Zn>.B, <Zda>.S { goOp: AZFDOT, - fixedBits: 0x64204000, - args: Zm_H_imm___Zn_H__Zda_S__3, + fixedBits: 0x64608400, + args: Zm_B__Zn_B__Zda_S, }, // ZFDOT <Zm>.H, <Zn>.H, <Zda>.S { @@ -2456,11 +2765,11 @@ var insts = [][]instEncoder{ fixedBits: 0x64208000, args: Zm_H__Zn_H__Zda_S, }, - // ZFDOT <Zm>.B, <Zn>.B, <Zda>.H + // ZFDOT <Zm>.B[<imm>], <Zn>.B, <Zda>.H { goOp: AZFDOT, - fixedBits: 0x64208400, - args: Zm_B__Zn_B__Zda_H, + fixedBits: 0x64204400, + args: Zm_B_imm___Zn_B__Zda_H__3, }, // ZFDOT <Zm>.B[<imm>], <Zn>.B, <Zda>.S { @@ -2468,11 +2777,20 @@ var insts = [][]instEncoder{ fixedBits: 0x64604400, args: Zm_B_imm___Zn_B__Zda_S__2, }, - // ZFDOT <Zm>.B, <Zn>.B, <Zda>.S + // ZFDOT <Zm>.H[<imm>], <Zn>.H, <Zda>.S { goOp: AZFDOT, - fixedBits: 0x64608400, - args: Zm_B__Zn_B__Zda_S, + fixedBits: 0x64204000, + args: Zm_H_imm___Zn_H__Zda_S__3, + }, + }, + // ZFDUP + { + // ZFDUP #<const>, <Zd>.<T> + { + goOp: AZFDUP, + fixedBits: 0x2539c000, + args: cconst__Zd_T__2, }, }, // ZFEXPA @@ -2516,6 +2834,12 @@ var insts = [][]instEncoder{ fixedBits: 0x65068000, args: Zm_T__Zdn_T__PgM__Zdn_T__3, }, + // ZFMAX <const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> + { + goOp: AZFMAX, + fixedBits: 0x651e8000, + args: const__Zdn_T__PgM__Zdn_T__1, + }, }, // ZFMAXNM { @@ -2525,6 +2849,12 @@ var insts = [][]instEncoder{ fixedBits: 0x65048000, args: Zm_T__Zdn_T__PgM__Zdn_T__3, }, + // ZFMAXNM <const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> + { + goOp: AZFMAXNM, + fixedBits: 0x651c8000, + args: const__Zdn_T__PgM__Zdn_T__1, + }, }, // ZFMAXNMP { @@ -2624,6 +2954,12 @@ var insts = [][]instEncoder{ fixedBits: 0x65078000, args: Zm_T__Zdn_T__PgM__Zdn_T__3, }, + // ZFMIN <const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> + { + goOp: AZFMIN, + fixedBits: 0x651f8000, + args: const__Zdn_T__PgM__Zdn_T__1, + }, }, // ZFMINNM { @@ -2633,6 +2969,12 @@ var insts = [][]instEncoder{ fixedBits: 0x65058000, args: Zm_T__Zdn_T__PgM__Zdn_T__3, }, + // ZFMINNM <const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> + { + goOp: AZFMINNM, + fixedBits: 0x651d8000, + args: const__Zdn_T__PgM__Zdn_T__1, + }, }, // ZFMINNMP { @@ -2726,18 +3068,18 @@ var insts = [][]instEncoder{ }, // ZFMLA { - // ZFMLA <Zm>.D[<imm>], <Zn>.D, <Zda>.D - { - goOp: AZFMLA, - fixedBits: 0x64e00000, - args: Zm_D_imm___Zn_D__Zda_D__2, - }, // ZFMLA <Zm>.<T>, <Zn>.<T>, <Pg>/M, <Zda>.<T> { goOp: AZFMLA, fixedBits: 0x65200000, args: Zm_T__Zn_T__PgM__Zda_T__1, }, + // ZFMLA <Zm>.D[<imm>], <Zn>.D, <Zda>.D + { + goOp: AZFMLA, + fixedBits: 0x64e00000, + args: Zm_D_imm___Zn_D__Zda_D__2, + }, // ZFMLA <Zm>.H[<imm>], <Zn>.H, <Zda>.H { goOp: AZFMLA, @@ -2753,23 +3095,17 @@ var insts = [][]instEncoder{ }, // ZFMLALB { - // ZFMLALB <Zm>.H, <Zn>.H, <Zda>.S - { - goOp: AZFMLALB, - fixedBits: 0x64a08000, - args: Zm_H__Zn_H__Zda_S, - }, // ZFMLALB <Zm>.B, <Zn>.B, <Zda>.H { goOp: AZFMLALB, fixedBits: 0x64a08800, args: Zm_B__Zn_B__Zda_H, }, - // ZFMLALB <Zm>.H[<imm>], <Zn>.H, <Zda>.S + // ZFMLALB <Zm>.H, <Zn>.H, <Zda>.S { goOp: AZFMLALB, - fixedBits: 0x64a04000, - args: Zm_H_imm___Zn_H__Zda_S__2, + fixedBits: 0x64a08000, + args: Zm_H__Zn_H__Zda_S, }, // ZFMLALB <Zm>.B[<imm>], <Zn>.B, <Zda>.H { @@ -2777,6 +3113,12 @@ var insts = [][]instEncoder{ fixedBits: 0x64205000, args: Zm_B_imm___Zn_B__Zda_H__1, }, + // ZFMLALB <Zm>.H[<imm>], <Zn>.H, <Zda>.S + { + goOp: AZFMLALB, + fixedBits: 0x64a04000, + args: Zm_H_imm___Zn_H__Zda_S__2, + }, }, // ZFMLALLBB { @@ -2795,33 +3137,33 @@ var insts = [][]instEncoder{ }, // ZFMLALLBT { - // ZFMLALLBT <Zm>.B[<imm>], <Zn>.B, <Zda>.S - { - goOp: AZFMLALLBT, - fixedBits: 0x6460c000, - args: Zm_B_imm___Zn_B__Zda_S__1, - }, // ZFMLALLBT <Zm>.B, <Zn>.B, <Zda>.S { goOp: AZFMLALLBT, fixedBits: 0x64209800, args: Zm_B__Zn_B__Zda_S, }, - }, - // ZFMLALLTB - { - // ZFMLALLTB <Zm>.B[<imm>], <Zn>.B, <Zda>.S + // ZFMLALLBT <Zm>.B[<imm>], <Zn>.B, <Zda>.S { - goOp: AZFMLALLTB, - fixedBits: 0x64a0c000, + goOp: AZFMLALLBT, + fixedBits: 0x6460c000, args: Zm_B_imm___Zn_B__Zda_S__1, }, + }, + // ZFMLALLTB + { // ZFMLALLTB <Zm>.B, <Zn>.B, <Zda>.S { goOp: AZFMLALLTB, fixedBits: 0x6420a800, args: Zm_B__Zn_B__Zda_S, }, + // ZFMLALLTB <Zm>.B[<imm>], <Zn>.B, <Zda>.S + { + goOp: AZFMLALLTB, + fixedBits: 0x64a0c000, + args: Zm_B_imm___Zn_B__Zda_S__1, + }, }, // ZFMLALLTT { @@ -2840,6 +3182,18 @@ var insts = [][]instEncoder{ }, // ZFMLALT { + // ZFMLALT <Zm>.B, <Zn>.B, <Zda>.H + { + goOp: AZFMLALT, + fixedBits: 0x64a09800, + args: Zm_B__Zn_B__Zda_H, + }, + // ZFMLALT <Zm>.H, <Zn>.H, <Zda>.S + { + goOp: AZFMLALT, + fixedBits: 0x64a08400, + args: Zm_H__Zn_H__Zda_S, + }, // ZFMLALT <Zm>.B[<imm>], <Zn>.B, <Zda>.H { goOp: AZFMLALT, @@ -2852,21 +3206,21 @@ var insts = [][]instEncoder{ fixedBits: 0x64a04400, args: Zm_H_imm___Zn_H__Zda_S__2, }, - // ZFMLALT <Zm>.H, <Zn>.H, <Zda>.S + }, + // ZFMLS + { + // ZFMLS <Zm>.<T>, <Zn>.<T>, <Pg>/M, <Zda>.<T> { - goOp: AZFMLALT, - fixedBits: 0x64a08400, - args: Zm_H__Zn_H__Zda_S, + goOp: AZFMLS, + fixedBits: 0x65202000, + args: Zm_T__Zn_T__PgM__Zda_T__1, }, - // ZFMLALT <Zm>.B, <Zn>.B, <Zda>.H + // ZFMLS <Zm>.D[<imm>], <Zn>.D, <Zda>.D { - goOp: AZFMLALT, - fixedBits: 0x64a09800, - args: Zm_B__Zn_B__Zda_H, + goOp: AZFMLS, + fixedBits: 0x64e00400, + args: Zm_D_imm___Zn_D__Zda_D__2, }, - }, - // ZFMLS - { // ZFMLS <Zm>.H[<imm>], <Zn>.H, <Zda>.H { goOp: AZFMLS, @@ -2879,33 +3233,21 @@ var insts = [][]instEncoder{ fixedBits: 0x64a00400, args: Zm_S_imm___Zn_S__Zda_S__2, }, - // ZFMLS <Zm>.D[<imm>], <Zn>.D, <Zda>.D - { - goOp: AZFMLS, - fixedBits: 0x64e00400, - args: Zm_D_imm___Zn_D__Zda_D__2, - }, - // ZFMLS <Zm>.<T>, <Zn>.<T>, <Pg>/M, <Zda>.<T> - { - goOp: AZFMLS, - fixedBits: 0x65202000, - args: Zm_T__Zn_T__PgM__Zda_T__1, - }, }, // ZFMLSLB { - // ZFMLSLB <Zm>.H[<imm>], <Zn>.H, <Zda>.S - { - goOp: AZFMLSLB, - fixedBits: 0x64a06000, - args: Zm_H_imm___Zn_H__Zda_S__2, - }, // ZFMLSLB <Zm>.H, <Zn>.H, <Zda>.S { goOp: AZFMLSLB, fixedBits: 0x64a0a000, args: Zm_H__Zn_H__Zda_S, }, + // ZFMLSLB <Zm>.H[<imm>], <Zn>.H, <Zda>.S + { + goOp: AZFMLSLB, + fixedBits: 0x64a06000, + args: Zm_H_imm___Zn_H__Zda_S__2, + }, }, // ZFMLSLT { @@ -2930,11 +3272,11 @@ var insts = [][]instEncoder{ fixedBits: 0x6460e000, args: Zm_B__Zn_B__Zda_H, }, - // ZFMMLA <Zm>.S, <Zn>.S, <Zda>.S + // ZFMMLA <Zm>.B, <Zn>.B, <Zda>.S { goOp: AZFMMLA, - fixedBits: 0x64a0e400, - args: Zm_S__Zn_S__Zda_S, + fixedBits: 0x6420e000, + args: Zm_B__Zn_B__Zda_S, }, // ZFMMLA <Zm>.D, <Zn>.D, <Zda>.D { @@ -2942,23 +3284,23 @@ var insts = [][]instEncoder{ fixedBits: 0x64e0e400, args: Zm_D__Zn_D__Zda_D, }, - // ZFMMLA <Zm>.H, <Zn>.H, <Zda>.S - { - goOp: AZFMMLA, - fixedBits: 0x6420e400, - args: Zm_H__Zn_H__Zda_S, - }, // ZFMMLA <Zm>.H, <Zn>.H, <Zda>.H { goOp: AZFMMLA, fixedBits: 0x64a0e000, args: Zm_H__Zn_H__Zda_H, }, - // ZFMMLA <Zm>.B, <Zn>.B, <Zda>.S + // ZFMMLA <Zm>.H, <Zn>.H, <Zda>.S { goOp: AZFMMLA, - fixedBits: 0x6420e000, - args: Zm_B__Zn_B__Zda_S, + fixedBits: 0x6420e400, + args: Zm_H__Zn_H__Zda_S, + }, + // ZFMMLA <Zm>.S, <Zn>.S, <Zda>.S + { + goOp: AZFMMLA, + fixedBits: 0x64a0e400, + args: Zm_S__Zn_S__Zda_S, }, }, // ZFMSB @@ -2978,6 +3320,18 @@ var insts = [][]instEncoder{ fixedBits: 0x65028000, args: Zm_T__Zdn_T__PgM__Zdn_T__3, }, + // ZFMUL <Zm>.<T>, <Zn>.<T>, <Zd>.<T> + { + goOp: AZFMUL, + fixedBits: 0x65000800, + args: Zm_T__Zn_T__Zd_T__2, + }, + // ZFMUL <Zm>.D[<imm>], <Zn>.D, <Zd>.D + { + goOp: AZFMUL, + fixedBits: 0x64e02000, + args: Zm_D_imm___Zn_D__Zd_D__2, + }, // ZFMUL <Zm>.H[<imm>], <Zn>.H, <Zd>.H { goOp: AZFMUL, @@ -2990,17 +3344,11 @@ var insts = [][]instEncoder{ fixedBits: 0x64a02000, args: Zm_S_imm___Zn_S__Zd_S__2, }, - // ZFMUL <Zm>.D[<imm>], <Zn>.D, <Zd>.D - { - goOp: AZFMUL, - fixedBits: 0x64e02000, - args: Zm_D_imm___Zn_D__Zd_D__2, - }, - // ZFMUL <Zm>.<T>, <Zn>.<T>, <Zd>.<T> + // ZFMUL <const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> { goOp: AZFMUL, - fixedBits: 0x65000800, - args: Zm_T__Zn_T__Zd_T__2, + fixedBits: 0x651a8000, + args: const__Zdn_T__PgM__Zdn_T__3, }, }, // ZFMULX @@ -3083,18 +3431,18 @@ var insts = [][]instEncoder{ }, // ZFRECPX { - // ZFRECPX <Zn>.<T>, <Pg>/Z, <Zd>.<T> - { - goOp: AZFRECPX, - fixedBits: 0x641b8000, - args: Zn_T__PgZ__Zd_T__1, - }, // ZFRECPX <Zn>.<T>, <Pg>/M, <Zd>.<T> { goOp: AZFRECPX, fixedBits: 0x650ca000, args: Zn_T__PgM__Zd_T__1, }, + // ZFRECPX <Zn>.<T>, <Pg>/Z, <Zd>.<T> + { + goOp: AZFRECPX, + fixedBits: 0x641b8000, + args: Zn_T__PgZ__Zd_T__1, + }, }, // ZFRINT32X { @@ -3113,18 +3461,18 @@ var insts = [][]instEncoder{ }, // ZFRINT32Z { - // ZFRINT32Z <Zn>.<T>, <Pg>/Z, <Zd>.<T> - { - goOp: AZFRINT32Z, - fixedBits: 0x641c8000, - args: Zn_T__PgZ__Zd_T__3, - }, // ZFRINT32Z <Zn>.<T>, <Pg>/M, <Zd>.<T> { goOp: AZFRINT32Z, fixedBits: 0x6510a000, args: Zn_T__PgM__Zd_T__3, }, + // ZFRINT32Z <Zn>.<T>, <Pg>/Z, <Zd>.<T> + { + goOp: AZFRINT32Z, + fixedBits: 0x641c8000, + args: Zn_T__PgZ__Zd_T__3, + }, }, // ZFRINT64X { @@ -3158,18 +3506,18 @@ var insts = [][]instEncoder{ }, // ZFRINTA { - // ZFRINTA <Zn>.<T>, <Pg>/Z, <Zd>.<T> - { - goOp: AZFRINTA, - fixedBits: 0x64198000, - args: Zn_T__PgZ__Zd_T__1, - }, // ZFRINTA <Zn>.<T>, <Pg>/M, <Zd>.<T> { goOp: AZFRINTA, fixedBits: 0x6504a000, args: Zn_T__PgM__Zd_T__1, }, + // ZFRINTA <Zn>.<T>, <Pg>/Z, <Zd>.<T> + { + goOp: AZFRINTA, + fixedBits: 0x64198000, + args: Zn_T__PgZ__Zd_T__1, + }, }, // ZFRINTI { @@ -3188,18 +3536,18 @@ var insts = [][]instEncoder{ }, // ZFRINTM { - // ZFRINTM <Zn>.<T>, <Pg>/Z, <Zd>.<T> - { - goOp: AZFRINTM, - fixedBits: 0x6418c000, - args: Zn_T__PgZ__Zd_T__1, - }, // ZFRINTM <Zn>.<T>, <Pg>/M, <Zd>.<T> { goOp: AZFRINTM, fixedBits: 0x6502a000, args: Zn_T__PgM__Zd_T__1, }, + // ZFRINTM <Zn>.<T>, <Pg>/Z, <Zd>.<T> + { + goOp: AZFRINTM, + fixedBits: 0x6418c000, + args: Zn_T__PgZ__Zd_T__1, + }, }, // ZFRINTN { @@ -3218,33 +3566,33 @@ var insts = [][]instEncoder{ }, // ZFRINTP { - // ZFRINTP <Zn>.<T>, <Pg>/Z, <Zd>.<T> - { - goOp: AZFRINTP, - fixedBits: 0x6418a000, - args: Zn_T__PgZ__Zd_T__1, - }, // ZFRINTP <Zn>.<T>, <Pg>/M, <Zd>.<T> { goOp: AZFRINTP, fixedBits: 0x6501a000, args: Zn_T__PgM__Zd_T__1, }, - }, - // ZFRINTX - { - // ZFRINTX <Zn>.<T>, <Pg>/Z, <Zd>.<T> + // ZFRINTP <Zn>.<T>, <Pg>/Z, <Zd>.<T> { - goOp: AZFRINTX, - fixedBits: 0x6419c000, + goOp: AZFRINTP, + fixedBits: 0x6418a000, args: Zn_T__PgZ__Zd_T__1, }, + }, + // ZFRINTX + { // ZFRINTX <Zn>.<T>, <Pg>/M, <Zd>.<T> { goOp: AZFRINTX, fixedBits: 0x6506a000, args: Zn_T__PgM__Zd_T__1, }, + // ZFRINTX <Zn>.<T>, <Pg>/Z, <Zd>.<T> + { + goOp: AZFRINTX, + fixedBits: 0x6419c000, + args: Zn_T__PgZ__Zd_T__1, + }, }, // ZFRINTZ { @@ -3317,6 +3665,12 @@ var insts = [][]instEncoder{ fixedBits: 0x65000400, args: Zm_T__Zn_T__Zd_T__2, }, + // ZFSUB <const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> + { + goOp: AZFSUB, + fixedBits: 0x65198000, + args: const__Zdn_T__PgM__Zdn_T__2, + }, }, // ZFSUBR { @@ -3326,6 +3680,21 @@ var insts = [][]instEncoder{ fixedBits: 0x65038000, args: Zm_T__Zdn_T__PgM__Zdn_T__2, }, + // ZFSUBR <const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> + { + goOp: AZFSUBR, + fixedBits: 0x651b8000, + args: const__Zdn_T__PgM__Zdn_T__2, + }, + }, + // ZFTMAD + { + // ZFTMAD #<imm>, <Zm>.<T>, <Zdn>.<T>, <Zdn>.<T> + { + goOp: AZFTMAD, + fixedBits: 0x65108000, + args: cimm__Zm_T__Zdn_T__Zdn_T, + }, }, // ZFTSMUL { @@ -3380,6 +3749,24 @@ var insts = [][]instEncoder{ fixedBits: 0x4e04c00, args: Rm__Rn__Zd_T, }, + // ZINDEX <R><m>, #<imm>, <Zd>.<T> + { + goOp: AZINDEX, + fixedBits: 0x4e04800, + args: Rm__cimm__Zd_T, + }, + // ZINDEX #<imm2>, #<imm1>, <Zd>.<T> + { + goOp: AZINDEX, + fixedBits: 0x4204000, + args: cimm2__cimm1__Zd_T, + }, + // ZINDEX #<imm>, <R><n>, <Zd>.<T> + { + goOp: AZINDEX, + fixedBits: 0x4e04400, + args: cimm__Rn__Zd_T, + }, }, // ZINDEXW { @@ -3389,6 +3776,18 @@ var insts = [][]instEncoder{ fixedBits: 0x4204c00, args: Rm__Rn__Zd_T, }, + // ZINDEXW <R><m>, #<imm>, <Zd>.<T> + { + goOp: AZINDEXW, + fixedBits: 0x4204800, + args: Rm__cimm__Zd_T, + }, + // ZINDEXW #<imm>, <R><n>, <Zd>.<T> + { + goOp: AZINDEXW, + fixedBits: 0x4204400, + args: cimm__Rn__Zd_T, + }, }, // ZINSR { @@ -3554,12 +3953,6 @@ var insts = [][]instEncoder{ }, // ZLSL { - // ZLSL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> - { - goOp: AZLSL, - fixedBits: 0x4138000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, - }, // ZLSL <Zm>.D, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> { goOp: AZLSL, @@ -3572,6 +3965,24 @@ var insts = [][]instEncoder{ fixedBits: 0x4208c00, args: Zm_D__Zn_T__Zd_T, }, + // ZLSL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> + { + goOp: AZLSL, + fixedBits: 0x4138000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZLSL #<const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> + { + goOp: AZLSL, + fixedBits: 0x4038000, + args: cconst__Zdn_T__PgM__Zdn_T__2, + }, + // ZLSL #<const>, <Zn>.<T>, <Zd>.<T> + { + goOp: AZLSL, + fixedBits: 0x4209c00, + args: cconst__Zn_T__Zd_T__2, + }, }, // ZLSLR { @@ -3584,12 +3995,6 @@ var insts = [][]instEncoder{ }, // ZLSR { - // ZLSR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> - { - goOp: AZLSR, - fixedBits: 0x4118000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, - }, // ZLSR <Zm>.D, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> { goOp: AZLSR, @@ -3602,6 +4007,24 @@ var insts = [][]instEncoder{ fixedBits: 0x4208400, args: Zm_D__Zn_T__Zd_T, }, + // ZLSR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> + { + goOp: AZLSR, + fixedBits: 0x4118000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZLSR #<const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> + { + goOp: AZLSR, + fixedBits: 0x4018000, + args: cconst__Zdn_T__PgM__Zdn_T__1, + }, + // ZLSR #<const>, <Zn>.<T>, <Zd>.<T> + { + goOp: AZLSR, + fixedBits: 0x4209400, + args: cconst__Zn_T__Zd_T__1, + }, }, // ZLSRR { @@ -3641,17 +4064,11 @@ var insts = [][]instEncoder{ }, // ZMLA { - // ZMLA <Zm>.H[<imm>], <Zn>.H, <Zda>.H - { - goOp: AZMLA, - fixedBits: 0x44200800, - args: Zm_H_imm___Zn_H__Zda_H__1, - }, - // ZMLA <Zm>.S[<imm>], <Zn>.S, <Zda>.S + // ZMLA <Zm>.<T>, <Zn>.<T>, <Pg>/M, <Zda>.<T> { goOp: AZMLA, - fixedBits: 0x44a00800, - args: Zm_S_imm___Zn_S__Zda_S__1, + fixedBits: 0x4004000, + args: Zm_T__Zn_T__PgM__Zda_T__2, }, // ZMLA <Zm>.D[<imm>], <Zn>.D, <Zda>.D { @@ -3659,11 +4076,17 @@ var insts = [][]instEncoder{ fixedBits: 0x44e00800, args: Zm_D_imm___Zn_D__Zda_D__1, }, - // ZMLA <Zm>.<T>, <Zn>.<T>, <Pg>/M, <Zda>.<T> + // ZMLA <Zm>.H[<imm>], <Zn>.H, <Zda>.H { goOp: AZMLA, - fixedBits: 0x4004000, - args: Zm_T__Zn_T__PgM__Zda_T__2, + fixedBits: 0x44200800, + args: Zm_H_imm___Zn_H__Zda_H__1, + }, + // ZMLA <Zm>.S[<imm>], <Zn>.S, <Zda>.S + { + goOp: AZMLA, + fixedBits: 0x44a00800, + args: Zm_S_imm___Zn_S__Zda_S__1, }, }, // ZMLAPT @@ -3683,6 +4106,12 @@ var insts = [][]instEncoder{ fixedBits: 0x4006000, args: Zm_T__Zn_T__PgM__Zda_T__2, }, + // ZMLS <Zm>.D[<imm>], <Zn>.D, <Zda>.D + { + goOp: AZMLS, + fixedBits: 0x44e00c00, + args: Zm_D_imm___Zn_D__Zda_D__1, + }, // ZMLS <Zm>.H[<imm>], <Zn>.H, <Zda>.H { goOp: AZMLS, @@ -3695,12 +4124,6 @@ var insts = [][]instEncoder{ fixedBits: 0x44a00c00, args: Zm_S_imm___Zn_S__Zda_S__1, }, - // ZMLS <Zm>.D[<imm>], <Zn>.D, <Zda>.D - { - goOp: AZMLS, - fixedBits: 0x44e00c00, - args: Zm_D_imm___Zn_D__Zda_D__1, - }, }, // ZMOVPRFX { @@ -3734,11 +4157,11 @@ var insts = [][]instEncoder{ fixedBits: 0x4100000, args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, - // ZMUL <Zm>.S[<imm>], <Zn>.S, <Zd>.S + // ZMUL <Zm>.<T>, <Zn>.<T>, <Zd>.<T> { goOp: AZMUL, - fixedBits: 0x44a0f800, - args: Zm_S_imm___Zn_S__Zd_S__1, + fixedBits: 0x4206000, + args: Zm_T__Zn_T__Zd_T__1, }, // ZMUL <Zm>.D[<imm>], <Zn>.D, <Zd>.D { @@ -3752,11 +4175,17 @@ var insts = [][]instEncoder{ fixedBits: 0x4420f800, args: Zm_H_imm___Zn_H__Zd_H__1, }, - // ZMUL <Zm>.<T>, <Zn>.<T>, <Zd>.<T> + // ZMUL <Zm>.S[<imm>], <Zn>.S, <Zd>.S { goOp: AZMUL, - fixedBits: 0x4206000, - args: Zm_T__Zn_T__Zd_T__1, + fixedBits: 0x44a0f800, + args: Zm_S_imm___Zn_S__Zd_S__1, + }, + // ZMUL #<imm>, <Zdn>.<T>, <Zdn>.<T> + { + goOp: AZMUL, + fixedBits: 0x2530c000, + args: cimm__Zdn_T__Zdn_T__1, }, }, // ZNBSL @@ -3818,17 +4247,23 @@ var insts = [][]instEncoder{ }, // ZORR { + // ZORR <Zm>.D, <Zn>.D, <Zd>.D + { + goOp: AZORR, + fixedBits: 0x4603000, + args: Zm_D__Zn_D__Zd_D, + }, // ZORR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> { goOp: AZORR, fixedBits: 0x4180000, args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, - // ZORR <Zm>.D, <Zn>.D, <Zd>.D + // ZORR #<const>, <Zdn>.<T>, <Zdn>.<T> { goOp: AZORR, - fixedBits: 0x4603000, - args: Zm_D__Zn_D__Zd_D, + fixedBits: 0x5000000, + args: cconst__Zdn_T__Zdn_T, }, }, // ZORVB @@ -3869,53 +4304,53 @@ var insts = [][]instEncoder{ }, // ZPMOV { - // ZPMOV <Pn>.S, <Zd>{[<imm>]} + // ZPMOV <Pn>.B, <Zd> { goOp: AZPMOV, - fixedBits: 0x5693800, - args: Pn_S__Zd_imm_, + fixedBits: 0x52b3800, + args: Pn_B__Zd, }, - // ZPMOV <Zn>{[<imm>]}, <Pd>.H + // ZPMOV <Zn>, <Pd>.B { goOp: AZPMOV, - fixedBits: 0x52c3800, - args: Zn_imm___Pd_H, + fixedBits: 0x52a3800, + args: Zn__Pd_B, }, - // ZPMOV <Zn>{[<imm>]}, <Pd>.D + // ZPMOV <Pn>.D, <Zd>{[<imm>]} { goOp: AZPMOV, - fixedBits: 0x5a83800, - args: Zn_imm___Pd_D, + fixedBits: 0x5a93800, + args: Pn_D__Zd_imm_, }, - // ZPMOV <Zn>, <Pd>.B + // ZPMOV <Pn>.H, <Zd>{[<imm>]} { goOp: AZPMOV, - fixedBits: 0x52a3800, - args: Zn__Pd_B, + fixedBits: 0x52d3800, + args: Pn_H__Zd_imm_, }, - // ZPMOV <Pn>.B, <Zd> + // ZPMOV <Pn>.S, <Zd>{[<imm>]} { goOp: AZPMOV, - fixedBits: 0x52b3800, - args: Pn_B__Zd, + fixedBits: 0x5693800, + args: Pn_S__Zd_imm_, }, - // ZPMOV <Zn>{[<imm>]}, <Pd>.S + // ZPMOV <Zn>{[<imm>]}, <Pd>.D { goOp: AZPMOV, - fixedBits: 0x5683800, - args: Zn_imm___Pd_S, + fixedBits: 0x5a83800, + args: Zn_imm___Pd_D, }, - // ZPMOV <Pn>.H, <Zd>{[<imm>]} + // ZPMOV <Zn>{[<imm>]}, <Pd>.H { goOp: AZPMOV, - fixedBits: 0x52d3800, - args: Pn_H__Zd_imm_, + fixedBits: 0x52c3800, + args: Zn_imm___Pd_H, }, - // ZPMOV <Pn>.D, <Zd>{[<imm>]} + // ZPMOV <Zn>{[<imm>]}, <Pd>.S { goOp: AZPMOV, - fixedBits: 0x5a93800, - args: Pn_D__Zd_imm_, + fixedBits: 0x5683800, + args: Zn_imm___Pd_S, }, }, // ZPMUL @@ -3929,17 +4364,17 @@ var insts = [][]instEncoder{ }, // ZPMULLB { - // ZPMULLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T> + // ZPMULLB <Zm>.D, <Zn>.D, <Zd>.Q { goOp: AZPMULLB, fixedBits: 0x45006800, - args: Zm_Tb__Zn_Tb__Zd_T__3, + args: Zm_D__Zn_D__Zd_Q, }, - // ZPMULLB <Zm>.D, <Zn>.D, <Zd>.Q + // ZPMULLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T> { goOp: AZPMULLB, fixedBits: 0x45006800, - args: Zm_D__Zn_D__Zd_Q, + args: Zm_Tb__Zn_Tb__Zd_T__3, }, }, // ZPMULLT @@ -4010,18 +4445,18 @@ var insts = [][]instEncoder{ }, // ZREVB { - // ZREVB <Zn>.<T>, <Pg>/Z, <Zd>.<T> - { - goOp: AZREVB, - fixedBits: 0x524a000, - args: Zn_T__PgZ__Zd_T__4, - }, // ZREVB <Zn>.<T>, <Pg>/M, <Zd>.<T> { goOp: AZREVB, fixedBits: 0x5248000, args: Zn_T__PgM__Zd_T__4, }, + // ZREVB <Zn>.<T>, <Pg>/Z, <Zd>.<T> + { + goOp: AZREVB, + fixedBits: 0x524a000, + args: Zn_T__PgZ__Zd_T__4, + }, }, // ZREVD { @@ -4055,17 +4490,35 @@ var insts = [][]instEncoder{ }, // ZREVW { + // ZREVW <Zn>.D, <Pg>/M, <Zd>.D + { + goOp: AZREVW, + fixedBits: 0x5e68000, + args: Zn_D__PgM__Zd_D, + }, // ZREVW <Zn>.D, <Pg>/Z, <Zd>.D { goOp: AZREVW, fixedBits: 0x5e6a000, args: Zn_D__PgZ__Zd_D, }, - // ZREVW <Zn>.D, <Pg>/M, <Zd>.D + }, + // ZRSHRNB + { + // ZRSHRNB #<const>, <Zn>.<Tb>, <Zd>.<T> { - goOp: AZREVW, - fixedBits: 0x5e68000, - args: Zn_D__PgM__Zd_D, + goOp: AZRSHRNB, + fixedBits: 0x45201800, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZRSHRNT + { + // ZRSHRNT #<const>, <Zn>.<Tb>, <Zd>.<T> + { + goOp: AZRSHRNT, + fixedBits: 0x45201c00, + args: cconst__Zn_Tb__Zd_T__1, }, }, // ZRSUBHNB @@ -4241,29 +4694,23 @@ var insts = [][]instEncoder{ }, // ZSCVTF { - // ZSCVTF <Zn>.H, <Pg>/M, <Zd>.H - { - goOp: AZSCVTF, - fixedBits: 0x6552a000, - args: Zn_H__PgM__Zd_H, - }, - // ZSCVTF <Zn>.S, <Pg>/M, <Zd>.H + // ZSCVTF <Zn>.D, <Pg>/M, <Zd>.D { goOp: AZSCVTF, - fixedBits: 0x6554a000, - args: Zn_S__PgM__Zd_H, + fixedBits: 0x65d6a000, + args: Zn_D__PgM__Zd_D, }, - // ZSCVTF <Zn>.<Tb>, <Zd>.<T> + // ZSCVTF <Zn>.D, <Pg>/M, <Zd>.H { goOp: AZSCVTF, - fixedBits: 0x650c3000, - args: Zn_Tb__Zd_T__1, + fixedBits: 0x6556a000, + args: Zn_D__PgM__Zd_H, }, - // ZSCVTF <Zn>.H, <Pg>/Z, <Zd>.H + // ZSCVTF <Zn>.D, <Pg>/M, <Zd>.S { goOp: AZSCVTF, - fixedBits: 0x645cc000, - args: Zn_H__PgZ__Zd_H, + fixedBits: 0x65d4a000, + args: Zn_D__PgM__Zd_S, }, // ZSCVTF <Zn>.D, <Pg>/Z, <Zd>.D { @@ -4271,11 +4718,11 @@ var insts = [][]instEncoder{ fixedBits: 0x64ddc000, args: Zn_D__PgZ__Zd_D, }, - // ZSCVTF <Zn>.D, <Pg>/M, <Zd>.D + // ZSCVTF <Zn>.D, <Pg>/Z, <Zd>.H { goOp: AZSCVTF, - fixedBits: 0x65d6a000, - args: Zn_D__PgM__Zd_D, + fixedBits: 0x645dc000, + args: Zn_D__PgZ__Zd_H, }, // ZSCVTF <Zn>.D, <Pg>/Z, <Zd>.S { @@ -4283,29 +4730,17 @@ var insts = [][]instEncoder{ fixedBits: 0x64dd8000, args: Zn_D__PgZ__Zd_S, }, - // ZSCVTF <Zn>.D, <Pg>/M, <Zd>.S - { - goOp: AZSCVTF, - fixedBits: 0x65d4a000, - args: Zn_D__PgM__Zd_S, - }, - // ZSCVTF <Zn>.D, <Pg>/Z, <Zd>.H - { - goOp: AZSCVTF, - fixedBits: 0x645dc000, - args: Zn_D__PgZ__Zd_H, - }, - // ZSCVTF <Zn>.D, <Pg>/M, <Zd>.H + // ZSCVTF <Zn>.H, <Pg>/M, <Zd>.H { goOp: AZSCVTF, - fixedBits: 0x6556a000, - args: Zn_D__PgM__Zd_H, + fixedBits: 0x6552a000, + args: Zn_H__PgM__Zd_H, }, - // ZSCVTF <Zn>.S, <Pg>/Z, <Zd>.D + // ZSCVTF <Zn>.H, <Pg>/Z, <Zd>.H { goOp: AZSCVTF, - fixedBits: 0x64dc8000, - args: Zn_S__PgZ__Zd_D, + fixedBits: 0x645cc000, + args: Zn_H__PgZ__Zd_H, }, // ZSCVTF <Zn>.S, <Pg>/M, <Zd>.D { @@ -4313,11 +4748,11 @@ var insts = [][]instEncoder{ fixedBits: 0x65d0a000, args: Zn_S__PgM__Zd_D, }, - // ZSCVTF <Zn>.S, <Pg>/Z, <Zd>.S + // ZSCVTF <Zn>.S, <Pg>/M, <Zd>.H { goOp: AZSCVTF, - fixedBits: 0x649d8000, - args: Zn_S__PgZ__Zd_S, + fixedBits: 0x6554a000, + args: Zn_S__PgM__Zd_H, }, // ZSCVTF <Zn>.S, <Pg>/M, <Zd>.S { @@ -4325,12 +4760,30 @@ var insts = [][]instEncoder{ fixedBits: 0x6594a000, args: Zn_S__PgM__Zd_S, }, + // ZSCVTF <Zn>.S, <Pg>/Z, <Zd>.D + { + goOp: AZSCVTF, + fixedBits: 0x64dc8000, + args: Zn_S__PgZ__Zd_D, + }, // ZSCVTF <Zn>.S, <Pg>/Z, <Zd>.H { goOp: AZSCVTF, fixedBits: 0x645d8000, args: Zn_S__PgZ__Zd_H, }, + // ZSCVTF <Zn>.S, <Pg>/Z, <Zd>.S + { + goOp: AZSCVTF, + fixedBits: 0x649d8000, + args: Zn_S__PgZ__Zd_S, + }, + // ZSCVTF <Zn>.<Tb>, <Zd>.<T> + { + goOp: AZSCVTF, + fixedBits: 0x650c3000, + args: Zn_Tb__Zd_T__1, + }, }, // ZSCVTFLT { @@ -4367,17 +4820,11 @@ var insts = [][]instEncoder{ fixedBits: 0x44400000, args: Zm_B__Zn_B__Zda_H, }, - // ZSDOT <Zm>.B[<imm>], <Zn>.B, <Zda>.H - { - goOp: AZSDOT, - fixedBits: 0x44200000, - args: Zm_B_imm___Zn_B__Zda_H__2, - }, - // ZSDOT <Zm>.H[<imm>], <Zn>.H, <Zda>.S + // ZSDOT <Zm>.H, <Zn>.H, <Zda>.S { goOp: AZSDOT, - fixedBits: 0x4480c800, - args: Zm_H_imm___Zn_H__Zda_S__4, + fixedBits: 0x4400c800, + args: Zm_H__Zn_H__Zda_S, }, // ZSDOT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T> { @@ -4385,11 +4832,11 @@ var insts = [][]instEncoder{ fixedBits: 0x44800000, args: Zm_Tb__Zn_Tb__Zda_T__2, }, - // ZSDOT <Zm>.H, <Zn>.H, <Zda>.S + // ZSDOT <Zm>.B[<imm>], <Zn>.B, <Zda>.H { goOp: AZSDOT, - fixedBits: 0x4400c800, - args: Zm_H__Zn_H__Zda_S, + fixedBits: 0x44200000, + args: Zm_B_imm___Zn_B__Zda_H__2, }, // ZSDOT <Zm>.B[<imm>], <Zn>.B, <Zda>.S { @@ -4403,6 +4850,12 @@ var insts = [][]instEncoder{ fixedBits: 0x44e00000, args: Zm_H_imm___Zn_H__Zda_D, }, + // ZSDOT <Zm>.H[<imm>], <Zn>.H, <Zda>.S + { + goOp: AZSDOT, + fixedBits: 0x4480c800, + args: Zm_H_imm___Zn_H__Zda_S__4, + }, }, // ZSEL { @@ -4422,6 +4875,24 @@ var insts = [][]instEncoder{ args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, }, + // ZSHRNB + { + // ZSHRNB #<const>, <Zn>.<Tb>, <Zd>.<T> + { + goOp: AZSHRNB, + fixedBits: 0x45201000, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZSHRNT + { + // ZSHRNT #<const>, <Zn>.<Tb>, <Zd>.<T> + { + goOp: AZSHRNT, + fixedBits: 0x45201400, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, // ZSHSUB { // ZSHSUB <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> @@ -4440,6 +4911,15 @@ var insts = [][]instEncoder{ args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, }, + // ZSLI + { + // ZSLI #<const>, <Zn>.<T>, <Zd>.<T> + { + goOp: AZSLI, + fixedBits: 0x4500f400, + args: cconst__Zn_T__Zd_T__2, + }, + }, // ZSM4E { // ZSM4E <Zm>.S, <Zdn>.S, <Zdn>.S @@ -4466,6 +4946,12 @@ var insts = [][]instEncoder{ fixedBits: 0x4080000, args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, + // ZSMAX #<imm>, <Zdn>.<T>, <Zdn>.<T> + { + goOp: AZSMAX, + fixedBits: 0x2528c000, + args: cimm__Zdn_T__Zdn_T__1, + }, }, // ZSMAXP { @@ -4529,6 +5015,12 @@ var insts = [][]instEncoder{ fixedBits: 0x40a0000, args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, + // ZSMIN #<imm>, <Zdn>.<T>, <Zdn>.<T> + { + goOp: AZSMIN, + fixedBits: 0x252ac000, + args: cimm__Zdn_T__Zdn_T__1, + }, }, // ZSMINP { @@ -4586,11 +5078,11 @@ var insts = [][]instEncoder{ }, // ZSMLALB { - // ZSMLALB <Zm>.S[<imm>], <Zn>.S, <Zda>.D + // ZSMLALB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T> { goOp: AZSMLALB, - fixedBits: 0x44e08000, - args: Zm_S_imm___Zn_S__Zda_D, + fixedBits: 0x44004000, + args: Zm_Tb__Zn_Tb__Zda_T__1, }, // ZSMLALB <Zm>.H[<imm>], <Zn>.H, <Zda>.S { @@ -4598,11 +5090,11 @@ var insts = [][]instEncoder{ fixedBits: 0x44a08000, args: Zm_H_imm___Zn_H__Zda_S__1, }, - // ZSMLALB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T> + // ZSMLALB <Zm>.S[<imm>], <Zn>.S, <Zda>.D { goOp: AZSMLALB, - fixedBits: 0x44004000, - args: Zm_Tb__Zn_Tb__Zda_T__1, + fixedBits: 0x44e08000, + args: Zm_S_imm___Zn_S__Zda_D, }, }, // ZSMLALT @@ -4649,6 +5141,12 @@ var insts = [][]instEncoder{ }, // ZSMLSLT { + // ZSMLSLT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T> + { + goOp: AZSMLSLT, + fixedBits: 0x44005400, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, // ZSMLSLT <Zm>.H[<imm>], <Zn>.H, <Zda>.S { goOp: AZSMLSLT, @@ -4661,12 +5159,6 @@ var insts = [][]instEncoder{ fixedBits: 0x44e0a400, args: Zm_S_imm___Zn_S__Zda_D, }, - // ZSMLSLT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T> - { - goOp: AZSMLSLT, - fixedBits: 0x44005400, - args: Zm_Tb__Zn_Tb__Zda_T__1, - }, }, // ZSMMLA { @@ -4715,6 +5207,12 @@ var insts = [][]instEncoder{ }, // ZSMULLT { + // ZSMULLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T> + { + goOp: AZSMULLT, + fixedBits: 0x45007400, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, // ZSMULLT <Zm>.H[<imm>], <Zn>.H, <Zd>.S { goOp: AZSMULLT, @@ -4727,12 +5225,6 @@ var insts = [][]instEncoder{ fixedBits: 0x44e0c400, args: Zm_S_imm___Zn_S__Zd_D, }, - // ZSMULLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T> - { - goOp: AZSMULLT, - fixedBits: 0x45007400, - args: Zm_Tb__Zn_Tb__Zd_T__1, - }, }, // ZSPLICE { @@ -4772,6 +5264,21 @@ var insts = [][]instEncoder{ fixedBits: 0x4201000, args: Zm_T__Zn_T__Zd_T__1, }, + // ZSQADD #<imm>{, <shift>}, <Zdn>.<T>, <Zdn>.<T> + { + goOp: AZSQADD, + fixedBits: 0x2524c000, + args: cimm__shift__Zdn_T__Zdn_T, + }, + }, + // ZSQCADD + { + // ZSQCADD <const>, <Zm>.<T>, <Zdn>.<T>, <Zdn>.<T> + { + goOp: AZSQCADD, + fixedBits: 0x4501d800, + args: const__Zm_T__Zdn_T__Zdn_T, + }, }, // ZSQDECP { @@ -4784,11 +5291,11 @@ var insts = [][]instEncoder{ }, // ZSQDMLALB { - // ZSQDMLALB <Zm>.S[<imm>], <Zn>.S, <Zda>.D + // ZSQDMLALB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T> { goOp: AZSQDMLALB, - fixedBits: 0x44e02000, - args: Zm_S_imm___Zn_S__Zda_D, + fixedBits: 0x44006000, + args: Zm_Tb__Zn_Tb__Zda_T__1, }, // ZSQDMLALB <Zm>.H[<imm>], <Zn>.H, <Zda>.S { @@ -4796,11 +5303,11 @@ var insts = [][]instEncoder{ fixedBits: 0x44a02000, args: Zm_H_imm___Zn_H__Zda_S__1, }, - // ZSQDMLALB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T> + // ZSQDMLALB <Zm>.S[<imm>], <Zn>.S, <Zda>.D { goOp: AZSQDMLALB, - fixedBits: 0x44006000, - args: Zm_Tb__Zn_Tb__Zda_T__1, + fixedBits: 0x44e02000, + args: Zm_S_imm___Zn_S__Zda_D, }, }, // ZSQDMLALBT @@ -4814,6 +5321,12 @@ var insts = [][]instEncoder{ }, // ZSQDMLALT { + // ZSQDMLALT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T> + { + goOp: AZSQDMLALT, + fixedBits: 0x44006400, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, // ZSQDMLALT <Zm>.H[<imm>], <Zn>.H, <Zda>.S { goOp: AZSQDMLALT, @@ -4826,15 +5339,15 @@ var insts = [][]instEncoder{ fixedBits: 0x44e02400, args: Zm_S_imm___Zn_S__Zda_D, }, - // ZSQDMLALT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T> - { - goOp: AZSQDMLALT, - fixedBits: 0x44006400, - args: Zm_Tb__Zn_Tb__Zda_T__1, - }, }, // ZSQDMLSLB { + // ZSQDMLSLB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T> + { + goOp: AZSQDMLSLB, + fixedBits: 0x44006800, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, // ZSQDMLSLB <Zm>.H[<imm>], <Zn>.H, <Zda>.S { goOp: AZSQDMLSLB, @@ -4847,12 +5360,6 @@ var insts = [][]instEncoder{ fixedBits: 0x44e03000, args: Zm_S_imm___Zn_S__Zda_D, }, - // ZSQDMLSLB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T> - { - goOp: AZSQDMLSLB, - fixedBits: 0x44006800, - args: Zm_Tb__Zn_Tb__Zda_T__1, - }, }, // ZSQDMLSLBT { @@ -4886,30 +5393,30 @@ var insts = [][]instEncoder{ }, // ZSQDMULH { - // ZSQDMULH <Zm>.H[<imm>], <Zn>.H, <Zd>.H - { - goOp: AZSQDMULH, - fixedBits: 0x4420f000, - args: Zm_H_imm___Zn_H__Zd_H__1, - }, // ZSQDMULH <Zm>.<T>, <Zn>.<T>, <Zd>.<T> { goOp: AZSQDMULH, fixedBits: 0x4207000, args: Zm_T__Zn_T__Zd_T__1, }, - // ZSQDMULH <Zm>.S[<imm>], <Zn>.S, <Zd>.S - { - goOp: AZSQDMULH, - fixedBits: 0x44a0f000, - args: Zm_S_imm___Zn_S__Zd_S__1, - }, // ZSQDMULH <Zm>.D[<imm>], <Zn>.D, <Zd>.D { goOp: AZSQDMULH, fixedBits: 0x44e0f000, args: Zm_D_imm___Zn_D__Zd_D__1, }, + // ZSQDMULH <Zm>.H[<imm>], <Zn>.H, <Zd>.H + { + goOp: AZSQDMULH, + fixedBits: 0x4420f000, + args: Zm_H_imm___Zn_H__Zd_H__1, + }, + // ZSQDMULH <Zm>.S[<imm>], <Zn>.S, <Zd>.S + { + goOp: AZSQDMULH, + fixedBits: 0x44a0f000, + args: Zm_S_imm___Zn_S__Zd_S__1, + }, }, // ZSQDMULLB { @@ -4919,21 +5426,27 @@ var insts = [][]instEncoder{ fixedBits: 0x45006000, args: Zm_Tb__Zn_Tb__Zd_T__1, }, - // ZSQDMULLB <Zm>.S[<imm>], <Zn>.S, <Zd>.D - { - goOp: AZSQDMULLB, - fixedBits: 0x44e0e000, - args: Zm_S_imm___Zn_S__Zd_D, - }, // ZSQDMULLB <Zm>.H[<imm>], <Zn>.H, <Zd>.S { goOp: AZSQDMULLB, fixedBits: 0x44a0e000, args: Zm_H_imm___Zn_H__Zd_S, }, + // ZSQDMULLB <Zm>.S[<imm>], <Zn>.S, <Zd>.D + { + goOp: AZSQDMULLB, + fixedBits: 0x44e0e000, + args: Zm_S_imm___Zn_S__Zd_D, + }, }, // ZSQDMULLT { + // ZSQDMULLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T> + { + goOp: AZSQDMULLT, + fixedBits: 0x45006400, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, // ZSQDMULLT <Zm>.H[<imm>], <Zn>.H, <Zd>.S { goOp: AZSQDMULLT, @@ -4946,12 +5459,6 @@ var insts = [][]instEncoder{ fixedBits: 0x44e0e400, args: Zm_S_imm___Zn_S__Zd_D, }, - // ZSQDMULLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T> - { - goOp: AZSQDMULLT, - fixedBits: 0x45006400, - args: Zm_Tb__Zn_Tb__Zd_T__1, - }, }, // ZSQINCP { @@ -4977,19 +5484,34 @@ var insts = [][]instEncoder{ args: Zn_T__PgZ__Zd_T__2, }, }, - // ZSQRDMLAH + // ZSQRDCMLAH { - // ZSQRDMLAH <Zm>.S[<imm>], <Zn>.S, <Zda>.S + // ZSQRDCMLAH <const>, <Zm>.H[<imm>], <Zn>.H, <Zda>.H { - goOp: AZSQRDMLAH, - fixedBits: 0x44a01000, - args: Zm_S_imm___Zn_S__Zda_S__1, + goOp: AZSQRDCMLAH, + fixedBits: 0x44a07000, + args: const__Zm_H_imm___Zn_H__Zda_H__1, }, - // ZSQRDMLAH <Zm>.H[<imm>], <Zn>.H, <Zda>.H + // ZSQRDCMLAH <const>, <Zm>.S[<imm>], <Zn>.S, <Zda>.S + { + goOp: AZSQRDCMLAH, + fixedBits: 0x44e07000, + args: const__Zm_S_imm___Zn_S__Zda_S__1, + }, + // ZSQRDCMLAH <const>, <Zm>.<T>, <Zn>.<T>, <Zda>.<T> + { + goOp: AZSQRDCMLAH, + fixedBits: 0x44003000, + args: const__Zm_T__Zn_T__Zda_T, + }, + }, + // ZSQRDMLAH + { + // ZSQRDMLAH <Zm>.<T>, <Zn>.<T>, <Zda>.<T> { goOp: AZSQRDMLAH, - fixedBits: 0x44201000, - args: Zm_H_imm___Zn_H__Zda_H__1, + fixedBits: 0x44007000, + args: Zm_T__Zn_T__Zda_T__2, }, // ZSQRDMLAH <Zm>.D[<imm>], <Zn>.D, <Zda>.D { @@ -4997,26 +5519,26 @@ var insts = [][]instEncoder{ fixedBits: 0x44e01000, args: Zm_D_imm___Zn_D__Zda_D__1, }, - // ZSQRDMLAH <Zm>.<T>, <Zn>.<T>, <Zda>.<T> + // ZSQRDMLAH <Zm>.H[<imm>], <Zn>.H, <Zda>.H { goOp: AZSQRDMLAH, - fixedBits: 0x44007000, - args: Zm_T__Zn_T__Zda_T__2, + fixedBits: 0x44201000, + args: Zm_H_imm___Zn_H__Zda_H__1, + }, + // ZSQRDMLAH <Zm>.S[<imm>], <Zn>.S, <Zda>.S + { + goOp: AZSQRDMLAH, + fixedBits: 0x44a01000, + args: Zm_S_imm___Zn_S__Zda_S__1, }, }, // ZSQRDMLSH { - // ZSQRDMLSH <Zm>.H[<imm>], <Zn>.H, <Zda>.H - { - goOp: AZSQRDMLSH, - fixedBits: 0x44201400, - args: Zm_H_imm___Zn_H__Zda_H__1, - }, - // ZSQRDMLSH <Zm>.S[<imm>], <Zn>.S, <Zda>.S + // ZSQRDMLSH <Zm>.<T>, <Zn>.<T>, <Zda>.<T> { goOp: AZSQRDMLSH, - fixedBits: 0x44a01400, - args: Zm_S_imm___Zn_S__Zda_S__1, + fixedBits: 0x44007400, + args: Zm_T__Zn_T__Zda_T__2, }, // ZSQRDMLSH <Zm>.D[<imm>], <Zn>.D, <Zda>.D { @@ -5024,11 +5546,17 @@ var insts = [][]instEncoder{ fixedBits: 0x44e01400, args: Zm_D_imm___Zn_D__Zda_D__1, }, - // ZSQRDMLSH <Zm>.<T>, <Zn>.<T>, <Zda>.<T> + // ZSQRDMLSH <Zm>.H[<imm>], <Zn>.H, <Zda>.H { goOp: AZSQRDMLSH, - fixedBits: 0x44007400, - args: Zm_T__Zn_T__Zda_T__2, + fixedBits: 0x44201400, + args: Zm_H_imm___Zn_H__Zda_H__1, + }, + // ZSQRDMLSH <Zm>.S[<imm>], <Zn>.S, <Zda>.S + { + goOp: AZSQRDMLSH, + fixedBits: 0x44a01400, + args: Zm_S_imm___Zn_S__Zda_S__1, }, }, // ZSQRDMULH @@ -5039,6 +5567,12 @@ var insts = [][]instEncoder{ fixedBits: 0x4207400, args: Zm_T__Zn_T__Zd_T__1, }, + // ZSQRDMULH <Zm>.D[<imm>], <Zn>.D, <Zd>.D + { + goOp: AZSQRDMULH, + fixedBits: 0x44e0f400, + args: Zm_D_imm___Zn_D__Zd_D__1, + }, // ZSQRDMULH <Zm>.H[<imm>], <Zn>.H, <Zd>.H { goOp: AZSQRDMULH, @@ -5051,12 +5585,6 @@ var insts = [][]instEncoder{ fixedBits: 0x44a0f400, args: Zm_S_imm___Zn_S__Zd_S__1, }, - // ZSQRDMULH <Zm>.D[<imm>], <Zn>.D, <Zd>.D - { - goOp: AZSQRDMULH, - fixedBits: 0x44e0f400, - args: Zm_D_imm___Zn_D__Zd_D__1, - }, }, // ZSQRSHL { @@ -5076,6 +5604,42 @@ var insts = [][]instEncoder{ args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, }, + // ZSQRSHRNB + { + // ZSQRSHRNB #<const>, <Zn>.<Tb>, <Zd>.<T> + { + goOp: AZSQRSHRNB, + fixedBits: 0x45202800, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZSQRSHRNT + { + // ZSQRSHRNT #<const>, <Zn>.<Tb>, <Zd>.<T> + { + goOp: AZSQRSHRNT, + fixedBits: 0x45202c00, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZSQRSHRUNB + { + // ZSQRSHRUNB #<const>, <Zn>.<Tb>, <Zd>.<T> + { + goOp: AZSQRSHRUNB, + fixedBits: 0x45200800, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZSQRSHRUNT + { + // ZSQRSHRUNT #<const>, <Zn>.<Tb>, <Zd>.<T> + { + goOp: AZSQRSHRUNT, + fixedBits: 0x45200c00, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, // ZSQSHL { // ZSQSHL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> @@ -5084,6 +5648,12 @@ var insts = [][]instEncoder{ fixedBits: 0x44088000, args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, + // ZSQSHL #<const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> + { + goOp: AZSQSHL, + fixedBits: 0x4068000, + args: cconst__Zdn_T__PgM__Zdn_T__2, + }, }, // ZSQSHLR { @@ -5094,6 +5664,51 @@ var insts = [][]instEncoder{ args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, }, + // ZSQSHLU + { + // ZSQSHLU #<const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> + { + goOp: AZSQSHLU, + fixedBits: 0x40f8000, + args: cconst__Zdn_T__PgM__Zdn_T__2, + }, + }, + // ZSQSHRNB + { + // ZSQSHRNB #<const>, <Zn>.<Tb>, <Zd>.<T> + { + goOp: AZSQSHRNB, + fixedBits: 0x45202000, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZSQSHRNT + { + // ZSQSHRNT #<const>, <Zn>.<Tb>, <Zd>.<T> + { + goOp: AZSQSHRNT, + fixedBits: 0x45202400, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZSQSHRUNB + { + // ZSQSHRUNB #<const>, <Zn>.<Tb>, <Zd>.<T> + { + goOp: AZSQSHRUNB, + fixedBits: 0x45200000, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZSQSHRUNT + { + // ZSQSHRUNT #<const>, <Zn>.<Tb>, <Zd>.<T> + { + goOp: AZSQSHRUNT, + fixedBits: 0x45200400, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, // ZSQSUB { // ZSQSUB <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> @@ -5108,6 +5723,12 @@ var insts = [][]instEncoder{ fixedBits: 0x4201800, args: Zm_T__Zn_T__Zd_T__1, }, + // ZSQSUB #<imm>{, <shift>}, <Zdn>.<T>, <Zdn>.<T> + { + goOp: AZSQSUB, + fixedBits: 0x2526c000, + args: cimm__shift__Zdn_T__Zdn_T, + }, }, // ZSQSUBR { @@ -5163,6 +5784,15 @@ var insts = [][]instEncoder{ args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, }, + // ZSRI + { + // ZSRI #<const>, <Zn>.<T>, <Zd>.<T> + { + goOp: AZSRI, + fixedBits: 0x4500f000, + args: cconst__Zn_T__Zd_T__1, + }, + }, // ZSRSHL { // ZSRSHL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> @@ -5181,6 +5811,51 @@ var insts = [][]instEncoder{ args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, }, + // ZSRSHR + { + // ZSRSHR #<const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> + { + goOp: AZSRSHR, + fixedBits: 0x40c8000, + args: cconst__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZSRSRA + { + // ZSRSRA #<const>, <Zn>.<T>, <Zda>.<T> + { + goOp: AZSRSRA, + fixedBits: 0x4500e800, + args: cconst__Zn_T__Zda_T, + }, + }, + // ZSSHLLB + { + // ZSSHLLB #<const>, <Zn>.<Tb>, <Zd>.<T> + { + goOp: AZSSHLLB, + fixedBits: 0x4500a000, + args: cconst__Zn_Tb__Zd_T__2, + }, + }, + // ZSSHLLT + { + // ZSSHLLT #<const>, <Zn>.<Tb>, <Zd>.<T> + { + goOp: AZSSHLLT, + fixedBits: 0x4500a400, + args: cconst__Zn_Tb__Zd_T__2, + }, + }, + // ZSSRA + { + // ZSSRA #<const>, <Zn>.<T>, <Zda>.<T> + { + goOp: AZSSRA, + fixedBits: 0x4500e000, + args: cconst__Zn_T__Zda_T, + }, + }, // ZSSUBLB { // ZSSUBLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T> @@ -5237,17 +5912,23 @@ var insts = [][]instEncoder{ }, // ZSUB { + // ZSUB <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> + { + goOp: AZSUB, + fixedBits: 0x4010000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, // ZSUB <Zm>.<T>, <Zn>.<T>, <Zd>.<T> { goOp: AZSUB, fixedBits: 0x4200400, args: Zm_T__Zn_T__Zd_T__1, }, - // ZSUB <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> + // ZSUB #<imm>{, <shift>}, <Zdn>.<T>, <Zdn>.<T> { goOp: AZSUB, - fixedBits: 0x4010000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + fixedBits: 0x2521c000, + args: cimm__shift__Zdn_T__Zdn_T, }, }, // ZSUBHNB @@ -5300,6 +5981,12 @@ var insts = [][]instEncoder{ fixedBits: 0x4030000, args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, + // ZSUBR #<imm>{, <shift>}, <Zdn>.<T>, <Zdn>.<T> + { + goOp: AZSUBR, + fixedBits: 0x2523c000, + args: cimm__shift__Zdn_T__Zdn_T, + }, }, // ZSUDOT { @@ -5402,33 +6089,33 @@ var insts = [][]instEncoder{ }, // ZTRN1 { - // ZTRN1 <Zm>.<T>, <Zn>.<T>, <Zd>.<T> - { - goOp: AZTRN1, - fixedBits: 0x5207000, - args: Zm_T__Zn_T__Zd_T__1, - }, // ZTRN1 <Zm>.Q, <Zn>.Q, <Zd>.Q { goOp: AZTRN1, fixedBits: 0x5a01800, args: Zm_Q__Zn_Q__Zd_Q, }, - }, - // ZTRN2 - { - // ZTRN2 <Zm>.<T>, <Zn>.<T>, <Zd>.<T> + // ZTRN1 <Zm>.<T>, <Zn>.<T>, <Zd>.<T> { - goOp: AZTRN2, - fixedBits: 0x5207400, + goOp: AZTRN1, + fixedBits: 0x5207000, args: Zm_T__Zn_T__Zd_T__1, }, + }, + // ZTRN2 + { // ZTRN2 <Zm>.Q, <Zn>.Q, <Zd>.Q { goOp: AZTRN2, fixedBits: 0x5a01c00, args: Zm_Q__Zn_Q__Zd_Q, }, + // ZTRN2 <Zm>.<T>, <Zn>.<T>, <Zd>.<T> + { + goOp: AZTRN2, + fixedBits: 0x5207400, + args: Zm_T__Zn_T__Zd_T__1, + }, }, // ZUABA { @@ -5558,53 +6245,53 @@ var insts = [][]instEncoder{ }, // ZUCVTF { - // ZUCVTF <Zn>.D, <Pg>/M, <Zd>.H + // ZUCVTF <Zn>.D, <Pg>/M, <Zd>.D { goOp: AZUCVTF, - fixedBits: 0x6557a000, - args: Zn_D__PgM__Zd_H, + fixedBits: 0x65d7a000, + args: Zn_D__PgM__Zd_D, }, - // ZUCVTF <Zn>.S, <Pg>/Z, <Zd>.S + // ZUCVTF <Zn>.D, <Pg>/M, <Zd>.H { goOp: AZUCVTF, - fixedBits: 0x649da000, - args: Zn_S__PgZ__Zd_S, + fixedBits: 0x6557a000, + args: Zn_D__PgM__Zd_H, }, - // ZUCVTF <Zn>.H, <Pg>/Z, <Zd>.H + // ZUCVTF <Zn>.D, <Pg>/M, <Zd>.S { goOp: AZUCVTF, - fixedBits: 0x645ce000, - args: Zn_H__PgZ__Zd_H, + fixedBits: 0x65d5a000, + args: Zn_D__PgM__Zd_S, }, - // ZUCVTF <Zn>.H, <Pg>/M, <Zd>.H + // ZUCVTF <Zn>.D, <Pg>/Z, <Zd>.D { goOp: AZUCVTF, - fixedBits: 0x6553a000, - args: Zn_H__PgM__Zd_H, + fixedBits: 0x64dde000, + args: Zn_D__PgZ__Zd_D, }, - // ZUCVTF <Zn>.<Tb>, <Zd>.<T> + // ZUCVTF <Zn>.D, <Pg>/Z, <Zd>.H { goOp: AZUCVTF, - fixedBits: 0x650c3400, - args: Zn_Tb__Zd_T__1, + fixedBits: 0x645de000, + args: Zn_D__PgZ__Zd_H, }, - // ZUCVTF <Zn>.S, <Pg>/Z, <Zd>.H + // ZUCVTF <Zn>.D, <Pg>/Z, <Zd>.S { goOp: AZUCVTF, - fixedBits: 0x645da000, - args: Zn_S__PgZ__Zd_H, + fixedBits: 0x64dda000, + args: Zn_D__PgZ__Zd_S, }, - // ZUCVTF <Zn>.S, <Pg>/M, <Zd>.S + // ZUCVTF <Zn>.H, <Pg>/M, <Zd>.H { goOp: AZUCVTF, - fixedBits: 0x6595a000, - args: Zn_S__PgM__Zd_S, + fixedBits: 0x6553a000, + args: Zn_H__PgM__Zd_H, }, - // ZUCVTF <Zn>.S, <Pg>/M, <Zd>.H + // ZUCVTF <Zn>.H, <Pg>/Z, <Zd>.H { goOp: AZUCVTF, - fixedBits: 0x6555a000, - args: Zn_S__PgM__Zd_H, + fixedBits: 0x645ce000, + args: Zn_H__PgZ__Zd_H, }, // ZUCVTF <Zn>.S, <Pg>/M, <Zd>.D { @@ -5612,41 +6299,41 @@ var insts = [][]instEncoder{ fixedBits: 0x65d1a000, args: Zn_S__PgM__Zd_D, }, - // ZUCVTF <Zn>.S, <Pg>/Z, <Zd>.D + // ZUCVTF <Zn>.S, <Pg>/M, <Zd>.H { goOp: AZUCVTF, - fixedBits: 0x64dca000, - args: Zn_S__PgZ__Zd_D, + fixedBits: 0x6555a000, + args: Zn_S__PgM__Zd_H, }, - // ZUCVTF <Zn>.D, <Pg>/Z, <Zd>.D + // ZUCVTF <Zn>.S, <Pg>/M, <Zd>.S { goOp: AZUCVTF, - fixedBits: 0x64dde000, - args: Zn_D__PgZ__Zd_D, + fixedBits: 0x6595a000, + args: Zn_S__PgM__Zd_S, }, - // ZUCVTF <Zn>.D, <Pg>/Z, <Zd>.H + // ZUCVTF <Zn>.S, <Pg>/Z, <Zd>.D { goOp: AZUCVTF, - fixedBits: 0x645de000, - args: Zn_D__PgZ__Zd_H, + fixedBits: 0x64dca000, + args: Zn_S__PgZ__Zd_D, }, - // ZUCVTF <Zn>.D, <Pg>/M, <Zd>.S + // ZUCVTF <Zn>.S, <Pg>/Z, <Zd>.H { goOp: AZUCVTF, - fixedBits: 0x65d5a000, - args: Zn_D__PgM__Zd_S, + fixedBits: 0x645da000, + args: Zn_S__PgZ__Zd_H, }, - // ZUCVTF <Zn>.D, <Pg>/Z, <Zd>.S + // ZUCVTF <Zn>.S, <Pg>/Z, <Zd>.S { goOp: AZUCVTF, - fixedBits: 0x64dda000, - args: Zn_D__PgZ__Zd_S, + fixedBits: 0x649da000, + args: Zn_S__PgZ__Zd_S, }, - // ZUCVTF <Zn>.D, <Pg>/M, <Zd>.D + // ZUCVTF <Zn>.<Tb>, <Zd>.<T> { goOp: AZUCVTF, - fixedBits: 0x65d7a000, - args: Zn_D__PgM__Zd_D, + fixedBits: 0x650c3400, + args: Zn_Tb__Zd_T__1, }, }, // ZUCVTFLT @@ -5678,18 +6365,6 @@ var insts = [][]instEncoder{ }, // ZUDOT { - // ZUDOT <Zm>.B[<imm>], <Zn>.B, <Zda>.H - { - goOp: AZUDOT, - fixedBits: 0x44200400, - args: Zm_B_imm___Zn_B__Zda_H__2, - }, - // ZUDOT <Zm>.H[<imm>], <Zn>.H, <Zda>.S - { - goOp: AZUDOT, - fixedBits: 0x4480cc00, - args: Zm_H_imm___Zn_H__Zda_S__4, - }, // ZUDOT <Zm>.B, <Zn>.B, <Zda>.H { goOp: AZUDOT, @@ -5702,6 +6377,18 @@ var insts = [][]instEncoder{ fixedBits: 0x4400cc00, args: Zm_H__Zn_H__Zda_S, }, + // ZUDOT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T> + { + goOp: AZUDOT, + fixedBits: 0x44800400, + args: Zm_Tb__Zn_Tb__Zda_T__2, + }, + // ZUDOT <Zm>.B[<imm>], <Zn>.B, <Zda>.H + { + goOp: AZUDOT, + fixedBits: 0x44200400, + args: Zm_B_imm___Zn_B__Zda_H__2, + }, // ZUDOT <Zm>.B[<imm>], <Zn>.B, <Zda>.S { goOp: AZUDOT, @@ -5714,11 +6401,11 @@ var insts = [][]instEncoder{ fixedBits: 0x44e00400, args: Zm_H_imm___Zn_H__Zda_D, }, - // ZUDOT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T> + // ZUDOT <Zm>.H[<imm>], <Zn>.H, <Zda>.S { goOp: AZUDOT, - fixedBits: 0x44800400, - args: Zm_Tb__Zn_Tb__Zda_T__2, + fixedBits: 0x4480cc00, + args: Zm_H_imm___Zn_H__Zda_S__4, }, }, // ZUHADD @@ -5756,6 +6443,12 @@ var insts = [][]instEncoder{ fixedBits: 0x4090000, args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, + // ZUMAX #<imm>, <Zdn>.<T>, <Zdn>.<T> + { + goOp: AZUMAX, + fixedBits: 0x2529c000, + args: cimm__Zdn_T__Zdn_T__2, + }, }, // ZUMAXP { @@ -5819,6 +6512,12 @@ var insts = [][]instEncoder{ fixedBits: 0x40b0000, args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, + // ZUMIN #<imm>, <Zdn>.<T>, <Zdn>.<T> + { + goOp: AZUMIN, + fixedBits: 0x252bc000, + args: cimm__Zdn_T__Zdn_T__2, + }, }, // ZUMINP { @@ -5897,6 +6596,12 @@ var insts = [][]instEncoder{ }, // ZUMLALT { + // ZUMLALT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T> + { + goOp: AZUMLALT, + fixedBits: 0x44004c00, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, // ZUMLALT <Zm>.H[<imm>], <Zn>.H, <Zda>.S { goOp: AZUMLALT, @@ -5909,15 +6614,15 @@ var insts = [][]instEncoder{ fixedBits: 0x44e09400, args: Zm_S_imm___Zn_S__Zda_D, }, - // ZUMLALT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T> - { - goOp: AZUMLALT, - fixedBits: 0x44004c00, - args: Zm_Tb__Zn_Tb__Zda_T__1, - }, }, // ZUMLSLB { + // ZUMLSLB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T> + { + goOp: AZUMLSLB, + fixedBits: 0x44005800, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, // ZUMLSLB <Zm>.H[<imm>], <Zn>.H, <Zda>.S { goOp: AZUMLSLB, @@ -5930,15 +6635,15 @@ var insts = [][]instEncoder{ fixedBits: 0x44e0b000, args: Zm_S_imm___Zn_S__Zda_D, }, - // ZUMLSLB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T> - { - goOp: AZUMLSLB, - fixedBits: 0x44005800, - args: Zm_Tb__Zn_Tb__Zda_T__1, - }, }, // ZUMLSLT { + // ZUMLSLT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T> + { + goOp: AZUMLSLT, + fixedBits: 0x44005c00, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, // ZUMLSLT <Zm>.H[<imm>], <Zn>.H, <Zda>.S { goOp: AZUMLSLT, @@ -5951,12 +6656,6 @@ var insts = [][]instEncoder{ fixedBits: 0x44e0b400, args: Zm_S_imm___Zn_S__Zda_D, }, - // ZUMLSLT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T> - { - goOp: AZUMLSLT, - fixedBits: 0x44005c00, - args: Zm_Tb__Zn_Tb__Zda_T__1, - }, }, // ZUMMLA { @@ -5984,6 +6683,12 @@ var insts = [][]instEncoder{ }, // ZUMULLB { + // ZUMULLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T> + { + goOp: AZUMULLB, + fixedBits: 0x45007800, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, // ZUMULLB <Zm>.H[<imm>], <Zn>.H, <Zd>.S { goOp: AZUMULLB, @@ -5996,15 +6701,15 @@ var insts = [][]instEncoder{ fixedBits: 0x44e0d000, args: Zm_S_imm___Zn_S__Zd_D, }, - // ZUMULLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T> - { - goOp: AZUMULLB, - fixedBits: 0x45007800, - args: Zm_Tb__Zn_Tb__Zd_T__1, - }, }, // ZUMULLT { + // ZUMULLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T> + { + goOp: AZUMULLT, + fixedBits: 0x45007c00, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, // ZUMULLT <Zm>.H[<imm>], <Zn>.H, <Zd>.S { goOp: AZUMULLT, @@ -6017,12 +6722,6 @@ var insts = [][]instEncoder{ fixedBits: 0x44e0d400, args: Zm_S_imm___Zn_S__Zd_D, }, - // ZUMULLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T> - { - goOp: AZUMULLT, - fixedBits: 0x45007c00, - args: Zm_Tb__Zn_Tb__Zd_T__1, - }, }, // ZUQADD { @@ -6038,6 +6737,12 @@ var insts = [][]instEncoder{ fixedBits: 0x4201400, args: Zm_T__Zn_T__Zd_T__1, }, + // ZUQADD #<imm>{, <shift>}, <Zdn>.<T>, <Zdn>.<T> + { + goOp: AZUQADD, + fixedBits: 0x2525c000, + args: cimm__shift__Zdn_T__Zdn_T, + }, }, // ZUQDECP { @@ -6075,6 +6780,24 @@ var insts = [][]instEncoder{ args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, }, + // ZUQRSHRNB + { + // ZUQRSHRNB #<const>, <Zn>.<Tb>, <Zd>.<T> + { + goOp: AZUQRSHRNB, + fixedBits: 0x45203800, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZUQRSHRNT + { + // ZUQRSHRNT #<const>, <Zn>.<Tb>, <Zd>.<T> + { + goOp: AZUQRSHRNT, + fixedBits: 0x45203c00, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, // ZUQSHL { // ZUQSHL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> @@ -6083,6 +6806,12 @@ var insts = [][]instEncoder{ fixedBits: 0x44098000, args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, + // ZUQSHL #<const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> + { + goOp: AZUQSHL, + fixedBits: 0x4078000, + args: cconst__Zdn_T__PgM__Zdn_T__2, + }, }, // ZUQSHLR { @@ -6093,6 +6822,24 @@ var insts = [][]instEncoder{ args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, }, + // ZUQSHRNB + { + // ZUQSHRNB #<const>, <Zn>.<Tb>, <Zd>.<T> + { + goOp: AZUQSHRNB, + fixedBits: 0x45203000, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZUQSHRNT + { + // ZUQSHRNT #<const>, <Zn>.<Tb>, <Zd>.<T> + { + goOp: AZUQSHRNT, + fixedBits: 0x45203400, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, // ZUQSUB { // ZUQSUB <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> @@ -6107,6 +6854,12 @@ var insts = [][]instEncoder{ fixedBits: 0x4201c00, args: Zm_T__Zn_T__Zd_T__1, }, + // ZUQSUB #<imm>{, <shift>}, <Zdn>.<T>, <Zdn>.<T> + { + goOp: AZUQSUB, + fixedBits: 0x2527c000, + args: cimm__shift__Zdn_T__Zdn_T, + }, }, // ZUQSUBR { @@ -6177,19 +6930,37 @@ var insts = [][]instEncoder{ args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, }, + // ZURSHR + { + // ZURSHR #<const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T> + { + goOp: AZURSHR, + fixedBits: 0x40d8000, + args: cconst__Zdn_T__PgM__Zdn_T__1, + }, + }, // ZURSQRTE { + // ZURSQRTE <Zn>.S, <Pg>/M, <Zd>.S + { + goOp: AZURSQRTE, + fixedBits: 0x4481a000, + args: Zn_S__PgM__Zd_S, + }, // ZURSQRTE <Zn>.S, <Pg>/Z, <Zd>.S { goOp: AZURSQRTE, fixedBits: 0x4483a000, args: Zn_S__PgZ__Zd_S, }, - // ZURSQRTE <Zn>.S, <Pg>/M, <Zd>.S + }, + // ZURSRA + { + // ZURSRA #<const>, <Zn>.<T>, <Zda>.<T> { - goOp: AZURSQRTE, - fixedBits: 0x4481a000, - args: Zn_S__PgM__Zd_S, + goOp: AZURSRA, + fixedBits: 0x4500ec00, + args: cconst__Zn_T__Zda_T, }, }, // ZUSDOT @@ -6207,6 +6978,24 @@ var insts = [][]instEncoder{ args: Zm_B_imm___Zn_B__Zda_S__2, }, }, + // ZUSHLLB + { + // ZUSHLLB #<const>, <Zn>.<Tb>, <Zd>.<T> + { + goOp: AZUSHLLB, + fixedBits: 0x4500a800, + args: cconst__Zn_Tb__Zd_T__2, + }, + }, + // ZUSHLLT + { + // ZUSHLLT #<const>, <Zn>.<Tb>, <Zd>.<T> + { + goOp: AZUSHLLT, + fixedBits: 0x4500ac00, + args: cconst__Zn_Tb__Zd_T__2, + }, + }, // ZUSMMLA { // ZUSMMLA <Zm>.B, <Zn>.B, <Zda>.S @@ -6225,6 +7014,15 @@ var insts = [][]instEncoder{ args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, }, + // ZUSRA + { + // ZUSRA #<const>, <Zn>.<T>, <Zda>.<T> + { + goOp: AZUSRA, + fixedBits: 0x4500e400, + args: cconst__Zn_T__Zda_T, + }, + }, // ZUSUBLB { // ZUSUBLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T> @@ -6281,33 +7079,33 @@ var insts = [][]instEncoder{ }, // ZUXTB { - // ZUXTB <Zn>.<T>, <Pg>/Z, <Zd>.<T> - { - goOp: AZUXTB, - fixedBits: 0x401a000, - args: Zn_T__PgZ__Zd_T__4, - }, // ZUXTB <Zn>.<T>, <Pg>/M, <Zd>.<T> { goOp: AZUXTB, fixedBits: 0x411a000, args: Zn_T__PgM__Zd_T__4, }, + // ZUXTB <Zn>.<T>, <Pg>/Z, <Zd>.<T> + { + goOp: AZUXTB, + fixedBits: 0x401a000, + args: Zn_T__PgZ__Zd_T__4, + }, }, // ZUXTH { - // ZUXTH <Zn>.<T>, <Pg>/Z, <Zd>.<T> - { - goOp: AZUXTH, - fixedBits: 0x483a000, - args: Zn_T__PgZ__Zd_T__5, - }, // ZUXTH <Zn>.<T>, <Pg>/M, <Zd>.<T> { goOp: AZUXTH, fixedBits: 0x493a000, args: Zn_T__PgM__Zd_T__5, }, + // ZUXTH <Zn>.<T>, <Pg>/Z, <Zd>.<T> + { + goOp: AZUXTH, + fixedBits: 0x483a000, + args: Zn_T__PgZ__Zd_T__5, + }, }, // ZUXTW { @@ -6341,18 +7139,18 @@ var insts = [][]instEncoder{ }, // ZUZP2 { - // ZUZP2 <Zm>.<T>, <Zn>.<T>, <Zd>.<T> - { - goOp: AZUZP2, - fixedBits: 0x5206c00, - args: Zm_T__Zn_T__Zd_T__1, - }, // ZUZP2 <Zm>.Q, <Zn>.Q, <Zd>.Q { goOp: AZUZP2, fixedBits: 0x5a00c00, args: Zm_Q__Zn_Q__Zd_Q, }, + // ZUZP2 <Zm>.<T>, <Zn>.<T>, <Zd>.<T> + { + goOp: AZUZP2, + fixedBits: 0x5206c00, + args: Zm_T__Zn_T__Zd_T__1, + }, }, // ZUZPQ1 { @@ -6372,35 +7170,44 @@ var insts = [][]instEncoder{ args: Zm_T__Zn_T__Zd_T__1, }, }, - // ZZIP1 + // ZXAR { - // ZZIP1 <Zm>.<T>, <Zn>.<T>, <Zd>.<T> + // ZXAR #<const>, <Zm>.<T>, <Zdn>.<T>, <Zdn>.<T> { - goOp: AZZIP1, - fixedBits: 0x5206000, - args: Zm_T__Zn_T__Zd_T__1, + goOp: AZXAR, + fixedBits: 0x4203400, + args: cconst__Zm_T__Zdn_T__Zdn_T, }, + }, + // ZZIP1 + { // ZZIP1 <Zm>.Q, <Zn>.Q, <Zd>.Q { goOp: AZZIP1, fixedBits: 0x5a00000, args: Zm_Q__Zn_Q__Zd_Q, }, - }, - // ZZIP2 - { - // ZZIP2 <Zm>.<T>, <Zn>.<T>, <Zd>.<T> + // ZZIP1 <Zm>.<T>, <Zn>.<T>, <Zd>.<T> { - goOp: AZZIP2, - fixedBits: 0x5206400, + goOp: AZZIP1, + fixedBits: 0x5206000, args: Zm_T__Zn_T__Zd_T__1, }, + }, + // ZZIP2 + { // ZZIP2 <Zm>.Q, <Zn>.Q, <Zd>.Q { goOp: AZZIP2, fixedBits: 0x5a00400, args: Zm_Q__Zn_Q__Zd_Q, }, + // ZZIP2 <Zm>.<T>, <Zn>.<T>, <Zd>.<T> + { + goOp: AZZIP2, + fixedBits: 0x5206400, + args: Zm_T__Zn_T__Zd_T__1, + }, }, // ZZIPQ1 { @@ -6502,70 +7309,102 @@ var a_ARNGIDX_Zm1620_DoublePrecision_ArngDCheck_I1_2021_DoublePrecision = operan }, } -var a_ARNGIDX_Zm_1619_Range0_7_ArngBCheck_I2_1921_8BitGroup = operand{ +var a_ARNGIDX_Zm_1619_Half_ArngHCheck_I2_1921_Half = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1619_Half, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + {encodeI2_1921_Half, enc_i2}, + }, +} + +var a_ARNGIDX_Zm_1619_Range0_7V1_ArngHCheck_I2_1921_16bit = operand{ class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm_1619_Range0_7, enc_Zm}, + {encodeZm_1619_Range0_7V1, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + {encodeI2_1921_16bit, enc_i2}, + }, +} + +var a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I2_1921_8BitGroup = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1619_Range0_7V2, enc_Zm}, {encodeArngBCheck, enc_NIL}, {encodeI2_1921_8BitGroup, enc_i2}, }, } -var a_ARNGIDX_Zm_1619_Range0_7_ArngBCheck_I3hI3l_1119_Pair8Bit = operand{ +var a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I3hI3l_1119_Pair8Bit = operand{ class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm_1619_Range0_7, enc_Zm}, + {encodeZm_1619_Range0_7V2, enc_Zm}, {encodeArngBCheck, enc_NIL}, {encodeI3hI3l_1119_Pair8Bit, enc_i3h_i3l}, }, } -var a_ARNGIDX_Zm_1619_Range0_7_ArngBCheck_I3hI3l_1923_8To16Bit = operand{ +var a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I3hI3l_1923_8To16Bit = operand{ class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm_1619_Range0_7, enc_Zm}, + {encodeZm_1619_Range0_7V2, enc_Zm}, {encodeArngBCheck, enc_NIL}, {encodeI3hI3l_1923_8To16Bit, enc_i3h_i3l}, }, } -var a_ARNGIDX_Zm_1619_Range0_7_ArngBCheck_I4hI4l_1019 = operand{ +var a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I4hI4l_1019 = operand{ class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm_1619_Range0_7, enc_Zm}, + {encodeZm_1619_Range0_7V2, enc_Zm}, {encodeArngBCheck, enc_NIL}, {encodeI4hI4l_1019, enc_i4h_i4l}, }, } -var a_ARNGIDX_Zm_1619_Range0_7_ArngHCheck_I2_1921_16To32Bit = operand{ +var a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I2_1921_16To32Bit = operand{ class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm_1619_Range0_7, enc_Zm}, + {encodeZm_1619_Range0_7V2, enc_Zm}, {encodeArngHCheck, enc_NIL}, {encodeI2_1921_16To32Bit, enc_i2}, }, } -var a_ARNGIDX_Zm_1619_Range0_7_ArngHCheck_I2_1921_Pair16Bit = operand{ +var a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I2_1921_Pair16Bit = operand{ class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm_1619_Range0_7, enc_Zm}, + {encodeZm_1619_Range0_7V2, enc_Zm}, {encodeArngHCheck, enc_NIL}, {encodeI2_1921_Pair16Bit, enc_i2}, }, } -var a_ARNGIDX_Zm_1619_Range0_7_ArngHCheck_I3hI3l_1119 = operand{ +var a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1119 = operand{ class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm_1619_Range0_7, enc_Zm}, + {encodeZm_1619_Range0_7V2, enc_Zm}, {encodeArngHCheck, enc_NIL}, {encodeI3hI3l_1119, enc_i3h_i3l}, }, } -var a_ARNGIDX_Zm_1619_Range0_7_ArngHCheck_I3hI3l_1922 = operand{ +var a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1922 = operand{ class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm_1619_Range0_7, enc_Zm}, + {encodeZm_1619_Range0_7V2, enc_Zm}, {encodeArngHCheck, enc_NIL}, {encodeI3hI3l_1922, enc_i3h_i3l}, }, } +var a_ARNGIDX_Zm_1620_Range0_15_ArngSCheck_I1_2021_32bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1620_Range0_15, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + {encodeI1_2021_32bit, enc_i1}, + }, +} + +var a_ARNGIDX_Zm_1620_Single_ArngSCheck_I1_2021_Single = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1620_Single, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + {encodeI1_2021_Single, enc_i1}, + }, +} + var a_ARNGIDX_Zn510Src_Tsz_1620_SizeSpecifier4_I1Tsz_Delegate = operand{ class: AC_ARNGIDX, elemEncoders: []elemEncoder{ {encodeZn510Src, enc_Zn}, @@ -6848,6 +7687,20 @@ var a_ARNG_Zd_SizeBHSD2224 = operand{ }, } +var a_ARNG_Zd_SizeBhsTsz1921 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeBhsTsz1921, enc_tszh_tszl}, + }, +} + +var a_ARNG_Zd_SizeBhsdTsz1921 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeBhsdTsz1921, enc_tszh_tszl}, + }, +} + var a_ARNG_Zd_SizeByteMergeZero = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ {encodeZd, enc_Zd}, @@ -6890,6 +7743,20 @@ var a_ARNG_Zd_SizeHSD2224No00 = operand{ }, } +var a_ARNG_Zd_SizeHsdTsz1921 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeHsdTsz1921, enc_tszh_tszl}, + }, +} + +var a_ARNG_Zd_SizeImm13NoOp = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeImm13NoOp, enc_imm13}, + }, +} + var a_ARNG_Zd_SzByteHalfword = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ {encodeZd, enc_Zd}, @@ -6974,6 +7841,13 @@ var a_ARNG_Zda3RdSrcDst_SizeBHSD2224 = operand{ }, } +var a_ARNG_Zda3RdSrcDst_SizeBhsdTsz1921 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZda3RdSrcDst, enc_Zda}, + {encodeSizeBhsdTsz1921, enc_tszh_tszl}, + }, +} + var a_ARNG_Zda3RdSrcDst_SizeHSD2224 = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ {encodeZda3RdSrcDst, enc_Zda}, @@ -7051,6 +7925,13 @@ var a_ARNG_ZdnDest_SizeBHSD2224 = operand{ }, } +var a_ARNG_ZdnDest_SizeBhsdTsz1921 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnDest, enc_Zdn}, + {encodeSizeBhsdTsz1921, enc_tszh_tszl}, + }, +} + var a_ARNG_ZdnDest_SizeHSD2224 = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ {encodeZdnDest, enc_Zdn}, @@ -7079,6 +7960,13 @@ var a_ARNG_ZdnSrcDst_SizeBHSD2224 = operand{ }, } +var a_ARNG_ZdnSrcDst_SizeBhsdTsz810 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnSrcDst, enc_Zdn}, + {encodeSizeBhsdTsz810, enc_tszh_tszl}, + }, +} + var a_ARNG_ZdnSrcDst_SizeHSD2224 = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ {encodeZdnSrcDst, enc_Zdn}, @@ -7086,6 +7974,13 @@ var a_ARNG_ZdnSrcDst_SizeHSD2224 = operand{ }, } +var a_ARNG_ZdnSrcDst_SizeImm13NoOp = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnSrcDst, enc_Zdn}, + {encodeSizeImm13NoOp, enc_imm13}, + }, +} + var a_ARNG_Zk5103Rd_ArngDCheck = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ {encodeZk5103Rd, enc_Zk}, @@ -7240,6 +8135,13 @@ var a_ARNG_Zm510V1_SizeBHSD2224 = operand{ }, } +var a_ARNG_Zm510V1_SizeBhsdTsz1921 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm510V1, enc_Zm}, + {encodeSizeBhsdTsz1921, enc_tszh_tszl}, + }, +} + var a_ARNG_Zm510V1_SizeHSD2224 = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ {encodeZm510V1, enc_Zm}, @@ -7324,6 +8226,20 @@ var a_ARNG_Zn510Src_SizeBHSD2224 = operand{ }, } +var a_ARNG_Zn510Src_SizeBhsTsz1921Unique = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSizeBhsTsz1921Unique, enc_tszh_tszl}, + }, +} + +var a_ARNG_Zn510Src_SizeBhsdTsz1921 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSizeBhsdTsz1921, enc_tszh_tszl}, + }, +} + var a_ARNG_Zn510Src_SizeByteMergeZero = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ {encodeZn510Src, enc_Zn}, @@ -7352,6 +8268,13 @@ var a_ARNG_Zn510Src_SizeHSD2224 = operand{ }, } +var a_ARNG_Zn510Src_SizeHsdTsz1921Unique = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSizeHsdTsz1921Unique, enc_tszh_tszl}, + }, +} + var a_ARNG_Zn510Src_SizeTbBHS2224 = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ {encodeZn510Src, enc_Zn}, @@ -7478,6 +8401,13 @@ var a_ARNG_Zn510_SizeBHSD2224 = operand{ }, } +var a_ARNG_Zn510_SizeBhsdTsz1921 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510, enc_Zn}, + {encodeSizeBhsdTsz1921, enc_tszh_tszl}, + }, +} + var a_ARNG_Zn510_SizeHSD2224 = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ {encodeZn510, enc_Zn}, @@ -7520,6 +8450,186 @@ var a_ARNG_Zn510_SzSD2223 = operand{ }, } +var a_IMM_Fimm0_0_1_0_56 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeFimm0_0_1_0_56, enc_i1}, + }, +} + +var a_IMM_Fimm0_0_56 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeFimm0_0_56, enc_NIL}, + }, +} + +var a_IMM_Fimm0_5_1_0_56 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeFimm0_5_1_0_56, enc_i1}, + }, +} + +var a_IMM_Fimm0_5_2_0_56 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeFimm0_5_2_0_56, enc_i1}, + }, +} + +var a_IMM_Imm13_518 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm13_518, enc_imm13}, + }, +} + +var a_IMM_Imm3Unsigned_1619 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm3Unsigned_1619, enc_imm3}, + }, +} + +var a_IMM_Imm4Unsigned_1620 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm4Unsigned_1620, enc_imm4}, + }, +} + +var a_IMM_Imm5Signed510Unique = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm5Signed510Unique, enc_imm5}, + }, +} + +var a_IMM_Imm5Signed_1621V1 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm5Signed_1621V1, enc_imm5}, + }, +} + +var a_IMM_Imm5Signed_1621V2 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm5Signed_1621V2, enc_imm5}, + }, +} + +var a_IMM_Imm5Signed_510 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm5Signed_510, enc_imm5}, + }, +} + +var a_IMM_Imm5bSigned_1621 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm5bSigned_1621, enc_imm5b}, + }, +} + +var a_IMM_Imm6Signed_511 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm6Signed_511, enc_imm6}, + }, +} + +var a_IMM_Imm7Unsigned_1421 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm7Unsigned_1421, enc_imm7}, + }, +} + +var a_IMM_Imm8SignedLsl8 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm8SignedLsl8, enc_imm8}, + }, +} + +var a_IMM_Imm8Signed_513 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm8Signed_513, enc_imm8}, + }, +} + +var a_IMM_Imm8UnsignedLsl8 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm8UnsignedLsl8, enc_imm8}, + }, +} + +var a_IMM_Imm8Unsigned_513 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm8Unsigned_513, enc_imm8}, + }, +} + +var a_IMM_Imm8_513_Fimm = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm8_513_Fimm, enc_imm8}, + }, +} + +var a_IMM_Imm8hImm8l_Unsigned = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm8hImm8l_Unsigned, enc_imm8h_imm8l}, + }, +} + +var a_IMM_Rot0_90_180_270_1012 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeRot0_90_180_270_1012, enc_rot}, + }, +} + +var a_IMM_Rot0_90_180_270_1315 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeRot0_90_180_270_1315, enc_rot}, + }, +} + +var a_IMM_Rot90_270_1011 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeRot90_270_1011, enc_rot}, + }, +} + +var a_IMM_Rot90_270_1617 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeRot90_270_1617, enc_rot}, + }, +} + +var a_IMM_ShiftTsz1619Range0V1 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeShiftTsz1619Range0V1, enc_tszh_tszl_imm3}, + }, +} + +var a_IMM_ShiftTsz1619Range0V2 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeShiftTsz1619Range0V2, enc_tszh_tszl_imm3}, + }, +} + +var a_IMM_ShiftTsz1619Range1V1 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeShiftTsz1619Range1V1, enc_tszh_tszl_imm3}, + }, +} + +var a_IMM_ShiftTsz1619Range1V2 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeShiftTsz1619Range1V2, enc_tszh_tszl_imm3}, + }, +} + +var a_IMM_ShiftTsz58Range0 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeShiftTsz58Range0, enc_tszh_tszl_imm3}, + }, +} + +var a_IMM_ShiftTsz58Range1 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeShiftTsz58Range1, enc_tszh_tszl_imm3}, + }, +} + var a_PREGIDX_PnN_58_Noop_Imm2_810 = operand{ class: AC_PREGIDX, elemEncoders: []elemEncoder{ {encodePnN_58, enc_PNn}, @@ -7563,6 +8673,20 @@ var a_PREGZM_Pg1014_ZeroPredCheck = operand{ }, } +var a_PREGZM_Pg1620_MergePredCheck = operand{ + class: AC_PREGZM, elemEncoders: []elemEncoder{ + {encodePg1620, enc_Pg}, + {encodeMergePredCheck, enc_NIL}, + }, +} + +var a_PREGZM_Pg1620_ZeroPredCheck = operand{ + class: AC_PREGZM, elemEncoders: []elemEncoder{ + {encodePg1620, enc_Pg}, + {encodeZeroPredCheck, enc_NIL}, + }, +} + var a_PREGZM_Pg59_ZeroPredCheck = operand{ class: AC_PREGZM, elemEncoders: []elemEncoder{ {encodePg59, enc_Pg}, @@ -7689,6 +8813,20 @@ var a_SPZGREG_Noop_Xdn05 = operand{ }, } +var a_SPZGREG_XCheck_Rd05_SPAllowed = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeXCheck, enc_NIL}, + {encodeRd05_SPAllowed, enc_Rd}, + }, +} + +var a_SPZGREG_XCheck_Rn1621_SPAllowed = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeXCheck, enc_NIL}, + {encodeRn1621_SPAllowed, enc_Rn}, + }, +} + var a_VREG_Noop_Vd05 = operand{ class: AC_VREG, elemEncoders: []elemEncoder{ {encodeNoop, enc_NIL}, @@ -7937,6 +9075,12 @@ var Rm__Zdn_T = []operand{ a_ARNG_ZdnSrcDst_SizeBHSD2224, } +var Rm__cimm__Zd_T = []operand{ + a_SPZGREG_Noop_Rm1621ZR, + a_IMM_Imm5Signed510Unique, + a_ARNG_Zd_SizeBHSD2224, +} + var RnSP__PgM__Zd_T = []operand{ a_SPZGREG_Noop_Rn510SP, a_PREGZM_Pg1013_MergePredCheck, @@ -8028,31 +9172,31 @@ var Zm_B__Zn_B__Zda_S = []operand{ } var Zm_B_imm___Zn_B__Zda_H__1 = []operand{ - a_ARNGIDX_Zm_1619_Range0_7_ArngBCheck_I4hI4l_1019, + a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I4hI4l_1019, a_ARNG_Zn510_ArngBCheck, a_ARNG_Zda3RdSrcDst_ArngHCheck, } var Zm_B_imm___Zn_B__Zda_H__2 = []operand{ - a_ARNGIDX_Zm_1619_Range0_7_ArngBCheck_I3hI3l_1923_8To16Bit, + a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I3hI3l_1923_8To16Bit, a_ARNG_Zn510_ArngBCheck, a_ARNG_Zda3RdSrcDst_ArngHCheck, } var Zm_B_imm___Zn_B__Zda_H__3 = []operand{ - a_ARNGIDX_Zm_1619_Range0_7_ArngBCheck_I3hI3l_1119_Pair8Bit, + a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I3hI3l_1119_Pair8Bit, a_ARNG_Zn510_ArngBCheck, a_ARNG_Zda3RdSrcDst_ArngHCheck, } var Zm_B_imm___Zn_B__Zda_S__1 = []operand{ - a_ARNGIDX_Zm_1619_Range0_7_ArngBCheck_I4hI4l_1019, + a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I4hI4l_1019, a_ARNG_Zn510_ArngBCheck, a_ARNG_Zda3RdSrcDst_ArngSCheck, } var Zm_B_imm___Zn_B__Zda_S__2 = []operand{ - a_ARNGIDX_Zm_1619_Range0_7_ArngBCheck_I2_1921_8BitGroup, + a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I2_1921_8BitGroup, a_ARNG_Zn510_ArngBCheck, a_ARNG_Zda3RdSrcDst_ArngSCheck, } @@ -8171,7 +9315,7 @@ var Zm_H_imm___Zn_H__Zd_H__1 = []operand{ } var Zm_H_imm___Zn_H__Zd_H__2 = []operand{ - a_ARNGIDX_Zm_1619_Range0_7_ArngHCheck_I3hI3l_1922, + a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1922, a_ARNG_Zn510_ArngHCheck, a_ARNG_Zd_ArngHCheck, } @@ -8201,7 +9345,7 @@ var Zm_H_imm___Zn_H__Zda_H__1 = []operand{ } var Zm_H_imm___Zn_H__Zda_H__2 = []operand{ - a_ARNGIDX_Zm_1619_Range0_7_ArngHCheck_I3hI3l_1922, + a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1922, a_ARNG_Zn510_ArngHCheck, a_ARNG_Zda3RdSrcDst_ArngHCheck, } @@ -8219,19 +9363,19 @@ var Zm_H_imm___Zn_H__Zda_S__1 = []operand{ } var Zm_H_imm___Zn_H__Zda_S__2 = []operand{ - a_ARNGIDX_Zm_1619_Range0_7_ArngHCheck_I3hI3l_1119, + a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1119, a_ARNG_Zn510_ArngHCheck, a_ARNG_Zda3RdSrcDst_ArngSCheck, } var Zm_H_imm___Zn_H__Zda_S__3 = []operand{ - a_ARNGIDX_Zm_1619_Range0_7_ArngHCheck_I2_1921_Pair16Bit, + a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I2_1921_Pair16Bit, a_ARNG_Zn510_ArngHCheck, a_ARNG_Zda3RdSrcDst_ArngSCheck, } var Zm_H_imm___Zn_H__Zda_S__4 = []operand{ - a_ARNGIDX_Zm_1619_Range0_7_ArngHCheck_I2_1921_16To32Bit, + a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I2_1921_16To32Bit, a_ARNG_Zn510_ArngHCheck, a_ARNG_Zda3RdSrcDst_ArngSCheck, } @@ -8798,4 +9942,277 @@ var Zn_imm___Pd_S = []operand{ a_ARNG_Pd_ArngSCheck, } +var c0_0__Zn_T__PgZ__Pd_T = []operand{ + a_IMM_Fimm0_0_56, + a_ARNG_Zn510Src_SizeHSD2224, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Pd_SizeHSD2224, +} + +var cconst__PgM__Zd_T = []operand{ + a_IMM_Imm8_513_Fimm, + a_PREGZM_Pg1620_MergePredCheck, + a_ARNG_Zd_SizeHSD2224, +} + +var cconst__Zd_T__1 = []operand{ + a_IMM_Imm13_518, + a_ARNG_Zd_SizeImm13NoOp, +} + +var cconst__Zd_T__2 = []operand{ + a_IMM_Imm8_513_Fimm, + a_ARNG_Zd_SizeHSD2224, +} + +var cconst__Zdn_T__PgM__Zdn_T__1 = []operand{ + a_IMM_ShiftTsz58Range1, + a_ARNG_ZdnSrcDst_SizeBhsdTsz810, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_ZdnSrcDst_SizeBhsdTsz810, +} + +var cconst__Zdn_T__PgM__Zdn_T__2 = []operand{ + a_IMM_ShiftTsz58Range0, + a_ARNG_ZdnSrcDst_SizeBhsdTsz810, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_ZdnSrcDst_SizeBhsdTsz810, +} + +var cconst__Zdn_T__Zdn_T = []operand{ + a_IMM_Imm13_518, + a_ARNG_ZdnSrcDst_SizeImm13NoOp, + a_ARNG_ZdnSrcDst_SizeImm13NoOp, +} + +var cconst__Zm_T__Zdn_T__Zdn_T = []operand{ + a_IMM_ShiftTsz1619Range1V2, + a_ARNG_Zm510V1_SizeBhsdTsz1921, + a_ARNG_ZdnDest_SizeBhsdTsz1921, + a_ARNG_ZdnDest_SizeBhsdTsz1921, +} + +var cconst__Zn_T__Zd_T__1 = []operand{ + a_IMM_ShiftTsz1619Range1V2, + a_ARNG_Zn510Src_SizeBhsdTsz1921, + a_ARNG_Zd_SizeBhsdTsz1921, +} + +var cconst__Zn_T__Zd_T__2 = []operand{ + a_IMM_ShiftTsz1619Range0V2, + a_ARNG_Zn510Src_SizeBhsdTsz1921, + a_ARNG_Zd_SizeBhsdTsz1921, +} + +var cconst__Zn_T__Zda_T = []operand{ + a_IMM_ShiftTsz1619Range1V2, + a_ARNG_Zn510_SizeBhsdTsz1921, + a_ARNG_Zda3RdSrcDst_SizeBhsdTsz1921, +} + +var cconst__Zn_Tb__Zd_T__1 = []operand{ + a_IMM_ShiftTsz1619Range1V1, + a_ARNG_Zn510Src_SizeHsdTsz1921Unique, + a_ARNG_Zd_SizeBhsTsz1921, +} + +var cconst__Zn_Tb__Zd_T__2 = []operand{ + a_IMM_ShiftTsz1619Range0V1, + a_ARNG_Zn510Src_SizeBhsTsz1921Unique, + a_ARNG_Zd_SizeHsdTsz1921, +} + +var cimm2__cimm1__Zd_T = []operand{ + a_IMM_Imm5bSigned_1621, + a_IMM_Imm5Signed_510, + a_ARNG_Zd_SizeBHSD2224, +} + +var cimm__Rn__Zd_T = []operand{ + a_IMM_Imm5Signed_1621V1, + a_SPZGREG_Noop_Rn510ZR, + a_ARNG_Zd_SizeBHSD2224, +} + +var cimm__Xd = []operand{ + a_IMM_Imm6Signed_511, + a_SPZGREG_Noop_Rd05, +} + +var cimm__XnSP__XdSP = []operand{ + a_IMM_Imm6Signed_511, + a_SPZGREG_XCheck_Rn1621_SPAllowed, + a_SPZGREG_XCheck_Rd05_SPAllowed, +} + +var cimm__Zdn_T__Zdn_T__1 = []operand{ + a_IMM_Imm8Signed_513, + a_ARNG_ZdnSrcDst_SizeBHSD2224, + a_ARNG_ZdnSrcDst_SizeBHSD2224, +} + +var cimm__Zdn_T__Zdn_T__2 = []operand{ + a_IMM_Imm8Unsigned_513, + a_ARNG_ZdnSrcDst_SizeBHSD2224, + a_ARNG_ZdnSrcDst_SizeBHSD2224, +} + +var cimm__Zm_B__Zdn_B__Zdn_B__1 = []operand{ + a_IMM_Imm8hImm8l_Unsigned, + a_ARNG_Zm510V1_ArngBCheck, + a_ARNG_ZdnDest_ArngBCheck, + a_ARNG_ZdnDest_ArngBCheck, +} + +var cimm__Zm_B__Zdn_B__Zdn_B__2 = []operand{ + a_IMM_Imm4Unsigned_1620, + a_ARNG_Zm510V1_ArngBCheck, + a_ARNG_ZdnDest_ArngBCheck, + a_ARNG_ZdnDest_ArngBCheck, +} + +var cimm__Zm_T__Zdn_T__Zdn_T = []operand{ + a_IMM_Imm3Unsigned_1619, + a_ARNG_Zm510V1_SizeHSD2224, + a_ARNG_ZdnDest_SizeHSD2224, + a_ARNG_ZdnDest_SizeHSD2224, +} + +var cimm__Zn_T__PgZ__Pd_T__1 = []operand{ + a_IMM_Imm5Signed_1621V2, + a_ARNG_Zn510Src_SizeBHSD2224, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Pd_SizeBHSD2224, +} + +var cimm__Zn_T__PgZ__Pd_T__2 = []operand{ + a_IMM_Imm7Unsigned_1421, + a_ARNG_Zn510Src_SizeBHSD2224, + a_PREGZM_Pg1013_ZeroPredCheck, + a_ARNG_Pd_SizeBHSD2224, +} + +var cimm__shift__PgM__Zd_T = []operand{ + a_IMM_Imm8SignedLsl8, + a_PREGZM_Pg1620_MergePredCheck, + a_ARNG_Zd_SizeBHSD2224, +} + +var cimm__shift__PgZ__Zd_T = []operand{ + a_IMM_Imm8SignedLsl8, + a_PREGZM_Pg1620_ZeroPredCheck, + a_ARNG_Zd_SizeBHSD2224, +} + +var cimm__shift__Zd_T = []operand{ + a_IMM_Imm8SignedLsl8, + a_ARNG_Zd_SizeBHSD2224, +} + +var cimm__shift__Zdn_T__Zdn_T = []operand{ + a_IMM_Imm8UnsignedLsl8, + a_ARNG_ZdnSrcDst_SizeBHSD2224, + a_ARNG_ZdnSrcDst_SizeBHSD2224, +} + +var const__Zdn_T__PgM__Zdn_T__1 = []operand{ + a_IMM_Fimm0_0_1_0_56, + a_ARNG_ZdnSrcDst_SizeHSD2224, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_ZdnSrcDst_SizeHSD2224, +} + +var const__Zdn_T__PgM__Zdn_T__2 = []operand{ + a_IMM_Fimm0_5_1_0_56, + a_ARNG_ZdnSrcDst_SizeHSD2224, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_ZdnSrcDst_SizeHSD2224, +} + +var const__Zdn_T__PgM__Zdn_T__3 = []operand{ + a_IMM_Fimm0_5_2_0_56, + a_ARNG_ZdnSrcDst_SizeHSD2224, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_ZdnSrcDst_SizeHSD2224, +} + +var const__Zm_B_imm___Zn_B__Zda_S = []operand{ + a_IMM_Rot0_90_180_270_1012, + a_ARNGIDX_Zm1619_8To32Bit_ArngBCheck_I2_1921_8To32Bit, + a_ARNG_Zn510_ArngBCheck, + a_ARNG_Zda3RdSrcDst_ArngSCheck, +} + +var const__Zm_H_imm___Zn_H__Zda_D = []operand{ + a_IMM_Rot0_90_180_270_1012, + a_ARNGIDX_Zm1620_16To64Bit_ArngHCheck_I1_2021_16To64Bit, + a_ARNG_Zn510_ArngHCheck, + a_ARNG_Zda3RdSrcDst_ArngDCheck, +} + +var const__Zm_H_imm___Zn_H__Zda_H__1 = []operand{ + a_IMM_Rot0_90_180_270_1012, + a_ARNGIDX_Zm_1619_Range0_7V1_ArngHCheck_I2_1921_16bit, + a_ARNG_Zn510_ArngHCheck, + a_ARNG_Zda3RdSrcDst_ArngHCheck, +} + +var const__Zm_H_imm___Zn_H__Zda_H__2 = []operand{ + a_IMM_Rot0_90_180_270_1012, + a_ARNGIDX_Zm_1619_Half_ArngHCheck_I2_1921_Half, + a_ARNG_Zn510_ArngHCheck, + a_ARNG_Zda3RdSrcDst_ArngHCheck, +} + +var const__Zm_S_imm___Zn_S__Zda_S__1 = []operand{ + a_IMM_Rot0_90_180_270_1012, + a_ARNGIDX_Zm_1620_Range0_15_ArngSCheck_I1_2021_32bit, + a_ARNG_Zn510_ArngSCheck, + a_ARNG_Zda3RdSrcDst_ArngSCheck, +} + +var const__Zm_S_imm___Zn_S__Zda_S__2 = []operand{ + a_IMM_Rot0_90_180_270_1012, + a_ARNGIDX_Zm_1620_Single_ArngSCheck_I1_2021_Single, + a_ARNG_Zn510_ArngSCheck, + a_ARNG_Zda3RdSrcDst_ArngSCheck, +} + +var const__Zm_T__Zdn_T__PgM__Zdn_T = []operand{ + a_IMM_Rot90_270_1617, + a_ARNG_Zm510V1_SizeHSD2224, + a_ARNG_ZdnDest_SizeHSD2224, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_ZdnDest_SizeHSD2224, +} + +var const__Zm_T__Zdn_T__Zdn_T = []operand{ + a_IMM_Rot90_270_1011, + a_ARNG_Zm510V1_SizeBHSD2224, + a_ARNG_ZdnDest_SizeBHSD2224, + a_ARNG_ZdnDest_SizeBHSD2224, +} + +var const__Zm_T__Zn_T__PgM__Zda_T = []operand{ + a_IMM_Rot0_90_180_270_1315, + a_ARNG_Zm1621_SizeHSD2224, + a_ARNG_Zn510_SizeHSD2224, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zda3RdSrcDst_SizeHSD2224, +} + +var const__Zm_T__Zn_T__Zda_T = []operand{ + a_IMM_Rot0_90_180_270_1012, + a_ARNG_Zm1621_SizeBHSD2224, + a_ARNG_Zn510_SizeBHSD2224, + a_ARNG_Zda3RdSrcDst_SizeBHSD2224, +} + +var const__Zm_Tb__Zn_Tb__Zda_T = []operand{ + a_IMM_Rot0_90_180_270_1012, + a_ARNG_Zm1621_Size0TbBH2223, + a_ARNG_Zn510_Size0TbBH2223, + a_ARNG_Zda3RdSrcDst_Size0SD2223, +} + var oc = []operand{} |