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| author | Wayne Zuo <wdvxdr@golangcn.org> | 2022-03-30 21:44:44 +0800 |
|---|---|---|
| committer | Emmanuel Odeke <emmanuel@orijtech.com> | 2022-04-04 04:01:17 +0000 |
| commit | a92ca515077e5cf54673eb8c5c2d9db4824330db (patch) | |
| tree | 7dc63db107f5cef14d2819196e7a85b082bc2dc3 /test/codegen/mathbits.go | |
| parent | ba6df85c7c94c7b26d4979e92fdb9ec7fa4cc1e4 (diff) | |
| download | go-a92ca515077e5cf54673eb8c5c2d9db4824330db.tar.xz | |
cmd/compile: use LZCNT instruction for GOAMD64>=3
LZCNT is similar to BSR, but BSR(x) is undefined when x == 0, so using
LZCNT can avoid a special case for zero input. Except that case,
LZCNTQ(x) == 63-BSRQ(x) and LZCNTL(x) == 31-BSRL(x).
And according to https://www.agner.org/optimize/instruction_tables.pdf,
LZCNT instructions are much faster than BSR on AMD CPU.
name old time/op new time/op delta
LeadingZeros-8 0.91ns ± 1% 0.80ns ± 7% -11.68% (p=0.000 n=9+9)
LeadingZeros8-8 0.98ns ±15% 0.91ns ± 1% -7.34% (p=0.000 n=9+9)
LeadingZeros16-8 0.94ns ± 3% 0.92ns ± 2% -2.36% (p=0.001 n=10+10)
LeadingZeros32-8 0.89ns ± 1% 0.78ns ± 2% -12.49% (p=0.000 n=10+10)
LeadingZeros64-8 0.92ns ± 1% 0.78ns ± 1% -14.48% (p=0.000 n=10+10)
Change-Id: I125147fe3d6994a4cfe558432780408e9a27557a
Reviewed-on: https://go-review.googlesource.com/c/go/+/396794
Reviewed-by: Keith Randall <khr@golang.org>
Trust: Emmanuel Odeke <emmanuel@orijtech.com>
Run-TryBot: Emmanuel Odeke <emmanuel@orijtech.com>
TryBot-Result: Gopher Robot <gobot@golang.org>
Diffstat (limited to 'test/codegen/mathbits.go')
| -rw-r--r-- | test/codegen/mathbits.go | 30 |
1 files changed, 20 insertions, 10 deletions
diff --git a/test/codegen/mathbits.go b/test/codegen/mathbits.go index 859490c363..58d57b3523 100644 --- a/test/codegen/mathbits.go +++ b/test/codegen/mathbits.go @@ -13,7 +13,8 @@ import "math/bits" // ----------------------- // func LeadingZeros(n uint) int { - // amd64:"BSRQ" + // amd64/v1,amd64/v2:"BSRQ" + // amd64/v3:"LZCNTQ", -"BSRQ" // s390x:"FLOGR" // arm:"CLZ" arm64:"CLZ" // mips:"CLZ" @@ -22,7 +23,8 @@ func LeadingZeros(n uint) int { } func LeadingZeros64(n uint64) int { - // amd64:"BSRQ" + // amd64/v1,amd64/v2:"BSRQ" + // amd64/v3:"LZCNTQ", -"BSRQ" // s390x:"FLOGR" // arm:"CLZ" arm64:"CLZ" // mips:"CLZ" @@ -31,7 +33,8 @@ func LeadingZeros64(n uint64) int { } func LeadingZeros32(n uint32) int { - // amd64:"BSRQ","LEAQ",-"CMOVQEQ" + // amd64/v1,amd64/v2:"BSRQ","LEAQ",-"CMOVQEQ" + // amd64/v3: "LZCNTL",- "BSRL" // s390x:"FLOGR" // arm:"CLZ" arm64:"CLZW" // mips:"CLZ" @@ -40,7 +43,8 @@ func LeadingZeros32(n uint32) int { } func LeadingZeros16(n uint16) int { - // amd64:"BSRL","LEAL",-"CMOVQEQ" + // amd64/v1,amd64/v2:"BSRL","LEAL",-"CMOVQEQ" + // amd64/v3: "LZCNTL",- "BSRL" // s390x:"FLOGR" // arm:"CLZ" arm64:"CLZ" // mips:"CLZ" @@ -49,7 +53,8 @@ func LeadingZeros16(n uint16) int { } func LeadingZeros8(n uint8) int { - // amd64:"BSRL","LEAL",-"CMOVQEQ" + // amd64/v1,amd64/v2:"BSRL","LEAL",-"CMOVQEQ" + // amd64/v3: "LZCNTL",- "BSRL" // s390x:"FLOGR" // arm:"CLZ" arm64:"CLZ" // mips:"CLZ" @@ -62,7 +67,8 @@ func LeadingZeros8(n uint8) int { // --------------- // func Len(n uint) int { - // amd64:"BSRQ" + // amd64/v1,amd64/v2:"BSRQ" + // amd64/v3: "LZCNTQ" // s390x:"FLOGR" // arm:"CLZ" arm64:"CLZ" // mips:"CLZ" @@ -71,7 +77,8 @@ func Len(n uint) int { } func Len64(n uint64) int { - // amd64:"BSRQ" + // amd64/v1,amd64/v2:"BSRQ" + // amd64/v3: "LZCNTQ" // s390x:"FLOGR" // arm:"CLZ" arm64:"CLZ" // mips:"CLZ" @@ -88,7 +95,8 @@ func SubFromLen64(n uint64) int { } func Len32(n uint32) int { - // amd64:"BSRQ","LEAQ",-"CMOVQEQ" + // amd64/v1,amd64/v2:"BSRQ","LEAQ",-"CMOVQEQ" + // amd64/v3: "LZCNTL" // s390x:"FLOGR" // arm:"CLZ" arm64:"CLZ" // mips:"CLZ" @@ -99,7 +107,8 @@ func Len32(n uint32) int { } func Len16(n uint16) int { - // amd64:"BSRL","LEAL",-"CMOVQEQ" + // amd64/v1,amd64/v2:"BSRL","LEAL",-"CMOVQEQ" + // amd64/v3: "LZCNTL" // s390x:"FLOGR" // arm:"CLZ" arm64:"CLZ" // mips:"CLZ" @@ -108,7 +117,8 @@ func Len16(n uint16) int { } func Len8(n uint8) int { - // amd64:"BSRL","LEAL",-"CMOVQEQ" + // amd64/v1,amd64/v2:"BSRL","LEAL",-"CMOVQEQ" + // amd64/v3: "LZCNTL" // s390x:"FLOGR" // arm:"CLZ" arm64:"CLZ" // mips:"CLZ" |