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| author | Paul E. Murphy <murp@ibm.com> | 2023-09-18 11:29:20 -0500 |
|---|---|---|
| committer | Paul Murphy <murp@ibm.com> | 2023-09-22 14:09:29 +0000 |
| commit | c8caad423cafcca7c39dbaf64b428aaf0e8ac80c (patch) | |
| tree | ce3fb1000a10b6bca7174941e3eb21b42b9b35ca /src | |
| parent | 795414d1c628f763defa43199ab51ea3dc3241d8 (diff) | |
| download | go-c8caad423cafcca7c39dbaf64b428aaf0e8ac80c.tar.xz | |
cmd/compile/internal/ssa: optimize (AND (MOVDconst [-1] x)) on PPC64
This sequence can show up in the lowering pass on PPC64. If it
makes it to the latelower pass, it will cause an error because
it looks like it can be turned into RLDICL, but -1 isn't an
accepted mask.
Also, print more debug info if panic is called from
encodePPC64RotateMask.
Fixes #62698
Change-Id: I0f3322e2205357abe7fc28f96e05e3f7ad65567c
Reviewed-on: https://go-review.googlesource.com/c/go/+/529195
Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com>
Run-TryBot: Paul Murphy <murp@ibm.com>
TryBot-Result: Gopher Robot <gobot@golang.org>
Reviewed-by: Matthew Dempsky <mdempsky@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cmd/compile/internal/ssa/_gen/PPC64.rules | 1 | ||||
| -rw-r--r-- | src/cmd/compile/internal/ssa/rewrite.go | 2 | ||||
| -rw-r--r-- | src/cmd/compile/internal/ssa/rewritePPC64.go | 13 |
3 files changed, 15 insertions, 1 deletions
diff --git a/src/cmd/compile/internal/ssa/_gen/PPC64.rules b/src/cmd/compile/internal/ssa/_gen/PPC64.rules index 97e592fd7e..4c4f7c8c17 100644 --- a/src/cmd/compile/internal/ssa/_gen/PPC64.rules +++ b/src/cmd/compile/internal/ssa/_gen/PPC64.rules @@ -559,6 +559,7 @@ (NOR (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [^(c|d)]) // Discover consts +(AND x (MOVDconst [-1])) => x (AND x (MOVDconst [c])) && isU16Bit(c) => (Select0 (ANDCCconst [c] x)) (XOR x (MOVDconst [c])) && isU32Bit(c) => (XORconst [c] x) (OR x (MOVDconst [c])) && isU32Bit(c) => (ORconst [c] x) diff --git a/src/cmd/compile/internal/ssa/rewrite.go b/src/cmd/compile/internal/ssa/rewrite.go index efbaae4d46..eebedea68c 100644 --- a/src/cmd/compile/internal/ssa/rewrite.go +++ b/src/cmd/compile/internal/ssa/rewrite.go @@ -1478,7 +1478,7 @@ func encodePPC64RotateMask(rotate, mask, nbits int64) int64 { // Determine boundaries and then decode them if mask == 0 || ^mask == 0 || rotate >= nbits { - panic("Invalid PPC64 rotate mask") + panic(fmt.Sprintf("invalid PPC64 rotate mask: %x %d %d", uint64(mask), rotate, nbits)) } else if nbits == 32 { mb = bits.LeadingZeros32(uint32(mask)) me = 32 - bits.TrailingZeros32(uint32(mask)) diff --git a/src/cmd/compile/internal/ssa/rewritePPC64.go b/src/cmd/compile/internal/ssa/rewritePPC64.go index d1c0c2b07f..2bcc27fbc8 100644 --- a/src/cmd/compile/internal/ssa/rewritePPC64.go +++ b/src/cmd/compile/internal/ssa/rewritePPC64.go @@ -4226,6 +4226,19 @@ func rewriteValuePPC64_OpPPC64AND(v *Value) bool { } break } + // match: (AND x (MOVDconst [-1])) + // result: x + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + x := v_0 + if v_1.Op != OpPPC64MOVDconst || auxIntToInt64(v_1.AuxInt) != -1 { + continue + } + v.copyOf(x) + return true + } + break + } // match: (AND x (MOVDconst [c])) // cond: isU16Bit(c) // result: (Select0 (ANDCCconst [c] x)) |