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| author | nimelehin <nimelehin@gmail.com> | 2021-12-06 11:46:57 +0300 |
|---|---|---|
| committer | Keith Randall <khr@golang.org> | 2022-04-01 00:06:53 +0000 |
| commit | a4ffeb9edd23e1edbea87eb9ebd8cbb84fad6efa (patch) | |
| tree | 6371d316bea9e88964e21e30c70be6d35fafb7f9 /src | |
| parent | 6a40bdcbaf97ca6a815bf48998d90ccfa5a0b6fc (diff) | |
| download | go-a4ffeb9edd23e1edbea87eb9ebd8cbb84fad6efa.tar.xz | |
cmd/compile: use opregreg for x86.AXOR* ops
Change-Id: Id087d86261744559685c687aa7bad6c55466f1b5
Reviewed-on: https://go-review.googlesource.com/c/go/+/369020
Reviewed-by: Keith Randall <khr@golang.org>
Run-TryBot: Keith Randall <khr@golang.org>
TryBot-Result: Gopher Robot <gobot@golang.org>
Trust: Alex Rakoczy <alex@golang.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cmd/compile/internal/amd64/ssa.go | 24 |
1 files changed, 4 insertions, 20 deletions
diff --git a/src/cmd/compile/internal/amd64/ssa.go b/src/cmd/compile/internal/amd64/ssa.go index 8ec54a8b03..0a3f80191b 100644 --- a/src/cmd/compile/internal/amd64/ssa.go +++ b/src/cmd/compile/internal/amd64/ssa.go @@ -288,11 +288,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { r := v.Args[1].Reg() // Zero extend dividend. - c := s.Prog(x86.AXORL) - c.From.Type = obj.TYPE_REG - c.From.Reg = x86.REG_DX - c.To.Type = obj.TYPE_REG - c.To.Reg = x86.REG_DX + opregreg(s, x86.AXORL, x86.REG_DX, x86.REG_DX) // Issue divide. p := s.Prog(v.Op.Asm()) @@ -362,11 +358,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { n1.To.Reg = x86.REG_AX // n % -1 == 0 - n2 := s.Prog(x86.AXORL) - n2.From.Type = obj.TYPE_REG - n2.From.Reg = x86.REG_DX - n2.To.Type = obj.TYPE_REG - n2.To.Reg = x86.REG_DX + opregreg(s, x86.AXORL, x86.REG_DX, x86.REG_DX) // TODO(khr): issue only the -1 fixup code we need. // For instance, if only the quotient is used, no point in zeroing the remainder. @@ -744,11 +736,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { // If flags aren't live (indicated by v.Aux == nil), // then we can rewrite MOV $0, AX into XOR AX, AX. if v.AuxInt == 0 && v.Aux == nil { - p := s.Prog(x86.AXORL) - p.From.Type = obj.TYPE_REG - p.From.Reg = x - p.To.Type = obj.TYPE_REG - p.To.Reg = x + opregreg(s, x86.AXORL, x, x) break } @@ -1142,11 +1130,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { // POPCNT/TZCNT/LZCNT have a false dependency on the destination register on Intel cpus. // TZCNT/LZCNT problem affects pre-Skylake models. See discussion at https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62011#c7. // Xor register with itself to break the dependency. - p := s.Prog(x86.AXORL) - p.From.Type = obj.TYPE_REG - p.From.Reg = v.Reg() - p.To.Type = obj.TYPE_REG - p.To.Reg = v.Reg() + opregreg(s, x86.AXORL, v.Reg(), v.Reg()) } p := s.Prog(v.Op.Asm()) p.From.Type = obj.TYPE_REG |