cmd/internal/obj/loong64: improve ARNG type register name conversion

When resolving ARNG type names, the base value was not subtracted
when calculating the variable simd_type, causing its actual value
to not match the expected meaning after the base value adjustment.

Fixes #77414

Change-Id: I713bab849ecdb5610d2593ba9bd9e1169842f00e
Reviewed-on: https://go-review.googlesource.com/c/go/+/742980
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Michael Pratt <mpratt@google.com>
Reviewed-by: Junyang Shao <shaojunyang@google.com>
Reviewed-by: Meidan Li <limeidan@loongson.cn>

2 files changed, 62 insertions, 56 deletions

diff --git a/src/cmd/asm/internal/arch/loong64.go b/src/cmd/asm/internal/arch/loong64.go
index 21263d3433..4f62f5210b 100644
--- a/src/cmd/asm/internal/arch/loong64.go
+++ b/src/cmd/asm/internal/arch/loong64.go
@@ -75,48 +75,51 @@ var loong64LasxArngExtMap = map[string]int16{
 // Loong64RegisterExtension constructs an Loong64 register with extension or arrangement.
 func Loong64RegisterExtension(a *obj.Addr, ext string, reg, num int16, isAmount, isIndex bool) error {
 	var ok bool
-	var arng_type int16
-	var simd_type int16
+	var arngType int16
+	var simdType int16
+	var simdReg int16
 
 	switch {
 	case reg >= loong64.REG_V0 && reg <= loong64.REG_V31:
-		simd_type = loong64.LSX
+		simdType = loong64.LSX
+		simdReg = reg - loong64.REG_V0
 	case reg >= loong64.REG_X0 && reg <= loong64.REG_X31:
-		simd_type = loong64.LASX
+		simdType = loong64.LASX
+		simdReg = reg - loong64.REG_X0
 	default:
 		return errors.New("Loong64 extension: invalid LSX/LASX register: " + fmt.Sprintf("%d", reg))
 	}
 
 	if isIndex {
-		arng_type, ok = loong64ElemExtMap[ext]
+		arngType, ok = loong64ElemExtMap[ext]
 		if !ok {
 			return errors.New("Loong64 extension: invalid LSX/LASX arrangement type: " + ext)
 		}
 
 		a.Reg = loong64.REG_ELEM
-		a.Reg += ((reg & loong64.EXT_REG_MASK) << loong64.EXT_REG_SHIFT)
-		a.Reg += ((arng_type & loong64.EXT_TYPE_MASK) << loong64.EXT_TYPE_SHIFT)
-		a.Reg += ((simd_type & loong64.EXT_SIMDTYPE_MASK) << loong64.EXT_SIMDTYPE_SHIFT)
+		a.Reg += ((simdReg & loong64.EXT_REG_MASK) << loong64.EXT_REG_SHIFT)
+		a.Reg += ((arngType & loong64.EXT_TYPE_MASK) << loong64.EXT_TYPE_SHIFT)
+		a.Reg += ((simdType & loong64.EXT_SIMDTYPE_MASK) << loong64.EXT_SIMDTYPE_SHIFT)
 		a.Index = num
 	} else {
-		switch simd_type {
+		switch simdType {
 		case loong64.LSX:
-			arng_type, ok = loong64LsxArngExtMap[ext]
+			arngType, ok = loong64LsxArngExtMap[ext]
 			if !ok {
 				return errors.New("Loong64 extension: invalid LSX arrangement type: " + ext)
 			}
 
 		case loong64.LASX:
-			arng_type, ok = loong64LasxArngExtMap[ext]
+			arngType, ok = loong64LasxArngExtMap[ext]
 			if !ok {
 				return errors.New("Loong64 extension: invalid LASX arrangement type: " + ext)
 			}
 		}
 
 		a.Reg = loong64.REG_ARNG
-		a.Reg += ((reg & loong64.EXT_REG_MASK) << loong64.EXT_REG_SHIFT)
-		a.Reg += ((arng_type & loong64.EXT_TYPE_MASK) << loong64.EXT_TYPE_SHIFT)
-		a.Reg += ((simd_type & loong64.EXT_SIMDTYPE_MASK) << loong64.EXT_SIMDTYPE_SHIFT)
+		a.Reg += ((simdReg & loong64.EXT_REG_MASK) << loong64.EXT_REG_SHIFT)
+		a.Reg += ((arngType & loong64.EXT_TYPE_MASK) << loong64.EXT_TYPE_SHIFT)
+		a.Reg += ((simdType & loong64.EXT_SIMDTYPE_MASK) << loong64.EXT_SIMDTYPE_SHIFT)
 	}
 
 	return nil
diff --git a/src/cmd/internal/obj/loong64/list.go b/src/cmd/internal/obj/loong64/list.go
index dba8aab029..1a7926f818 100644
--- a/src/cmd/internal/obj/loong64/list.go
+++ b/src/cmd/internal/obj/loong64/list.go
@@ -10,52 +10,73 @@ import (
 )
 
 func init() {
-	obj.RegisterRegister(obj.RBaseLOONG64, REG_LAST, rconv)
+	obj.RegisterRegister(obj.RBaseLOONG64, REG_LAST, RegName)
 	obj.RegisterOpcode(obj.ABaseLoong64, Anames)
 }
 
-func arrange(a int16) string {
-	switch a {
+func arrange(valid int16) string {
+	var regPrefix string
+	var arngName string
+
+	// bits 0-4 indicates register: Vn or Xn
+	// bits 5-9 indicates arrangement: <T>
+	// bits 10 indicates SMID type: 0: LSX, 1: LASX
+	simdType := (valid >> EXT_SIMDTYPE_SHIFT) & EXT_SIMDTYPE_MASK
+	simdReg := (valid >> EXT_REG_SHIFT) & EXT_REG_MASK
+	arngType := (valid >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK
+
+	switch simdType {
+	case LSX:
+		regPrefix = "V"
+	case LASX:
+		regPrefix = "X"
+	default:
+		regPrefix = "#"
+	}
+
+	switch arngType {
 	case ARNG_32B:
-		return "B32"
+		arngName = "B32"
 	case ARNG_16H:
-		return "H16"
+		arngName = "H16"
 	case ARNG_8W:
-		return "W8"
+		arngName = "W8"
 	case ARNG_4V:
-		return "V4"
+		arngName = "V4"
 	case ARNG_2Q:
-		return "Q2"
+		arngName = "Q2"
 	case ARNG_16B:
-		return "B16"
+		arngName = "B16"
 	case ARNG_8H:
-		return "H8"
+		arngName = "H8"
 	case ARNG_4W:
-		return "W4"
+		arngName = "W4"
 	case ARNG_2V:
-		return "V2"
+		arngName = "V2"
 	case ARNG_B:
-		return "B"
+		arngName = "B"
 	case ARNG_H:
-		return "H"
+		arngName = "H"
 	case ARNG_W:
-		return "W"
+		arngName = "W"
 	case ARNG_V:
-		return "V"
+		arngName = "V"
 	case ARNG_BU:
-		return "BU"
+		arngName = "BU"
 	case ARNG_HU:
-		return "HU"
+		arngName = "HU"
 	case ARNG_WU:
-		return "WU"
+		arngName = "WU"
 	case ARNG_VU:
-		return "VU"
+		arngName = "VU"
 	default:
-		return "ARNG_???"
+		arngName = "ARNG_???"
 	}
+
+	return fmt.Sprintf("%s%d.%s", regPrefix, simdReg, arngName)
 }
 
-func rconv(r int) string {
+func RegName(r int) string {
 	switch {
 	case r == 0:
 		return "NONE"
@@ -74,28 +95,10 @@ func rconv(r int) string {
 		return fmt.Sprintf("V%d", r-REG_V0)
 	case REG_X0 <= r && r <= REG_X31:
 		return fmt.Sprintf("X%d", r-REG_X0)
-	}
-
-	// bits 0-4 indicates register: Vn or Xn
-	// bits 5-9 indicates arrangement: <T>
-	// bits 10 indicates SMID type: 0: LSX, 1: LASX
-	simd_type := (int16(r) >> EXT_SIMDTYPE_SHIFT) & EXT_SIMDTYPE_MASK
-	reg_num := (int16(r) >> EXT_REG_SHIFT) & EXT_REG_MASK
-	arng_type := (int16(r) >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK
-	reg_prefix := "#"
-	switch simd_type {
-	case LSX:
-		reg_prefix = "V"
-	case LASX:
-		reg_prefix = "X"
-	}
-
-	switch {
 	case REG_ARNG <= r && r < REG_ELEM:
-		return fmt.Sprintf("%s%d.%s", reg_prefix, reg_num, arrange(arng_type))
-
+		return arrange(int16(r - REG_ARNG))
 	case REG_ELEM <= r && r < REG_ELEM_END:
-		return fmt.Sprintf("%s%d.%s", reg_prefix, reg_num, arrange(arng_type))
+		return arrange(int16(r - REG_ELEM))
 	}
 
 	return fmt.Sprintf("badreg(%d)", r-obj.RBaseLOONG64)