diff options
| author | Cherry Zhang <cherryyz@google.com> | 2017-04-11 10:39:55 -0400 |
|---|---|---|
| committer | Cherry Zhang <cherryyz@google.com> | 2017-05-16 17:15:11 +0000 |
| commit | b53acd89db5847b9ddcba076df89bef8788dd348 (patch) | |
| tree | 493bcde661137e8aee2d73c96a3774f2c9bfd127 /src/sync/atomic | |
| parent | 84a51432a80686267e131f5d516559b3d82122b8 (diff) | |
| download | go-b53acd89db5847b9ddcba076df89bef8788dd348.tar.xz | |
cmd/internal/obj/mips: add support of LLV, SCV, NOOP instructions
LLV and SCV are 64-bit load-linked and store-conditional. They
were used in runtime as #define WORD. Change them to normal
instruction form.
NOOP is hardware no-op. It was written as WORD $0. Make a name
for it for better disassembly output.
Fixes #12561.
Fixes #18238.
Change-Id: I82c667ce756fa83ef37b034b641e8c4366335e83
Reviewed-on: https://go-review.googlesource.com/40297
Reviewed-by: Minux Ma <minux@golang.org>
Run-TryBot: Minux Ma <minux@golang.org>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Diffstat (limited to 'src/sync/atomic')
| -rw-r--r-- | src/sync/atomic/asm_mips64x.s | 30 |
1 files changed, 12 insertions, 18 deletions
diff --git a/src/sync/atomic/asm_mips64x.s b/src/sync/atomic/asm_mips64x.s index b7d4168a42..03aac8705f 100644 --- a/src/sync/atomic/asm_mips64x.s +++ b/src/sync/atomic/asm_mips64x.s @@ -6,12 +6,6 @@ #include "textflag.h" -#define LL(base, rt) WORD $((060<<26)|((base)<<21)|((rt)<<16)) -#define LLV(base, rt) WORD $((064<<26)|((base)<<21)|((rt)<<16)) -#define SC(base, rt) WORD $((070<<26)|((base)<<21)|((rt)<<16)) -#define SCV(base, rt) WORD $((074<<26)|((base)<<21)|((rt)<<16)) -#define SYNC WORD $0xf - TEXT ·SwapInt32(SB),NOSPLIT,$0-20 JMP ·SwapUint32(SB) @@ -20,8 +14,8 @@ TEXT ·SwapUint32(SB),NOSPLIT,$0-20 MOVW new+8(FP), R5 SYNC MOVV R5, R3 - LL(2, 1) // R1 = *R2 - SC(2, 3) // *R2 = R3 + LL (R2), R1 + SC R3, (R2) BEQ R3, -3(PC) MOVW R1, old+16(FP) SYNC @@ -35,8 +29,8 @@ TEXT ·SwapUint64(SB),NOSPLIT,$0-24 MOVV new+8(FP), R5 SYNC MOVV R5, R3 - LLV(2, 1) // R1 = *R2 - SCV(2, 3) // *R2 = R3 + LLV (R2), R1 + SCV R3, (R2) BEQ R3, -3(PC) MOVV R1, old+16(FP) SYNC @@ -55,9 +49,9 @@ TEXT ·CompareAndSwapUint32(SB),NOSPLIT,$0-17 SYNC cas_again: MOVV R5, R3 - LL(1, 4) // R4 = *R1 + LL (R1), R4 BNE R2, R4, cas_fail - SC(1, 3) // *R1 = R3 + SC R3, (R1) BEQ R3, cas_again MOVV $1, R1 MOVB R1, swapped+16(FP) @@ -80,9 +74,9 @@ TEXT ·CompareAndSwapUint64(SB),NOSPLIT,$0-25 SYNC cas64_again: MOVV R5, R3 - LLV(1, 4) // R4 = *R1 + LLV (R1), R4 BNE R2, R4, cas64_fail - SCV(1, 3) // *R1 = R3 + SCV R3, (R1) BEQ R3, cas64_again MOVV $1, R1 MOVB R1, swapped+24(FP) @@ -99,10 +93,10 @@ TEXT ·AddUint32(SB),NOSPLIT,$0-20 MOVV addr+0(FP), R2 MOVW delta+8(FP), R3 SYNC - LL(2, 1) // R1 = *R2 + LL (R2), R1 ADDU R1, R3, R4 MOVV R4, R1 - SC(2, 4) // *R2 = R4 + SC R4, (R2) BEQ R4, -4(PC) MOVW R1, new+16(FP) SYNC @@ -118,10 +112,10 @@ TEXT ·AddUint64(SB),NOSPLIT,$0-24 MOVV addr+0(FP), R2 MOVV delta+8(FP), R3 SYNC - LLV(2, 1) // R1 = *R2 + LLV (R2), R1 ADDVU R1, R3, R4 MOVV R4, R1 - SCV(2, 4) // *R2 = R4 + SCV R4, (R2) BEQ R4, -4(PC) MOVV R1, new+16(FP) SYNC |