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| author | Junyang Shao <shaojunyang@google.com> | 2025-09-17 14:44:49 +0000 |
|---|---|---|
| committer | Junyang Shao <shaojunyang@google.com> | 2025-09-18 11:06:52 -0700 |
| commit | 4eb5c6e07b56b75033d98941c8fadd3304ee4965 (patch) | |
| tree | 2f48610e7b8ebd6a2a893703fb1df8307560dee8 /src/simd | |
| parent | 443b7aeddb82d90345b8e7c8a4ef7c145dac7ce4 (diff) | |
| download | go-4eb5c6e07b56b75033d98941c8fadd3304ee4965.tar.xz | |
[dev.simd] cmd/compile, simd/_gen: add rewrite for const load ops
This CL adds rewrite rules for ops with const imm8 that takes a load to
its memory form.
Change-Id: I74d0df48715ab48b88b04c8e1bfb3c6b8e528aeb
Reviewed-on: https://go-review.googlesource.com/c/go/+/704635
TryBot-Bypass: Junyang Shao <shaojunyang@google.com>
Reviewed-by: David Chase <drchase@google.com>
Diffstat (limited to 'src/simd')
| -rw-r--r-- | src/simd/_gen/simdgen/gen_simdrules.go | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/src/simd/_gen/simdgen/gen_simdrules.go b/src/simd/_gen/simdgen/gen_simdrules.go index c9fae4eed7..2339a1910d 100644 --- a/src/simd/_gen/simdgen/gen_simdrules.go +++ b/src/simd/_gen/simdgen/gen_simdrules.go @@ -236,7 +236,7 @@ func writeSIMDRules(ops []Operation) *bytes.Buffer { panic("simdgen sees unknwon special lower " + *gOp.SpecialLower + ", maybe implement it?") } } - if gOp.MemFeatures != nil && *gOp.MemFeatures == "vbcst" && immType == NoImm { + if gOp.MemFeatures != nil && *gOp.MemFeatures == "vbcst" { // sanity check selected := true for _, a := range gOp.In { @@ -257,9 +257,21 @@ func writeSIMDRules(ops []Operation) *bytes.Buffer { } memOpData := data // Remove the last vreg from the arg and change it to a load. - memOpData.ArgsLoadAddr = data.Args[:len(data.Args)-1] + fmt.Sprintf("l:(VMOVDQUload%d {sym} [off] ptr mem)", *lastVreg.Bits) + origArgs := data.Args[:len(data.Args)-1] + // Prepare imm args. + immArg := "" + immArgCombineOff := " [off] " + if immType != NoImm && immType != InvalidImm { + _, after, found := strings.Cut(origArgs, "]") + if found { + origArgs = after + } + immArg = "[c] " + immArgCombineOff = " [makeValAndOff(int32(int8(c)),off)] " + } + memOpData.ArgsLoadAddr = immArg + origArgs + fmt.Sprintf("l:(VMOVDQUload%d {sym} [off] ptr mem)", *lastVreg.Bits) // Remove the last vreg from the arg and change it to "ptr". - memOpData.ArgsAddr = "{sym} [off] " + data.Args[:len(data.Args)-1] + "ptr" + memOpData.ArgsAddr = "{sym}" + immArgCombineOff + origArgs + "ptr" if maskType == OneMask { memOpData.ArgsAddr += " mask" memOpData.ArgsLoadAddr += " mask" |