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authorJoel Sing <joel@sing.id.au>2020-02-21 02:30:09 +1100
committerJoel Sing <joel@sing.id.au>2020-03-15 07:51:41 +0000
commit85a8526a7e8d12a31f2f1d9ebcec2841a27dc493 (patch)
treed593e38d6bd5ff2d71ace71965323bac033a8474 /src/runtime/internal
parent2a08f3c18127f91b22ef4f3f96c52850959b25ac (diff)
downloadgo-85a8526a7e8d12a31f2f1d9ebcec2841a27dc493.tar.xz
cmd/asm,cmd/internal/obj/riscv: add LR/SC instructions
Add support for Load-Reserved (LR) and Store-Conditional (SC) instructions. Use instructions in place of currently used defines. Updates #36765 Change-Id: I77e660639802293ece40cfde4865ac237e3308d6 Reviewed-on: https://go-review.googlesource.com/c/go/+/220540 Reviewed-by: Cherry Zhang <cherryyz@google.com>
Diffstat (limited to 'src/runtime/internal')
-rw-r--r--src/runtime/internal/atomic/atomic_riscv64.s12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/runtime/internal/atomic/atomic_riscv64.s b/src/runtime/internal/atomic/atomic_riscv64.s
index 80c84cf7d3..e4b7902d52 100644
--- a/src/runtime/internal/atomic/atomic_riscv64.s
+++ b/src/runtime/internal/atomic/atomic_riscv64.s
@@ -52,9 +52,9 @@ TEXT ·Cas(SB), NOSPLIT, $0-17
MOVW old+8(FP), A1
MOVW new+12(FP), A2
cas_again:
- AMOWSC(LR_,13,10,0) // lr.w.aq a3,(a0)
+ LRW (A0), A3
BNE A3, A1, cas_fail
- AMOWSC(SC_,14,10,12) // sc.w.aq a4,a2,(a0)
+ SCW A2, (A0), A4
BNE A4, ZERO, cas_again
MOV $1, A0
MOVB A0, ret+16(FP)
@@ -70,9 +70,9 @@ TEXT ·Cas64(SB), NOSPLIT, $0-25
MOV old+8(FP), A1
MOV new+16(FP), A2
cas_again:
- AMODSC(LR_,13,10,0) // lr.d.aq a3,(a0)
+ LRD (A0), A3
BNE A3, A1, cas_fail
- AMODSC(SC_,14,10,12) // sc.d.aq a4,a2,(a0)
+ SCD A2, (A0), A4
BNE A4, ZERO, cas_again
MOV $1, A0
MOVB A0, ret+24(FP)
@@ -84,7 +84,7 @@ cas_fail:
// func Load(ptr *uint32) uint32
TEXT ·Load(SB),NOSPLIT|NOFRAME,$0-12
MOV ptr+0(FP), A0
- AMOWSC(LR_,10,10,0)
+ LRW (A0), A0
MOVW A0, ret+8(FP)
RET
@@ -100,7 +100,7 @@ TEXT ·Load8(SB),NOSPLIT|NOFRAME,$0-9
// func Load64(ptr *uint64) uint64
TEXT ·Load64(SB),NOSPLIT|NOFRAME,$0-16
MOV ptr+0(FP), A0
- AMODSC(LR_,10,10,0)
+ LRD (A0), A0
MOV A0, ret+8(FP)
RET