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| author | Cherry Zhang <cherryyz@google.com> | 2018-05-03 14:22:05 -0400 |
|---|---|---|
| committer | Cherry Zhang <cherryyz@google.com> | 2018-05-03 21:37:31 +0000 |
| commit | 14f929af91c6096e25b5cfe0549110ccc0e3db7b (patch) | |
| tree | 283411153ffb07ecb86e12388a920d0843fd2b00 /src/runtime/internal/atomic/sys_linux_arm.s | |
| parent | 150b728675c64addd24d79ad3bb68fec4c137940 (diff) | |
| download | go-14f929af91c6096e25b5cfe0549110ccc0e3db7b.tar.xz | |
runtime/internal/atomic: improve ARM atomics
This is a follow-up of CL 93637. There, when we redirect sync/atomic
to runtime/internal/atomic, a few good implementations of ARM atomics
were lost. This CL brings most of them back, with some improvements.
- Change atomic Store to a plain store with memory barrier, as we
already changed atomic Load to plain load with memory barrier.
- Use native 64-bit atomics on ARMv7, jump to Go implementations
on older machines. But drop the kernel helper. In particular,
for Load64, just do loads, not using Cas on the address being
load from, so it works also for read-only memory (since we have
already fixed 32-bit Load).
Change-Id: I725cd65cf945ae5200db81a35be3f251c9f7af14
Reviewed-on: https://go-review.googlesource.com/111315
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Austin Clements <austin@google.com>
Diffstat (limited to 'src/runtime/internal/atomic/sys_linux_arm.s')
| -rw-r--r-- | src/runtime/internal/atomic/sys_linux_arm.s | 33 |
1 files changed, 26 insertions, 7 deletions
diff --git a/src/runtime/internal/atomic/sys_linux_arm.s b/src/runtime/internal/atomic/sys_linux_arm.s index 7e234d8f26..715231fbaa 100644 --- a/src/runtime/internal/atomic/sys_linux_arm.s +++ b/src/runtime/internal/atomic/sys_linux_arm.s @@ -55,9 +55,6 @@ check: MOVB R0, ret+12(FP) RET -TEXT runtime∕internal∕atomic·Casp1(SB),NOSPLIT,$0 - B runtime∕internal∕atomic·Cas(SB) - // As for cas, memory barriers are complicated on ARM, but the kernel // provides a user helper. ARMv5 does not support SMP and has no // memory barrier instruction at all. ARMv6 added SMP support and has @@ -70,7 +67,7 @@ TEXT runtime∕internal∕atomic·Casp1(SB),NOSPLIT,$0 TEXT memory_barrier<>(SB),NOSPLIT|NOFRAME,$0 MOVW $0xffff0fa0, R15 // R15 is hardware PC. -TEXT runtime∕internal∕atomic·Load(SB),NOSPLIT,$0-8 +TEXT ·Load(SB),NOSPLIT,$0-8 MOVW addr+0(FP), R0 MOVW (R0), R1 @@ -78,10 +75,32 @@ TEXT runtime∕internal∕atomic·Load(SB),NOSPLIT,$0-8 CMP $7, R11 BGE native_barrier BL memory_barrier<>(SB) - B prolog + B end native_barrier: DMB MB_ISH - -prolog: +end: MOVW R1, ret+4(FP) RET + +TEXT ·Store(SB),NOSPLIT,$0-8 + MOVW addr+0(FP), R1 + MOVW v+4(FP), R2 + + MOVB runtime·goarm(SB), R8 + CMP $7, R8 + BGE native_barrier + BL memory_barrier<>(SB) + B store +native_barrier: + DMB MB_ISH + +store: + MOVW R2, (R1) + + CMP $7, R8 + BGE native_barrier2 + BL memory_barrier<>(SB) + RET +native_barrier2: + DMB MB_ISH + RET |