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| author | Junyang Shao <shaojunyang@google.com> | 2025-07-01 18:00:33 +0000 |
|---|---|---|
| committer | Junyang Shao <shaojunyang@google.com> | 2025-07-01 13:51:57 -0700 |
| commit | 1ee72a15a3e893c82cc7108c49f141e824f941c2 (patch) | |
| tree | 9a5f10330952e6386ba00a5e6eb5ceab9b79867b /src/internal/cpu/cpu.go | |
| parent | 0710cce6eb0d75db1fc6c45807773f40edb14d73 (diff) | |
| download | go-1ee72a15a3e893c82cc7108c49f141e824f941c2.tar.xz | |
[dev.simd] internal/cpu: add GFNI feature check
This CL amends HasAVX512 flag with GFNI check.
This is needed because our SIMD API supports Galois Field operations.
Change-Id: I3e957b7b2215d2b7b6b8a7a0ca3e2e60d453b2e5
Reviewed-on: https://go-review.googlesource.com/c/go/+/685295
Reviewed-by: David Chase <drchase@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Diffstat (limited to 'src/internal/cpu/cpu.go')
| -rw-r--r-- | src/internal/cpu/cpu.go | 54 |
1 files changed, 28 insertions, 26 deletions
diff --git a/src/internal/cpu/cpu.go b/src/internal/cpu/cpu.go index a93eb54ddf..1eeb580711 100644 --- a/src/internal/cpu/cpu.go +++ b/src/internal/cpu/cpu.go @@ -26,32 +26,34 @@ var CacheLineSize uintptr = CacheLinePadSize // in addition to the cpuid feature bit being set. // The struct is padded to avoid false sharing. var X86 struct { - _ CacheLinePad - HasAES bool - HasADX bool - HasAVX bool - HasAVX2 bool - HasAVX512 bool // Virtual feature: F+CD+BW+DQ+VL - HasAVX512F bool - HasAVX512CD bool - HasAVX512BW bool - HasAVX512DQ bool - HasAVX512VL bool - HasBMI1 bool - HasBMI2 bool - HasERMS bool - HasFSRM bool - HasFMA bool - HasOSXSAVE bool - HasPCLMULQDQ bool - HasPOPCNT bool - HasRDTSCP bool - HasSHA bool - HasSSE3 bool - HasSSSE3 bool - HasSSE41 bool - HasSSE42 bool - _ CacheLinePad + _ CacheLinePad + HasAES bool + HasADX bool + HasAVX bool + HasAVX2 bool + HasAVX512GFNI bool // Virtual feature: F+CD+BW+DQ+VL+GFNI + HasAVX512 bool // Virtual feature: F+CD+BW+DQ+VL + HasAVX512F bool + HasAVX512CD bool + HasAVX512BW bool + HasAVX512DQ bool + HasAVX512VL bool + HasBMI1 bool + HasBMI2 bool + HasERMS bool + HasFSRM bool + HasFMA bool + HasGFNI bool + HasOSXSAVE bool + HasPCLMULQDQ bool + HasPOPCNT bool + HasRDTSCP bool + HasSHA bool + HasSSE3 bool + HasSSSE3 bool + HasSSE41 bool + HasSSE42 bool + _ CacheLinePad } // The booleans in ARM contain the correspondingly named cpu feature bit. |