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| author | Meng Zhuo <mzh@golangcn.org> | 2021-10-22 14:36:06 +0800 |
|---|---|---|
| committer | mzh <mzh@golangcn.org> | 2022-03-10 01:28:37 +0000 |
| commit | 9faef5a6540f56af0129610db8a55b443229075f (patch) | |
| tree | 78d2113994ea482a0e415d4680e3816398843851 /src/internal/bytealg | |
| parent | 3a5e3d8173df547d8360a609097fc80f01182db1 (diff) | |
| download | go-9faef5a6540f56af0129610db8a55b443229075f.tar.xz | |
cmd/compile,bytealg: change context register on riscv64
The register ABI will use X8-X23 (CL 356519),
this CL changes context register from X20(S4) to X26(S10) to meet the
prerequisite.
Update #40724
Change-Id: I93d51d22fe7b3ea5ceffe96dff93e3af60fbe7f6
Reviewed-on: https://go-review.googlesource.com/c/go/+/357974
Trust: mzh <mzh@golangcn.org>
Run-TryBot: mzh <mzh@golangcn.org>
Reviewed-by: Joel Sing <joel@sing.id.au>
Reviewed-by: Cherry Mui <cherryyz@google.com>
TryBot-Result: Gopher Robot <gobot@golang.org>
Diffstat (limited to 'src/internal/bytealg')
| -rw-r--r-- | src/internal/bytealg/equal_riscv64.s | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/internal/bytealg/equal_riscv64.s b/src/internal/bytealg/equal_riscv64.s index 959a996f81..5dd13beb55 100644 --- a/src/internal/bytealg/equal_riscv64.s +++ b/src/internal/bytealg/equal_riscv64.s @@ -5,7 +5,7 @@ #include "go_asm.h" #include "textflag.h" -#define CTXT S4 +#define CTXT S10 // func memequal(a, b unsafe.Pointer, size uintptr) bool TEXT runtime·memequal(SB),NOSPLIT|NOFRAME,$0-25 |