cmd/asm, cmd/internal/obj/arm64: support memory with imm offset in SVE

This CL is generated by CL 765100

This CL supports this addressing pattern:
imm(reg.T)

Change-Id: I16789e8e6cf03c4fa225c0fe1bd31dc23c9feb21
Reviewed-on: https://go-review.googlesource.com/c/go/+/765080
Reviewed-by: David Chase <drchase@google.com>
LUCI-TryBot-Result: golang-scoped@luci-project-accounts.iam.gserviceaccount.com <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>

9 files changed, 1028 insertions, 2 deletions

diff --git a/src/cmd/asm/internal/asm/parse.go b/src/cmd/asm/internal/asm/parse.go
index 38acb47afc..935be172cc 100644
--- a/src/cmd/asm/internal/asm/parse.go
+++ b/src/cmd/asm/internal/asm/parse.go
@@ -1045,7 +1045,7 @@ func (p *Parser) registerIndirect(a *obj.Addr, prefix rune) {
 		}
 
 		if p.peek() != '(' {
-			p.errorf("expected second parenthesis for SVE extended addressing")
+			a.Reg = encodedR1
 			return
 		}
 		p.get('(')
diff --git a/src/cmd/asm/internal/asm/testdata/arm64sveenc.s b/src/cmd/asm/internal/asm/testdata/arm64sveenc.s
index 6a0dd9838a..04a1eb9b98 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64sveenc.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64sveenc.s
@@ -1146,4 +1146,67 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
 	ZPRFW (Z6.S.SXTW<<2)(R14), P2, PLDL1STRM          // c1496684
 	ZPRFW (Z6.D.SXTW<<2)(R14), P2, PLDL1STRM          // c14966c4
 	ZPRFW (Z8.D<<2)(RSP), P3, PSTL3KEEP               // eccf68c4
+	ZLD1B 6(Z7.S), P4.Z, [Z13.S]                      // edd02684
+	ZLD1B 6(Z7.D), P4.Z, [Z13.D]                      // edd026c4
+	ZLD1D 8(Z14.D), P6.Z, [Z6.D]                      // c6d9a1c5
+	ZLD1H 6(Z7.S), P4.Z, [Z13.S]                      // edd0a384
+	ZLD1H 6(Z7.D), P4.Z, [Z13.D]                      // edd0a3c4
+	ZLD1RB 6(R14), P4.Z, [Z13.B]                      // cd914684
+	ZLD1RB 6(R14), P4.Z, [Z13.H]                      // cdb14684
+	ZLD1RB 6(R14), P4.Z, [Z13.S]                      // cdd14684
+	ZLD1RB 6(R14), P4.Z, [Z13.D]                      // cdf14684
+	ZLD1RD 8(R29), P6.Z, [Z6.D]                       // a6fbc185
+	ZLD1RH 6(R14), P4.Z, [Z13.H]                      // cdb1c384
+	ZLD1RH 6(R14), P4.Z, [Z13.S]                      // cdd1c384
+	ZLD1RH 6(R14), P4.Z, [Z13.D]                      // cdf1c384
+	ZLD1ROB (R5), P2.Z, [Z23.B]                       // b72820a4
+	ZLD1ROD (R5), P2.Z, [Z23.D]                       // b728a0a5
+	ZLD1ROH (R5), P2.Z, [Z23.H]                       // b728a0a4
+	ZLD1ROW (R5), P2.Z, [Z23.S]                       // b72820a5
+	ZLD1RQB (R5), P2.Z, [Z23.B]                       // b72800a4
+	ZLD1RQD (R5), P2.Z, [Z23.D]                       // b72880a5
+	ZLD1RQH (R5), P2.Z, [Z23.H]                       // b72880a4
+	ZLD1RQW (R5), P2.Z, [Z23.S]                       // b72800a5
+	ZLD1RSB 6(R14), P4.Z, [Z13.H]                     // cdd1c685
+	ZLD1RSB 6(R14), P4.Z, [Z13.S]                     // cdb1c685
+	ZLD1RSB 6(R14), P4.Z, [Z13.D]                     // cd91c685
+	ZLD1RSH 6(R14), P4.Z, [Z13.S]                     // cdb14385
+	ZLD1RSH 6(R14), P4.Z, [Z13.D]                     // cd914385
+	ZLD1RSW 12(R4), P6.Z, [Z25.D]                     // 9998c384
+	ZLD1RW 12(R4), P6.Z, [Z25.S]                      // 99d84385
+	ZLD1RW 12(R4), P6.Z, [Z25.D]                      // 99f84385
+	ZLD1SB 6(Z7.S), P4.Z, [Z13.S]                     // ed902684
+	ZLD1SB 6(Z7.D), P4.Z, [Z13.D]                     // ed9026c4
+	ZLD1SH 6(Z7.S), P4.Z, [Z13.S]                     // ed90a384
+	ZLD1SH 6(Z7.D), P4.Z, [Z13.D]                     // ed90a3c4
+	ZLD1SW 12(Z0.D), P6.Z, [Z25.D]                    // 199823c5
+	ZLD1W 12(Z0.S), P6.Z, [Z25.S]                     // 19d82385
+	ZLD1W 12(Z0.D), P6.Z, [Z25.D]                     // 19d823c5
+	ZLDFF1B 6(Z7.S), P4.Z, [Z13.S]                    // edf02684
+	ZLDFF1B 6(Z7.D), P4.Z, [Z13.D]                    // edf026c4
+	ZLDFF1D 8(Z14.D), P6.Z, [Z6.D]                    // c6f9a1c5
+	ZLDFF1H 6(Z7.S), P4.Z, [Z13.S]                    // edf0a384
+	ZLDFF1H 6(Z7.D), P4.Z, [Z13.D]                    // edf0a3c4
+	ZLDFF1SB 6(Z7.S), P4.Z, [Z13.S]                   // edb02684
+	ZLDFF1SB 6(Z7.D), P4.Z, [Z13.D]                   // edb026c4
+	ZLDFF1SH 6(Z7.S), P4.Z, [Z13.S]                   // edb0a384
+	ZLDFF1SH 6(Z7.D), P4.Z, [Z13.D]                   // edb0a3c4
+	ZLDFF1SW 12(Z0.D), P6.Z, [Z25.D]                  // 19b823c5
+	ZLDFF1W 12(Z0.S), P6.Z, [Z25.S]                   // 19f82385
+	ZLDFF1W 12(Z0.D), P6.Z, [Z25.D]                   // 19f823c5
+	ZPRFB 8(Z10.S), P3, PSTL3KEEP                     // 4ced0884
+	ZPRFB 8(Z10.D), P3, PSTL3KEEP                     // 4ced08c4
+	ZPRFD 8(Z10.S), P3, PSTL3KEEP                     // 4ced8185
+	ZPRFD 8(Z10.D), P3, PSTL3KEEP                     // 4ced81c5
+	ZPRFH 8(Z10.S), P3, PSTL3KEEP                     // 4ced8484
+	ZPRFH 8(Z10.D), P3, PSTL3KEEP                     // 4ced84c4
+	ZPRFW 8(Z10.S), P3, PSTL3KEEP                     // 4ced0285
+	ZPRFW 8(Z10.D), P3, PSTL3KEEP                     // 4ced02c5
+	ZST1B 6(Z7.S), P4, [Z13.S]                        // edb066e4
+	ZST1B 6(Z7.D), P4, [Z13.D]                        // edb046e4
+	ZST1D 8(Z14.D), P6, [Z6.D]                        // c6b9c1e5
+	ZST1H 6(Z7.S), P4, [Z13.S]                        // edb0e3e4
+	ZST1H 6(Z7.D), P4, [Z13.D]                        // edb0c3e4
+	ZST1W 12(Z0.S), P6, [Z25.S]                       // 19b863e5
+	ZST1W 12(Z0.D), P6, [Z25.D]                       // 19b843e5
 	RET
diff --git a/src/cmd/asm/internal/asm/testdata/arm64sveerror.s b/src/cmd/asm/internal/asm/testdata/arm64sveerror.s
index 7fb955dcb0..ea33010739 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64sveerror.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64sveerror.s
@@ -1145,4 +1145,67 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
 	ZPRFW (Z27.S.UXTW<<2)(RSP), P7.Z, PLDL1KEEP       // ERROR "illegal combination from SVE"
 	ZPRFW (Z27.D.UXTW<<2)(RSP), P7.Z, PLDL1KEEP       // ERROR "illegal combination from SVE"
 	ZPRFW (Z27.D<<2)(RSP), P13.Z, PSTL3STRM           // ERROR "illegal combination from SVE"
+	ZLD1B 11(Z1.S), P13.Z, [Z11.B]                    // ERROR "illegal combination from SVE"
+	ZLD1B 11(Z1.D), P13.Z, [Z11.B]                    // ERROR "illegal combination from SVE"
+	ZLD1D 11(Z1.D), P13.Z, [Z11.B]                    // ERROR "illegal combination from SVE"
+	ZLD1H 11(Z1.S), P13.Z, [Z11.B]                    // ERROR "illegal combination from SVE"
+	ZLD1H 11(Z1.D), P13.Z, [Z11.B]                    // ERROR "illegal combination from SVE"
+	ZLD1RB 11(RSP), P13.Z, [Z11.B]                    // ERROR "illegal combination from SVE"
+	ZLD1RB 11(RSP), P13.Z, [Z11.B]                    // ERROR "illegal combination from SVE"
+	ZLD1RB 11(RSP), P13.Z, [Z11.B]                    // ERROR "illegal combination from SVE"
+	ZLD1RB 11(RSP), P13.Z, [Z11.B]                    // ERROR "illegal combination from SVE"
+	ZLD1RD 11(RSP), P13.Z, [Z11.B]                    // ERROR "illegal combination from SVE"
+	ZLD1RH 11(RSP), P13.Z, [Z11.B]                    // ERROR "illegal combination from SVE"
+	ZLD1RH 11(RSP), P13.Z, [Z11.B]                    // ERROR "illegal combination from SVE"
+	ZLD1RH 11(RSP), P13.Z, [Z11.B]                    // ERROR "illegal combination from SVE"
+	ZLD1ROB 11(RSP), P13.Z, [Z11.B]                   // ERROR "illegal combination from SVE"
+	ZLD1ROD 11(RSP), P13.Z, [Z11.B]                   // ERROR "illegal combination from SVE"
+	ZLD1ROH 11(RSP), P13.Z, [Z11.B]                   // ERROR "illegal combination from SVE"
+	ZLD1ROW 11(RSP), P13.Z, [Z11.B]                   // ERROR "illegal combination from SVE"
+	ZLD1RQB 11(RSP), P13.Z, [Z11.B]                   // ERROR "illegal combination from SVE"
+	ZLD1RQD 11(RSP), P13.Z, [Z11.B]                   // ERROR "illegal combination from SVE"
+	ZLD1RQH 11(RSP), P13.Z, [Z11.B]                   // ERROR "illegal combination from SVE"
+	ZLD1RQW 11(RSP), P13.Z, [Z11.B]                   // ERROR "illegal combination from SVE"
+	ZLD1RSB 11(RSP), P13.Z, [Z11.B]                   // ERROR "illegal combination from SVE"
+	ZLD1RSB 11(RSP), P13.Z, [Z11.B]                   // ERROR "illegal combination from SVE"
+	ZLD1RSB 11(RSP), P13.Z, [Z11.B]                   // ERROR "illegal combination from SVE"
+	ZLD1RSH 11(RSP), P13.Z, [Z11.B]                   // ERROR "illegal combination from SVE"
+	ZLD1RSH 11(RSP), P13.Z, [Z11.B]                   // ERROR "illegal combination from SVE"
+	ZLD1RSW 11(RSP), P13.Z, [Z11.B]                   // ERROR "illegal combination from SVE"
+	ZLD1RW 11(RSP), P13.Z, [Z11.B]                    // ERROR "illegal combination from SVE"
+	ZLD1RW 11(RSP), P13.Z, [Z11.B]                    // ERROR "illegal combination from SVE"
+	ZLD1SB 11(Z1.S), P13.Z, [Z11.B]                   // ERROR "illegal combination from SVE"
+	ZLD1SB 11(Z1.D), P13.Z, [Z11.B]                   // ERROR "illegal combination from SVE"
+	ZLD1SH 11(Z1.S), P13.Z, [Z11.B]                   // ERROR "illegal combination from SVE"
+	ZLD1SH 11(Z1.D), P13.Z, [Z11.B]                   // ERROR "illegal combination from SVE"
+	ZLD1SW 11(Z1.D), P13.Z, [Z11.B]                   // ERROR "illegal combination from SVE"
+	ZLD1W 11(Z1.S), P13.Z, [Z11.B]                    // ERROR "illegal combination from SVE"
+	ZLD1W 11(Z1.D), P13.Z, [Z11.B]                    // ERROR "illegal combination from SVE"
+	ZLDFF1B 11(Z1.S), P13.Z, [Z11.B]                  // ERROR "illegal combination from SVE"
+	ZLDFF1B 11(Z1.D), P13.Z, [Z11.B]                  // ERROR "illegal combination from SVE"
+	ZLDFF1D 11(Z1.D), P13.Z, [Z11.B]                  // ERROR "illegal combination from SVE"
+	ZLDFF1H 11(Z1.S), P13.Z, [Z11.B]                  // ERROR "illegal combination from SVE"
+	ZLDFF1H 11(Z1.D), P13.Z, [Z11.B]                  // ERROR "illegal combination from SVE"
+	ZLDFF1SB 11(Z1.S), P13.Z, [Z11.B]                 // ERROR "illegal combination from SVE"
+	ZLDFF1SB 11(Z1.D), P13.Z, [Z11.B]                 // ERROR "illegal combination from SVE"
+	ZLDFF1SH 11(Z1.S), P13.Z, [Z11.B]                 // ERROR "illegal combination from SVE"
+	ZLDFF1SH 11(Z1.D), P13.Z, [Z11.B]                 // ERROR "illegal combination from SVE"
+	ZLDFF1SW 11(Z1.D), P13.Z, [Z11.B]                 // ERROR "illegal combination from SVE"
+	ZLDFF1W 11(Z1.S), P13.Z, [Z11.B]                  // ERROR "illegal combination from SVE"
+	ZLDFF1W 11(Z1.D), P13.Z, [Z11.B]                  // ERROR "illegal combination from SVE"
+	ZPRFB 11(Z1.S), P13.Z, PSTL3STRM                  // ERROR "illegal combination from SVE"
+	ZPRFB 11(Z1.D), P13.Z, PSTL3STRM                  // ERROR "illegal combination from SVE"
+	ZPRFD 11(Z1.S), P13.Z, PSTL3STRM                  // ERROR "illegal combination from SVE"
+	ZPRFD 11(Z1.D), P13.Z, PSTL3STRM                  // ERROR "illegal combination from SVE"
+	ZPRFH 11(Z1.S), P13.Z, PSTL3STRM                  // ERROR "illegal combination from SVE"
+	ZPRFH 11(Z1.D), P13.Z, PSTL3STRM                  // ERROR "illegal combination from SVE"
+	ZPRFW 11(Z1.S), P13.Z, PSTL3STRM                  // ERROR "illegal combination from SVE"
+	ZPRFW 11(Z1.D), P13.Z, PSTL3STRM                  // ERROR "illegal combination from SVE"
+	ZST1B 11(Z1.S), P13.Z, [Z11.B]                    // ERROR "illegal combination from SVE"
+	ZST1B 11(Z1.D), P13.Z, [Z11.B]                    // ERROR "illegal combination from SVE"
+	ZST1D 11(Z1.D), P13.Z, [Z11.B]                    // ERROR "illegal combination from SVE"
+	ZST1H 11(Z1.S), P13.Z, [Z11.B]                    // ERROR "illegal combination from SVE"
+	ZST1H 11(Z1.D), P13.Z, [Z11.B]                    // ERROR "illegal combination from SVE"
+	ZST1W 11(Z1.S), P13.Z, [Z11.B]                    // ERROR "illegal combination from SVE"
+	ZST1W 11(Z1.D), P13.Z, [Z11.B]                    // ERROR "illegal combination from SVE"
 	RET
diff --git a/src/cmd/internal/obj/arm64/anames_gen.go b/src/cmd/internal/obj/arm64/anames_gen.go
index 28bc47c02d..5ca4524997 100644
--- a/src/cmd/internal/obj/arm64/anames_gen.go
+++ b/src/cmd/internal/obj/arm64/anames_gen.go
@@ -336,6 +336,9 @@ var sveAnames = []string{
 	"ZLD1D",
 	"ZLD1H",
 	"ZLD1Q",
+	"ZLD1RB",
+	"ZLD1RD",
+	"ZLD1RH",
 	"ZLD1ROB",
 	"ZLD1ROD",
 	"ZLD1ROH",
@@ -344,6 +347,10 @@ var sveAnames = []string{
 	"ZLD1RQD",
 	"ZLD1RQH",
 	"ZLD1RQW",
+	"ZLD1RSB",
+	"ZLD1RSH",
+	"ZLD1RSW",
+	"ZLD1RW",
 	"ZLD1SB",
 	"ZLD1SH",
 	"ZLD1SW",
diff --git a/src/cmd/internal/obj/arm64/encoding_gen.go b/src/cmd/internal/obj/arm64/encoding_gen.go
index cb3fba2587..ef2fe64286 100644
--- a/src/cmd/internal/obj/arm64/encoding_gen.go
+++ b/src/cmd/internal/obj/arm64/encoding_gen.go
@@ -1997,6 +1997,118 @@ func encodeRm1621XZR(v uint32) (uint32, bool) {
 	return (v & 31) << 16, true
 }
 
+// encodeImm41620V1 is the implementation of the following encoding logic:
+// Is the optional signed immediate byte offset, a multiple of 16 in the range -128 to 112, defaulting to 0, encoded in the "imm4" field.
+// bit range mappings:
+// imm4: [16:20)
+func encodeImm41620V1(v uint32) (uint32, bool) {
+	vi := int32(v)
+	if vi >= -128 && vi <= 112 && vi%16 == 0 {
+		return uint32((vi/16)&15) << 16, true
+	}
+	return 0, false
+}
+
+// encodeImm41620V2 is the implementation of the following encoding logic:
+// Is the optional signed immediate byte offset, a multiple of 32 in the range -256 to 224, defaulting to 0, encoded in the "imm4" field.
+// bit range mappings:
+// imm4: [16:20)
+func encodeImm41620V2(v uint32) (uint32, bool) {
+	vi := int32(v)
+	if vi >= -256 && vi <= 224 && vi%32 == 0 {
+		return uint32((vi/32)&15) << 16, true
+	}
+	return 0, false
+}
+
+// encodeImm61622V1 is the implementation of the following encoding logic:
+// Is the optional unsigned immediate byte offset, a multiple of 2 in the range 0 to 126, defaulting to 0, encoded in the "imm6" field.
+// bit range mappings:
+// imm6: [16:22)
+func encodeImm61622V1(v uint32) (uint32, bool) {
+	if v <= 126 && v%2 == 0 {
+		return (v / 2) << 16, true
+	}
+	return 0, false
+}
+
+// encodeImm51621V1 is the implementation of the following encoding logic:
+// Is the optional unsigned immediate byte offset, a multiple of 2 in the range 0 to 62, defaulting to 0, encoded in the "imm5" field.
+// bit range mappings:
+// imm5: [16:21)
+func encodeImm51621V1(v uint32) (uint32, bool) {
+	if v <= 62 && v%2 == 0 {
+		return (v / 2) << 16, true
+	}
+	return 0, false
+}
+
+// encodeImm51621V2 is the implementation of the following encoding logic:
+// Is the optional unsigned immediate byte offset, a multiple of 4 in the range 0 to 124, defaulting to 0, encoded in the "imm5" field.
+// bit range mappings:
+// imm5: [16:21)
+func encodeImm51621V2(v uint32) (uint32, bool) {
+	if v <= 124 && v%4 == 0 {
+		return (v / 4) << 16, true
+	}
+	return 0, false
+}
+
+// encodeImm61622V2 is the implementation of the following encoding logic:
+// Is the optional unsigned immediate byte offset, a multiple of 4 in the range 0 to 252, defaulting to 0, encoded in the "imm6" field.
+// bit range mappings:
+// imm6: [16:22)
+func encodeImm61622V2(v uint32) (uint32, bool) {
+	if v <= 252 && v%4 == 0 {
+		return (v / 4) << 16, true
+	}
+	return 0, false
+}
+
+// encodeImm51621V3 is the implementation of the following encoding logic:
+// Is the optional unsigned immediate byte offset, a multiple of 8 in the range 0 to 248, defaulting to 0, encoded in the "imm5" field.
+// bit range mappings:
+// imm5: [16:21)
+func encodeImm51621V3(v uint32) (uint32, bool) {
+	if v <= 248 && v%8 == 0 {
+		return (v / 8) << 16, true
+	}
+	return 0, false
+}
+
+// encodeImm61622V3 is the implementation of the following encoding logic:
+// Is the optional unsigned immediate byte offset, a multiple of 8 in the range 0 to 504, defaulting to 0, encoded in the "imm6" field.
+// bit range mappings:
+// imm6: [16:22)
+func encodeImm61622V3(v uint32) (uint32, bool) {
+	if v <= 504 && v%8 == 0 {
+		return (v / 8) << 16, true
+	}
+	return 0, false
+}
+
+// encodeImm51621V4 is the implementation of the following encoding logic:
+// Is the optional unsigned immediate byte offset, in the range 0 to 31, defaulting to 0, encoded in the "imm5" field.
+// bit range mappings:
+// imm5: [16:21)
+func encodeImm51621V4(v uint32) (uint32, bool) {
+	if v <= 31 {
+		return v << 16, true
+	}
+	return 0, false
+}
+
+// encodeImm61622V4 is the implementation of the following encoding logic:
+// Is the optional unsigned immediate byte offset, in the range 0 to 63, defaulting to 0, encoded in the "imm6" field.
+// bit range mappings:
+// imm6: [16:22)
+func encodeImm61622V4(v uint32) (uint32, bool) {
+	if v <= 63 {
+		return v << 16, true
+	}
+	return 0, false
+}
+
 // encodeI189 is the implementation of the following encoding logic:
 // Is the portion index, in the range 0 to 1, encoded in the "i1" field.
 // bit range mappings:
diff --git a/src/cmd/internal/obj/arm64/goops_gen.go b/src/cmd/internal/obj/arm64/goops_gen.go
index b7bf97b591..77ecfff4a9 100644
--- a/src/cmd/internal/obj/arm64/goops_gen.go
+++ b/src/cmd/internal/obj/arm64/goops_gen.go
@@ -337,6 +337,9 @@ const (
 	AZLD1D
 	AZLD1H
 	AZLD1Q
+	AZLD1RB
+	AZLD1RD
+	AZLD1RH
 	AZLD1ROB
 	AZLD1ROD
 	AZLD1ROH
@@ -345,6 +348,10 @@ const (
 	AZLD1RQD
 	AZLD1RQH
 	AZLD1RQW
+	AZLD1RSB
+	AZLD1RSH
+	AZLD1RSW
+	AZLD1RW
 	AZLD1SB
 	AZLD1SH
 	AZLD1SW
diff --git a/src/cmd/internal/obj/arm64/inst.go b/src/cmd/internal/obj/arm64/inst.go
index ed415c3ee3..111f707bdd 100644
--- a/src/cmd/internal/obj/arm64/inst.go
+++ b/src/cmd/internal/obj/arm64/inst.go
@@ -144,6 +144,9 @@ func aclass(a *obj.Addr) AClass {
 		}
 	}
 	if a.Type == obj.TYPE_MEM {
+		if a.Index == 0 {
+			return AC_MEMOFF
+		}
 		return AC_MEMEXT
 	}
 	if a.Type == obj.TYPE_SPECIAL {
@@ -349,6 +352,25 @@ func addrComponent(a *obj.Addr, acl AClass, index int) uint32 {
 		default:
 			panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl))
 		}
+	//	AClass: AC_MEMOFF
+	//	GNU mnemonic: [<reg>.<T>, #<imm>]
+	//	Go mnemonic:
+	//		imm(reg.T)
+	//	Encoding:
+	//		Type = TYPE_MEM
+	//		Reg = Base register (with arrangement if applicable)
+	//		Offset = Immediate offset
+	case AC_MEMOFF:
+		switch index {
+		case 0:
+			return uint32(a.Reg & 31)
+		case 1:
+			return uint32((a.Reg >> 5) & 15)
+		case 2:
+			return uint32(a.Offset)
+		default:
+			panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl))
+		}
 	//	AClass: AC_MEMEXT
 	//	GNU mnemonic: [<reg1>.<T1>, <reg2>.<T2>, <mod> <amount>]
 	//	Go mnemonic:
@@ -758,5 +780,6 @@ func (i *instEncoder) tryEncode(p *obj.Prog) (uint32, bool) {
 			}
 		}
 	}
+
 	return bin, true
 }
diff --git a/src/cmd/internal/obj/arm64/inst_gen.go b/src/cmd/internal/obj/arm64/inst_gen.go
index ac36eea943..577ebf3657 100644
--- a/src/cmd/internal/obj/arm64/inst_gen.go
+++ b/src/cmd/internal/obj/arm64/inst_gen.go
@@ -4166,6 +4166,18 @@ var insts = [][]instEncoder{
 			fixedBits: 0x84004000,
 			args:      XnSP__Zm_S__mod___PgZ___Zt_S_,
 		},
+		// ZLD1B [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1B,
+			fixedBits: 0xc420c000,
+			args:      Zn_D__cimm___PgZ___Zt_D___1,
+		},
+		// ZLD1B [<Zn>.S{, #<imm>}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1B,
+			fixedBits: 0x8420c000,
+			args:      Zn_S__cimm___PgZ___Zt_S___1,
+		},
 	},
 	// ZLD1D
 	{
@@ -4193,6 +4205,12 @@ var insts = [][]instEncoder{
 			fixedBits: 0xc5a04000,
 			args:      XnSP__Zm_D__mod_c3___PgZ___Zt_D_,
 		},
+		// ZLD1D [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1D,
+			fixedBits: 0xc5a0c000,
+			args:      Zn_D__cimm___PgZ___Zt_D___4,
+		},
 	},
 	// ZLD1H
 	{
@@ -4250,6 +4268,18 @@ var insts = [][]instEncoder{
 			fixedBits: 0x84a04000,
 			args:      XnSP__Zm_S__mod_c1___PgZ___Zt_S_,
 		},
+		// ZLD1H [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1H,
+			fixedBits: 0xc4a0c000,
+			args:      Zn_D__cimm___PgZ___Zt_D___2,
+		},
+		// ZLD1H [<Zn>.S{, #<imm>}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1H,
+			fixedBits: 0x84a0c000,
+			args:      Zn_S__cimm___PgZ___Zt_S___2,
+		},
 	},
 	// ZLD1Q
 	{
@@ -4260,6 +4290,63 @@ var insts = [][]instEncoder{
 			args:      Zn_D__Xm___PgZ___Zt_Q_,
 		},
 	},
+	// ZLD1RB
+	{
+		// ZLD1RB [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.B }
+		{
+			goOp:      AZLD1RB,
+			fixedBits: 0x84408000,
+			args:      XnSP__cimm___PgZ___Zt_B___1,
+		},
+		// ZLD1RB [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1RB,
+			fixedBits: 0x8440e000,
+			args:      XnSP__cimm___PgZ___Zt_D___1,
+		},
+		// ZLD1RB [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.H }
+		{
+			goOp:      AZLD1RB,
+			fixedBits: 0x8440a000,
+			args:      XnSP__cimm___PgZ___Zt_H___1,
+		},
+		// ZLD1RB [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1RB,
+			fixedBits: 0x8440c000,
+			args:      XnSP__cimm___PgZ___Zt_S___1,
+		},
+	},
+	// ZLD1RD
+	{
+		// ZLD1RD [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1RD,
+			fixedBits: 0x85c0e000,
+			args:      XnSP__cimm___PgZ___Zt_D___4,
+		},
+	},
+	// ZLD1RH
+	{
+		// ZLD1RH [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1RH,
+			fixedBits: 0x84c0e000,
+			args:      XnSP__cimm___PgZ___Zt_D___2,
+		},
+		// ZLD1RH [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.H }
+		{
+			goOp:      AZLD1RH,
+			fixedBits: 0x84c0a000,
+			args:      XnSP__cimm___PgZ___Zt_H___2,
+		},
+		// ZLD1RH [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1RH,
+			fixedBits: 0x84c0c000,
+			args:      XnSP__cimm___PgZ___Zt_S___2,
+		},
+	},
 	// ZLD1ROB
 	{
 		// ZLD1ROB [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt>.B }
@@ -4268,6 +4355,12 @@ var insts = [][]instEncoder{
 			fixedBits: 0xa4200000,
 			args:      XnSP__Xm___PgZ___Zt_B_,
 		},
+		// ZLD1ROB [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.B }
+		{
+			goOp:      AZLD1ROB,
+			fixedBits: 0xa4202000,
+			args:      XnSP__cimm___PgZ___Zt_B___2,
+		},
 	},
 	// ZLD1ROD
 	{
@@ -4277,6 +4370,12 @@ var insts = [][]instEncoder{
 			fixedBits: 0xa5a00000,
 			args:      XnSP__Xm__LSL_c3___PgZ___Zt_D_,
 		},
+		// ZLD1ROD [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1ROD,
+			fixedBits: 0xa5a02000,
+			args:      XnSP__cimm___PgZ___Zt_D___5,
+		},
 	},
 	// ZLD1ROH
 	{
@@ -4286,6 +4385,12 @@ var insts = [][]instEncoder{
 			fixedBits: 0xa4a00000,
 			args:      XnSP__Xm__LSL_c1___PgZ___Zt_H_,
 		},
+		// ZLD1ROH [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.H }
+		{
+			goOp:      AZLD1ROH,
+			fixedBits: 0xa4a02000,
+			args:      XnSP__cimm___PgZ___Zt_H___3,
+		},
 	},
 	// ZLD1ROW
 	{
@@ -4295,6 +4400,12 @@ var insts = [][]instEncoder{
 			fixedBits: 0xa5200000,
 			args:      XnSP__Xm__LSL_c2___PgZ___Zt_S_,
 		},
+		// ZLD1ROW [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1ROW,
+			fixedBits: 0xa5202000,
+			args:      XnSP__cimm___PgZ___Zt_S___3,
+		},
 	},
 	// ZLD1RQB
 	{
@@ -4304,6 +4415,12 @@ var insts = [][]instEncoder{
 			fixedBits: 0xa4000000,
 			args:      XnSP__Xm___PgZ___Zt_B_,
 		},
+		// ZLD1RQB [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.B }
+		{
+			goOp:      AZLD1RQB,
+			fixedBits: 0xa4002000,
+			args:      XnSP__cimm___PgZ___Zt_B___3,
+		},
 	},
 	// ZLD1RQD
 	{
@@ -4313,6 +4430,12 @@ var insts = [][]instEncoder{
 			fixedBits: 0xa5800000,
 			args:      XnSP__Xm__LSL_c3___PgZ___Zt_D_,
 		},
+		// ZLD1RQD [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1RQD,
+			fixedBits: 0xa5802000,
+			args:      XnSP__cimm___PgZ___Zt_D___6,
+		},
 	},
 	// ZLD1RQH
 	{
@@ -4322,6 +4445,12 @@ var insts = [][]instEncoder{
 			fixedBits: 0xa4800000,
 			args:      XnSP__Xm__LSL_c1___PgZ___Zt_H_,
 		},
+		// ZLD1RQH [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.H }
+		{
+			goOp:      AZLD1RQH,
+			fixedBits: 0xa4802000,
+			args:      XnSP__cimm___PgZ___Zt_H___4,
+		},
 	},
 	// ZLD1RQW
 	{
@@ -4331,6 +4460,72 @@ var insts = [][]instEncoder{
 			fixedBits: 0xa5000000,
 			args:      XnSP__Xm__LSL_c2___PgZ___Zt_S_,
 		},
+		// ZLD1RQW [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1RQW,
+			fixedBits: 0xa5002000,
+			args:      XnSP__cimm___PgZ___Zt_S___4,
+		},
+	},
+	// ZLD1RSB
+	{
+		// ZLD1RSB [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1RSB,
+			fixedBits: 0x85c08000,
+			args:      XnSP__cimm___PgZ___Zt_D___1,
+		},
+		// ZLD1RSB [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.H }
+		{
+			goOp:      AZLD1RSB,
+			fixedBits: 0x85c0c000,
+			args:      XnSP__cimm___PgZ___Zt_H___1,
+		},
+		// ZLD1RSB [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1RSB,
+			fixedBits: 0x85c0a000,
+			args:      XnSP__cimm___PgZ___Zt_S___1,
+		},
+	},
+	// ZLD1RSH
+	{
+		// ZLD1RSH [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1RSH,
+			fixedBits: 0x85408000,
+			args:      XnSP__cimm___PgZ___Zt_D___2,
+		},
+		// ZLD1RSH [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1RSH,
+			fixedBits: 0x8540a000,
+			args:      XnSP__cimm___PgZ___Zt_S___2,
+		},
+	},
+	// ZLD1RSW
+	{
+		// ZLD1RSW [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1RSW,
+			fixedBits: 0x84c08000,
+			args:      XnSP__cimm___PgZ___Zt_D___3,
+		},
+	},
+	// ZLD1RW
+	{
+		// ZLD1RW [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1RW,
+			fixedBits: 0x8540e000,
+			args:      XnSP__cimm___PgZ___Zt_D___3,
+		},
+		// ZLD1RW [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1RW,
+			fixedBits: 0x8540c000,
+			args:      XnSP__cimm___PgZ___Zt_S___5,
+		},
 	},
 	// ZLD1SB
 	{
@@ -4370,6 +4565,18 @@ var insts = [][]instEncoder{
 			fixedBits: 0x84000000,
 			args:      XnSP__Zm_S__mod___PgZ___Zt_S_,
 		},
+		// ZLD1SB [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1SB,
+			fixedBits: 0xc4208000,
+			args:      Zn_D__cimm___PgZ___Zt_D___1,
+		},
+		// ZLD1SB [<Zn>.S{, #<imm>}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1SB,
+			fixedBits: 0x84208000,
+			args:      Zn_S__cimm___PgZ___Zt_S___1,
+		},
 	},
 	// ZLD1SH
 	{
@@ -4421,6 +4628,18 @@ var insts = [][]instEncoder{
 			fixedBits: 0x84a00000,
 			args:      XnSP__Zm_S__mod_c1___PgZ___Zt_S_,
 		},
+		// ZLD1SH [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1SH,
+			fixedBits: 0xc4a08000,
+			args:      Zn_D__cimm___PgZ___Zt_D___2,
+		},
+		// ZLD1SH [<Zn>.S{, #<imm>}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1SH,
+			fixedBits: 0x84a08000,
+			args:      Zn_S__cimm___PgZ___Zt_S___2,
+		},
 	},
 	// ZLD1SW
 	{
@@ -4454,6 +4673,12 @@ var insts = [][]instEncoder{
 			fixedBits: 0xc5200000,
 			args:      XnSP__Zm_D__mod_c2___PgZ___Zt_D_,
 		},
+		// ZLD1SW [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1SW,
+			fixedBits: 0xc5208000,
+			args:      Zn_D__cimm___PgZ___Zt_D___3,
+		},
 	},
 	// ZLD1W
 	{
@@ -4493,6 +4718,18 @@ var insts = [][]instEncoder{
 			fixedBits: 0x85204000,
 			args:      XnSP__Zm_S__mod_c2___PgZ___Zt_S_,
 		},
+		// ZLD1W [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1W,
+			fixedBits: 0xc520c000,
+			args:      Zn_D__cimm___PgZ___Zt_D___3,
+		},
+		// ZLD1W [<Zn>.S{, #<imm>}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1W,
+			fixedBits: 0x8520c000,
+			args:      Zn_S__cimm___PgZ___Zt_S___3,
+		},
 	},
 	// ZLD2B
 	{
@@ -4673,6 +4910,18 @@ var insts = [][]instEncoder{
 			fixedBits: 0x84006000,
 			args:      XnSP__Zm_S__mod___PgZ___Zt_S_,
 		},
+		// ZLDFF1B [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1B,
+			fixedBits: 0xc420e000,
+			args:      Zn_D__cimm___PgZ___Zt_D___1,
+		},
+		// ZLDFF1B [<Zn>.S{, #<imm>}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLDFF1B,
+			fixedBits: 0x8420e000,
+			args:      Zn_S__cimm___PgZ___Zt_S___1,
+		},
 	},
 	// ZLDFF1D
 	{
@@ -4706,6 +4955,12 @@ var insts = [][]instEncoder{
 			fixedBits: 0xc5a06000,
 			args:      XnSP__Zm_D__mod_c3___PgZ___Zt_D_,
 		},
+		// ZLDFF1D [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1D,
+			fixedBits: 0xc5a0e000,
+			args:      Zn_D__cimm___PgZ___Zt_D___4,
+		},
 	},
 	// ZLDFF1H
 	{
@@ -4763,6 +5018,18 @@ var insts = [][]instEncoder{
 			fixedBits: 0x84a06000,
 			args:      XnSP__Zm_S__mod_c1___PgZ___Zt_S_,
 		},
+		// ZLDFF1H [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1H,
+			fixedBits: 0xc4a0e000,
+			args:      Zn_D__cimm___PgZ___Zt_D___2,
+		},
+		// ZLDFF1H [<Zn>.S{, #<imm>}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLDFF1H,
+			fixedBits: 0x84a0e000,
+			args:      Zn_S__cimm___PgZ___Zt_S___2,
+		},
 	},
 	// ZLDFF1SB
 	{
@@ -4802,6 +5069,18 @@ var insts = [][]instEncoder{
 			fixedBits: 0x84002000,
 			args:      XnSP__Zm_S__mod___PgZ___Zt_S_,
 		},
+		// ZLDFF1SB [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1SB,
+			fixedBits: 0xc420a000,
+			args:      Zn_D__cimm___PgZ___Zt_D___1,
+		},
+		// ZLDFF1SB [<Zn>.S{, #<imm>}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLDFF1SB,
+			fixedBits: 0x8420a000,
+			args:      Zn_S__cimm___PgZ___Zt_S___1,
+		},
 	},
 	// ZLDFF1SH
 	{
@@ -4853,6 +5132,18 @@ var insts = [][]instEncoder{
 			fixedBits: 0x84a02000,
 			args:      XnSP__Zm_S__mod_c1___PgZ___Zt_S_,
 		},
+		// ZLDFF1SH [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1SH,
+			fixedBits: 0xc4a0a000,
+			args:      Zn_D__cimm___PgZ___Zt_D___2,
+		},
+		// ZLDFF1SH [<Zn>.S{, #<imm>}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLDFF1SH,
+			fixedBits: 0x84a0a000,
+			args:      Zn_S__cimm___PgZ___Zt_S___2,
+		},
 	},
 	// ZLDFF1SW
 	{
@@ -4886,6 +5177,12 @@ var insts = [][]instEncoder{
 			fixedBits: 0xc5202000,
 			args:      XnSP__Zm_D__mod_c2___PgZ___Zt_D_,
 		},
+		// ZLDFF1SW [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1SW,
+			fixedBits: 0xc520a000,
+			args:      Zn_D__cimm___PgZ___Zt_D___3,
+		},
 	},
 	// ZLDFF1W
 	{
@@ -4937,6 +5234,18 @@ var insts = [][]instEncoder{
 			fixedBits: 0x85206000,
 			args:      XnSP__Zm_S__mod_c2___PgZ___Zt_S_,
 		},
+		// ZLDFF1W [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1W,
+			fixedBits: 0xc520e000,
+			args:      Zn_D__cimm___PgZ___Zt_D___3,
+		},
+		// ZLDFF1W [<Zn>.S{, #<imm>}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLDFF1W,
+			fixedBits: 0x8520e000,
+			args:      Zn_S__cimm___PgZ___Zt_S___3,
+		},
 	},
 	// ZLDNT1B
 	{
@@ -5567,6 +5876,18 @@ var insts = [][]instEncoder{
 			fixedBits: 0x84200000,
 			args:      XnSP__Zm_S__mod___Pg__prfop,
 		},
+		// ZPRFB [<Zn>.D{, #<imm>}], <Pg>, <prfop>
+		{
+			goOp:      AZPRFB,
+			fixedBits: 0xc400e000,
+			args:      Zn_D__cimm___Pg__prfop__1,
+		},
+		// ZPRFB [<Zn>.S{, #<imm>}], <Pg>, <prfop>
+		{
+			goOp:      AZPRFB,
+			fixedBits: 0x8400e000,
+			args:      Zn_S__cimm___Pg__prfop__1,
+		},
 	},
 	// ZPRFD
 	{
@@ -5588,6 +5909,18 @@ var insts = [][]instEncoder{
 			fixedBits: 0x84206000,
 			args:      XnSP__Zm_S__mod_c3___Pg__prfop,
 		},
+		// ZPRFD [<Zn>.D{, #<imm>}], <Pg>, <prfop>
+		{
+			goOp:      AZPRFD,
+			fixedBits: 0xc580e000,
+			args:      Zn_D__cimm___Pg__prfop__2,
+		},
+		// ZPRFD [<Zn>.S{, #<imm>}], <Pg>, <prfop>
+		{
+			goOp:      AZPRFD,
+			fixedBits: 0x8580e000,
+			args:      Zn_S__cimm___Pg__prfop__2,
+		},
 	},
 	// ZPRFH
 	{
@@ -5609,6 +5942,18 @@ var insts = [][]instEncoder{
 			fixedBits: 0x84202000,
 			args:      XnSP__Zm_S__mod_c1___Pg__prfop,
 		},
+		// ZPRFH [<Zn>.D{, #<imm>}], <Pg>, <prfop>
+		{
+			goOp:      AZPRFH,
+			fixedBits: 0xc480e000,
+			args:      Zn_D__cimm___Pg__prfop__3,
+		},
+		// ZPRFH [<Zn>.S{, #<imm>}], <Pg>, <prfop>
+		{
+			goOp:      AZPRFH,
+			fixedBits: 0x8480e000,
+			args:      Zn_S__cimm___Pg__prfop__3,
+		},
 	},
 	// ZPRFW
 	{
@@ -5630,6 +5975,18 @@ var insts = [][]instEncoder{
 			fixedBits: 0x84204000,
 			args:      XnSP__Zm_S__mod_c2___Pg__prfop,
 		},
+		// ZPRFW [<Zn>.D{, #<imm>}], <Pg>, <prfop>
+		{
+			goOp:      AZPRFW,
+			fixedBits: 0xc500e000,
+			args:      Zn_D__cimm___Pg__prfop__4,
+		},
+		// ZPRFW [<Zn>.S{, #<imm>}], <Pg>, <prfop>
+		{
+			goOp:      AZPRFW,
+			fixedBits: 0x8500e000,
+			args:      Zn_S__cimm___Pg__prfop__4,
+		},
 	},
 	// ZRADDHNB
 	{
@@ -7181,6 +7538,18 @@ var insts = [][]instEncoder{
 			fixedBits: 0xe4408000,
 			args:      XnSP__Zm_S__mod___Pg___Zt_S_,
 		},
+		// ZST1B [<Zn>.D{, #<imm>}], <Pg>, { <Zt>.D }
+		{
+			goOp:      AZST1B,
+			fixedBits: 0xe440a000,
+			args:      Zn_D__cimm___Pg___Zt_D___1,
+		},
+		// ZST1B [<Zn>.S{, #<imm>}], <Pg>, { <Zt>.S }
+		{
+			goOp:      AZST1B,
+			fixedBits: 0xe460a000,
+			args:      Zn_S__cimm___Pg___Zt_S___1,
+		},
 	},
 	// ZST1D
 	{
@@ -7208,6 +7577,12 @@ var insts = [][]instEncoder{
 			fixedBits: 0xe5a08000,
 			args:      XnSP__Zm_D__mod_c3___Pg___Zt_D_,
 		},
+		// ZST1D [<Zn>.D{, #<imm>}], <Pg>, { <Zt>.D }
+		{
+			goOp:      AZST1D,
+			fixedBits: 0xe5c0a000,
+			args:      Zn_D__cimm___Pg___Zt_D___2,
+		},
 	},
 	// ZST1H
 	{
@@ -7253,6 +7628,18 @@ var insts = [][]instEncoder{
 			fixedBits: 0xe4e08000,
 			args:      XnSP__Zm_S__mod_c1___Pg___Zt_S_,
 		},
+		// ZST1H [<Zn>.D{, #<imm>}], <Pg>, { <Zt>.D }
+		{
+			goOp:      AZST1H,
+			fixedBits: 0xe4c0a000,
+			args:      Zn_D__cimm___Pg___Zt_D___3,
+		},
+		// ZST1H [<Zn>.S{, #<imm>}], <Pg>, { <Zt>.S }
+		{
+			goOp:      AZST1H,
+			fixedBits: 0xe4e0a000,
+			args:      Zn_S__cimm___Pg___Zt_S___2,
+		},
 	},
 	// ZST1Q
 	{
@@ -7301,6 +7688,18 @@ var insts = [][]instEncoder{
 			fixedBits: 0xe5608000,
 			args:      XnSP__Zm_S__mod_c2___Pg___Zt_S_,
 		},
+		// ZST1W [<Zn>.D{, #<imm>}], <Pg>, { <Zt>.D }
+		{
+			goOp:      AZST1W,
+			fixedBits: 0xe540a000,
+			args:      Zn_D__cimm___Pg___Zt_D___4,
+		},
+		// ZST1W [<Zn>.S{, #<imm>}], <Pg>, { <Zt>.S }
+		{
+			goOp:      AZST1W,
+			fixedBits: 0xe560a000,
+			args:      Zn_S__cimm___Pg___Zt_S___3,
+		},
 	},
 	// ZST2B
 	{
@@ -10621,6 +11020,118 @@ var a_MEMEXT_Zn510V2_SzSD2223_Zm1621V3_SzSD2223_Msz1012_Msz1012Amount = operand{
 	},
 }
 
+var a_MEMOFF_Rn510SPV2_Noop_Imm41620V1 = operand{
+	class: AC_MEMOFF, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeImm41620V1, enc_imm4},
+	},
+}
+
+var a_MEMOFF_Rn510SPV2_Noop_Imm41620V2 = operand{
+	class: AC_MEMOFF, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeImm41620V2, enc_imm4},
+	},
+}
+
+var a_MEMOFF_Rn510SPV2_Noop_Imm61622V1 = operand{
+	class: AC_MEMOFF, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeImm61622V1, enc_imm6},
+	},
+}
+
+var a_MEMOFF_Rn510SPV2_Noop_Imm61622V2 = operand{
+	class: AC_MEMOFF, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeImm61622V2, enc_imm6},
+	},
+}
+
+var a_MEMOFF_Rn510SPV2_Noop_Imm61622V3 = operand{
+	class: AC_MEMOFF, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeImm61622V3, enc_imm6},
+	},
+}
+
+var a_MEMOFF_Rn510SPV2_Noop_Imm61622V4 = operand{
+	class: AC_MEMOFF, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeImm61622V4, enc_imm6},
+	},
+}
+
+var a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V1 = operand{
+	class: AC_MEMOFF, elemEncoders: []elemEncoder{
+		{encodeZn510V2, enc_Zn},
+		{encodeArngDCheck, enc_NIL},
+		{encodeImm51621V1, enc_imm5},
+	},
+}
+
+var a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V2 = operand{
+	class: AC_MEMOFF, elemEncoders: []elemEncoder{
+		{encodeZn510V2, enc_Zn},
+		{encodeArngDCheck, enc_NIL},
+		{encodeImm51621V2, enc_imm5},
+	},
+}
+
+var a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V3 = operand{
+	class: AC_MEMOFF, elemEncoders: []elemEncoder{
+		{encodeZn510V2, enc_Zn},
+		{encodeArngDCheck, enc_NIL},
+		{encodeImm51621V3, enc_imm5},
+	},
+}
+
+var a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V4 = operand{
+	class: AC_MEMOFF, elemEncoders: []elemEncoder{
+		{encodeZn510V2, enc_Zn},
+		{encodeArngDCheck, enc_NIL},
+		{encodeImm51621V4, enc_imm5},
+	},
+}
+
+var a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V1 = operand{
+	class: AC_MEMOFF, elemEncoders: []elemEncoder{
+		{encodeZn510V2, enc_Zn},
+		{encodeArngSCheck, enc_NIL},
+		{encodeImm51621V1, enc_imm5},
+	},
+}
+
+var a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V2 = operand{
+	class: AC_MEMOFF, elemEncoders: []elemEncoder{
+		{encodeZn510V2, enc_Zn},
+		{encodeArngSCheck, enc_NIL},
+		{encodeImm51621V2, enc_imm5},
+	},
+}
+
+var a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V3 = operand{
+	class: AC_MEMOFF, elemEncoders: []elemEncoder{
+		{encodeZn510V2, enc_Zn},
+		{encodeArngSCheck, enc_NIL},
+		{encodeImm51621V3, enc_imm5},
+	},
+}
+
+var a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V4 = operand{
+	class: AC_MEMOFF, elemEncoders: []elemEncoder{
+		{encodeZn510V2, enc_Zn},
+		{encodeArngSCheck, enc_NIL},
+		{encodeImm51621V4, enc_imm5},
+	},
+}
+
 var a_PREGIDX_PnN_58_Noop_I189 = operand{
 	class: AC_PREGIDX, elemEncoders: []elemEncoder{
 		{encodePnN_58, enc_PNn},
@@ -12043,6 +12554,114 @@ var XnSP__Zm_S__mod_c3___Pg__prfop = []operand{
 	a_SPECIAL_Prfop04,
 }
 
+var XnSP__cimm___PgZ___Zt_B___1 = []operand{
+	a_MEMOFF_Rn510SPV2_Noop_Imm61622V4,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngBCheck,
+}
+
+var XnSP__cimm___PgZ___Zt_B___2 = []operand{
+	a_MEMOFF_Rn510SPV2_Noop_Imm41620V2,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngBCheck,
+}
+
+var XnSP__cimm___PgZ___Zt_B___3 = []operand{
+	a_MEMOFF_Rn510SPV2_Noop_Imm41620V1,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngBCheck,
+}
+
+var XnSP__cimm___PgZ___Zt_D___1 = []operand{
+	a_MEMOFF_Rn510SPV2_Noop_Imm61622V4,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__cimm___PgZ___Zt_D___2 = []operand{
+	a_MEMOFF_Rn510SPV2_Noop_Imm61622V1,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__cimm___PgZ___Zt_D___3 = []operand{
+	a_MEMOFF_Rn510SPV2_Noop_Imm61622V2,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__cimm___PgZ___Zt_D___4 = []operand{
+	a_MEMOFF_Rn510SPV2_Noop_Imm61622V3,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__cimm___PgZ___Zt_D___5 = []operand{
+	a_MEMOFF_Rn510SPV2_Noop_Imm41620V2,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__cimm___PgZ___Zt_D___6 = []operand{
+	a_MEMOFF_Rn510SPV2_Noop_Imm41620V1,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__cimm___PgZ___Zt_H___1 = []operand{
+	a_MEMOFF_Rn510SPV2_Noop_Imm61622V4,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngHCheck,
+}
+
+var XnSP__cimm___PgZ___Zt_H___2 = []operand{
+	a_MEMOFF_Rn510SPV2_Noop_Imm61622V1,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngHCheck,
+}
+
+var XnSP__cimm___PgZ___Zt_H___3 = []operand{
+	a_MEMOFF_Rn510SPV2_Noop_Imm41620V2,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngHCheck,
+}
+
+var XnSP__cimm___PgZ___Zt_H___4 = []operand{
+	a_MEMOFF_Rn510SPV2_Noop_Imm41620V1,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngHCheck,
+}
+
+var XnSP__cimm___PgZ___Zt_S___1 = []operand{
+	a_MEMOFF_Rn510SPV2_Noop_Imm61622V4,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var XnSP__cimm___PgZ___Zt_S___2 = []operand{
+	a_MEMOFF_Rn510SPV2_Noop_Imm61622V1,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var XnSP__cimm___PgZ___Zt_S___3 = []operand{
+	a_MEMOFF_Rn510SPV2_Noop_Imm41620V2,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var XnSP__cimm___PgZ___Zt_S___4 = []operand{
+	a_MEMOFF_Rn510SPV2_Noop_Imm41620V1,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var XnSP__cimm___PgZ___Zt_S___5 = []operand{
+	a_MEMOFF_Rn510SPV2_Noop_Imm61622V2,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
 var Za_D__Zm_D__Zdn_D = []operand{
 	a_ARNG_Za5103Rd_ArngDCheck,
 	a_ARNG_Zm1621V2_ArngDCheck,
@@ -12675,6 +13294,78 @@ var Zn_D__Zm_D__UXTWamount___Zd_D = []operand{
 	a_ARNG_Zd_ArngDCheck,
 }
 
+var Zn_D__cimm___PgZ___Zt_D___1 = []operand{
+	a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V4,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var Zn_D__cimm___PgZ___Zt_D___2 = []operand{
+	a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V1,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var Zn_D__cimm___PgZ___Zt_D___3 = []operand{
+	a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V2,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var Zn_D__cimm___PgZ___Zt_D___4 = []operand{
+	a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V3,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var Zn_D__cimm___Pg___Zt_D___1 = []operand{
+	a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V4,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var Zn_D__cimm___Pg___Zt_D___2 = []operand{
+	a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V3,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var Zn_D__cimm___Pg___Zt_D___3 = []operand{
+	a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V1,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var Zn_D__cimm___Pg___Zt_D___4 = []operand{
+	a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V2,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var Zn_D__cimm___Pg__prfop__1 = []operand{
+	a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V4,
+	a_PREG_Pg1013_Noop,
+	a_SPECIAL_Prfop04,
+}
+
+var Zn_D__cimm___Pg__prfop__2 = []operand{
+	a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V3,
+	a_PREG_Pg1013_Noop,
+	a_SPECIAL_Prfop04,
+}
+
+var Zn_D__cimm___Pg__prfop__3 = []operand{
+	a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V1,
+	a_PREG_Pg1013_Noop,
+	a_SPECIAL_Prfop04,
+}
+
+var Zn_D__cimm___Pg__prfop__4 = []operand{
+	a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V2,
+	a_PREG_Pg1013_Noop,
+	a_SPECIAL_Prfop04,
+}
+
 var Zn_H__PgM__Zd_D = []operand{
 	a_ARNG_Zn510Src_ArngHCheck,
 	a_PREGZM_Pg1013_MergePredCheck,
@@ -12771,6 +13462,66 @@ var Zn_S__Xm___Pg___Zt_S_ = []operand{
 	a_REGLIST1_Zt05_ArngSCheck,
 }
 
+var Zn_S__cimm___PgZ___Zt_S___1 = []operand{
+	a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V4,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var Zn_S__cimm___PgZ___Zt_S___2 = []operand{
+	a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V1,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var Zn_S__cimm___PgZ___Zt_S___3 = []operand{
+	a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V2,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var Zn_S__cimm___Pg___Zt_S___1 = []operand{
+	a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V4,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var Zn_S__cimm___Pg___Zt_S___2 = []operand{
+	a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V1,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var Zn_S__cimm___Pg___Zt_S___3 = []operand{
+	a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V2,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var Zn_S__cimm___Pg__prfop__1 = []operand{
+	a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V4,
+	a_PREG_Pg1013_Noop,
+	a_SPECIAL_Prfop04,
+}
+
+var Zn_S__cimm___Pg__prfop__2 = []operand{
+	a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V3,
+	a_PREG_Pg1013_Noop,
+	a_SPECIAL_Prfop04,
+}
+
+var Zn_S__cimm___Pg__prfop__3 = []operand{
+	a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V1,
+	a_PREG_Pg1013_Noop,
+	a_SPECIAL_Prfop04,
+}
+
+var Zn_S__cimm___Pg__prfop__4 = []operand{
+	a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V2,
+	a_PREG_Pg1013_Noop,
+	a_SPECIAL_Prfop04,
+}
+
 var Zn_T__PgM__Zd_T__1 = []operand{
 	a_ARNG_Zn510Src_SizeHSD2224,
 	a_PREGZM_Pg1013_MergePredCheck,
diff --git a/src/cmd/internal/obj/util.go b/src/cmd/internal/obj/util.go
index 4349f4d741..fffafeba05 100644
--- a/src/cmd/internal/obj/util.go
+++ b/src/cmd/internal/obj/util.go
@@ -302,7 +302,7 @@ func writeDconv(w io.Writer, p *Prog, a *Addr, abiDetail bool) {
 		a.writeNameTo(w, abiDetail)
 
 	case TYPE_MEM:
-		if buildcfg.GOARCH == "arm64" && (a.Scale < 0 || isZReg(int(a.Reg)) || isZReg(int(a.Index))) {
+		if buildcfg.GOARCH == "arm64" && (a.Scale < 0 || (a.Index != REG_NONE && (isZReg(int(a.Reg)) || isZReg(int(a.Index))))) {
 			// SVE extended addressing pattern
 			amount := 0
 			mod := 0