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authorJonathan Swinney <jswinney@amazon.com>2020-11-02 16:36:10 +0000
committerCherry Zhang <cherryyz@google.com>2020-11-04 15:53:19 +0000
commit5f0fca1475e042a6e85f81ff6db676ec18805041 (patch)
treec97daf65903d64f864da4a409876c104d7180989 /src/cmd
parent633f9e206045176a12c301eb2c249c1c1d9a5d2e (diff)
downloadgo-5f0fca1475e042a6e85f81ff6db676ec18805041.tar.xz
cmd/asm: rename arm64 instructions LDANDx to LDCLRx
The LDANDx instructions were misleading because they correspond to the mnemonic LDCLRx as defined in the Arm Architecture Reference Manual for Armv8. This changes the assembler to use the same mnemonic as the GNU assembler and the manual. The instruction has the form: LDCLRx Rs, (Rb), Rt: *Rb -> Rt, Rs AND NOT(*Rb) -> *Rb Change-Id: I94ae003e99e817209bba1afe960e612bf3a0b410 Reviewed-on: https://go-review.googlesource.com/c/go/+/267138 Reviewed-by: Cherry Zhang <cherryyz@google.com> Reviewed-by: fannie zhang <Fannie.Zhang@arm.com> Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Go Bot <gobot@golang.org> Trust: fannie zhang <Fannie.Zhang@arm.com>
Diffstat (limited to 'src/cmd')
-rw-r--r--src/cmd/asm/internal/asm/testdata/arm64.s64
-rw-r--r--src/cmd/asm/internal/asm/testdata/arm64error.s48
-rw-r--r--src/cmd/internal/obj/arm64/a.out.go32
-rw-r--r--src/cmd/internal/obj/arm64/anames.go32
-rw-r--r--src/cmd/internal/obj/arm64/asm7.go34
5 files changed, 105 insertions, 105 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/arm64.s b/src/cmd/asm/internal/asm/testdata/arm64.s
index 5547cf634c..91e3a0ca0a 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64.s
@@ -681,38 +681,38 @@ again:
LDADDLH R5, (RSP), R7 // e7036578
LDADDLB R5, (R6), R7 // c7006538
LDADDLB R5, (RSP), R7 // e7036538
- LDANDAD R5, (R6), R7 // c710a5f8
- LDANDAD R5, (RSP), R7 // e713a5f8
- LDANDAW R5, (R6), R7 // c710a5b8
- LDANDAW R5, (RSP), R7 // e713a5b8
- LDANDAH R5, (R6), R7 // c710a578
- LDANDAH R5, (RSP), R7 // e713a578
- LDANDAB R5, (R6), R7 // c710a538
- LDANDAB R5, (RSP), R7 // e713a538
- LDANDALD R5, (R6), R7 // c710e5f8
- LDANDALD R5, (RSP), R7 // e713e5f8
- LDANDALW R5, (R6), R7 // c710e5b8
- LDANDALW R5, (RSP), R7 // e713e5b8
- LDANDALH R5, (R6), R7 // c710e578
- LDANDALH R5, (RSP), R7 // e713e578
- LDANDALB R5, (R6), R7 // c710e538
- LDANDALB R5, (RSP), R7 // e713e538
- LDANDD R5, (R6), R7 // c71025f8
- LDANDD R5, (RSP), R7 // e71325f8
- LDANDW R5, (R6), R7 // c71025b8
- LDANDW R5, (RSP), R7 // e71325b8
- LDANDH R5, (R6), R7 // c7102578
- LDANDH R5, (RSP), R7 // e7132578
- LDANDB R5, (R6), R7 // c7102538
- LDANDB R5, (RSP), R7 // e7132538
- LDANDLD R5, (R6), R7 // c71065f8
- LDANDLD R5, (RSP), R7 // e71365f8
- LDANDLW R5, (R6), R7 // c71065b8
- LDANDLW R5, (RSP), R7 // e71365b8
- LDANDLH R5, (R6), R7 // c7106578
- LDANDLH R5, (RSP), R7 // e7136578
- LDANDLB R5, (R6), R7 // c7106538
- LDANDLB R5, (RSP), R7 // e7136538
+ LDCLRAD R5, (R6), R7 // c710a5f8
+ LDCLRAD R5, (RSP), R7 // e713a5f8
+ LDCLRAW R5, (R6), R7 // c710a5b8
+ LDCLRAW R5, (RSP), R7 // e713a5b8
+ LDCLRAH R5, (R6), R7 // c710a578
+ LDCLRAH R5, (RSP), R7 // e713a578
+ LDCLRAB R5, (R6), R7 // c710a538
+ LDCLRAB R5, (RSP), R7 // e713a538
+ LDCLRALD R5, (R6), R7 // c710e5f8
+ LDCLRALD R5, (RSP), R7 // e713e5f8
+ LDCLRALW R5, (R6), R7 // c710e5b8
+ LDCLRALW R5, (RSP), R7 // e713e5b8
+ LDCLRALH R5, (R6), R7 // c710e578
+ LDCLRALH R5, (RSP), R7 // e713e578
+ LDCLRALB R5, (R6), R7 // c710e538
+ LDCLRALB R5, (RSP), R7 // e713e538
+ LDCLRD R5, (R6), R7 // c71025f8
+ LDCLRD R5, (RSP), R7 // e71325f8
+ LDCLRW R5, (R6), R7 // c71025b8
+ LDCLRW R5, (RSP), R7 // e71325b8
+ LDCLRH R5, (R6), R7 // c7102578
+ LDCLRH R5, (RSP), R7 // e7132578
+ LDCLRB R5, (R6), R7 // c7102538
+ LDCLRB R5, (RSP), R7 // e7132538
+ LDCLRLD R5, (R6), R7 // c71065f8
+ LDCLRLD R5, (RSP), R7 // e71365f8
+ LDCLRLW R5, (R6), R7 // c71065b8
+ LDCLRLW R5, (RSP), R7 // e71365b8
+ LDCLRLH R5, (R6), R7 // c7106578
+ LDCLRLH R5, (RSP), R7 // e7136578
+ LDCLRLB R5, (R6), R7 // c7106538
+ LDCLRLB R5, (RSP), R7 // e7136538
LDEORAD R5, (R6), R7 // c720a5f8
LDEORAD R5, (RSP), R7 // e723a5f8
LDEORAW R5, (R6), R7 // c720a5b8
diff --git a/src/cmd/asm/internal/asm/testdata/arm64error.s b/src/cmd/asm/internal/asm/testdata/arm64error.s
index 99e4d62d25..e579f20836 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64error.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64error.s
@@ -123,14 +123,14 @@ TEXT errors(SB),$0
LDADDLW R5, (R6), ZR // ERROR "illegal destination register"
LDADDLH R5, (R6), ZR // ERROR "illegal destination register"
LDADDLB R5, (R6), ZR // ERROR "illegal destination register"
- LDANDD R5, (R6), ZR // ERROR "illegal destination register"
- LDANDW R5, (R6), ZR // ERROR "illegal destination register"
- LDANDH R5, (R6), ZR // ERROR "illegal destination register"
- LDANDB R5, (R6), ZR // ERROR "illegal destination register"
- LDANDLD R5, (R6), ZR // ERROR "illegal destination register"
- LDANDLW R5, (R6), ZR // ERROR "illegal destination register"
- LDANDLH R5, (R6), ZR // ERROR "illegal destination register"
- LDANDLB R5, (R6), ZR // ERROR "illegal destination register"
+ LDCLRD R5, (R6), ZR // ERROR "illegal destination register"
+ LDCLRW R5, (R6), ZR // ERROR "illegal destination register"
+ LDCLRH R5, (R6), ZR // ERROR "illegal destination register"
+ LDCLRB R5, (R6), ZR // ERROR "illegal destination register"
+ LDCLRLD R5, (R6), ZR // ERROR "illegal destination register"
+ LDCLRLW R5, (R6), ZR // ERROR "illegal destination register"
+ LDCLRLH R5, (R6), ZR // ERROR "illegal destination register"
+ LDCLRLB R5, (R6), ZR // ERROR "illegal destination register"
LDEORD R5, (R6), ZR // ERROR "illegal destination register"
LDEORW R5, (R6), ZR // ERROR "illegal destination register"
LDEORH R5, (R6), ZR // ERROR "illegal destination register"
@@ -163,22 +163,22 @@ TEXT errors(SB),$0
LDADDLW R5, (R6), RSP // ERROR "illegal destination register"
LDADDLH R5, (R6), RSP // ERROR "illegal destination register"
LDADDLB R5, (R6), RSP // ERROR "illegal destination register"
- LDANDAD R5, (R6), RSP // ERROR "illegal destination register"
- LDANDAW R5, (R6), RSP // ERROR "illegal destination register"
- LDANDAH R5, (R6), RSP // ERROR "illegal destination register"
- LDANDAB R5, (R6), RSP // ERROR "illegal destination register"
- LDANDALD R5, (R6), RSP // ERROR "illegal destination register"
- LDANDALW R5, (R6), RSP // ERROR "illegal destination register"
- LDANDALH R5, (R6), RSP // ERROR "illegal destination register"
- LDANDALB R5, (R6), RSP // ERROR "illegal destination register"
- LDANDD R5, (R6), RSP // ERROR "illegal destination register"
- LDANDW R5, (R6), RSP // ERROR "illegal destination register"
- LDANDH R5, (R6), RSP // ERROR "illegal destination register"
- LDANDB R5, (R6), RSP // ERROR "illegal destination register"
- LDANDLD R5, (R6), RSP // ERROR "illegal destination register"
- LDANDLW R5, (R6), RSP // ERROR "illegal destination register"
- LDANDLH R5, (R6), RSP // ERROR "illegal destination register"
- LDANDLB R5, (R6), RSP // ERROR "illegal destination register"
+ LDCLRAD R5, (R6), RSP // ERROR "illegal destination register"
+ LDCLRAW R5, (R6), RSP // ERROR "illegal destination register"
+ LDCLRAH R5, (R6), RSP // ERROR "illegal destination register"
+ LDCLRAB R5, (R6), RSP // ERROR "illegal destination register"
+ LDCLRALD R5, (R6), RSP // ERROR "illegal destination register"
+ LDCLRALW R5, (R6), RSP // ERROR "illegal destination register"
+ LDCLRALH R5, (R6), RSP // ERROR "illegal destination register"
+ LDCLRALB R5, (R6), RSP // ERROR "illegal destination register"
+ LDCLRD R5, (R6), RSP // ERROR "illegal destination register"
+ LDCLRW R5, (R6), RSP // ERROR "illegal destination register"
+ LDCLRH R5, (R6), RSP // ERROR "illegal destination register"
+ LDCLRB R5, (R6), RSP // ERROR "illegal destination register"
+ LDCLRLD R5, (R6), RSP // ERROR "illegal destination register"
+ LDCLRLW R5, (R6), RSP // ERROR "illegal destination register"
+ LDCLRLH R5, (R6), RSP // ERROR "illegal destination register"
+ LDCLRLB R5, (R6), RSP // ERROR "illegal destination register"
LDEORAD R5, (R6), RSP // ERROR "illegal destination register"
LDEORAW R5, (R6), RSP // ERROR "illegal destination register"
LDEORAH R5, (R6), RSP // ERROR "illegal destination register"
diff --git a/src/cmd/internal/obj/arm64/a.out.go b/src/cmd/internal/obj/arm64/a.out.go
index 5844b71ca7..1d1bea505c 100644
--- a/src/cmd/internal/obj/arm64/a.out.go
+++ b/src/cmd/internal/obj/arm64/a.out.go
@@ -617,22 +617,6 @@ const (
ALDADDLD
ALDADDLH
ALDADDLW
- ALDANDAB
- ALDANDAD
- ALDANDAH
- ALDANDAW
- ALDANDALB
- ALDANDALD
- ALDANDALH
- ALDANDALW
- ALDANDB
- ALDANDD
- ALDANDH
- ALDANDW
- ALDANDLB
- ALDANDLD
- ALDANDLH
- ALDANDLW
ALDAR
ALDARB
ALDARH
@@ -643,6 +627,22 @@ const (
ALDAXRB
ALDAXRH
ALDAXRW
+ ALDCLRAB
+ ALDCLRAD
+ ALDCLRAH
+ ALDCLRAW
+ ALDCLRALB
+ ALDCLRALD
+ ALDCLRALH
+ ALDCLRALW
+ ALDCLRB
+ ALDCLRD
+ ALDCLRH
+ ALDCLRW
+ ALDCLRLB
+ ALDCLRLD
+ ALDCLRLH
+ ALDCLRLW
ALDEORAB
ALDEORAD
ALDEORAH
diff --git a/src/cmd/internal/obj/arm64/anames.go b/src/cmd/internal/obj/arm64/anames.go
index fb216f9a94..a98f8c7ed5 100644
--- a/src/cmd/internal/obj/arm64/anames.go
+++ b/src/cmd/internal/obj/arm64/anames.go
@@ -111,22 +111,6 @@ var Anames = []string{
"LDADDLD",
"LDADDLH",
"LDADDLW",
- "LDANDAB",
- "LDANDAD",
- "LDANDAH",
- "LDANDAW",
- "LDANDALB",
- "LDANDALD",
- "LDANDALH",
- "LDANDALW",
- "LDANDB",
- "LDANDD",
- "LDANDH",
- "LDANDW",
- "LDANDLB",
- "LDANDLD",
- "LDANDLH",
- "LDANDLW",
"LDAR",
"LDARB",
"LDARH",
@@ -137,6 +121,22 @@ var Anames = []string{
"LDAXRB",
"LDAXRH",
"LDAXRW",
+ "LDCLRAB",
+ "LDCLRAD",
+ "LDCLRAH",
+ "LDCLRAW",
+ "LDCLRALB",
+ "LDCLRALD",
+ "LDCLRALH",
+ "LDCLRALW",
+ "LDCLRB",
+ "LDCLRD",
+ "LDCLRH",
+ "LDCLRW",
+ "LDCLRLB",
+ "LDCLRLD",
+ "LDCLRLH",
+ "LDCLRLW",
"LDEORAB",
"LDEORAD",
"LDEORAH",
diff --git a/src/cmd/internal/obj/arm64/asm7.go b/src/cmd/internal/obj/arm64/asm7.go
index 4fc62d5c7f..1a359f1921 100644
--- a/src/cmd/internal/obj/arm64/asm7.go
+++ b/src/cmd/internal/obj/arm64/asm7.go
@@ -107,22 +107,22 @@ var atomicLDADD = map[obj.As]uint32{
ALDADDLW: 2<<30 | 0x1c3<<21 | 0x00<<10,
ALDADDLH: 1<<30 | 0x1c3<<21 | 0x00<<10,
ALDADDLB: 0<<30 | 0x1c3<<21 | 0x00<<10,
- ALDANDAD: 3<<30 | 0x1c5<<21 | 0x04<<10,
- ALDANDAW: 2<<30 | 0x1c5<<21 | 0x04<<10,
- ALDANDAH: 1<<30 | 0x1c5<<21 | 0x04<<10,
- ALDANDAB: 0<<30 | 0x1c5<<21 | 0x04<<10,
- ALDANDALD: 3<<30 | 0x1c7<<21 | 0x04<<10,
- ALDANDALW: 2<<30 | 0x1c7<<21 | 0x04<<10,
- ALDANDALH: 1<<30 | 0x1c7<<21 | 0x04<<10,
- ALDANDALB: 0<<30 | 0x1c7<<21 | 0x04<<10,
- ALDANDD: 3<<30 | 0x1c1<<21 | 0x04<<10,
- ALDANDW: 2<<30 | 0x1c1<<21 | 0x04<<10,
- ALDANDH: 1<<30 | 0x1c1<<21 | 0x04<<10,
- ALDANDB: 0<<30 | 0x1c1<<21 | 0x04<<10,
- ALDANDLD: 3<<30 | 0x1c3<<21 | 0x04<<10,
- ALDANDLW: 2<<30 | 0x1c3<<21 | 0x04<<10,
- ALDANDLH: 1<<30 | 0x1c3<<21 | 0x04<<10,
- ALDANDLB: 0<<30 | 0x1c3<<21 | 0x04<<10,
+ ALDCLRAD: 3<<30 | 0x1c5<<21 | 0x04<<10,
+ ALDCLRAW: 2<<30 | 0x1c5<<21 | 0x04<<10,
+ ALDCLRAH: 1<<30 | 0x1c5<<21 | 0x04<<10,
+ ALDCLRAB: 0<<30 | 0x1c5<<21 | 0x04<<10,
+ ALDCLRALD: 3<<30 | 0x1c7<<21 | 0x04<<10,
+ ALDCLRALW: 2<<30 | 0x1c7<<21 | 0x04<<10,
+ ALDCLRALH: 1<<30 | 0x1c7<<21 | 0x04<<10,
+ ALDCLRALB: 0<<30 | 0x1c7<<21 | 0x04<<10,
+ ALDCLRD: 3<<30 | 0x1c1<<21 | 0x04<<10,
+ ALDCLRW: 2<<30 | 0x1c1<<21 | 0x04<<10,
+ ALDCLRH: 1<<30 | 0x1c1<<21 | 0x04<<10,
+ ALDCLRB: 0<<30 | 0x1c1<<21 | 0x04<<10,
+ ALDCLRLD: 3<<30 | 0x1c3<<21 | 0x04<<10,
+ ALDCLRLW: 2<<30 | 0x1c3<<21 | 0x04<<10,
+ ALDCLRLH: 1<<30 | 0x1c3<<21 | 0x04<<10,
+ ALDCLRLB: 0<<30 | 0x1c3<<21 | 0x04<<10,
ALDEORAD: 3<<30 | 0x1c5<<21 | 0x08<<10,
ALDEORAW: 2<<30 | 0x1c5<<21 | 0x08<<10,
ALDEORAH: 1<<30 | 0x1c5<<21 | 0x08<<10,
@@ -4028,7 +4028,7 @@ func (c *ctxt7) asmout(p *obj.Prog, o *Optab, out []uint32) {
o1 |= uint32(p.From.Reg&31) << 5
o1 |= uint32(p.To.Reg & 31)
- case 47: // SWPx/LDADDx/LDANDx/LDEORx/LDORx/CASx Rs, (Rb), Rt
+ case 47: // SWPx/LDADDx/LDCLRx/LDEORx/LDORx/CASx Rs, (Rb), Rt
rs := p.From.Reg
rt := p.RegTo2
rb := p.To.Reg
generated by cgit v1.3 (git 2.53.0) at 2026-04-15 17:27:47 +0000