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| author | Joel Sing <joel@sing.id.au> | 2025-02-02 22:26:07 +1100 |
|---|---|---|
| committer | Joel Sing <joel@sing.id.au> | 2025-05-02 04:24:27 -0700 |
| commit | 2e60916f6e153db682fd4ea269c7d0a32e3d1768 (patch) | |
| tree | 8da7ea22ca1a386f5db6704f804a554f5ac3ce3a /src/cmd/internal | |
| parent | 7785528c505f6ef9afdb3e089d23dadb860aee11 (diff) | |
| download | go-2e60916f6e153db682fd4ea269c7d0a32e3d1768.tar.xz | |
cmd/internal/obj/riscv: add support for vector reduction instructions
Add support for vector reduction instructions to the RISC-V assembler,
including single-width integer reduction, widening integer reduction,
single-width floating-point reduction and widening floating-point
reduction.
Change-Id: I8f17bef11389f3a017e0430275023fc5d75936e3
Reviewed-on: https://go-review.googlesource.com/c/go/+/646778
Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Carlos Amedee <carlos@golang.org>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
Diffstat (limited to 'src/cmd/internal')
| -rw-r--r-- | src/cmd/internal/obj/riscv/obj.go | 28 |
1 files changed, 27 insertions, 1 deletions
diff --git a/src/cmd/internal/obj/riscv/obj.go b/src/cmd/internal/obj/riscv/obj.go index 5563af9129..83ce7e21df 100644 --- a/src/cmd/internal/obj/riscv/obj.go +++ b/src/cmd/internal/obj/riscv/obj.go @@ -2585,6 +2585,30 @@ var instructions = [ALAST & obj.AMask]instructionData{ AVFNCVTFFW & obj.AMask: {enc: rVVEncoding}, AVFNCVTRODFFW & obj.AMask: {enc: rVVEncoding}, + // 31.14.1: Vector Single-Width Integer Reduction Instructions + AVREDSUMVS & obj.AMask: {enc: rVVVEncoding}, + AVREDMAXUVS & obj.AMask: {enc: rVVVEncoding}, + AVREDMAXVS & obj.AMask: {enc: rVVVEncoding}, + AVREDMINUVS & obj.AMask: {enc: rVVVEncoding}, + AVREDMINVS & obj.AMask: {enc: rVVVEncoding}, + AVREDANDVS & obj.AMask: {enc: rVVVEncoding}, + AVREDORVS & obj.AMask: {enc: rVVVEncoding}, + AVREDXORVS & obj.AMask: {enc: rVVVEncoding}, + + // 31.14.2: Vector Widening Integer Reduction Instructions + AVWREDSUMUVS & obj.AMask: {enc: rVVVEncoding}, + AVWREDSUMVS & obj.AMask: {enc: rVVVEncoding}, + + // 31.14.3: Vector Single-Width Floating-Point Reduction Instructions + AVFREDOSUMVS & obj.AMask: {enc: rVVVEncoding}, + AVFREDUSUMVS & obj.AMask: {enc: rVVVEncoding}, + AVFREDMAXVS & obj.AMask: {enc: rVVVEncoding}, + AVFREDMINVS & obj.AMask: {enc: rVVVEncoding}, + + // 31.14.4: Vector Widening Floating-Point Reduction Instructions + AVFWREDOSUMVS & obj.AMask: {enc: rVVVEncoding}, + AVFWREDUSUMVS & obj.AMask: {enc: rVVVEncoding}, + // // Privileged ISA // @@ -3578,7 +3602,9 @@ func instructionsForProg(p *obj.Prog) []*instruction { AVFMULVV, AVFMULVF, AVFDIVVV, AVFDIVVF, AVFRDIVVF, AVFWMULVV, AVFWMULVF, AVFMINVV, AVFMINVF, AVFMAXVV, AVFMAXVF, AVFSGNJVV, AVFSGNJVF, AVFSGNJNVV, AVFSGNJNVF, AVFSGNJXVV, AVFSGNJXVF, - AVMFEQVV, AVMFEQVF, AVMFNEVV, AVMFNEVF, AVMFLTVV, AVMFLTVF, AVMFLEVV, AVMFLEVF, AVMFGTVF, AVMFGEVF: + AVMFEQVV, AVMFEQVF, AVMFNEVV, AVMFNEVF, AVMFLTVV, AVMFLTVF, AVMFLEVV, AVMFLEVF, AVMFGTVF, AVMFGEVF, + AVREDSUMVS, AVREDMAXUVS, AVREDMAXVS, AVREDMINUVS, AVREDMINVS, AVREDANDVS, AVREDORVS, AVREDXORVS, + AVWREDSUMUVS, AVWREDSUMVS, AVFREDOSUMVS, AVFREDUSUMVS, AVFREDMAXVS, AVFREDMINVS, AVFWREDOSUMVS, AVFWREDUSUMVS: // Set mask bit switch { case ins.rs3 == obj.REG_NONE: |