diff options
| author | Xiaolin Zhao <zhaoxiaolin@loongson.cn> | 2025-08-06 11:07:57 +0800 |
|---|---|---|
| committer | abner chenc <chenguoqi@loongson.cn> | 2025-08-07 19:04:20 -0700 |
| commit | ee7bb8969a62b12f466f818e4e3d836a2e126940 (patch) | |
| tree | 36df8dd7c496896b2c8f24e33fca76bf84f7a44e /src/cmd/internal/obj | |
| parent | 1f7ffca171cd8c50fe6a10eb77a84a95c5b37c61 (diff) | |
| download | go-ee7bb8969a62b12f466f818e4e3d836a2e126940.tar.xz | |
cmd/internal/obj/loong64: add support for FSEL instruction
Go asm syntax:
FSEL FCC, FK, FJ, FD
Equivalent platform assembler syntax:
fsel fd, fj, fk, ca
Change-Id: If75f16fca0adfc03f4952f8a5143d22da33ed425
Reviewed-on: https://go-review.googlesource.com/c/go/+/693457
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Meidan Li <limeidan@loongson.cn>
Reviewed-by: abner chenc <chenguoqi@loongson.cn>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
Reviewed-by: Mark Freeman <markfreeman@google.com>
Diffstat (limited to 'src/cmd/internal/obj')
| -rw-r--r-- | src/cmd/internal/obj/loong64/a.out.go | 3 | ||||
| -rw-r--r-- | src/cmd/internal/obj/loong64/anames.go | 1 | ||||
| -rw-r--r-- | src/cmd/internal/obj/loong64/asm.go | 14 |
3 files changed, 18 insertions, 0 deletions
diff --git a/src/cmd/internal/obj/loong64/a.out.go b/src/cmd/internal/obj/loong64/a.out.go index 46bb0b5b91..f5d20cfabe 100644 --- a/src/cmd/internal/obj/loong64/a.out.go +++ b/src/cmd/internal/obj/loong64/a.out.go @@ -748,6 +748,9 @@ const ( AFTINTRNEVF AFTINTRNEVD + // 3.2.4.2 + AFSEL + // LSX and LASX memory access instructions AVMOVQ AXVMOVQ diff --git a/src/cmd/internal/obj/loong64/anames.go b/src/cmd/internal/obj/loong64/anames.go index 02c392be76..67b5f2fc80 100644 --- a/src/cmd/internal/obj/loong64/anames.go +++ b/src/cmd/internal/obj/loong64/anames.go @@ -264,6 +264,7 @@ var Anames = []string{ "FTINTRNEWD", "FTINTRNEVF", "FTINTRNEVD", + "FSEL", "VMOVQ", "XVMOVQ", "VADDB", diff --git a/src/cmd/internal/obj/loong64/asm.go b/src/cmd/internal/obj/loong64/asm.go index 4e66ddd6cd..1d10ad67d9 100644 --- a/src/cmd/internal/obj/loong64/asm.go +++ b/src/cmd/internal/obj/loong64/asm.go @@ -154,6 +154,9 @@ var optab = []Optab{ {AFMADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 37, 4, 0, 0}, {AFMADDF, C_FREG, C_FREG, C_FREG, C_FREG, C_NONE, 37, 4, 0, 0}, + {AFSEL, C_FCCREG, C_FREG, C_FREG, C_FREG, C_NONE, 33, 4, 0, 0}, + {AFSEL, C_FCCREG, C_FREG, C_NONE, C_FREG, C_NONE, 33, 4, 0, 0}, + {AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0}, {AMOVWU, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0}, {AMOVV, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0}, @@ -1517,6 +1520,7 @@ func buildop(ctxt *obj.Link) { AWORD, APRELD, APRELDX, + AFSEL, obj.ANOP, obj.ATEXT, obj.AFUNCDATA, @@ -2387,6 +2391,16 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { } o1 = OP_6IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg)) + case 33: // fsel ca, fk, [fj], fd + ca := uint32(p.From.Reg) + fk := uint32(p.Reg) + fd := uint32(p.To.Reg) + fj := fd + if len(p.RestArgs) > 0 { + fj = uint32(p.GetFrom3().Reg) + } + o1 = 0x340<<18 | (ca&0x7)<<15 | (fk&0x1F)<<10 | (fj&0x1F)<<5 | (fd & 0x1F) + case 34: // mov $con,fr v := c.regoff(&p.From) a := AADDU |