cmd/internal/obj/riscv: add encoding for compressed riscv64 instructions

Regenerate instruction encodings for riscv64, including rv64_c, rv_c
and rv_c_d.

Updates #71105

Change-Id: I004cc00290bf018ebb848592d84d924481f03851
Reviewed-on: https://go-review.googlesource.com/c/go/+/523476
Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>

3 files changed, 178 insertions, 4 deletions

diff --git a/src/cmd/internal/obj/riscv/anames.go b/src/cmd/internal/obj/riscv/anames.go
index a689f2de27..f0be8f6b87 100644
--- a/src/cmd/internal/obj/riscv/anames.go
+++ b/src/cmd/internal/obj/riscv/anames.go
@@ -192,6 +192,47 @@ var Anames = []string{
 	"FLEQ",
 	"FLTQ",
 	"FCLASSQ",
+	"CLWSP",
+	"CFLWSP",
+	"CLDSP",
+	"CFLDSP",
+	"CSWSP",
+	"CSDSP",
+	"CFSWSP",
+	"CFSDSP",
+	"CLW",
+	"CLD",
+	"CFLW",
+	"CFLD",
+	"CSW",
+	"CSD",
+	"CFSW",
+	"CFSD",
+	"CJ",
+	"CJR",
+	"CJALR",
+	"CBEQZ",
+	"CBNEZ",
+	"CLI",
+	"CLUI",
+	"CADDI",
+	"CADDIW",
+	"CADDI16SP",
+	"CADDI4SPN",
+	"CSLLI",
+	"CSRLI",
+	"CSRAI",
+	"CANDI",
+	"CMV",
+	"CADD",
+	"CAND",
+	"COR",
+	"CXOR",
+	"CSUB",
+	"CADDW",
+	"CSUBW",
+	"CNOP",
+	"CEBREAK",
 	"ADDUW",
 	"SH1ADD",
 	"SH1ADDUW",
diff --git a/src/cmd/internal/obj/riscv/cpu.go b/src/cmd/internal/obj/riscv/cpu.go
index 382c08a9d9..116ccb4ea4 100644
--- a/src/cmd/internal/obj/riscv/cpu.go
+++ b/src/cmd/internal/obj/riscv/cpu.go
@@ -551,7 +551,7 @@ const (
 	AFNMADDQ
 	AFNMSUBQ
 
-	// 22.3 Quad-Precision Convert and Move Instructions
+	// 22.3: Quad-Precision Convert and Move Instructions
 	AFCVTWQ
 	AFCVTLQ
 	AFCVTSQ
@@ -568,15 +568,74 @@ const (
 	AFSGNJNQ
 	AFSGNJXQ
 
-	// 22.4 Quad-Precision Floating-Point Compare Instructions
+	// 22.4: Quad-Precision Floating-Point Compare Instructions
 	AFEQQ
 	AFLEQ
 	AFLTQ
 
-	// 22.5 Quad-Precision Floating-Point Classify Instruction
+	// 22.5: Quad-Precision Floating-Point Classify Instruction
 	AFCLASSQ
 
 	//
+	// "C" Extension for Compressed Instructions
+	//
+
+	// 26.3.1: Compressed Stack-Pointer-Based Loads and Stores
+	ACLWSP
+	ACFLWSP
+	ACLDSP
+	ACFLDSP
+	ACSWSP
+	ACSDSP
+	ACFSWSP
+	ACFSDSP
+
+	// 26.3.2: Compressed Register-Based Loads and Stores
+	ACLW
+	ACLD
+	ACFLW
+	ACFLD
+	ACSW
+	ACSD
+	ACFSW
+	ACFSD
+
+	// 26.4: Compressed Control Transfer Instructions
+	ACJ
+	ACJR
+	ACJALR
+	ACBEQZ
+	ACBNEZ
+
+	// 26.5.1: Compressed Integer Constant-Generation Instructions
+	ACLI
+	ACLUI
+	ACADDI
+	ACADDIW
+	ACADDI16SP
+	ACADDI4SPN
+	ACSLLI
+	ACSRLI
+	ACSRAI
+	ACANDI
+
+	// 26.5.3: Compressed Integer Register-Register Operations
+	ACMV
+	ACADD
+	ACAND
+	ACOR
+	ACXOR
+	ACSUB
+	ACADDW
+	ACSUBW
+
+	// 26.5.5: Compressed NOP Instruction
+	ACNOP
+
+	// 26.5.6: Compressed Breakpoint Instruction
+	ACEBREAK
+
+	//
 	// "B" Extension for Bit Manipulation, Version 1.0.0
 	//
 
diff --git a/src/cmd/internal/obj/riscv/inst.go b/src/cmd/internal/obj/riscv/inst.go
index 5ee5bda361..16f2272b03 100644
--- a/src/cmd/internal/obj/riscv/inst.go
+++ b/src/cmd/internal/obj/riscv/inst.go
@@ -1,4 +1,4 @@
-// Code generated by ./parse.py -go rv64_a rv64_d rv64_f rv64_i rv64_m rv64_q rv64_zba rv64_zbb rv64_zbs rv_a rv_d rv_f rv_i rv_m rv_q rv_s rv_system rv_v rv_zba rv_zbb rv_zbs rv_zicsr; DO NOT EDIT.
+// Code generated by ./parse.py -go rv64_a rv64_c rv64_d rv64_f rv64_i rv64_m rv64_q rv64_zba rv64_zbb rv64_zbs rv_a rv_c rv_c_d rv_d rv_f rv_i rv_m rv_q rv_s rv_system rv_v rv_zba rv_zbb rv_zbs rv_zicsr; DO NOT EDIT.
 package riscv
 
 import "cmd/internal/obj"
@@ -96,6 +96,80 @@ func encode(a obj.As) *inst {
 		return &inst{0x33, 0x1, 0x0, 0x0, 640, 0x14}
 	case ABSETI:
 		return &inst{0x13, 0x1, 0x0, 0x0, 640, 0x14}
+	case ACADD:
+		return &inst{0x2, 0x1, 0x1, 0x0, 0, 0x0}
+	case ACADDI:
+		return &inst{0x1, 0x0, 0x0, 0x0, 0, 0x0}
+	case ACADDI16SP:
+		return &inst{0x1, 0x6, 0x0, 0x0, 0, 0x0}
+	case ACADDI4SPN:
+		return &inst{0x0, 0x0, 0x0, 0x0, 0, 0x0}
+	case ACADDIW:
+		return &inst{0x1, 0x2, 0x0, 0x0, 0, 0x0}
+	case ACADDW:
+		return &inst{0x21, 0x1, 0x1, 0x0, 0, 0x0}
+	case ACAND:
+		return &inst{0x61, 0x0, 0x1, 0x0, 0, 0x0}
+	case ACANDI:
+		return &inst{0x1, 0x0, 0x1, 0x0, 0, 0x0}
+	case ACBEQZ:
+		return &inst{0x1, 0x4, 0x1, 0x0, 0, 0x0}
+	case ACBNEZ:
+		return &inst{0x1, 0x6, 0x1, 0x0, 0, 0x0}
+	case ACEBREAK:
+		return &inst{0x2, 0x1, 0x1, 0x0, 0, 0x0}
+	case ACFLD:
+		return &inst{0x0, 0x2, 0x0, 0x0, 0, 0x0}
+	case ACFLDSP:
+		return &inst{0x2, 0x2, 0x0, 0x0, 0, 0x0}
+	case ACFSD:
+		return &inst{0x0, 0x2, 0x1, 0x0, 0, 0x0}
+	case ACFSDSP:
+		return &inst{0x2, 0x2, 0x1, 0x0, 0, 0x0}
+	case ACJ:
+		return &inst{0x1, 0x2, 0x1, 0x0, 0, 0x0}
+	case ACJALR:
+		return &inst{0x2, 0x1, 0x1, 0x0, 0, 0x0}
+	case ACJR:
+		return &inst{0x2, 0x0, 0x1, 0x0, 0, 0x0}
+	case ACLD:
+		return &inst{0x0, 0x6, 0x0, 0x0, 0, 0x0}
+	case ACLDSP:
+		return &inst{0x2, 0x6, 0x0, 0x0, 0, 0x0}
+	case ACLI:
+		return &inst{0x1, 0x4, 0x0, 0x0, 0, 0x0}
+	case ACLUI:
+		return &inst{0x1, 0x6, 0x0, 0x0, 0, 0x0}
+	case ACLW:
+		return &inst{0x0, 0x4, 0x0, 0x0, 0, 0x0}
+	case ACLWSP:
+		return &inst{0x2, 0x4, 0x0, 0x0, 0, 0x0}
+	case ACMV:
+		return &inst{0x2, 0x0, 0x1, 0x0, 0, 0x0}
+	case ACNOP:
+		return &inst{0x1, 0x0, 0x0, 0x0, 0, 0x0}
+	case ACOR:
+		return &inst{0x41, 0x0, 0x1, 0x0, 0, 0x0}
+	case ACSD:
+		return &inst{0x0, 0x6, 0x1, 0x0, 0, 0x0}
+	case ACSDSP:
+		return &inst{0x2, 0x6, 0x1, 0x0, 0, 0x0}
+	case ACSLLI:
+		return &inst{0x2, 0x0, 0x0, 0x0, 0, 0x0}
+	case ACSRAI:
+		return &inst{0x1, 0x0, 0x1, 0x0, 0, 0x0}
+	case ACSRLI:
+		return &inst{0x1, 0x0, 0x1, 0x0, 0, 0x0}
+	case ACSUB:
+		return &inst{0x1, 0x0, 0x1, 0x0, 0, 0x0}
+	case ACSUBW:
+		return &inst{0x1, 0x1, 0x1, 0x0, 0, 0x0}
+	case ACSW:
+		return &inst{0x0, 0x4, 0x1, 0x0, 0, 0x0}
+	case ACSWSP:
+		return &inst{0x2, 0x4, 0x1, 0x0, 0, 0x0}
+	case ACXOR:
+		return &inst{0x21, 0x0, 0x1, 0x0, 0, 0x0}
 	case ACLZ:
 		return &inst{0x13, 0x1, 0x0, 0x0, 1536, 0x30}
 	case ACLZW: