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authorJunyang Shao <shaojunyang@google.com>2026-02-04 17:19:04 +0000
committerJunyang Shao <shaojunyang@google.com>2026-03-20 10:02:17 -0700
commit79f3d38562bb62221313aacaf1b8d18178b1ff67 (patch)
tree0cd52d1f8e1b3de0b58951d7ff7a3341f9e0d0b9 /src/cmd/internal/obj
parenta45c8032bbfdfb4c43cb56536f987501e6709a70 (diff)
downloadgo-79f3d38562bb62221313aacaf1b8d18178b1ff67.tar.xz
cmd/internal/obj/arm64: new arm64 assembling path for SVE
This CL integrates a new assembling path specifically designed for SVE and other modern ARM64 instructions, utilizing generated instruction tables. It contains the foundational files and modifications to direct the assembling pipeline to use this new data-driven path. In a.out.go, it registers new constants for registers and operand types used by SVE. A new file inst.go is added, which defines the instruction table data types and utility functions for the new path. The entry point from the upstream pipeline is `tryEncode`. `tryEncode` returns false upon an encoding failure, which allows the upstream matching logic to handle multiple potential matches. The exact match is not finalized until an instruction is actually encoded, as detailed in the comments for `elemEncoders`. This CL also introduces the core generated tables (`anames_gen.go`, `encoding_gen.go`, `goops_gen.go`, and `inst_gen.go`) which handle a wide variety of SVE instructions. A comprehensive end-to-end assembly test file (`arm64sveenc.s`) is added, containing hundreds of test cases for these SVE instructions to verify the new encoding path. To facilitate these encodings, this CL implements handling for operand types such as AC_ARNG, AC_PREG, AC_PREGZM, and AC_ZREG. Others are left as TODOs. The generated files in this CL are produced by the `instgen` tool in CL 755180. Original author Eric Fang (eric.fang@arm.com, CL 424137) Change-Id: I483f170c776fcd8edd8b8b04520f9d69ee0855dd Reviewed-on: https://go-review.googlesource.com/c/go/+/742620 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: David Chase <drchase@google.com>
Diffstat (limited to 'src/cmd/internal/obj')
-rw-r--r--src/cmd/internal/obj/arm64/a.out.go176
-rw-r--r--src/cmd/internal/obj/arm64/anames.go1
-rw-r--r--src/cmd/internal/obj/arm64/anames_gen.go416
-rw-r--r--src/cmd/internal/obj/arm64/asm7.go72
-rw-r--r--src/cmd/internal/obj/arm64/encoding_gen.go877
-rw-r--r--src/cmd/internal/obj/arm64/goops_gen.go413
-rw-r--r--src/cmd/internal/obj/arm64/inst.go188
-rw-r--r--src/cmd/internal/obj/arm64/inst_gen.go6307
-rw-r--r--src/cmd/internal/obj/arm64/list7.go25
-rw-r--r--src/cmd/internal/obj/util.go12
10 files changed, 8473 insertions, 14 deletions
diff --git a/src/cmd/internal/obj/arm64/a.out.go b/src/cmd/internal/obj/arm64/a.out.go
index 05ee9d173e..3a39f2719d 100644
--- a/src/cmd/internal/obj/arm64/a.out.go
+++ b/src/cmd/internal/obj/arm64/a.out.go
@@ -143,7 +143,77 @@ const (
REG_V30
REG_V31
- REG_RSP = REG_V31 + 32 // to differentiate ZR/SP, REG_RSP&0x1f = 31
+ // SVE (Scalable Vector Extension) scalable vector registers
+ // The order matters, make sure that each
+ // kind of register starts numbering from the lowest bit.
+ REG_Z0
+ REG_Z1
+ REG_Z2
+ REG_Z3
+ REG_Z4
+ REG_Z5
+ REG_Z6
+ REG_Z7
+ REG_Z8
+ REG_Z9
+ REG_Z10
+ REG_Z11
+ REG_Z12
+ REG_Z13
+ REG_Z14
+ REG_Z15
+ REG_Z16
+ REG_Z17
+ REG_Z18
+ REG_Z19
+ REG_Z20
+ REG_Z21
+ REG_Z22
+ REG_Z23
+ REG_Z24
+ REG_Z25
+ REG_Z26
+ REG_Z27
+ REG_Z28
+ REG_Z29
+ REG_Z30
+ REG_Z31
+
+ REG_P0
+ REG_P1
+ REG_P2
+ REG_P3
+ REG_P4
+ REG_P5
+ REG_P6
+ REG_P7
+ REG_P8
+ REG_P9
+ REG_P10
+ REG_P11
+ REG_P12
+ REG_P13
+ REG_P14
+ REG_P15
+
+ REG_PN0
+ REG_PN1
+ REG_PN2
+ REG_PN3
+ REG_PN4
+ REG_PN5
+ REG_PN6
+ REG_PN7
+ REG_PN8
+ REG_PN9
+ REG_PN10
+ REG_PN11
+ REG_PN12
+ REG_PN13
+ REG_PN14
+ REG_PN15
+
+ REG_RSP = (REG_PN15 + 1) | 0x1f // to differentiate ZR/SP, REG_RSP&0x1f = 31
)
// bits 0-4 indicates register: Vn
@@ -152,15 +222,18 @@ const (
REG_ARNG = obj.RBaseARM64 + 1<<10 + iota<<9 // Vn.<T>
REG_ELEM // Vn.<T>[index]
REG_ELEM_END
+ REG_ZARNG // Zn.<T>
+ REG_PARNGZM // Pn.<T> or Pn/M, Pn/Z
+ REG_PARNGZM_END
)
// Not registers, but flags that can be combined with regular register
// constants to indicate extended register conversion. When checking,
-// you should subtract obj.RBaseARM64 first. From this difference, bit 11
+// you should subtract obj.RBaseARM64 first. From this difference, bit 12
// indicates extended register, bits 8-10 select the conversion mode.
// REG_LSL is the index shift specifier, bit 9 indicates shifted offset register.
const REG_LSL = obj.RBaseARM64 + 1<<9
-const REG_EXT = obj.RBaseARM64 + 1<<11
+const REG_EXT = obj.RBaseARM64 + 1<<12
const (
REG_UXTB = REG_EXT + iota<<8
@@ -173,14 +246,14 @@ const (
REG_SXTX
)
-// Special registers, after subtracting obj.RBaseARM64, bit 12 indicates
+// Special registers, after subtracting obj.RBaseARM64, bit 13 indicates
// a special register and the low bits select the register.
// SYSREG_END is the last item in the automatically generated system register
// declaration, and it is defined in the sysRegEnc.go file.
// Define the special register after REG_SPECIAL, the first value of it should be
// REG_{name} = SYSREG_END + iota.
const (
- REG_SPECIAL = obj.RBaseARM64 + 1<<12
+ REG_SPECIAL = obj.RBaseARM64 + 1<<13
)
// Register assignments:
@@ -250,6 +323,24 @@ var ARM64DWARFRegisters = map[int16]int16{
REG_R29: 29,
REG_R30: 30,
+ // SVE predicate registers
+ REG_P0: 48,
+ REG_P1: 49,
+ REG_P2: 50,
+ REG_P3: 51,
+ REG_P4: 52,
+ REG_P5: 53,
+ REG_P6: 54,
+ REG_P7: 55,
+ REG_P8: 56,
+ REG_P9: 57,
+ REG_P10: 58,
+ REG_P11: 59,
+ REG_P12: 60,
+ REG_P13: 61,
+ REG_P14: 62,
+ REG_P15: 63,
+
// floating point
REG_F0: 64,
REG_F1: 65,
@@ -317,6 +408,40 @@ var ARM64DWARFRegisters = map[int16]int16{
REG_V29: 93,
REG_V30: 94,
REG_V31: 95,
+
+ // SVE vector registers
+ REG_Z0: 96,
+ REG_Z1: 97,
+ REG_Z2: 98,
+ REG_Z3: 99,
+ REG_Z4: 100,
+ REG_Z5: 101,
+ REG_Z6: 102,
+ REG_Z7: 103,
+ REG_Z8: 104,
+ REG_Z9: 105,
+ REG_Z10: 106,
+ REG_Z11: 107,
+ REG_Z12: 108,
+ REG_Z13: 109,
+ REG_Z14: 110,
+ REG_Z15: 111,
+ REG_Z16: 112,
+ REG_Z17: 113,
+ REG_Z18: 114,
+ REG_Z19: 115,
+ REG_Z20: 116,
+ REG_Z21: 117,
+ REG_Z22: 118,
+ REG_Z23: 119,
+ REG_Z24: 120,
+ REG_Z25: 121,
+ REG_Z26: 122,
+ REG_Z27: 123,
+ REG_Z28: 124,
+ REG_Z29: 125,
+ REG_Z30: 126,
+ REG_Z31: 127,
}
const (
@@ -485,6 +610,42 @@ const (
C_XPOST = 1 << 5 // match arm.C_PBIT, so Prog.String know how to print it
)
+type AClass uint16 // operand type
+
+// [insts] is sorted based on the order of these constants and the first match is chosen.
+const (
+ AC_NONE AClass = iota
+ AC_REG // general purpose registers R0..R30 and ZR
+ AC_RSP // general purpose registers R0..R30 and RSP
+ AC_VREG // vector registers, such as V1
+ AC_ZREG // the scalable vector registers, such as Z1
+ AC_PREG // the scalable predicate registers, such as P1
+ AC_PREGZM // Pg.Z or Pg.M
+ AC_REGIDX // P8[1]
+ AC_ZREGIDX // Z1[1]
+ AC_PREGIDX // P0[R1, 1]
+ AC_ARNG // vector register with arrangement, such as Z1.D
+ AC_ARNGIDX // vector register with arrangement and index, such as Z1.D[1]
+
+ AC_IMM // constants
+
+ AC_REGLIST1 // list of 1 vector register, such as [Z1]
+ AC_REGLIST2 // list of 2 vector registers, such as [Z0, Z8]
+ AC_REGLIST3 // list of 3 vector registers, such as [Z1, Z2, Z3]
+ AC_REGLIST4 // list of 4 vector registers, such as [Z0, Z4, Z8, Z12]
+ AC_REGLIST_RANGE // list of vector register lists in range format, such as [Z0-Z4].
+
+ AC_MEMOFF // address with optional constant offset, the offset is an immediate, such as 4(Z1.D)
+ AC_MEMOFFMULVL // address with optional constant offset, the offset is an immediate multiplied by the vector's in-memory size, such as (2*VL)(Z1.D)
+ AC_MEMEXT // address with register offset with extensions, such as (Z2.D.UXTW<<3)(RSP)
+
+ AC_PREG_PATTERN // register with pattern, such as VL1*3(P1.D)
+ AC_REG_PATTERN // register with pattern, such as VL1*3(R1)
+ AC_ZREG_PATTERN // register with pattern, such as VL1*3(Z1.D)
+
+ AC_SPECIAL // VL*i pattern, one of: VL*2, VL*4, or prefetch pattern, such as PLDL1KEEP, more patterns might come in the future.
+)
+
//go:generate go run ../stringer.go -i $GOFILE -o anames.go -p arm64
const (
@@ -1027,7 +1188,7 @@ const (
AAUTIBSP
AAUTIA1716
AAUTIB1716
- ALAST
+ ASVESTART
AB = obj.AJMP
ABL = obj.ACALL
)
@@ -1056,6 +1217,9 @@ const (
ARNG_H
ARNG_S
ARNG_D
+ ARNG_Q
+ PRED_M
+ PRED_Z
)
//go:generate stringer -type SpecialOperand -trimprefix SPOP_
diff --git a/src/cmd/internal/obj/arm64/anames.go b/src/cmd/internal/obj/arm64/anames.go
index 5ec231270b..564e0faa8b 100644
--- a/src/cmd/internal/obj/arm64/anames.go
+++ b/src/cmd/internal/obj/arm64/anames.go
@@ -544,5 +544,4 @@ var Anames = []string{
"AUTIBSP",
"AUTIA1716",
"AUTIB1716",
- "LAST",
}
diff --git a/src/cmd/internal/obj/arm64/anames_gen.go b/src/cmd/internal/obj/arm64/anames_gen.go
new file mode 100644
index 0000000000..c7b8a17664
--- /dev/null
+++ b/src/cmd/internal/obj/arm64/anames_gen.go
@@ -0,0 +1,416 @@
+// Code generated by 'instgen -o=$GOROOT # from go install golang.org/x/arch/arm64/instgen@latest'. DO NOT EDIT.
+
+package arm64
+
+var sveAnames = []string{
+ "SVESTART",
+ "PAND",
+ "PANDS",
+ "PBIC",
+ "PBICS",
+ "PBRKA",
+ "PBRKAS",
+ "PBRKB",
+ "PBRKBS",
+ "PBRKN",
+ "PBRKNS",
+ "PBRKPA",
+ "PBRKPAS",
+ "PBRKPB",
+ "PBRKPBS",
+ "PEOR",
+ "PEORS",
+ "PNAND",
+ "PNANDS",
+ "PNOR",
+ "PNORS",
+ "PORN",
+ "PORNS",
+ "PORR",
+ "PORRS",
+ "PPFALSE",
+ "PPFIRST",
+ "PPNEXT",
+ "PPTEST",
+ "PPTRUE",
+ "PPUNPKHI",
+ "PPUNPKLO",
+ "PRDFFR",
+ "PRDFFRS",
+ "PREV",
+ "PSEL",
+ "PTRN1",
+ "PTRN2",
+ "PUZP1",
+ "PUZP2",
+ "PWRFFR",
+ "PZIP1",
+ "PZIP2",
+ "SETFFR",
+ "ZABS",
+ "ZADCLB",
+ "ZADCLT",
+ "ZADD",
+ "ZADDHNB",
+ "ZADDHNT",
+ "ZADDP",
+ "ZADDPT",
+ "ZADDQP",
+ "ZADDQV",
+ "ZADDSUBP",
+ "ZAESD",
+ "ZAESE",
+ "ZAESIMC",
+ "ZAESMC",
+ "ZAND",
+ "ZANDQV",
+ "ZASR",
+ "ZASRR",
+ "ZBCAX",
+ "ZBDEP",
+ "ZBEXT",
+ "ZBF1CVT",
+ "ZBF1CVTLT",
+ "ZBF2CVT",
+ "ZBF2CVTLT",
+ "ZBFADD",
+ "ZBFCLAMP",
+ "ZBFCVT",
+ "ZBFCVTNT",
+ "ZBFDOT",
+ "ZBFMAX",
+ "ZBFMAXNM",
+ "ZBFMIN",
+ "ZBFMINNM",
+ "ZBFMLA",
+ "ZBFMLALB",
+ "ZBFMLALT",
+ "ZBFMLS",
+ "ZBFMLSLB",
+ "ZBFMLSLT",
+ "ZBFMMLA",
+ "ZBFMUL",
+ "ZBFSCALE",
+ "ZBFSUB",
+ "ZBGRP",
+ "ZBIC",
+ "ZBSL",
+ "ZBSL1N",
+ "ZBSL2N",
+ "ZCLASTA",
+ "ZCLASTB",
+ "ZCLS",
+ "ZCLZ",
+ "ZCMPEQ",
+ "ZCMPGE",
+ "ZCMPGT",
+ "ZCMPHI",
+ "ZCMPHS",
+ "ZCMPLE",
+ "ZCMPLO",
+ "ZCMPLS",
+ "ZCMPLT",
+ "ZCMPNE",
+ "ZCNOT",
+ "ZCNT",
+ "ZCOMPACT",
+ "ZDECP",
+ "ZEOR",
+ "ZEOR3",
+ "ZEORBT",
+ "ZEORQV",
+ "ZEORTB",
+ "ZEXPAND",
+ "ZF1CVT",
+ "ZF1CVTLT",
+ "ZF2CVT",
+ "ZF2CVTLT",
+ "ZFABD",
+ "ZFABS",
+ "ZFACGE",
+ "ZFACGT",
+ "ZFADD",
+ "ZFADDP",
+ "ZFADDQV",
+ "ZFAMAX",
+ "ZFAMIN",
+ "ZFCLAMP",
+ "ZFCMEQ",
+ "ZFCMGE",
+ "ZFCMGT",
+ "ZFCMNE",
+ "ZFCMUO",
+ "ZFCVT",
+ "ZFCVTLT",
+ "ZFCVTNT",
+ "ZFCVTX",
+ "ZFCVTXNT",
+ "ZFCVTZS",
+ "ZFCVTZU",
+ "ZFDIV",
+ "ZFDIVR",
+ "ZFDOT",
+ "ZFEXPA",
+ "ZFLOGB",
+ "ZFMAD",
+ "ZFMAX",
+ "ZFMAXNM",
+ "ZFMAXNMP",
+ "ZFMAXNMQV",
+ "ZFMAXP",
+ "ZFMAXQV",
+ "ZFMIN",
+ "ZFMINNM",
+ "ZFMINNMP",
+ "ZFMINNMQV",
+ "ZFMINP",
+ "ZFMINQV",
+ "ZFMLA",
+ "ZFMLALB",
+ "ZFMLALLBB",
+ "ZFMLALLBT",
+ "ZFMLALLTB",
+ "ZFMLALLTT",
+ "ZFMLALT",
+ "ZFMLS",
+ "ZFMLSLB",
+ "ZFMLSLT",
+ "ZFMMLA",
+ "ZFMSB",
+ "ZFMUL",
+ "ZFMULX",
+ "ZFNEG",
+ "ZFNMAD",
+ "ZFNMLA",
+ "ZFNMLS",
+ "ZFNMSB",
+ "ZFRECPE",
+ "ZFRECPS",
+ "ZFRECPX",
+ "ZFRINT32X",
+ "ZFRINT32Z",
+ "ZFRINT64X",
+ "ZFRINT64Z",
+ "ZFRINTA",
+ "ZFRINTI",
+ "ZFRINTM",
+ "ZFRINTN",
+ "ZFRINTP",
+ "ZFRINTX",
+ "ZFRINTZ",
+ "ZFRSQRTE",
+ "ZFRSQRTS",
+ "ZFSCALE",
+ "ZFSQRT",
+ "ZFSUB",
+ "ZFSUBR",
+ "ZFTSMUL",
+ "ZFTSSEL",
+ "ZHISTCNT",
+ "ZHISTSEG",
+ "ZINCP",
+ "ZLSL",
+ "ZLSLR",
+ "ZLSR",
+ "ZLSRR",
+ "ZMAD",
+ "ZMADPT",
+ "ZMATCH",
+ "ZMLA",
+ "ZMLAPT",
+ "ZMLS",
+ "ZMOVPRFX",
+ "ZMSB",
+ "ZMUL",
+ "ZNBSL",
+ "ZNEG",
+ "ZNMATCH",
+ "ZNOT",
+ "ZORQV",
+ "ZORR",
+ "ZPMOV",
+ "ZPMUL",
+ "ZPMULLB",
+ "ZPMULLT",
+ "ZRADDHNB",
+ "ZRADDHNT",
+ "ZRAX1",
+ "ZRBIT",
+ "ZREV",
+ "ZREVB",
+ "ZREVD",
+ "ZREVH",
+ "ZREVW",
+ "ZRSUBHNB",
+ "ZRSUBHNT",
+ "ZSABA",
+ "ZSABAL",
+ "ZSABALB",
+ "ZSABALT",
+ "ZSABD",
+ "ZSABDLB",
+ "ZSABDLT",
+ "ZSADALP",
+ "ZSADDLB",
+ "ZSADDLBT",
+ "ZSADDLT",
+ "ZSADDWB",
+ "ZSADDWT",
+ "ZSBCLB",
+ "ZSBCLT",
+ "ZSCLAMP",
+ "ZSCVTF",
+ "ZSCVTFLT",
+ "ZSDIV",
+ "ZSDIVR",
+ "ZSDOT",
+ "ZSEL",
+ "ZSHADD",
+ "ZSHSUB",
+ "ZSHSUBR",
+ "ZSM4E",
+ "ZSM4EKEY",
+ "ZSMAX",
+ "ZSMAXP",
+ "ZSMAXQV",
+ "ZSMIN",
+ "ZSMINP",
+ "ZSMINQV",
+ "ZSMLALB",
+ "ZSMLALT",
+ "ZSMLSLB",
+ "ZSMLSLT",
+ "ZSMMLA",
+ "ZSMULH",
+ "ZSMULLB",
+ "ZSMULLT",
+ "ZSPLICE",
+ "ZSQABS",
+ "ZSQADD",
+ "ZSQDECP",
+ "ZSQDMLALB",
+ "ZSQDMLALBT",
+ "ZSQDMLALT",
+ "ZSQDMLSLB",
+ "ZSQDMLSLBT",
+ "ZSQDMLSLT",
+ "ZSQDMULH",
+ "ZSQDMULLB",
+ "ZSQDMULLT",
+ "ZSQINCP",
+ "ZSQNEG",
+ "ZSQRDMLAH",
+ "ZSQRDMLSH",
+ "ZSQRDMULH",
+ "ZSQRSHL",
+ "ZSQRSHLR",
+ "ZSQSHL",
+ "ZSQSHLR",
+ "ZSQSUB",
+ "ZSQSUBR",
+ "ZSQXTNB",
+ "ZSQXTNT",
+ "ZSQXTUNB",
+ "ZSQXTUNT",
+ "ZSRHADD",
+ "ZSRSHL",
+ "ZSRSHLR",
+ "ZSSUBLB",
+ "ZSSUBLBT",
+ "ZSSUBLT",
+ "ZSSUBLTB",
+ "ZSSUBWB",
+ "ZSSUBWT",
+ "ZSUB",
+ "ZSUBHNB",
+ "ZSUBHNT",
+ "ZSUBP",
+ "ZSUBPT",
+ "ZSUBR",
+ "ZSUNPKHI",
+ "ZSUNPKLO",
+ "ZSUQADD",
+ "ZSXTB",
+ "ZSXTH",
+ "ZSXTW",
+ "ZTBX",
+ "ZTBXQ",
+ "ZTRN1",
+ "ZTRN2",
+ "ZUABA",
+ "ZUABAL",
+ "ZUABALB",
+ "ZUABALT",
+ "ZUABD",
+ "ZUABDLB",
+ "ZUABDLT",
+ "ZUADALP",
+ "ZUADDLB",
+ "ZUADDLT",
+ "ZUADDWB",
+ "ZUADDWT",
+ "ZUCLAMP",
+ "ZUCVTF",
+ "ZUCVTFLT",
+ "ZUDIV",
+ "ZUDIVR",
+ "ZUDOT",
+ "ZUHADD",
+ "ZUHSUB",
+ "ZUHSUBR",
+ "ZUMAX",
+ "ZUMAXP",
+ "ZUMAXQV",
+ "ZUMIN",
+ "ZUMINP",
+ "ZUMINQV",
+ "ZUMLALB",
+ "ZUMLALT",
+ "ZUMLSLB",
+ "ZUMLSLT",
+ "ZUMMLA",
+ "ZUMULH",
+ "ZUMULLB",
+ "ZUMULLT",
+ "ZUQADD",
+ "ZUQDECP",
+ "ZUQINCP",
+ "ZUQRSHL",
+ "ZUQRSHLR",
+ "ZUQSHL",
+ "ZUQSHLR",
+ "ZUQSUB",
+ "ZUQSUBR",
+ "ZUQXTNB",
+ "ZUQXTNT",
+ "ZURECPE",
+ "ZURHADD",
+ "ZURSHL",
+ "ZURSHLR",
+ "ZURSQRTE",
+ "ZUSDOT",
+ "ZUSMMLA",
+ "ZUSQADD",
+ "ZUSUBLB",
+ "ZUSUBLT",
+ "ZUSUBWB",
+ "ZUSUBWT",
+ "ZUUNPKHI",
+ "ZUUNPKLO",
+ "ZUXTB",
+ "ZUXTH",
+ "ZUXTW",
+ "ZUZP1",
+ "ZUZP2",
+ "ZUZPQ1",
+ "ZUZPQ2",
+ "ZZIP1",
+ "ZZIP2",
+ "ZZIPQ1",
+ "ZZIPQ2",
+ "LAST",
+}
+
+func init() {
+ Anames = append(Anames, sveAnames...)
+}
diff --git a/src/cmd/internal/obj/arm64/asm7.go b/src/cmd/internal/obj/arm64/asm7.go
index 898977d62a..d8d63b19ba 100644
--- a/src/cmd/internal/obj/arm64/asm7.go
+++ b/src/cmd/internal/obj/arm64/asm7.go
@@ -196,7 +196,7 @@ var atomicCASP = map[obj.As]uint32{
ACASPW: 0<<30 | 0x41<<21 | 0x1f<<10,
}
-var oprange [ALAST & obj.AMask][]Optab
+var oprange [obj.AllowedOpCodes][]Optab
var xcmp [C_NCLASS][C_NCLASS]bool
@@ -2183,7 +2183,23 @@ func (c *ctxt7) aclass(a *obj.Addr) int {
return C_GOK
}
+// SVE instructions, type 127 is reserved for SVE instructions.
+// All SVE instructions are sized 4 bytes.
+var sveOptab = Optab{0, C_GOK, C_GOK, C_GOK, C_GOK, C_GOK, 127, 4, 0, 0, 0}
+
+func isSVE(as obj.As) bool {
+ // A64 opcodes are prefixed with AZ or AP for SVE/SVE2
+ // In goops_gen.go they are defined starting from ASVESTART + 1.
+ return as > ASVESTART
+}
+
func (c *ctxt7) oplook(p *obj.Prog) *Optab {
+ if isSVE(p.As) {
+ // All SVE instructions are in the Insts table.
+ // Matching happens in asmout.
+ return &sveOptab
+ }
+
a1 := int(p.Optab)
if a1 != 0 {
return &optab[a1-1]
@@ -5808,6 +5824,22 @@ func (c *ctxt7) asmout(p *obj.Prog, out []uint32) (count int) {
c.ctxt.Diag("illegal argument: %v\n", p)
break
}
+ case 127:
+ // Generic SVE instruction encoding
+ matched := false
+ groupIdx := int(p.As - ASVESTART - 1)
+ if groupIdx >= 0 && groupIdx < len(insts) {
+ for _, inst := range insts[groupIdx] {
+ if bin, ok := inst.tryEncode(p); ok {
+ o1 = bin
+ matched = true
+ break
+ }
+ }
+ }
+ if !matched {
+ c.ctxt.Diag("illegal combination from SVE: %v", p)
+ }
}
out[0] = o1
out[1] = o2
@@ -7921,6 +7953,44 @@ func EncodeRegisterExtension(a *obj.Addr, ext string, reg, num int16, isAmount,
return errors.New("unsupported general register extension type: " + ext)
}
+ } else if REG_Z0 <= reg && reg <= REG_Z31 {
+ var arng int
+ switch ext {
+ case "B":
+ arng = ARNG_B
+ case "H":
+ arng = ARNG_H
+ case "S":
+ arng = ARNG_S
+ case "D":
+ arng = ARNG_D
+ case "Q":
+ arng = ARNG_Q
+ default:
+ return errors.New("invalid Z register arrangement: " + ext)
+ }
+ a.Reg = REG_ZARNG + (reg & 31) + int16((arng&15)<<5)
+ } else if REG_P0 <= reg && reg <= REG_PN15 {
+ var arng int
+ switch ext {
+ case "B":
+ arng = ARNG_B
+ case "H":
+ arng = ARNG_H
+ case "S":
+ arng = ARNG_S
+ case "D":
+ arng = ARNG_D
+ case "Q":
+ arng = ARNG_Q
+ case "Z":
+ arng = PRED_Z
+ case "M":
+ arng = PRED_M
+ default:
+ return errors.New("invalid P register arrangement: " + ext)
+ }
+ a.Reg = REG_PARNGZM + (reg & 31) + int16((arng&15)<<5)
} else if reg <= REG_V31 && reg >= REG_V0 {
switch ext {
case "B8":
diff --git a/src/cmd/internal/obj/arm64/encoding_gen.go b/src/cmd/internal/obj/arm64/encoding_gen.go
new file mode 100644
index 0000000000..e15f9b67fb
--- /dev/null
+++ b/src/cmd/internal/obj/arm64/encoding_gen.go
@@ -0,0 +1,877 @@
+// Code generated by 'instgen -o=$GOROOT # from go install golang.org/x/arch/arm64/instgen@latest'.
+
+package arm64
+
+const (
+ enc_NIL component = iota
+ enc_tszh_tszl
+ enc_M
+ enc_PNd
+ enc_Pd
+ enc_Pdm
+ enc_Pdn
+ enc_Pg
+ enc_Pm
+ enc_Pn
+ enc_Pv
+ enc_Vd
+ enc_Za
+ enc_Zd
+ enc_Zda
+ enc_Zdn
+ enc_Zk
+ enc_Zm
+ enc_Zn
+ enc_size
+ enc_size0
+ enc_sz
+)
+
+// encodeArngBCheck is the implementation of the following encoding logic:
+// Check this is a B arrangement
+func encodeArngBCheck(v uint32) (uint32, bool) {
+ if v == ARNG_B {
+ return 0, true
+ }
+ return 0, false
+}
+
+// encodeArngDCheck is the implementation of the following encoding logic:
+// Check this is a D arrangement
+func encodeArngDCheck(v uint32) (uint32, bool) {
+ if v == ARNG_D {
+ return 0, true
+ }
+ return 0, false
+}
+
+// encodeArngHCheck is the implementation of the following encoding logic:
+// Check this is a H arrangement
+func encodeArngHCheck(v uint32) (uint32, bool) {
+ if v == ARNG_H {
+ return 0, true
+ }
+ return 0, false
+}
+
+// encodeArngQCheck is the implementation of the following encoding logic:
+// Check this is a Q arrangement
+func encodeArngQCheck(v uint32) (uint32, bool) {
+ if v == ARNG_Q {
+ return 0, true
+ }
+ return 0, false
+}
+
+// encodeArngSCheck is the implementation of the following encoding logic:
+// Check this is a S arrangement
+func encodeArngSCheck(v uint32) (uint32, bool) {
+ if v == ARNG_S {
+ return 0, true
+ }
+ return 0, false
+}
+
+// encodeMergePredCheck is the implementation of the following encoding logic:
+// Check this is a merging predication
+func encodeMergePredCheck(v uint32) (uint32, bool) {
+ if v == PRED_M {
+ return 0, true
+ }
+ return 0, false
+}
+
+// encodeZeroPredCheck is the implementation of the following encoding logic:
+// Check this is a zeroing predication
+func encodeZeroPredCheck(v uint32) (uint32, bool) {
+ if v == PRED_Z {
+ return 0, true
+ }
+ return 0, false
+}
+
+// encodeSzByteHalfword is the implementation of the following encoding logic:
+// For the "Byte and halfword" variant: is the size specifier,
+// sz <T>
+// 0 B
+// 1 H
+// bit range mappings:
+// sz: [22:23)
+func encodeSzByteHalfword(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_B:
+ return 0, true
+ case ARNG_H:
+ return 1 << 22, true
+ }
+ return 0, false
+}
+
+// encodeSizeByteMergeZero is the implementation of the following encoding logic:
+// For the "Byte, merging" and "Byte, zeroing" variants: is the size specifier,
+// size <T>
+// 00 RESERVED
+// 01 H
+// 10 S
+// 11 D
+// bit range mappings:
+// size: [22:24)
+func encodeSizeByteMergeZero(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_H:
+ return 1 << 22, true
+ case ARNG_S:
+ return 2 << 22, true
+ case ARNG_D:
+ return 3 << 22, true
+ }
+ return 0, false
+}
+
+// encodeSize0HalfwordMergeZero is the implementation of the following encoding logic:
+// For the "Halfword, merging" and "Halfword, zeroing" variants: is the size specifier,
+// size[0] <T>
+// 0 S
+// 1 D
+// bit range mappings:
+// size: [22:23)
+func encodeSize0HalfwordMergeZero(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_S:
+ return 0, true
+ case ARNG_D:
+ return 1 << 22, true
+ }
+ return 0, false
+}
+
+// encodeSzWordDoubleword is the implementation of the following encoding logic:
+// For the "Word and doubleword" variant: is the size specifier,
+// sz <T>
+// 0 S
+// 1 D
+// bit range mappings:
+// sz: [22:23)
+func encodeSzWordDoubleword(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_S:
+ return 0, true
+ case ARNG_D:
+ return 1 << 22, true
+ }
+ return 0, false
+}
+
+// encodeSize16B8H4S2D is the implementation of the following encoding logic:
+// Is an arrangement specifier,
+// size <T>
+// 00 16B
+// 01 8H
+// 10 4S
+// 11 2D
+// bit range mappings:
+// size: [22:24)
+func encodeSize16B8H4S2D(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_16B:
+ return 0, true
+ case ARNG_8H:
+ return 1 << 22, true
+ case ARNG_4S:
+ return 2 << 22, true
+ case ARNG_2D:
+ return 3 << 22, true
+ }
+ return 0, false
+}
+
+// encodeSize8H4S2D is the implementation of the following encoding logic:
+// Is an arrangement specifier,
+// size <T>
+// 00 RESERVED
+// 01 8H
+// 10 4S
+// 11 2D
+// bit range mappings:
+// size: [22:24)
+func encodeSize8H4S2D(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_8H:
+ return 1 << 22, true
+ case ARNG_4S:
+ return 2 << 22, true
+ case ARNG_2D:
+ return 3 << 22, true
+ }
+ return 0, false
+}
+
+// encodeVd is the implementation of the following encoding logic:
+// Is the name of the destination SIMD&FP register, encoded in the "Vd" field.
+// bit range mappings:
+// Vd: [0:5)
+func encodeVd(v uint32) (uint32, bool) {
+ return v, true
+}
+
+// encodePNd is the implementation of the following encoding logic:
+// Is the name of the destination scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNd" field.
+// bit range mappings:
+// PNd: [0:3)
+func encodePNd(v uint32) (uint32, bool) {
+ if v >= 24 && v <= 31 {
+ // PN registers starts from 16.
+ return v - 24, true
+ }
+ return 0, false
+}
+
+// encodePd is the implementation of the following encoding logic:
+// Is the name of the destination scalable predicate register, encoded in the "Pd" field.
+// bit range mappings:
+// Pd: [0:4)
+func encodePd(v uint32) (uint32, bool) {
+ return v, true
+}
+
+// encodeZd is the implementation of the following encoding logic:
+// Is the name of the destination scalable vector register, encoded in the "Zd" field.
+// bit range mappings:
+// Zd: [0:5)
+func encodeZd(v uint32) (uint32, bool) {
+ return v, true
+}
+
+// encodePdnDest is the implementation of the following encoding logic:
+// Is the name of the first source and destination scalable predicate register, encoded in the "Pdn" field.
+// bit range mappings:
+// Pdn: [0:4)
+func encodePdnDest(v uint32) (uint32, bool) {
+ return v, true
+}
+
+// encodeZdnDest is the implementation of the following encoding logic:
+// Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.
+// bit range mappings:
+// Zdn: [0:5)
+func encodeZdnDest(v uint32) (uint32, bool) {
+ return v, true
+}
+
+// encodePn59 is the implementation of the following encoding logic:
+// Is the name of the first source scalable predicate register, encoded in the "Pn" field.
+// bit range mappings:
+// Pn: [5:9)
+func encodePn59(v uint32) (uint32, bool) {
+ return v << 5, true
+}
+
+// encodeZn510 is the implementation of the following encoding logic:
+// Is the name of the first source scalable vector register, encoded in the "Zn" field.
+// bit range mappings:
+// Zn: [5:10)
+func encodeZn510(v uint32) (uint32, bool) {
+ return v << 5, true
+}
+
+// encodePg1013 is the implementation of the following encoding logic:
+// Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
+// bit range mappings:
+// Pg: [10:13)
+func encodePg1013(v uint32) (uint32, bool) {
+ if v <= 7 {
+ return v << 10, true
+ }
+ return 0, false
+}
+
+// encodePg1014 is the implementation of the following encoding logic:
+// Is the name of the governing scalable predicate register, encoded in the "Pg" field.
+// bit range mappings:
+// Pg: [10:14)
+func encodePg1014(v uint32) (uint32, bool) {
+ return v << 10, true
+}
+
+// encodePg59 is the implementation of the following encoding logic:
+// Is the name of the governing scalable predicate register, encoded in the "Pg" field.
+// bit range mappings:
+// Pg: [5:9)
+func encodePg59(v uint32) (uint32, bool) {
+ return v << 5, true
+}
+
+// encodePdmDest is the implementation of the following encoding logic:
+// Is the name of the second source and destination scalable predicate register, encoded in the "Pdm" field.
+// bit range mappings:
+// Pdm: [0:4)
+func encodePdmDest(v uint32) (uint32, bool) {
+ return v, true
+}
+
+// encodeZdaDest is the implementation of the following encoding logic:
+// Is the name of the second source and destination scalable vector register, encoded in the "Zda" field.
+// bit range mappings:
+// Zda: [0:5)
+func encodeZdaDest(v uint32) (uint32, bool) {
+ return v, true
+}
+
+// encodePm1620 is the implementation of the following encoding logic:
+// Is the name of the second source scalable predicate register, encoded in the "Pm" field.
+// bit range mappings:
+// Pm: [16:20)
+func encodePm1620(v uint32) (uint32, bool) {
+ return v << 16, true
+}
+
+// encodeZm1621 is the implementation of the following encoding logic:
+// Is the name of the second source scalable vector register, encoded in the "Zm" field.
+// bit range mappings:
+// Zm: [16:21)
+func encodeZm1621(v uint32) (uint32, bool) {
+ return v << 16, true
+}
+
+// encodeZm510 is the implementation of the following encoding logic:
+// Is the name of the second source scalable vector register, encoded in the "Zm" field.
+// bit range mappings:
+// Zm: [5:10)
+func encodeZm510(v uint32) (uint32, bool) {
+ return v << 5, true
+}
+
+// encodePdnSrcDst is the implementation of the following encoding logic:
+// Is the name of the source and destination scalable predicate register, encoded in the "Pdn" field.
+// bit range mappings:
+// Pdn: [0:4)
+func encodePdnSrcDst(v uint32) (uint32, bool) {
+ return v, true
+}
+
+// encodeZdnSrcDst is the implementation of the following encoding logic:
+// Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.
+// bit range mappings:
+// Zdn: [0:5)
+func encodeZdnSrcDst(v uint32) (uint32, bool) {
+ return v, true
+}
+
+// encodePm59v1 is the implementation of the following encoding logic:
+// Is the name of the source scalable predicate register, encoded in the "Pm" field.
+// bit range mappings:
+// Pm: [5:9)
+func encodePm59v1(v uint32) (uint32, bool) {
+ return v << 5, true
+}
+
+// encodePn59v2 is the implementation of the following encoding logic:
+// Is the name of the source scalable predicate register, encoded in the "Pn" field.
+// bit range mappings:
+// Pn: [5:9)
+func encodePn59v2(v uint32) (uint32, bool) {
+ return v << 5, true
+}
+
+// encodeZn510Src is the implementation of the following encoding logic:
+// Is the name of the source scalable vector register, encoded in the "Zn" field.
+// bit range mappings:
+// Zn: [5:10)
+func encodeZn510Src(v uint32) (uint32, bool) {
+ return v << 5, true
+}
+
+// encodeZda3RdSrcDst is the implementation of the following encoding logic:
+// Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.
+// bit range mappings:
+// Zda: [0:5)
+func encodeZda3RdSrcDst(v uint32) (uint32, bool) {
+ return v, true
+}
+
+// encodeZa16213Rd is the implementation of the following encoding logic:
+// Is the name of the third source scalable vector register, encoded in the "Za" field.
+// bit range mappings:
+// Za: [16:21)
+func encodeZa16213Rd(v uint32) (uint32, bool) {
+ return v << 16, true
+}
+
+// encodeZa5103Rd is the implementation of the following encoding logic:
+// Is the name of the third source scalable vector register, encoded in the "Za" field.
+// bit range mappings:
+// Za: [5:10)
+func encodeZa5103Rd(v uint32) (uint32, bool) {
+ return v << 5, true
+}
+
+// encodeZk5103Rd is the implementation of the following encoding logic:
+// Is the name of the third source scalable vector register, encoded in the "Zk" field.
+// bit range mappings:
+// Zk: [5:10)
+func encodeZk5103Rd(v uint32) (uint32, bool) {
+ return v << 5, true
+}
+
+// encodePv1013 is the implementation of the following encoding logic:
+// Is the name of the vector select predicate register P0-P7, encoded in the "Pv" field.
+// bit range mappings:
+// Pv: [10:13)
+func encodePv1013(v uint32) (uint32, bool) {
+ return v << 10, true
+}
+
+// encodePv1014 is the implementation of the following encoding logic:
+// Is the name of the vector select predicate register, encoded in the "Pv" field.
+// bit range mappings:
+// Pv: [10:14)
+func encodePv1014(v uint32) (uint32, bool) {
+ return v << 10, true
+}
+
+// encodePv59 is the implementation of the following encoding logic:
+// Is the name of the vector select predicate register, encoded in the "Pv" field.
+// bit range mappings:
+// Pv: [5:9)
+func encodePv59(v uint32) (uint32, bool) {
+ return v << 5, true
+}
+
+// encodePredQualM1617 is the implementation of the following encoding logic:
+// Is the predication qualifier,
+// M <ZM>
+// 0 Z
+// 1 M
+// bit range mappings:
+// M: [16:17)
+func encodePredQualM1617(v uint32) (uint32, bool) {
+ switch v {
+ case PRED_Z:
+ return 0, true
+ case PRED_M:
+ return 1 << 16, true
+ }
+ return 0, false
+}
+
+// encodePredQualM45 is the implementation of the following encoding logic:
+// Is the predication qualifier,
+// M <ZM>
+// 0 Z
+// 1 M
+// bit range mappings:
+// M: [4:5)
+func encodePredQualM45(v uint32) (uint32, bool) {
+ switch v {
+ case PRED_Z:
+ return 0, true
+ case PRED_M:
+ return 1 << 4, true
+ }
+ return 0, false
+}
+
+// encodeSizeBHSD2224 is the implementation of the following encoding logic:
+// Is the size specifier,
+// size <T>
+// 00 B
+// 01 H
+// 10 S
+// 11 D
+// bit range mappings:
+// size: [22:24)
+func encodeSizeBHSD2224(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_B:
+ return 0 << 22, true
+ case ARNG_H:
+ return 1 << 22, true
+ case ARNG_S:
+ return 2 << 22, true
+ case ARNG_D:
+ return 3 << 22, true
+ }
+ return 0, false
+}
+
+// encodeSizeBHS2224 is the implementation of the following encoding logic:
+// Is the size specifier,
+// size <T>
+// 00 B
+// 01 H
+// 10 S
+// 11 RESERVED
+// bit range mappings:
+// size: [22:24)
+func encodeSizeBHS2224(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_B:
+ return 0 << 22, true
+ case ARNG_H:
+ return 1 << 22, true
+ case ARNG_S:
+ return 2 << 22, true
+ }
+ return 0, false
+}
+
+// encodeSizeBHS2224Offset1 is the implementation of the following encoding logic:
+// Is the size specifier,
+// size <T>
+// 00 RESERVED
+// 01 B
+// 10 H
+// 11 S
+// bit range mappings:
+// size: [22:24)
+func encodeSizeBHS2224Offset1(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_B:
+ return 1 << 22, true
+ case ARNG_H:
+ return 2 << 22, true
+ case ARNG_S:
+ return 3 << 22, true
+ }
+ return 0, false
+}
+
+// encodeSizeHSD1315 is the implementation of the following encoding logic:
+// Is the size specifier,
+// size <T>
+// 00 RESERVED
+// 01 H
+// 10 S
+// 11 D
+// bit range mappings:
+// size: [13:15)
+func encodeSizeHSD1315(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_H:
+ return 1 << 13, true
+ case ARNG_S:
+ return 2 << 13, true
+ case ARNG_D:
+ return 3 << 13, true
+ }
+ return 0, false
+}
+
+// encodeSizeHSD1719 is the implementation of the following encoding logic:
+// Is the size specifier,
+// size <T>
+// 00 RESERVED
+// 01 H
+// 10 S
+// 11 D
+// bit range mappings:
+// size: [17:19)
+func encodeSizeHSD1719(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_H:
+ return 1 << 17, true
+ case ARNG_S:
+ return 2 << 17, true
+ case ARNG_D:
+ return 3 << 17, true
+ }
+ return 0, false
+}
+
+// encodeSizeHSD2224 is the implementation of the following encoding logic:
+// Is the size specifier,
+// size <T>
+// 00 RESERVED
+// 01 H
+// 10 S
+// 11 D
+// bit range mappings:
+// size: [22:24)
+func encodeSizeHSD2224(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_H:
+ return 1 << 22, true
+ case ARNG_S:
+ return 2 << 22, true
+ case ARNG_D:
+ return 3 << 22, true
+ }
+ return 0, false
+}
+
+// encodeSizeHSD2224No00 is the implementation of the following encoding logic:
+// Is the size specifier,
+// size <T>
+// 01 H
+// 10 S
+// 11 D
+// bit range mappings:
+// size: [22:24)
+func encodeSizeHSD2224No00(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_H:
+ return 1 << 22, true
+ case ARNG_S:
+ return 2 << 22, true
+ case ARNG_D:
+ return 3 << 22, true
+ }
+ return 0, false
+}
+
+// encodeSizeHD2224 is the implementation of the following encoding logic:
+// Is the size specifier,
+// size <T>
+// 01 H
+// 1x D
+// bit range mappings:
+// size: [22:24)
+func encodeSizeHD2224(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_H:
+ return 1 << 22, true
+ case ARNG_D:
+ return 3 << 22, true
+ }
+ return 0, false
+}
+
+// encodeSizeTbBHSD2224 is the implementation of the following encoding logic:
+// Is the size specifier,
+// size <Tb>
+// 00 B
+// 01 H
+// 10 S
+// 11 D
+// bit range mappings:
+// size: [22:24)
+func encodeSizeTbBHSD2224(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_B:
+ return 0 << 22, true
+ case ARNG_H:
+ return 1 << 22, true
+ case ARNG_S:
+ return 2 << 22, true
+ case ARNG_D:
+ return 3 << 22, true
+ }
+ return 0, false
+}
+
+// encodeSizeTbBHS2224 is the implementation of the following encoding logic:
+// Is the size specifier,
+// size <Tb>
+// 00 RESERVED
+// 01 B
+// 10 H
+// 11 S
+// bit range mappings:
+// size: [22:24)
+func encodeSizeTbBHS2224(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_B:
+ return 1 << 22, true
+ case ARNG_H:
+ return 2 << 22, true
+ case ARNG_S:
+ return 3 << 22, true
+ }
+ return 0, false
+}
+
+// encodeSizeTbHSD2224Offset1 is the implementation of the following encoding logic:
+// Is the size specifier,
+// size <Tb>
+// 00 RESERVED
+// 01 H
+// 10 S
+// 11 D
+// bit range mappings:
+// size: [22:24)
+func encodeSizeTbHSD2224Offset1(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_H:
+ return 1 << 22, true
+ case ARNG_S:
+ return 2 << 22, true
+ case ARNG_D:
+ return 3 << 22, true
+ }
+ return 0, false
+}
+
+// encodeSizeTbBS2224 is the implementation of the following encoding logic:
+// Is the size specifier,
+// size <Tb>
+// 01 B
+// 1x S
+// bit range mappings:
+// size: [22:24)
+func encodeSizeTbBS2224(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_B:
+ return 1 << 22, true
+ case ARNG_S:
+ return 3 << 22, true
+ }
+ return 0, false
+}
+
+// encodeSize0BH2223 is the implementation of the following encoding logic:
+// Is the size specifier,
+// size[0] <T>
+// 0 B
+// 1 H
+// bit range mappings:
+// size: [22:23)
+func encodeSize0BH2223(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_B:
+ return 0 << 22, true
+ case ARNG_H:
+ return 1 << 22, true
+ }
+ return 0, false
+}
+
+// encodeSize0SD2223 is the implementation of the following encoding logic:
+// Is the size specifier,
+// size[0] <T>
+// 0 S
+// 1 D
+// bit range mappings:
+// size: [22:23)
+func encodeSize0SD2223(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_S:
+ return 0 << 22, true
+ case ARNG_D:
+ return 1 << 22, true
+ }
+ return 0, false
+}
+
+// encodeSize0TbBH2223 is the implementation of the following encoding logic:
+// Is the size specifier,
+// size[0] <Tb>
+// 0 B
+// 1 H
+// bit range mappings:
+// size: [22:23)
+func encodeSize0TbBH2223(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_B:
+ return 0 << 22, true
+ case ARNG_H:
+ return 1 << 22, true
+ }
+ return 0, false
+}
+
+// encodeSzSD1415 is the implementation of the following encoding logic:
+// Is the size specifier,
+// sz <T>
+// 0 S
+// 1 D
+// bit range mappings:
+// sz: [14:15)
+func encodeSzSD1415(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_S:
+ return 0 << 14, true
+ case ARNG_D:
+ return 1 << 14, true
+ }
+ return 0, false
+}
+
+// encodeSzSD1718 is the implementation of the following encoding logic:
+// Is the size specifier,
+// sz <T>
+// 0 S
+// 1 D
+// bit range mappings:
+// sz: [17:18)
+func encodeSzSD1718(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_S:
+ return 0 << 17, true
+ case ARNG_D:
+ return 1 << 17, true
+ }
+ return 0, false
+}
+
+// encodeSzSD2223 is the implementation of the following encoding logic:
+// Is the size specifier,
+// sz <T>
+// 0 S
+// 1 D
+// bit range mappings:
+// sz: [22:23)
+func encodeSzSD2223(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_S:
+ return 0 << 22, true
+ case ARNG_D:
+ return 1 << 22, true
+ }
+ return 0, false
+}
+
+// encodeTszhTszlBHS is the implementation of the following encoding logic:
+// Is the size specifier,
+// tszh tszl <T>
+// 0 00 RESERVED
+// 0 01 B
+// 0 10 H
+// 0 11 RESERVED
+// 1 00 S
+// 1 01 RESERVED
+// 1 1x RESERVED
+// bit range mappings:
+// tszh: [22:23)
+// tszl: [19:21)
+func encodeTszhTszlBHS(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_B:
+ return 0<<22 | 1<<19, true
+ case ARNG_H:
+ return 0<<22 | 2<<19, true
+ case ARNG_S:
+ return 1 << 22, true
+ }
+ return 0, false
+}
+
+// encodeTszhTszlTbHSD is the implementation of the following encoding logic:
+// Is the size specifier,
+// tszh tszl <Tb>
+// 0 00 RESERVED
+// 0 01 H
+// 0 10 S
+// 0 11 RESERVED
+// 1 00 D
+// 1 01 RESERVED
+// 1 1x RESERVED
+// bit range mappings:
+// tszh: [22:23)
+// tszl: [19:21)
+func encodeTszhTszlTbHSD(v uint32) (uint32, bool) {
+ switch v {
+ case ARNG_H:
+ return 0<<22 | 1<<19, true
+ case ARNG_S:
+ return 0<<22 | 2<<19, true
+ case ARNG_D:
+ return 1 << 22, true
+ }
+ return 0, false
+}
+
+// encodeNoop is the implementation of the following encoding logic:
+// No-op check, returns true
+func encodeNoop(v uint32) (uint32, bool) {
+ return 0, true
+}
diff --git a/src/cmd/internal/obj/arm64/goops_gen.go b/src/cmd/internal/obj/arm64/goops_gen.go
new file mode 100644
index 0000000000..52ce71d744
--- /dev/null
+++ b/src/cmd/internal/obj/arm64/goops_gen.go
@@ -0,0 +1,413 @@
+// Code generated by 'instgen -o=$GOROOT # from go install golang.org/x/arch/arm64/instgen@latest'. DO NOT EDIT.
+
+package arm64
+
+import "cmd/internal/obj"
+
+const (
+ APAND obj.As = ASVESTART + 1 + iota
+ APANDS
+ APBIC
+ APBICS
+ APBRKA
+ APBRKAS
+ APBRKB
+ APBRKBS
+ APBRKN
+ APBRKNS
+ APBRKPA
+ APBRKPAS
+ APBRKPB
+ APBRKPBS
+ APEOR
+ APEORS
+ APNAND
+ APNANDS
+ APNOR
+ APNORS
+ APORN
+ APORNS
+ APORR
+ APORRS
+ APPFALSE
+ APPFIRST
+ APPNEXT
+ APPTEST
+ APPTRUE
+ APPUNPKHI
+ APPUNPKLO
+ APRDFFR
+ APRDFFRS
+ APREV
+ APSEL
+ APTRN1
+ APTRN2
+ APUZP1
+ APUZP2
+ APWRFFR
+ APZIP1
+ APZIP2
+ ASETFFR
+ AZABS
+ AZADCLB
+ AZADCLT
+ AZADD
+ AZADDHNB
+ AZADDHNT
+ AZADDP
+ AZADDPT
+ AZADDQP
+ AZADDQV
+ AZADDSUBP
+ AZAESD
+ AZAESE
+ AZAESIMC
+ AZAESMC
+ AZAND
+ AZANDQV
+ AZASR
+ AZASRR
+ AZBCAX
+ AZBDEP
+ AZBEXT
+ AZBF1CVT
+ AZBF1CVTLT
+ AZBF2CVT
+ AZBF2CVTLT
+ AZBFADD
+ AZBFCLAMP
+ AZBFCVT
+ AZBFCVTNT
+ AZBFDOT
+ AZBFMAX
+ AZBFMAXNM
+ AZBFMIN
+ AZBFMINNM
+ AZBFMLA
+ AZBFMLALB
+ AZBFMLALT
+ AZBFMLS
+ AZBFMLSLB
+ AZBFMLSLT
+ AZBFMMLA
+ AZBFMUL
+ AZBFSCALE
+ AZBFSUB
+ AZBGRP
+ AZBIC
+ AZBSL
+ AZBSL1N
+ AZBSL2N
+ AZCLASTA
+ AZCLASTB
+ AZCLS
+ AZCLZ
+ AZCMPEQ
+ AZCMPGE
+ AZCMPGT
+ AZCMPHI
+ AZCMPHS
+ AZCMPLE
+ AZCMPLO
+ AZCMPLS
+ AZCMPLT
+ AZCMPNE
+ AZCNOT
+ AZCNT
+ AZCOMPACT
+ AZDECP
+ AZEOR
+ AZEOR3
+ AZEORBT
+ AZEORQV
+ AZEORTB
+ AZEXPAND
+ AZF1CVT
+ AZF1CVTLT
+ AZF2CVT
+ AZF2CVTLT
+ AZFABD
+ AZFABS
+ AZFACGE
+ AZFACGT
+ AZFADD
+ AZFADDP
+ AZFADDQV
+ AZFAMAX
+ AZFAMIN
+ AZFCLAMP
+ AZFCMEQ
+ AZFCMGE
+ AZFCMGT
+ AZFCMNE
+ AZFCMUO
+ AZFCVT
+ AZFCVTLT
+ AZFCVTNT
+ AZFCVTX
+ AZFCVTXNT
+ AZFCVTZS
+ AZFCVTZU
+ AZFDIV
+ AZFDIVR
+ AZFDOT
+ AZFEXPA
+ AZFLOGB
+ AZFMAD
+ AZFMAX
+ AZFMAXNM
+ AZFMAXNMP
+ AZFMAXNMQV
+ AZFMAXP
+ AZFMAXQV
+ AZFMIN
+ AZFMINNM
+ AZFMINNMP
+ AZFMINNMQV
+ AZFMINP
+ AZFMINQV
+ AZFMLA
+ AZFMLALB
+ AZFMLALLBB
+ AZFMLALLBT
+ AZFMLALLTB
+ AZFMLALLTT
+ AZFMLALT
+ AZFMLS
+ AZFMLSLB
+ AZFMLSLT
+ AZFMMLA
+ AZFMSB
+ AZFMUL
+ AZFMULX
+ AZFNEG
+ AZFNMAD
+ AZFNMLA
+ AZFNMLS
+ AZFNMSB
+ AZFRECPE
+ AZFRECPS
+ AZFRECPX
+ AZFRINT32X
+ AZFRINT32Z
+ AZFRINT64X
+ AZFRINT64Z
+ AZFRINTA
+ AZFRINTI
+ AZFRINTM
+ AZFRINTN
+ AZFRINTP
+ AZFRINTX
+ AZFRINTZ
+ AZFRSQRTE
+ AZFRSQRTS
+ AZFSCALE
+ AZFSQRT
+ AZFSUB
+ AZFSUBR
+ AZFTSMUL
+ AZFTSSEL
+ AZHISTCNT
+ AZHISTSEG
+ AZINCP
+ AZLSL
+ AZLSLR
+ AZLSR
+ AZLSRR
+ AZMAD
+ AZMADPT
+ AZMATCH
+ AZMLA
+ AZMLAPT
+ AZMLS
+ AZMOVPRFX
+ AZMSB
+ AZMUL
+ AZNBSL
+ AZNEG
+ AZNMATCH
+ AZNOT
+ AZORQV
+ AZORR
+ AZPMOV
+ AZPMUL
+ AZPMULLB
+ AZPMULLT
+ AZRADDHNB
+ AZRADDHNT
+ AZRAX1
+ AZRBIT
+ AZREV
+ AZREVB
+ AZREVD
+ AZREVH
+ AZREVW
+ AZRSUBHNB
+ AZRSUBHNT
+ AZSABA
+ AZSABAL
+ AZSABALB
+ AZSABALT
+ AZSABD
+ AZSABDLB
+ AZSABDLT
+ AZSADALP
+ AZSADDLB
+ AZSADDLBT
+ AZSADDLT
+ AZSADDWB
+ AZSADDWT
+ AZSBCLB
+ AZSBCLT
+ AZSCLAMP
+ AZSCVTF
+ AZSCVTFLT
+ AZSDIV
+ AZSDIVR
+ AZSDOT
+ AZSEL
+ AZSHADD
+ AZSHSUB
+ AZSHSUBR
+ AZSM4E
+ AZSM4EKEY
+ AZSMAX
+ AZSMAXP
+ AZSMAXQV
+ AZSMIN
+ AZSMINP
+ AZSMINQV
+ AZSMLALB
+ AZSMLALT
+ AZSMLSLB
+ AZSMLSLT
+ AZSMMLA
+ AZSMULH
+ AZSMULLB
+ AZSMULLT
+ AZSPLICE
+ AZSQABS
+ AZSQADD
+ AZSQDECP
+ AZSQDMLALB
+ AZSQDMLALBT
+ AZSQDMLALT
+ AZSQDMLSLB
+ AZSQDMLSLBT
+ AZSQDMLSLT
+ AZSQDMULH
+ AZSQDMULLB
+ AZSQDMULLT
+ AZSQINCP
+ AZSQNEG
+ AZSQRDMLAH
+ AZSQRDMLSH
+ AZSQRDMULH
+ AZSQRSHL
+ AZSQRSHLR
+ AZSQSHL
+ AZSQSHLR
+ AZSQSUB
+ AZSQSUBR
+ AZSQXTNB
+ AZSQXTNT
+ AZSQXTUNB
+ AZSQXTUNT
+ AZSRHADD
+ AZSRSHL
+ AZSRSHLR
+ AZSSUBLB
+ AZSSUBLBT
+ AZSSUBLT
+ AZSSUBLTB
+ AZSSUBWB
+ AZSSUBWT
+ AZSUB
+ AZSUBHNB
+ AZSUBHNT
+ AZSUBP
+ AZSUBPT
+ AZSUBR
+ AZSUNPKHI
+ AZSUNPKLO
+ AZSUQADD
+ AZSXTB
+ AZSXTH
+ AZSXTW
+ AZTBX
+ AZTBXQ
+ AZTRN1
+ AZTRN2
+ AZUABA
+ AZUABAL
+ AZUABALB
+ AZUABALT
+ AZUABD
+ AZUABDLB
+ AZUABDLT
+ AZUADALP
+ AZUADDLB
+ AZUADDLT
+ AZUADDWB
+ AZUADDWT
+ AZUCLAMP
+ AZUCVTF
+ AZUCVTFLT
+ AZUDIV
+ AZUDIVR
+ AZUDOT
+ AZUHADD
+ AZUHSUB
+ AZUHSUBR
+ AZUMAX
+ AZUMAXP
+ AZUMAXQV
+ AZUMIN
+ AZUMINP
+ AZUMINQV
+ AZUMLALB
+ AZUMLALT
+ AZUMLSLB
+ AZUMLSLT
+ AZUMMLA
+ AZUMULH
+ AZUMULLB
+ AZUMULLT
+ AZUQADD
+ AZUQDECP
+ AZUQINCP
+ AZUQRSHL
+ AZUQRSHLR
+ AZUQSHL
+ AZUQSHLR
+ AZUQSUB
+ AZUQSUBR
+ AZUQXTNB
+ AZUQXTNT
+ AZURECPE
+ AZURHADD
+ AZURSHL
+ AZURSHLR
+ AZURSQRTE
+ AZUSDOT
+ AZUSMMLA
+ AZUSQADD
+ AZUSUBLB
+ AZUSUBLT
+ AZUSUBWB
+ AZUSUBWT
+ AZUUNPKHI
+ AZUUNPKLO
+ AZUXTB
+ AZUXTH
+ AZUXTW
+ AZUZP1
+ AZUZP2
+ AZUZPQ1
+ AZUZPQ2
+ AZZIP1
+ AZZIP2
+ AZZIPQ1
+ AZZIPQ2
+ ALAST
+)
diff --git a/src/cmd/internal/obj/arm64/inst.go b/src/cmd/internal/obj/arm64/inst.go
new file mode 100644
index 0000000000..abd464eb00
--- /dev/null
+++ b/src/cmd/internal/obj/arm64/inst.go
@@ -0,0 +1,188 @@
+// Copyright 2026 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package arm64
+
+import (
+ "cmd/internal/obj"
+ "fmt"
+ "iter"
+)
+
+// instEncoder represents an instruction encoder.
+type instEncoder struct {
+ goOp obj.As // Go opcode mnemonic
+ fixedBits uint32 // Known bits
+ args []operand // Operands, in Go order
+}
+
+type varBits struct {
+ // The low and high bit index in the binary encoding, exclusive on hi
+ lo, hi int
+ encoded bool // If true then its value is already encoded
+ bits uint32
+}
+
+// component is the component of an binary encoding.
+// e.g. for operand <Zda>.<T>, <T>'s encoding function might be described as:
+//
+// For the "Byte and halfword" variant: is the size specifier,
+// sz <T>
+// 0 B
+// 1 H
+// bit range mappings:
+// sz: [22:23)
+//
+// Then sz is the component of the binary encoding.
+type component uint16
+
+type elemEncoder struct {
+ fn func(uint32) (uint32, bool)
+ // comp is the component of the binary encoding.
+ comp component
+}
+
+// operand is the operand type of an instruction.
+type operand struct {
+ class AClass // Operand class, register, constant, memory operation etc.
+ // The elements that this operand includes, this only includes the encoding-related parts
+ // They are represented as a list of pointers to the encoding functions.
+ // The first returned value is the encoded binary, the second is the ok signal.
+ // The encoding functions return the ok signal for deduplication purposes:
+ // For example:
+ // SDOT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
+ // SDOT <Zda>.H, <Zn>.B, <Zm>.B
+ // SDOT <Zda>.S, <Zn>.H, <Zm>.H
+ //
+ // <T> and <Tb> are specified in the encoding text, that there is a constraint "T = 4*Tb".
+ // We don't know this fact by looking at the encoding format solely, without this information
+ // the first encoding domain entails the other 2. And at instruction matching phase we simply
+ // cannot deduplicate them. So we defer this deduplication to the encoding phase.
+ // We need the ok signal with [elemEncoder.comp] field to deduplicate them.
+ elemEncoders []elemEncoder
+}
+
+// opsInProg returns an iterator over the operands ([Addr]) of p
+func opsInProg(p *obj.Prog) iter.Seq[*obj.Addr] {
+ return func(yield func(*obj.Addr) bool) {
+ // Go order: From, Reg, RestArgs..., To
+ // For SVE, Reg is unused as it's so common that registers have arrangements.
+ if p.From.Type != obj.TYPE_NONE {
+ if !yield(&p.From) {
+ return
+ }
+ }
+ for j := range p.RestArgs {
+ if !yield(&p.RestArgs[j].Addr) {
+ return
+ }
+ }
+ if p.To.Type != obj.TYPE_NONE {
+ if !yield(&p.To) {
+ return
+ }
+ }
+ }
+}
+
+// aclass returns the AClass of an Addr.
+func aclass(a *obj.Addr) AClass {
+ if a.Type == obj.TYPE_REG {
+ if a.Reg >= REG_Z0 && a.Reg <= REG_Z31 {
+ return AC_ZREG
+ }
+ if a.Reg >= REG_P0 && a.Reg <= REG_P15 {
+ return AC_PREG
+ }
+ if a.Reg >= REG_ARNG && a.Reg < REG_ELEM {
+ return AC_ARNG
+ }
+ if a.Reg >= REG_ZARNG && a.Reg < REG_PARNGZM {
+ return AC_ARNG
+ }
+ if a.Reg >= REG_PARNGZM && a.Reg < REG_PARNGZM_END {
+ switch (a.Reg >> 5) & 15 {
+ case PRED_M, PRED_Z:
+ return AC_PREGZM
+ default:
+ return AC_ARNG
+ }
+ }
+ }
+ panic("unknown AClass")
+}
+
+// addrComponent returns the binary (component) of the stored element in a at index, for operand
+// of type aclass.
+//
+// For example, for operand of type AC_ARNG, it has 2 permissible components (identified by index)
+// 0. register: <reg>
+// 1. arrangement: <T>
+//
+// They are stored in a.Reg as:
+//
+// reg | (arrangement << 5)
+//
+// More details are in the comments in the switch cases of this function.
+func addrComponent(a *obj.Addr, acl AClass, index int) uint32 {
+ switch acl {
+ // AClass: AC_ARNG, AC_PREG, AC_PREGZ, AC_PREGM, AC_ZREG
+ // GNU mnemonic: <reg>.<T> Or <reg>/<T> (T is M or Z)
+ // Go mnemonic:
+ // reg.<T>
+ // Encoding:
+ // Type = TYPE_REG
+ // Reg = reg | (arrangement or predication << 5)
+ case AC_ARNG, AC_PREG, AC_PREGZM, AC_ZREG:
+ switch index {
+ case 0:
+ return uint32(a.Reg & 31)
+ case 1:
+ return uint32((a.Reg >> 5) & 15)
+ default:
+ panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl))
+ }
+ }
+ // TODO: handle more AClasses.
+ panic(fmt.Errorf("unknown AClass %d", acl))
+}
+
+// tryEncode tries to encode p with i, it returns the encoded binary and ok signal.
+func (i *instEncoder) tryEncode(p *obj.Prog) (uint32, bool) {
+ bin := i.fixedBits
+ // Some elements are encoded in the same component, they need to be equal.
+ // For example { <Zn1>.<Tb>-<Zn2>.<Tb> }.
+ // The 2 instances of <Tb> must encode to the same value.
+ encoded := map[component]uint32{}
+ opIdx := 0
+ for addr := range opsInProg(p) {
+ if opIdx >= len(i.args) {
+ return 0, false
+ }
+ op := i.args[opIdx]
+ opIdx++
+ acl := aclass(addr)
+ if acl != op.class {
+ return 0, false
+ }
+ for i, enc := range op.elemEncoders {
+ val := addrComponent(addr, acl, i)
+ if b, ok := enc.fn(val); ok {
+ bin |= b
+ if _, ok := encoded[enc.comp]; ok && b != encoded[enc.comp] {
+ return 0, false
+ }
+ if enc.comp != enc_NIL {
+ encoded[enc.comp] = b
+ }
+ } else {
+ return 0, false
+ }
+ }
+ }
+ if opIdx != len(i.args) {
+ return 0, false
+ }
+ return bin, true
+}
diff --git a/src/cmd/internal/obj/arm64/inst_gen.go b/src/cmd/internal/obj/arm64/inst_gen.go
new file mode 100644
index 0000000000..cb05ef50bc
--- /dev/null
+++ b/src/cmd/internal/obj/arm64/inst_gen.go
@@ -0,0 +1,6307 @@
+// Code generated by 'instgen -o=$GOROOT # from go install golang.org/x/arch/arm64/instgen@latest'. DO NOT EDIT.
+
+// The following constants are generated from the XML specification.
+
+package arm64
+
+// insts are grouped by [goOp].
+var insts = [][]instEncoder{
+ // PAND
+ {
+ // PAND <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
+ {
+ goOp: APAND,
+ fixedBits: 0x25004000,
+ args: Pm_B__Pn_B__PgZ__Pd_B,
+ },
+ },
+ // PANDS
+ {
+ // PANDS <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
+ {
+ goOp: APANDS,
+ fixedBits: 0x25404000,
+ args: Pm_B__Pn_B__PgZ__Pd_B,
+ },
+ },
+ // PBIC
+ {
+ // PBIC <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
+ {
+ goOp: APBIC,
+ fixedBits: 0x25004010,
+ args: Pm_B__Pn_B__PgZ__Pd_B,
+ },
+ },
+ // PBICS
+ {
+ // PBICS <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
+ {
+ goOp: APBICS,
+ fixedBits: 0x25404010,
+ args: Pm_B__Pn_B__PgZ__Pd_B,
+ },
+ },
+ // PBRKA
+ {
+ // PBRKA <Pn>.B, <Pg>/<ZM>, <Pd>.B
+ {
+ goOp: APBRKA,
+ fixedBits: 0x25104000,
+ args: Pn_B__PgZM__Pd_B,
+ },
+ },
+ // PBRKAS
+ {
+ // PBRKAS <Pn>.B, <Pg>/Z, <Pd>.B
+ {
+ goOp: APBRKAS,
+ fixedBits: 0x25504000,
+ args: Pn_B__PgZ__Pd_B,
+ },
+ },
+ // PBRKB
+ {
+ // PBRKB <Pn>.B, <Pg>/<ZM>, <Pd>.B
+ {
+ goOp: APBRKB,
+ fixedBits: 0x25904000,
+ args: Pn_B__PgZM__Pd_B,
+ },
+ },
+ // PBRKBS
+ {
+ // PBRKBS <Pn>.B, <Pg>/Z, <Pd>.B
+ {
+ goOp: APBRKBS,
+ fixedBits: 0x25d04000,
+ args: Pn_B__PgZ__Pd_B,
+ },
+ },
+ // PBRKN
+ {
+ // PBRKN <Pdm>.B, <Pn>.B, <Pg>/Z, <Pdm>.B
+ {
+ goOp: APBRKN,
+ fixedBits: 0x25184000,
+ args: Pdm_B__Pn_B__PgZ__Pdm_B,
+ },
+ },
+ // PBRKNS
+ {
+ // PBRKNS <Pdm>.B, <Pn>.B, <Pg>/Z, <Pdm>.B
+ {
+ goOp: APBRKNS,
+ fixedBits: 0x25584000,
+ args: Pdm_B__Pn_B__PgZ__Pdm_B,
+ },
+ },
+ // PBRKPA
+ {
+ // PBRKPA <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
+ {
+ goOp: APBRKPA,
+ fixedBits: 0x2500c000,
+ args: Pm_B__Pn_B__PgZ__Pd_B,
+ },
+ },
+ // PBRKPAS
+ {
+ // PBRKPAS <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
+ {
+ goOp: APBRKPAS,
+ fixedBits: 0x2540c000,
+ args: Pm_B__Pn_B__PgZ__Pd_B,
+ },
+ },
+ // PBRKPB
+ {
+ // PBRKPB <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
+ {
+ goOp: APBRKPB,
+ fixedBits: 0x2500c010,
+ args: Pm_B__Pn_B__PgZ__Pd_B,
+ },
+ },
+ // PBRKPBS
+ {
+ // PBRKPBS <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
+ {
+ goOp: APBRKPBS,
+ fixedBits: 0x2540c010,
+ args: Pm_B__Pn_B__PgZ__Pd_B,
+ },
+ },
+ // PEOR
+ {
+ // PEOR <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
+ {
+ goOp: APEOR,
+ fixedBits: 0x25004200,
+ args: Pm_B__Pn_B__PgZ__Pd_B,
+ },
+ },
+ // PEORS
+ {
+ // PEORS <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
+ {
+ goOp: APEORS,
+ fixedBits: 0x25404200,
+ args: Pm_B__Pn_B__PgZ__Pd_B,
+ },
+ },
+ // PNAND
+ {
+ // PNAND <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
+ {
+ goOp: APNAND,
+ fixedBits: 0x25804210,
+ args: Pm_B__Pn_B__PgZ__Pd_B,
+ },
+ },
+ // PNANDS
+ {
+ // PNANDS <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
+ {
+ goOp: APNANDS,
+ fixedBits: 0x25c04210,
+ args: Pm_B__Pn_B__PgZ__Pd_B,
+ },
+ },
+ // PNOR
+ {
+ // PNOR <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
+ {
+ goOp: APNOR,
+ fixedBits: 0x25804200,
+ args: Pm_B__Pn_B__PgZ__Pd_B,
+ },
+ },
+ // PNORS
+ {
+ // PNORS <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
+ {
+ goOp: APNORS,
+ fixedBits: 0x25c04200,
+ args: Pm_B__Pn_B__PgZ__Pd_B,
+ },
+ },
+ // PORN
+ {
+ // PORN <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
+ {
+ goOp: APORN,
+ fixedBits: 0x25804010,
+ args: Pm_B__Pn_B__PgZ__Pd_B,
+ },
+ },
+ // PORNS
+ {
+ // PORNS <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
+ {
+ goOp: APORNS,
+ fixedBits: 0x25c04010,
+ args: Pm_B__Pn_B__PgZ__Pd_B,
+ },
+ },
+ // PORR
+ {
+ // PORR <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
+ {
+ goOp: APORR,
+ fixedBits: 0x25804000,
+ args: Pm_B__Pn_B__PgZ__Pd_B,
+ },
+ },
+ // PORRS
+ {
+ // PORRS <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
+ {
+ goOp: APORRS,
+ fixedBits: 0x25c04000,
+ args: Pm_B__Pn_B__PgZ__Pd_B,
+ },
+ },
+ // PPFALSE
+ {
+ // PPFALSE <Pd>.B
+ {
+ goOp: APPFALSE,
+ fixedBits: 0x2518e400,
+ args: Pd_B,
+ },
+ },
+ // PPFIRST
+ {
+ // PPFIRST <Pdn>.B, <Pg>, <Pdn>.B
+ {
+ goOp: APPFIRST,
+ fixedBits: 0x2558c000,
+ args: Pdn_B__Pg__Pdn_B,
+ },
+ },
+ // PPNEXT
+ {
+ // PPNEXT <Pdn>.<T>, <Pv>, <Pdn>.<T>
+ {
+ goOp: APPNEXT,
+ fixedBits: 0x2519c400,
+ args: Pdn_T__Pv__Pdn_T,
+ },
+ },
+ // PPTEST
+ {
+ // PPTEST <Pn>.B, <Pg>
+ {
+ goOp: APPTEST,
+ fixedBits: 0x2550c000,
+ args: Pn_B__Pg,
+ },
+ },
+ // PPTRUE
+ {
+ // PPTRUE <PNd>.<T>
+ {
+ goOp: APPTRUE,
+ fixedBits: 0x25207810,
+ args: PNd_T,
+ },
+ },
+ // PPUNPKHI
+ {
+ // PPUNPKHI <Pn>.B, <Pd>.H
+ {
+ goOp: APPUNPKHI,
+ fixedBits: 0x5314000,
+ args: Pn_B__Pd_H,
+ },
+ },
+ // PPUNPKLO
+ {
+ // PPUNPKLO <Pn>.B, <Pd>.H
+ {
+ goOp: APPUNPKLO,
+ fixedBits: 0x5304000,
+ args: Pn_B__Pd_H,
+ },
+ },
+ // PRDFFR
+ {
+ // PRDFFR <Pd>.B
+ {
+ goOp: APRDFFR,
+ fixedBits: 0x2519f000,
+ args: Pd_B,
+ },
+ // PRDFFR <Pg>/Z, <Pd>.B
+ {
+ goOp: APRDFFR,
+ fixedBits: 0x2518f000,
+ args: PgZ__Pd_B,
+ },
+ },
+ // PRDFFRS
+ {
+ // PRDFFRS <Pg>/Z, <Pd>.B
+ {
+ goOp: APRDFFRS,
+ fixedBits: 0x2558f000,
+ args: PgZ__Pd_B,
+ },
+ },
+ // PREV
+ {
+ // PREV <Pn>.<T>, <Pd>.<T>
+ {
+ goOp: APREV,
+ fixedBits: 0x5344000,
+ args: Pn_T__Pd_T,
+ },
+ },
+ // PSEL
+ {
+ // PSEL <Pm>.B, <Pn>.B, <Pg>, <Pd>.B
+ {
+ goOp: APSEL,
+ fixedBits: 0x25004210,
+ args: Pm_B__Pn_B__Pg__Pd_B,
+ },
+ },
+ // PTRN1
+ {
+ // PTRN1 <Pm>.<T>, <Pn>.<T>, <Pd>.<T>
+ {
+ goOp: APTRN1,
+ fixedBits: 0x5205000,
+ args: Pm_T__Pn_T__Pd_T,
+ },
+ },
+ // PTRN2
+ {
+ // PTRN2 <Pm>.<T>, <Pn>.<T>, <Pd>.<T>
+ {
+ goOp: APTRN2,
+ fixedBits: 0x5205400,
+ args: Pm_T__Pn_T__Pd_T,
+ },
+ },
+ // PUZP1
+ {
+ // PUZP1 <Pm>.<T>, <Pn>.<T>, <Pd>.<T>
+ {
+ goOp: APUZP1,
+ fixedBits: 0x5204800,
+ args: Pm_T__Pn_T__Pd_T,
+ },
+ },
+ // PUZP2
+ {
+ // PUZP2 <Pm>.<T>, <Pn>.<T>, <Pd>.<T>
+ {
+ goOp: APUZP2,
+ fixedBits: 0x5204c00,
+ args: Pm_T__Pn_T__Pd_T,
+ },
+ },
+ // PWRFFR
+ {
+ // PWRFFR <Pn>.B
+ {
+ goOp: APWRFFR,
+ fixedBits: 0x25289000,
+ args: Pn_B,
+ },
+ },
+ // PZIP1
+ {
+ // PZIP1 <Pm>.<T>, <Pn>.<T>, <Pd>.<T>
+ {
+ goOp: APZIP1,
+ fixedBits: 0x5204000,
+ args: Pm_T__Pn_T__Pd_T,
+ },
+ },
+ // PZIP2
+ {
+ // PZIP2 <Pm>.<T>, <Pn>.<T>, <Pd>.<T>
+ {
+ goOp: APZIP2,
+ fixedBits: 0x5204400,
+ args: Pm_T__Pn_T__Pd_T,
+ },
+ },
+ // SETFFR
+ {
+ // SETFFR
+ {
+ goOp: ASETFFR,
+ fixedBits: 0x252c9000,
+ args: oc,
+ },
+ },
+ // ZABS
+ {
+ // ZABS <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZABS,
+ fixedBits: 0x416a000,
+ args: Zn_T__PgM__Zd_T__2,
+ },
+ // ZABS <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZABS,
+ fixedBits: 0x406a000,
+ args: Zn_T__PgZ__Zd_T__2,
+ },
+ },
+ // ZADCLB
+ {
+ // ZADCLB <Zm>.<T>, <Zn>.<T>, <Zda>.<T>
+ {
+ goOp: AZADCLB,
+ fixedBits: 0x4500d000,
+ args: Zm_T__Zn_T__Zda_T__1,
+ },
+ },
+ // ZADCLT
+ {
+ // ZADCLT <Zm>.<T>, <Zn>.<T>, <Zda>.<T>
+ {
+ goOp: AZADCLT,
+ fixedBits: 0x4500d400,
+ args: Zm_T__Zn_T__Zda_T__1,
+ },
+ },
+ // ZADD
+ {
+ // ZADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZADD,
+ fixedBits: 0x4000000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ // ZADD <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZADD,
+ fixedBits: 0x4200000,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ },
+ // ZADDHNB
+ {
+ // ZADDHNB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZADDHNB,
+ fixedBits: 0x45206000,
+ args: Zm_Tb__Zn_Tb__Zd_T__2,
+ },
+ },
+ // ZADDHNT
+ {
+ // ZADDHNT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZADDHNT,
+ fixedBits: 0x45206400,
+ args: Zm_Tb__Zn_Tb__Zd_T__2,
+ },
+ },
+ // ZADDP
+ {
+ // ZADDP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZADDP,
+ fixedBits: 0x4411a000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZADDPT
+ {
+ // ZADDPT <Zm>.D, <Zdn>.D, <Pg>/M, <Zdn>.D
+ {
+ goOp: AZADDPT,
+ fixedBits: 0x4c40000,
+ args: Zm_D__Zdn_D__PgM__Zdn_D,
+ },
+ // ZADDPT <Zm>.D, <Zn>.D, <Zd>.D
+ {
+ goOp: AZADDPT,
+ fixedBits: 0x4e00800,
+ args: Zm_D__Zn_D__Zd_D,
+ },
+ },
+ // ZADDQP
+ {
+ // ZADDQP <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZADDQP,
+ fixedBits: 0x4207800,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ },
+ // ZADDQV
+ {
+ // ZADDQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
+ {
+ goOp: AZADDQV,
+ fixedBits: 0x4052000,
+ args: Zn_Tb__Pg__Vd_T__1,
+ },
+ },
+ // ZADDSUBP
+ {
+ // ZADDSUBP <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZADDSUBP,
+ fixedBits: 0x4207c00,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ },
+ // ZAESD
+ {
+ // ZAESD <Zm>.B, <Zdn>.B, <Zdn>.B
+ {
+ goOp: AZAESD,
+ fixedBits: 0x4522e400,
+ args: Zm_B__Zdn_B__Zdn_B,
+ },
+ },
+ // ZAESE
+ {
+ // ZAESE <Zm>.B, <Zdn>.B, <Zdn>.B
+ {
+ goOp: AZAESE,
+ fixedBits: 0x4522e000,
+ args: Zm_B__Zdn_B__Zdn_B,
+ },
+ },
+ // ZAESIMC
+ {
+ // ZAESIMC <Zdn>.B, <Zdn>.B
+ {
+ goOp: AZAESIMC,
+ fixedBits: 0x4520e400,
+ args: Zdn_B__Zdn_B,
+ },
+ },
+ // ZAESMC
+ {
+ // ZAESMC <Zdn>.B, <Zdn>.B
+ {
+ goOp: AZAESMC,
+ fixedBits: 0x4520e000,
+ args: Zdn_B__Zdn_B,
+ },
+ },
+ // ZAND
+ {
+ // ZAND <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZAND,
+ fixedBits: 0x41a0000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ // ZAND <Zm>.D, <Zn>.D, <Zd>.D
+ {
+ goOp: AZAND,
+ fixedBits: 0x4203000,
+ args: Zm_D__Zn_D__Zd_D,
+ },
+ },
+ // ZANDQV
+ {
+ // ZANDQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
+ {
+ goOp: AZANDQV,
+ fixedBits: 0x41e2000,
+ args: Zn_Tb__Pg__Vd_T__1,
+ },
+ },
+ // ZASR
+ {
+ // ZASR <Zm>.D, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZASR,
+ fixedBits: 0x4188000,
+ args: Zm_D__Zdn_T__PgM__Zdn_T,
+ },
+ // ZASR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZASR,
+ fixedBits: 0x4108000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ // ZASR <Zm>.D, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZASR,
+ fixedBits: 0x4208000,
+ args: Zm_D__Zn_T__Zd_T,
+ },
+ },
+ // ZASRR
+ {
+ // ZASRR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZASRR,
+ fixedBits: 0x4148000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZBCAX
+ {
+ // ZBCAX <Zk>.D, <Zm>.D, <Zdn>.D, <Zdn>.D
+ {
+ goOp: AZBCAX,
+ fixedBits: 0x4603800,
+ args: Zk_D__Zm_D__Zdn_D__Zdn_D,
+ },
+ },
+ // ZBDEP
+ {
+ // ZBDEP <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZBDEP,
+ fixedBits: 0x4500b400,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ },
+ // ZBEXT
+ {
+ // ZBEXT <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZBEXT,
+ fixedBits: 0x4500b000,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ },
+ // ZBF1CVT
+ {
+ // ZBF1CVT <Zn>.B, <Zd>.H
+ {
+ goOp: AZBF1CVT,
+ fixedBits: 0x65083800,
+ args: Zn_B__Zd_H,
+ },
+ },
+ // ZBF1CVTLT
+ {
+ // ZBF1CVTLT <Zn>.B, <Zd>.H
+ {
+ goOp: AZBF1CVTLT,
+ fixedBits: 0x65093800,
+ args: Zn_B__Zd_H,
+ },
+ },
+ // ZBF2CVT
+ {
+ // ZBF2CVT <Zn>.B, <Zd>.H
+ {
+ goOp: AZBF2CVT,
+ fixedBits: 0x65083c00,
+ args: Zn_B__Zd_H,
+ },
+ },
+ // ZBF2CVTLT
+ {
+ // ZBF2CVTLT <Zn>.B, <Zd>.H
+ {
+ goOp: AZBF2CVTLT,
+ fixedBits: 0x65093c00,
+ args: Zn_B__Zd_H,
+ },
+ },
+ // ZBFADD
+ {
+ // ZBFADD <Zm>.H, <Zdn>.H, <Pg>/M, <Zdn>.H
+ {
+ goOp: AZBFADD,
+ fixedBits: 0x65008000,
+ args: Zm_H__Zdn_H__PgM__Zdn_H,
+ },
+ // ZBFADD <Zm>.H, <Zn>.H, <Zd>.H
+ {
+ goOp: AZBFADD,
+ fixedBits: 0x65000000,
+ args: Zm_H__Zn_H__Zd_H,
+ },
+ },
+ // ZBFCLAMP
+ {
+ // ZBFCLAMP <Zm>.H, <Zn>.H, <Zd>.H
+ {
+ goOp: AZBFCLAMP,
+ fixedBits: 0x64202400,
+ args: Zm_H__Zn_H__Zd_H,
+ },
+ },
+ // ZBFCVT
+ {
+ // ZBFCVT <Zn>.S, <Pg>/Z, <Zd>.H
+ {
+ goOp: AZBFCVT,
+ fixedBits: 0x649ac000,
+ args: Zn_S__PgZ__Zd_H,
+ },
+ // ZBFCVT <Zn>.S, <Pg>/M, <Zd>.H
+ {
+ goOp: AZBFCVT,
+ fixedBits: 0x658aa000,
+ args: Zn_S__PgM__Zd_H,
+ },
+ },
+ // ZBFCVTNT
+ {
+ // ZBFCVTNT <Zn>.S, <Pg>/M, <Zd>.H
+ {
+ goOp: AZBFCVTNT,
+ fixedBits: 0x648aa000,
+ args: Zn_S__PgM__Zd_H,
+ },
+ // ZBFCVTNT <Zn>.S, <Pg>/Z, <Zd>.H
+ {
+ goOp: AZBFCVTNT,
+ fixedBits: 0x6482a000,
+ args: Zn_S__PgZ__Zd_H,
+ },
+ },
+ // ZBFDOT
+ {
+ // ZBFDOT <Zm>.H, <Zn>.H, <Zda>.S
+ {
+ goOp: AZBFDOT,
+ fixedBits: 0x64608000,
+ args: Zm_H__Zn_H__Zda_S,
+ },
+ },
+ // ZBFMAX
+ {
+ // ZBFMAX <Zm>.H, <Zdn>.H, <Pg>/M, <Zdn>.H
+ {
+ goOp: AZBFMAX,
+ fixedBits: 0x65068000,
+ args: Zm_H__Zdn_H__PgM__Zdn_H,
+ },
+ },
+ // ZBFMAXNM
+ {
+ // ZBFMAXNM <Zm>.H, <Zdn>.H, <Pg>/M, <Zdn>.H
+ {
+ goOp: AZBFMAXNM,
+ fixedBits: 0x65048000,
+ args: Zm_H__Zdn_H__PgM__Zdn_H,
+ },
+ },
+ // ZBFMIN
+ {
+ // ZBFMIN <Zm>.H, <Zdn>.H, <Pg>/M, <Zdn>.H
+ {
+ goOp: AZBFMIN,
+ fixedBits: 0x65078000,
+ args: Zm_H__Zdn_H__PgM__Zdn_H,
+ },
+ },
+ // ZBFMINNM
+ {
+ // ZBFMINNM <Zm>.H, <Zdn>.H, <Pg>/M, <Zdn>.H
+ {
+ goOp: AZBFMINNM,
+ fixedBits: 0x65058000,
+ args: Zm_H__Zdn_H__PgM__Zdn_H,
+ },
+ },
+ // ZBFMLA
+ {
+ // ZBFMLA <Zm>.H, <Zn>.H, <Pg>/M, <Zda>.H
+ {
+ goOp: AZBFMLA,
+ fixedBits: 0x65200000,
+ args: Zm_H__Zn_H__PgM__Zda_H,
+ },
+ },
+ // ZBFMLALB
+ {
+ // ZBFMLALB <Zm>.H, <Zn>.H, <Zda>.S
+ {
+ goOp: AZBFMLALB,
+ fixedBits: 0x64e08000,
+ args: Zm_H__Zn_H__Zda_S,
+ },
+ },
+ // ZBFMLALT
+ {
+ // ZBFMLALT <Zm>.H, <Zn>.H, <Zda>.S
+ {
+ goOp: AZBFMLALT,
+ fixedBits: 0x64e08400,
+ args: Zm_H__Zn_H__Zda_S,
+ },
+ },
+ // ZBFMLS
+ {
+ // ZBFMLS <Zm>.H, <Zn>.H, <Pg>/M, <Zda>.H
+ {
+ goOp: AZBFMLS,
+ fixedBits: 0x65202000,
+ args: Zm_H__Zn_H__PgM__Zda_H,
+ },
+ },
+ // ZBFMLSLB
+ {
+ // ZBFMLSLB <Zm>.H, <Zn>.H, <Zda>.S
+ {
+ goOp: AZBFMLSLB,
+ fixedBits: 0x64e0a000,
+ args: Zm_H__Zn_H__Zda_S,
+ },
+ },
+ // ZBFMLSLT
+ {
+ // ZBFMLSLT <Zm>.H, <Zn>.H, <Zda>.S
+ {
+ goOp: AZBFMLSLT,
+ fixedBits: 0x64e0a400,
+ args: Zm_H__Zn_H__Zda_S,
+ },
+ },
+ // ZBFMMLA
+ {
+ // ZBFMMLA <Zm>.H, <Zn>.H, <Zda>.H
+ {
+ goOp: AZBFMMLA,
+ fixedBits: 0x64e0e000,
+ args: Zm_H__Zn_H__Zda_H,
+ },
+ // ZBFMMLA <Zm>.H, <Zn>.H, <Zda>.S
+ {
+ goOp: AZBFMMLA,
+ fixedBits: 0x6460e400,
+ args: Zm_H__Zn_H__Zda_S,
+ },
+ },
+ // ZBFMUL
+ {
+ // ZBFMUL <Zm>.H, <Zdn>.H, <Pg>/M, <Zdn>.H
+ {
+ goOp: AZBFMUL,
+ fixedBits: 0x65028000,
+ args: Zm_H__Zdn_H__PgM__Zdn_H,
+ },
+ // ZBFMUL <Zm>.H, <Zn>.H, <Zd>.H
+ {
+ goOp: AZBFMUL,
+ fixedBits: 0x65000800,
+ args: Zm_H__Zn_H__Zd_H,
+ },
+ },
+ // ZBFSCALE
+ {
+ // ZBFSCALE <Zm>.H, <Zdn>.H, <Pg>/M, <Zdn>.H
+ {
+ goOp: AZBFSCALE,
+ fixedBits: 0x65098000,
+ args: Zm_H__Zdn_H__PgM__Zdn_H,
+ },
+ },
+ // ZBFSUB
+ {
+ // ZBFSUB <Zm>.H, <Zn>.H, <Zd>.H
+ {
+ goOp: AZBFSUB,
+ fixedBits: 0x65000400,
+ args: Zm_H__Zn_H__Zd_H,
+ },
+ // ZBFSUB <Zm>.H, <Zdn>.H, <Pg>/M, <Zdn>.H
+ {
+ goOp: AZBFSUB,
+ fixedBits: 0x65018000,
+ args: Zm_H__Zdn_H__PgM__Zdn_H,
+ },
+ },
+ // ZBGRP
+ {
+ // ZBGRP <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZBGRP,
+ fixedBits: 0x4500b800,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ },
+ // ZBIC
+ {
+ // ZBIC <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZBIC,
+ fixedBits: 0x41b0000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ // ZBIC <Zm>.D, <Zn>.D, <Zd>.D
+ {
+ goOp: AZBIC,
+ fixedBits: 0x4e03000,
+ args: Zm_D__Zn_D__Zd_D,
+ },
+ },
+ // ZBSL
+ {
+ // ZBSL <Zk>.D, <Zm>.D, <Zdn>.D, <Zdn>.D
+ {
+ goOp: AZBSL,
+ fixedBits: 0x4203c00,
+ args: Zk_D__Zm_D__Zdn_D__Zdn_D,
+ },
+ },
+ // ZBSL1N
+ {
+ // ZBSL1N <Zk>.D, <Zm>.D, <Zdn>.D, <Zdn>.D
+ {
+ goOp: AZBSL1N,
+ fixedBits: 0x4603c00,
+ args: Zk_D__Zm_D__Zdn_D__Zdn_D,
+ },
+ },
+ // ZBSL2N
+ {
+ // ZBSL2N <Zk>.D, <Zm>.D, <Zdn>.D, <Zdn>.D
+ {
+ goOp: AZBSL2N,
+ fixedBits: 0x4a03c00,
+ args: Zk_D__Zm_D__Zdn_D__Zdn_D,
+ },
+ },
+ // ZCLASTA
+ {
+ // ZCLASTA <Zm>.<T>, <Zdn>.<T>, <Pg>, <Zdn>.<T>
+ {
+ goOp: AZCLASTA,
+ fixedBits: 0x5288000,
+ args: Zm_T__Zdn_T__Pg__Zdn_T,
+ },
+ },
+ // ZCLASTB
+ {
+ // ZCLASTB <Zm>.<T>, <Zdn>.<T>, <Pg>, <Zdn>.<T>
+ {
+ goOp: AZCLASTB,
+ fixedBits: 0x5298000,
+ args: Zm_T__Zdn_T__Pg__Zdn_T,
+ },
+ },
+ // ZCLS
+ {
+ // ZCLS <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZCLS,
+ fixedBits: 0x408a000,
+ args: Zn_T__PgZ__Zd_T__2,
+ },
+ // ZCLS <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZCLS,
+ fixedBits: 0x418a000,
+ args: Zn_T__PgM__Zd_T__2,
+ },
+ },
+ // ZCLZ
+ {
+ // ZCLZ <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZCLZ,
+ fixedBits: 0x409a000,
+ args: Zn_T__PgZ__Zd_T__2,
+ },
+ // ZCLZ <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZCLZ,
+ fixedBits: 0x419a000,
+ args: Zn_T__PgM__Zd_T__2,
+ },
+ },
+ // ZCMPEQ
+ {
+ // ZCMPEQ <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZCMPEQ,
+ fixedBits: 0x2400a000,
+ args: Zm_T__Zn_T__PgZ__Pd_T__2,
+ },
+ // ZCMPEQ <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZCMPEQ,
+ fixedBits: 0x24002000,
+ args: Zm_D__Zn_T__PgZ__Pd_T,
+ },
+ },
+ // ZCMPGE
+ {
+ // ZCMPGE <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZCMPGE,
+ fixedBits: 0x24008000,
+ args: Zm_T__Zn_T__PgZ__Pd_T__2,
+ },
+ // ZCMPGE <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZCMPGE,
+ fixedBits: 0x24004000,
+ args: Zm_D__Zn_T__PgZ__Pd_T,
+ },
+ },
+ // ZCMPGT
+ {
+ // ZCMPGT <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZCMPGT,
+ fixedBits: 0x24008010,
+ args: Zm_T__Zn_T__PgZ__Pd_T__2,
+ },
+ // ZCMPGT <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZCMPGT,
+ fixedBits: 0x24004010,
+ args: Zm_D__Zn_T__PgZ__Pd_T,
+ },
+ },
+ // ZCMPHI
+ {
+ // ZCMPHI <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZCMPHI,
+ fixedBits: 0x2400c010,
+ args: Zm_D__Zn_T__PgZ__Pd_T,
+ },
+ // ZCMPHI <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZCMPHI,
+ fixedBits: 0x24000010,
+ args: Zm_T__Zn_T__PgZ__Pd_T__2,
+ },
+ },
+ // ZCMPHS
+ {
+ // ZCMPHS <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZCMPHS,
+ fixedBits: 0x24000000,
+ args: Zm_T__Zn_T__PgZ__Pd_T__2,
+ },
+ // ZCMPHS <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZCMPHS,
+ fixedBits: 0x2400c000,
+ args: Zm_D__Zn_T__PgZ__Pd_T,
+ },
+ },
+ // ZCMPLE
+ {
+ // ZCMPLE <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZCMPLE,
+ fixedBits: 0x24006010,
+ args: Zm_D__Zn_T__PgZ__Pd_T,
+ },
+ },
+ // ZCMPLO
+ {
+ // ZCMPLO <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZCMPLO,
+ fixedBits: 0x2400e000,
+ args: Zm_D__Zn_T__PgZ__Pd_T,
+ },
+ },
+ // ZCMPLS
+ {
+ // ZCMPLS <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZCMPLS,
+ fixedBits: 0x2400e010,
+ args: Zm_D__Zn_T__PgZ__Pd_T,
+ },
+ },
+ // ZCMPLT
+ {
+ // ZCMPLT <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZCMPLT,
+ fixedBits: 0x24006000,
+ args: Zm_D__Zn_T__PgZ__Pd_T,
+ },
+ },
+ // ZCMPNE
+ {
+ // ZCMPNE <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZCMPNE,
+ fixedBits: 0x24002010,
+ args: Zm_D__Zn_T__PgZ__Pd_T,
+ },
+ // ZCMPNE <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZCMPNE,
+ fixedBits: 0x2400a010,
+ args: Zm_T__Zn_T__PgZ__Pd_T__2,
+ },
+ },
+ // ZCNOT
+ {
+ // ZCNOT <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZCNOT,
+ fixedBits: 0x41ba000,
+ args: Zn_T__PgM__Zd_T__2,
+ },
+ // ZCNOT <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZCNOT,
+ fixedBits: 0x40ba000,
+ args: Zn_T__PgZ__Zd_T__2,
+ },
+ },
+ // ZCNT
+ {
+ // ZCNT <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZCNT,
+ fixedBits: 0x41aa000,
+ args: Zn_T__PgM__Zd_T__2,
+ },
+ // ZCNT <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZCNT,
+ fixedBits: 0x40aa000,
+ args: Zn_T__PgZ__Zd_T__2,
+ },
+ },
+ // ZCOMPACT
+ {
+ // ZCOMPACT <Zn>.<T>, <Pg>, <Zd>.<T>
+ {
+ goOp: AZCOMPACT,
+ fixedBits: 0x5218000,
+ args: Zn_T__Pg__Zd_T__1,
+ },
+ // ZCOMPACT <Zn>.<T>, <Pg>, <Zd>.<T>
+ {
+ goOp: AZCOMPACT,
+ fixedBits: 0x5a18000,
+ args: Zn_T__Pg__Zd_T__2,
+ },
+ },
+ // ZDECP
+ {
+ // ZDECP <Pm>.<T>, <Zdn>.<T>
+ {
+ goOp: AZDECP,
+ fixedBits: 0x252d8000,
+ args: Pm_T__Zdn_T,
+ },
+ },
+ // ZEOR
+ {
+ // ZEOR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZEOR,
+ fixedBits: 0x4190000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ // ZEOR <Zm>.D, <Zn>.D, <Zd>.D
+ {
+ goOp: AZEOR,
+ fixedBits: 0x4a03000,
+ args: Zm_D__Zn_D__Zd_D,
+ },
+ },
+ // ZEOR3
+ {
+ // ZEOR3 <Zk>.D, <Zm>.D, <Zdn>.D, <Zdn>.D
+ {
+ goOp: AZEOR3,
+ fixedBits: 0x4203800,
+ args: Zk_D__Zm_D__Zdn_D__Zdn_D,
+ },
+ },
+ // ZEORBT
+ {
+ // ZEORBT <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZEORBT,
+ fixedBits: 0x45009000,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ },
+ // ZEORQV
+ {
+ // ZEORQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
+ {
+ goOp: AZEORQV,
+ fixedBits: 0x41d2000,
+ args: Zn_Tb__Pg__Vd_T__1,
+ },
+ },
+ // ZEORTB
+ {
+ // ZEORTB <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZEORTB,
+ fixedBits: 0x45009400,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ },
+ // ZEXPAND
+ {
+ // ZEXPAND <Zn>.<T>, <Pg>, <Zd>.<T>
+ {
+ goOp: AZEXPAND,
+ fixedBits: 0x5318000,
+ args: Zn_T__Pg__Zd_T__3,
+ },
+ },
+ // ZF1CVT
+ {
+ // ZF1CVT <Zn>.B, <Zd>.H
+ {
+ goOp: AZF1CVT,
+ fixedBits: 0x65083000,
+ args: Zn_B__Zd_H,
+ },
+ },
+ // ZF1CVTLT
+ {
+ // ZF1CVTLT <Zn>.B, <Zd>.H
+ {
+ goOp: AZF1CVTLT,
+ fixedBits: 0x65093000,
+ args: Zn_B__Zd_H,
+ },
+ },
+ // ZF2CVT
+ {
+ // ZF2CVT <Zn>.B, <Zd>.H
+ {
+ goOp: AZF2CVT,
+ fixedBits: 0x65083400,
+ args: Zn_B__Zd_H,
+ },
+ },
+ // ZF2CVTLT
+ {
+ // ZF2CVTLT <Zn>.B, <Zd>.H
+ {
+ goOp: AZF2CVTLT,
+ fixedBits: 0x65093400,
+ args: Zn_B__Zd_H,
+ },
+ },
+ // ZFABD
+ {
+ // ZFABD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZFABD,
+ fixedBits: 0x65088000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__2,
+ },
+ },
+ // ZFABS
+ {
+ // ZFABS <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZFABS,
+ fixedBits: 0x40ca000,
+ args: Zn_T__PgZ__Zd_T__1,
+ },
+ // ZFABS <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZFABS,
+ fixedBits: 0x41ca000,
+ args: Zn_T__PgM__Zd_T__1,
+ },
+ },
+ // ZFACGE
+ {
+ // ZFACGE <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZFACGE,
+ fixedBits: 0x6500c010,
+ args: Zm_T__Zn_T__PgZ__Pd_T__1,
+ },
+ },
+ // ZFACGT
+ {
+ // ZFACGT <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZFACGT,
+ fixedBits: 0x6500e010,
+ args: Zm_T__Zn_T__PgZ__Pd_T__1,
+ },
+ },
+ // ZFADD
+ {
+ // ZFADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZFADD,
+ fixedBits: 0x65008000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__3,
+ },
+ // ZFADD <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZFADD,
+ fixedBits: 0x65000000,
+ args: Zm_T__Zn_T__Zd_T__2,
+ },
+ },
+ // ZFADDP
+ {
+ // ZFADDP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZFADDP,
+ fixedBits: 0x64108000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__2,
+ },
+ },
+ // ZFADDQV
+ {
+ // ZFADDQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
+ {
+ goOp: AZFADDQV,
+ fixedBits: 0x6410a000,
+ args: Zn_Tb__Pg__Vd_T__2,
+ },
+ },
+ // ZFAMAX
+ {
+ // ZFAMAX <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZFAMAX,
+ fixedBits: 0x650e8000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__2,
+ },
+ },
+ // ZFAMIN
+ {
+ // ZFAMIN <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZFAMIN,
+ fixedBits: 0x650f8000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__2,
+ },
+ },
+ // ZFCLAMP
+ {
+ // ZFCLAMP <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZFCLAMP,
+ fixedBits: 0x64202400,
+ args: Zm_T__Zn_T__Zd_T__2,
+ },
+ },
+ // ZFCMEQ
+ {
+ // ZFCMEQ <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZFCMEQ,
+ fixedBits: 0x65006000,
+ args: Zm_T__Zn_T__PgZ__Pd_T__1,
+ },
+ },
+ // ZFCMGE
+ {
+ // ZFCMGE <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZFCMGE,
+ fixedBits: 0x65004000,
+ args: Zm_T__Zn_T__PgZ__Pd_T__1,
+ },
+ },
+ // ZFCMGT
+ {
+ // ZFCMGT <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZFCMGT,
+ fixedBits: 0x65004010,
+ args: Zm_T__Zn_T__PgZ__Pd_T__1,
+ },
+ },
+ // ZFCMNE
+ {
+ // ZFCMNE <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZFCMNE,
+ fixedBits: 0x65006010,
+ args: Zm_T__Zn_T__PgZ__Pd_T__1,
+ },
+ },
+ // ZFCMUO
+ {
+ // ZFCMUO <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZFCMUO,
+ fixedBits: 0x6500c000,
+ args: Zm_T__Zn_T__PgZ__Pd_T__1,
+ },
+ },
+ // ZFCVT
+ {
+ // ZFCVT <Zn>.H, <Pg>/M, <Zd>.S
+ {
+ goOp: AZFCVT,
+ fixedBits: 0x6589a000,
+ args: Zn_H__PgM__Zd_S,
+ },
+ // ZFCVT <Zn>.S, <Pg>/M, <Zd>.D
+ {
+ goOp: AZFCVT,
+ fixedBits: 0x65cba000,
+ args: Zn_S__PgM__Zd_D,
+ },
+ // ZFCVT <Zn>.H, <Pg>/Z, <Zd>.S
+ {
+ goOp: AZFCVT,
+ fixedBits: 0x649aa000,
+ args: Zn_H__PgZ__Zd_S,
+ },
+ // ZFCVT <Zn>.H, <Pg>/M, <Zd>.D
+ {
+ goOp: AZFCVT,
+ fixedBits: 0x65c9a000,
+ args: Zn_H__PgM__Zd_D,
+ },
+ // ZFCVT <Zn>.H, <Pg>/Z, <Zd>.D
+ {
+ goOp: AZFCVT,
+ fixedBits: 0x64daa000,
+ args: Zn_H__PgZ__Zd_D,
+ },
+ // ZFCVT <Zn>.S, <Pg>/M, <Zd>.H
+ {
+ goOp: AZFCVT,
+ fixedBits: 0x6588a000,
+ args: Zn_S__PgM__Zd_H,
+ },
+ // ZFCVT <Zn>.S, <Pg>/Z, <Zd>.H
+ {
+ goOp: AZFCVT,
+ fixedBits: 0x649a8000,
+ args: Zn_S__PgZ__Zd_H,
+ },
+ // ZFCVT <Zn>.S, <Pg>/Z, <Zd>.D
+ {
+ goOp: AZFCVT,
+ fixedBits: 0x64dae000,
+ args: Zn_S__PgZ__Zd_D,
+ },
+ // ZFCVT <Zn>.D, <Pg>/M, <Zd>.H
+ {
+ goOp: AZFCVT,
+ fixedBits: 0x65c8a000,
+ args: Zn_D__PgM__Zd_H,
+ },
+ // ZFCVT <Zn>.D, <Pg>/Z, <Zd>.H
+ {
+ goOp: AZFCVT,
+ fixedBits: 0x64da8000,
+ args: Zn_D__PgZ__Zd_H,
+ },
+ // ZFCVT <Zn>.D, <Pg>/M, <Zd>.S
+ {
+ goOp: AZFCVT,
+ fixedBits: 0x65caa000,
+ args: Zn_D__PgM__Zd_S,
+ },
+ // ZFCVT <Zn>.D, <Pg>/Z, <Zd>.S
+ {
+ goOp: AZFCVT,
+ fixedBits: 0x64dac000,
+ args: Zn_D__PgZ__Zd_S,
+ },
+ },
+ // ZFCVTLT
+ {
+ // ZFCVTLT <Zn>.H, <Pg>/M, <Zd>.S
+ {
+ goOp: AZFCVTLT,
+ fixedBits: 0x6489a000,
+ args: Zn_H__PgM__Zd_S,
+ },
+ // ZFCVTLT <Zn>.H, <Pg>/Z, <Zd>.S
+ {
+ goOp: AZFCVTLT,
+ fixedBits: 0x6481a000,
+ args: Zn_H__PgZ__Zd_S,
+ },
+ // ZFCVTLT <Zn>.S, <Pg>/M, <Zd>.D
+ {
+ goOp: AZFCVTLT,
+ fixedBits: 0x64cba000,
+ args: Zn_S__PgM__Zd_D,
+ },
+ // ZFCVTLT <Zn>.S, <Pg>/Z, <Zd>.D
+ {
+ goOp: AZFCVTLT,
+ fixedBits: 0x64c3a000,
+ args: Zn_S__PgZ__Zd_D,
+ },
+ },
+ // ZFCVTNT
+ {
+ // ZFCVTNT <Zn>.S, <Pg>/M, <Zd>.H
+ {
+ goOp: AZFCVTNT,
+ fixedBits: 0x6488a000,
+ args: Zn_S__PgM__Zd_H,
+ },
+ // ZFCVTNT <Zn>.S, <Pg>/Z, <Zd>.H
+ {
+ goOp: AZFCVTNT,
+ fixedBits: 0x6480a000,
+ args: Zn_S__PgZ__Zd_H,
+ },
+ // ZFCVTNT <Zn>.D, <Pg>/M, <Zd>.S
+ {
+ goOp: AZFCVTNT,
+ fixedBits: 0x64caa000,
+ args: Zn_D__PgM__Zd_S,
+ },
+ // ZFCVTNT <Zn>.D, <Pg>/Z, <Zd>.S
+ {
+ goOp: AZFCVTNT,
+ fixedBits: 0x64c2a000,
+ args: Zn_D__PgZ__Zd_S,
+ },
+ },
+ // ZFCVTX
+ {
+ // ZFCVTX <Zn>.D, <Pg>/Z, <Zd>.S
+ {
+ goOp: AZFCVTX,
+ fixedBits: 0x641ac000,
+ args: Zn_D__PgZ__Zd_S,
+ },
+ // ZFCVTX <Zn>.D, <Pg>/M, <Zd>.S
+ {
+ goOp: AZFCVTX,
+ fixedBits: 0x650aa000,
+ args: Zn_D__PgM__Zd_S,
+ },
+ },
+ // ZFCVTXNT
+ {
+ // ZFCVTXNT <Zn>.D, <Pg>/M, <Zd>.S
+ {
+ goOp: AZFCVTXNT,
+ fixedBits: 0x640aa000,
+ args: Zn_D__PgM__Zd_S,
+ },
+ // ZFCVTXNT <Zn>.D, <Pg>/Z, <Zd>.S
+ {
+ goOp: AZFCVTXNT,
+ fixedBits: 0x6402a000,
+ args: Zn_D__PgZ__Zd_S,
+ },
+ },
+ // ZFCVTZS
+ {
+ // ZFCVTZS <Zn>.H, <Pg>/M, <Zd>.H
+ {
+ goOp: AZFCVTZS,
+ fixedBits: 0x655aa000,
+ args: Zn_H__PgM__Zd_H,
+ },
+ // ZFCVTZS <Zn>.H, <Pg>/Z, <Zd>.H
+ {
+ goOp: AZFCVTZS,
+ fixedBits: 0x645ec000,
+ args: Zn_H__PgZ__Zd_H,
+ },
+ // ZFCVTZS <Zn>.H, <Pg>/M, <Zd>.S
+ {
+ goOp: AZFCVTZS,
+ fixedBits: 0x655ca000,
+ args: Zn_H__PgM__Zd_S,
+ },
+ // ZFCVTZS <Zn>.H, <Pg>/Z, <Zd>.S
+ {
+ goOp: AZFCVTZS,
+ fixedBits: 0x645f8000,
+ args: Zn_H__PgZ__Zd_S,
+ },
+ // ZFCVTZS <Zn>.H, <Pg>/M, <Zd>.D
+ {
+ goOp: AZFCVTZS,
+ fixedBits: 0x655ea000,
+ args: Zn_H__PgM__Zd_D,
+ },
+ // ZFCVTZS <Zn>.H, <Pg>/Z, <Zd>.D
+ {
+ goOp: AZFCVTZS,
+ fixedBits: 0x645fc000,
+ args: Zn_H__PgZ__Zd_D,
+ },
+ // ZFCVTZS <Zn>.S, <Pg>/M, <Zd>.S
+ {
+ goOp: AZFCVTZS,
+ fixedBits: 0x659ca000,
+ args: Zn_S__PgM__Zd_S,
+ },
+ // ZFCVTZS <Zn>.S, <Pg>/Z, <Zd>.S
+ {
+ goOp: AZFCVTZS,
+ fixedBits: 0x649f8000,
+ args: Zn_S__PgZ__Zd_S,
+ },
+ // ZFCVTZS <Zn>.S, <Pg>/M, <Zd>.D
+ {
+ goOp: AZFCVTZS,
+ fixedBits: 0x65dca000,
+ args: Zn_S__PgM__Zd_D,
+ },
+ // ZFCVTZS <Zn>.S, <Pg>/Z, <Zd>.D
+ {
+ goOp: AZFCVTZS,
+ fixedBits: 0x64df8000,
+ args: Zn_S__PgZ__Zd_D,
+ },
+ // ZFCVTZS <Zn>.D, <Pg>/M, <Zd>.S
+ {
+ goOp: AZFCVTZS,
+ fixedBits: 0x65d8a000,
+ args: Zn_D__PgM__Zd_S,
+ },
+ // ZFCVTZS <Zn>.D, <Pg>/Z, <Zd>.S
+ {
+ goOp: AZFCVTZS,
+ fixedBits: 0x64de8000,
+ args: Zn_D__PgZ__Zd_S,
+ },
+ // ZFCVTZS <Zn>.D, <Pg>/M, <Zd>.D
+ {
+ goOp: AZFCVTZS,
+ fixedBits: 0x65dea000,
+ args: Zn_D__PgM__Zd_D,
+ },
+ // ZFCVTZS <Zn>.D, <Pg>/Z, <Zd>.D
+ {
+ goOp: AZFCVTZS,
+ fixedBits: 0x64dfc000,
+ args: Zn_D__PgZ__Zd_D,
+ },
+ },
+ // ZFCVTZU
+ {
+ // ZFCVTZU <Zn>.D, <Pg>/Z, <Zd>.S
+ {
+ goOp: AZFCVTZU,
+ fixedBits: 0x64dea000,
+ args: Zn_D__PgZ__Zd_S,
+ },
+ // ZFCVTZU <Zn>.H, <Pg>/M, <Zd>.D
+ {
+ goOp: AZFCVTZU,
+ fixedBits: 0x655fa000,
+ args: Zn_H__PgM__Zd_D,
+ },
+ // ZFCVTZU <Zn>.H, <Pg>/M, <Zd>.H
+ {
+ goOp: AZFCVTZU,
+ fixedBits: 0x655ba000,
+ args: Zn_H__PgM__Zd_H,
+ },
+ // ZFCVTZU <Zn>.H, <Pg>/Z, <Zd>.H
+ {
+ goOp: AZFCVTZU,
+ fixedBits: 0x645ee000,
+ args: Zn_H__PgZ__Zd_H,
+ },
+ // ZFCVTZU <Zn>.D, <Pg>/Z, <Zd>.D
+ {
+ goOp: AZFCVTZU,
+ fixedBits: 0x64dfe000,
+ args: Zn_D__PgZ__Zd_D,
+ },
+ // ZFCVTZU <Zn>.H, <Pg>/M, <Zd>.S
+ {
+ goOp: AZFCVTZU,
+ fixedBits: 0x655da000,
+ args: Zn_H__PgM__Zd_S,
+ },
+ // ZFCVTZU <Zn>.H, <Pg>/Z, <Zd>.S
+ {
+ goOp: AZFCVTZU,
+ fixedBits: 0x645fa000,
+ args: Zn_H__PgZ__Zd_S,
+ },
+ // ZFCVTZU <Zn>.H, <Pg>/Z, <Zd>.D
+ {
+ goOp: AZFCVTZU,
+ fixedBits: 0x645fe000,
+ args: Zn_H__PgZ__Zd_D,
+ },
+ // ZFCVTZU <Zn>.D, <Pg>/M, <Zd>.D
+ {
+ goOp: AZFCVTZU,
+ fixedBits: 0x65dfa000,
+ args: Zn_D__PgM__Zd_D,
+ },
+ // ZFCVTZU <Zn>.S, <Pg>/M, <Zd>.S
+ {
+ goOp: AZFCVTZU,
+ fixedBits: 0x659da000,
+ args: Zn_S__PgM__Zd_S,
+ },
+ // ZFCVTZU <Zn>.D, <Pg>/M, <Zd>.S
+ {
+ goOp: AZFCVTZU,
+ fixedBits: 0x65d9a000,
+ args: Zn_D__PgM__Zd_S,
+ },
+ // ZFCVTZU <Zn>.S, <Pg>/Z, <Zd>.D
+ {
+ goOp: AZFCVTZU,
+ fixedBits: 0x64dfa000,
+ args: Zn_S__PgZ__Zd_D,
+ },
+ // ZFCVTZU <Zn>.S, <Pg>/M, <Zd>.D
+ {
+ goOp: AZFCVTZU,
+ fixedBits: 0x65dda000,
+ args: Zn_S__PgM__Zd_D,
+ },
+ // ZFCVTZU <Zn>.S, <Pg>/Z, <Zd>.S
+ {
+ goOp: AZFCVTZU,
+ fixedBits: 0x649fa000,
+ args: Zn_S__PgZ__Zd_S,
+ },
+ },
+ // ZFDIV
+ {
+ // ZFDIV <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZFDIV,
+ fixedBits: 0x650d8000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__2,
+ },
+ },
+ // ZFDIVR
+ {
+ // ZFDIVR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZFDIVR,
+ fixedBits: 0x650c8000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__2,
+ },
+ },
+ // ZFDOT
+ {
+ // ZFDOT <Zm>.B, <Zn>.B, <Zda>.S
+ {
+ goOp: AZFDOT,
+ fixedBits: 0x64608400,
+ args: Zm_B__Zn_B__Zda_S,
+ },
+ // ZFDOT <Zm>.B, <Zn>.B, <Zda>.H
+ {
+ goOp: AZFDOT,
+ fixedBits: 0x64208400,
+ args: Zm_B__Zn_B__Zda_H,
+ },
+ // ZFDOT <Zm>.H, <Zn>.H, <Zda>.S
+ {
+ goOp: AZFDOT,
+ fixedBits: 0x64208000,
+ args: Zm_H__Zn_H__Zda_S,
+ },
+ },
+ // ZFEXPA
+ {
+ // ZFEXPA <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZFEXPA,
+ fixedBits: 0x420b800,
+ args: Zn_T__Zd_T__1,
+ },
+ },
+ // ZFLOGB
+ {
+ // ZFLOGB <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZFLOGB,
+ fixedBits: 0x6518a000,
+ args: Zn_T__PgM__Zd_T__6,
+ },
+ // ZFLOGB <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZFLOGB,
+ fixedBits: 0x641e8000,
+ args: Zn_T__PgZ__Zd_T__6,
+ },
+ },
+ // ZFMAD
+ {
+ // ZFMAD <Za>.<T>, <Zm>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZFMAD,
+ fixedBits: 0x65208000,
+ args: Za_T__Zm_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZFMAX
+ {
+ // ZFMAX <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZFMAX,
+ fixedBits: 0x65068000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__3,
+ },
+ },
+ // ZFMAXNM
+ {
+ // ZFMAXNM <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZFMAXNM,
+ fixedBits: 0x65048000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__3,
+ },
+ },
+ // ZFMAXNMP
+ {
+ // ZFMAXNMP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZFMAXNMP,
+ fixedBits: 0x64148000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__2,
+ },
+ },
+ // ZFMAXNMQV
+ {
+ // ZFMAXNMQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
+ {
+ goOp: AZFMAXNMQV,
+ fixedBits: 0x6414a000,
+ args: Zn_Tb__Pg__Vd_T__2,
+ },
+ },
+ // ZFMAXP
+ {
+ // ZFMAXP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZFMAXP,
+ fixedBits: 0x64168000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__2,
+ },
+ },
+ // ZFMAXQV
+ {
+ // ZFMAXQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
+ {
+ goOp: AZFMAXQV,
+ fixedBits: 0x6416a000,
+ args: Zn_Tb__Pg__Vd_T__2,
+ },
+ },
+ // ZFMIN
+ {
+ // ZFMIN <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZFMIN,
+ fixedBits: 0x65078000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__3,
+ },
+ },
+ // ZFMINNM
+ {
+ // ZFMINNM <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZFMINNM,
+ fixedBits: 0x65058000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__3,
+ },
+ },
+ // ZFMINNMP
+ {
+ // ZFMINNMP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZFMINNMP,
+ fixedBits: 0x64158000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__2,
+ },
+ },
+ // ZFMINNMQV
+ {
+ // ZFMINNMQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
+ {
+ goOp: AZFMINNMQV,
+ fixedBits: 0x6415a000,
+ args: Zn_Tb__Pg__Vd_T__2,
+ },
+ },
+ // ZFMINP
+ {
+ // ZFMINP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZFMINP,
+ fixedBits: 0x64178000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__2,
+ },
+ },
+ // ZFMINQV
+ {
+ // ZFMINQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
+ {
+ goOp: AZFMINQV,
+ fixedBits: 0x6417a000,
+ args: Zn_Tb__Pg__Vd_T__2,
+ },
+ },
+ // ZFMLA
+ {
+ // ZFMLA <Zm>.<T>, <Zn>.<T>, <Pg>/M, <Zda>.<T>
+ {
+ goOp: AZFMLA,
+ fixedBits: 0x65200000,
+ args: Zm_T__Zn_T__PgM__Zda_T__1,
+ },
+ },
+ // ZFMLALB
+ {
+ // ZFMLALB <Zm>.H, <Zn>.H, <Zda>.S
+ {
+ goOp: AZFMLALB,
+ fixedBits: 0x64a08000,
+ args: Zm_H__Zn_H__Zda_S,
+ },
+ // ZFMLALB <Zm>.B, <Zn>.B, <Zda>.H
+ {
+ goOp: AZFMLALB,
+ fixedBits: 0x64a08800,
+ args: Zm_B__Zn_B__Zda_H,
+ },
+ },
+ // ZFMLALLBB
+ {
+ // ZFMLALLBB <Zm>.B, <Zn>.B, <Zda>.S
+ {
+ goOp: AZFMLALLBB,
+ fixedBits: 0x64208800,
+ args: Zm_B__Zn_B__Zda_S,
+ },
+ },
+ // ZFMLALLBT
+ {
+ // ZFMLALLBT <Zm>.B, <Zn>.B, <Zda>.S
+ {
+ goOp: AZFMLALLBT,
+ fixedBits: 0x64209800,
+ args: Zm_B__Zn_B__Zda_S,
+ },
+ },
+ // ZFMLALLTB
+ {
+ // ZFMLALLTB <Zm>.B, <Zn>.B, <Zda>.S
+ {
+ goOp: AZFMLALLTB,
+ fixedBits: 0x6420a800,
+ args: Zm_B__Zn_B__Zda_S,
+ },
+ },
+ // ZFMLALLTT
+ {
+ // ZFMLALLTT <Zm>.B, <Zn>.B, <Zda>.S
+ {
+ goOp: AZFMLALLTT,
+ fixedBits: 0x6420b800,
+ args: Zm_B__Zn_B__Zda_S,
+ },
+ },
+ // ZFMLALT
+ {
+ // ZFMLALT <Zm>.B, <Zn>.B, <Zda>.H
+ {
+ goOp: AZFMLALT,
+ fixedBits: 0x64a09800,
+ args: Zm_B__Zn_B__Zda_H,
+ },
+ // ZFMLALT <Zm>.H, <Zn>.H, <Zda>.S
+ {
+ goOp: AZFMLALT,
+ fixedBits: 0x64a08400,
+ args: Zm_H__Zn_H__Zda_S,
+ },
+ },
+ // ZFMLS
+ {
+ // ZFMLS <Zm>.<T>, <Zn>.<T>, <Pg>/M, <Zda>.<T>
+ {
+ goOp: AZFMLS,
+ fixedBits: 0x65202000,
+ args: Zm_T__Zn_T__PgM__Zda_T__1,
+ },
+ },
+ // ZFMLSLB
+ {
+ // ZFMLSLB <Zm>.H, <Zn>.H, <Zda>.S
+ {
+ goOp: AZFMLSLB,
+ fixedBits: 0x64a0a000,
+ args: Zm_H__Zn_H__Zda_S,
+ },
+ },
+ // ZFMLSLT
+ {
+ // ZFMLSLT <Zm>.H, <Zn>.H, <Zda>.S
+ {
+ goOp: AZFMLSLT,
+ fixedBits: 0x64a0a400,
+ args: Zm_H__Zn_H__Zda_S,
+ },
+ },
+ // ZFMMLA
+ {
+ // ZFMMLA <Zm>.H, <Zn>.H, <Zda>.H
+ {
+ goOp: AZFMMLA,
+ fixedBits: 0x64a0e000,
+ args: Zm_H__Zn_H__Zda_H,
+ },
+ // ZFMMLA <Zm>.S, <Zn>.S, <Zda>.S
+ {
+ goOp: AZFMMLA,
+ fixedBits: 0x64a0e400,
+ args: Zm_S__Zn_S__Zda_S,
+ },
+ // ZFMMLA <Zm>.D, <Zn>.D, <Zda>.D
+ {
+ goOp: AZFMMLA,
+ fixedBits: 0x64e0e400,
+ args: Zm_D__Zn_D__Zda_D,
+ },
+ // ZFMMLA <Zm>.H, <Zn>.H, <Zda>.S
+ {
+ goOp: AZFMMLA,
+ fixedBits: 0x6420e400,
+ args: Zm_H__Zn_H__Zda_S,
+ },
+ // ZFMMLA <Zm>.B, <Zn>.B, <Zda>.H
+ {
+ goOp: AZFMMLA,
+ fixedBits: 0x6460e000,
+ args: Zm_B__Zn_B__Zda_H,
+ },
+ // ZFMMLA <Zm>.B, <Zn>.B, <Zda>.S
+ {
+ goOp: AZFMMLA,
+ fixedBits: 0x6420e000,
+ args: Zm_B__Zn_B__Zda_S,
+ },
+ },
+ // ZFMSB
+ {
+ // ZFMSB <Za>.<T>, <Zm>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZFMSB,
+ fixedBits: 0x6520a000,
+ args: Za_T__Zm_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZFMUL
+ {
+ // ZFMUL <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZFMUL,
+ fixedBits: 0x65000800,
+ args: Zm_T__Zn_T__Zd_T__2,
+ },
+ // ZFMUL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZFMUL,
+ fixedBits: 0x65028000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__3,
+ },
+ },
+ // ZFMULX
+ {
+ // ZFMULX <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZFMULX,
+ fixedBits: 0x650a8000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__2,
+ },
+ },
+ // ZFNEG
+ {
+ // ZFNEG <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZFNEG,
+ fixedBits: 0x41da000,
+ args: Zn_T__PgM__Zd_T__1,
+ },
+ // ZFNEG <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZFNEG,
+ fixedBits: 0x40da000,
+ args: Zn_T__PgZ__Zd_T__1,
+ },
+ },
+ // ZFNMAD
+ {
+ // ZFNMAD <Za>.<T>, <Zm>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZFNMAD,
+ fixedBits: 0x6520c000,
+ args: Za_T__Zm_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZFNMLA
+ {
+ // ZFNMLA <Zm>.<T>, <Zn>.<T>, <Pg>/M, <Zda>.<T>
+ {
+ goOp: AZFNMLA,
+ fixedBits: 0x65204000,
+ args: Zm_T__Zn_T__PgM__Zda_T__1,
+ },
+ },
+ // ZFNMLS
+ {
+ // ZFNMLS <Zm>.<T>, <Zn>.<T>, <Pg>/M, <Zda>.<T>
+ {
+ goOp: AZFNMLS,
+ fixedBits: 0x65206000,
+ args: Zm_T__Zn_T__PgM__Zda_T__1,
+ },
+ },
+ // ZFNMSB
+ {
+ // ZFNMSB <Za>.<T>, <Zm>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZFNMSB,
+ fixedBits: 0x6520e000,
+ args: Za_T__Zm_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZFRECPE
+ {
+ // ZFRECPE <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZFRECPE,
+ fixedBits: 0x650e3000,
+ args: Zn_T__Zd_T__1,
+ },
+ },
+ // ZFRECPS
+ {
+ // ZFRECPS <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZFRECPS,
+ fixedBits: 0x65001800,
+ args: Zm_T__Zn_T__Zd_T__3,
+ },
+ },
+ // ZFRECPX
+ {
+ // ZFRECPX <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZFRECPX,
+ fixedBits: 0x650ca000,
+ args: Zn_T__PgM__Zd_T__1,
+ },
+ // ZFRECPX <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZFRECPX,
+ fixedBits: 0x641b8000,
+ args: Zn_T__PgZ__Zd_T__1,
+ },
+ },
+ // ZFRINT32X
+ {
+ // ZFRINT32X <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZFRINT32X,
+ fixedBits: 0x6511a000,
+ args: Zn_T__PgM__Zd_T__3,
+ },
+ // ZFRINT32X <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZFRINT32X,
+ fixedBits: 0x641ca000,
+ args: Zn_T__PgZ__Zd_T__3,
+ },
+ },
+ // ZFRINT32Z
+ {
+ // ZFRINT32Z <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZFRINT32Z,
+ fixedBits: 0x641c8000,
+ args: Zn_T__PgZ__Zd_T__3,
+ },
+ // ZFRINT32Z <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZFRINT32Z,
+ fixedBits: 0x6510a000,
+ args: Zn_T__PgM__Zd_T__3,
+ },
+ },
+ // ZFRINT64X
+ {
+ // ZFRINT64X <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZFRINT64X,
+ fixedBits: 0x641da000,
+ args: Zn_T__PgZ__Zd_T__3,
+ },
+ // ZFRINT64X <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZFRINT64X,
+ fixedBits: 0x6515a000,
+ args: Zn_T__PgM__Zd_T__3,
+ },
+ },
+ // ZFRINT64Z
+ {
+ // ZFRINT64Z <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZFRINT64Z,
+ fixedBits: 0x6514a000,
+ args: Zn_T__PgM__Zd_T__3,
+ },
+ // ZFRINT64Z <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZFRINT64Z,
+ fixedBits: 0x641d8000,
+ args: Zn_T__PgZ__Zd_T__3,
+ },
+ },
+ // ZFRINTA
+ {
+ // ZFRINTA <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZFRINTA,
+ fixedBits: 0x6504a000,
+ args: Zn_T__PgM__Zd_T__1,
+ },
+ // ZFRINTA <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZFRINTA,
+ fixedBits: 0x64198000,
+ args: Zn_T__PgZ__Zd_T__1,
+ },
+ },
+ // ZFRINTI
+ {
+ // ZFRINTI <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZFRINTI,
+ fixedBits: 0x6419e000,
+ args: Zn_T__PgZ__Zd_T__1,
+ },
+ // ZFRINTI <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZFRINTI,
+ fixedBits: 0x6507a000,
+ args: Zn_T__PgM__Zd_T__1,
+ },
+ },
+ // ZFRINTM
+ {
+ // ZFRINTM <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZFRINTM,
+ fixedBits: 0x6418c000,
+ args: Zn_T__PgZ__Zd_T__1,
+ },
+ // ZFRINTM <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZFRINTM,
+ fixedBits: 0x6502a000,
+ args: Zn_T__PgM__Zd_T__1,
+ },
+ },
+ // ZFRINTN
+ {
+ // ZFRINTN <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZFRINTN,
+ fixedBits: 0x6500a000,
+ args: Zn_T__PgM__Zd_T__1,
+ },
+ // ZFRINTN <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZFRINTN,
+ fixedBits: 0x64188000,
+ args: Zn_T__PgZ__Zd_T__1,
+ },
+ },
+ // ZFRINTP
+ {
+ // ZFRINTP <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZFRINTP,
+ fixedBits: 0x6501a000,
+ args: Zn_T__PgM__Zd_T__1,
+ },
+ // ZFRINTP <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZFRINTP,
+ fixedBits: 0x6418a000,
+ args: Zn_T__PgZ__Zd_T__1,
+ },
+ },
+ // ZFRINTX
+ {
+ // ZFRINTX <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZFRINTX,
+ fixedBits: 0x6419c000,
+ args: Zn_T__PgZ__Zd_T__1,
+ },
+ // ZFRINTX <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZFRINTX,
+ fixedBits: 0x6506a000,
+ args: Zn_T__PgM__Zd_T__1,
+ },
+ },
+ // ZFRINTZ
+ {
+ // ZFRINTZ <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZFRINTZ,
+ fixedBits: 0x6503a000,
+ args: Zn_T__PgM__Zd_T__1,
+ },
+ // ZFRINTZ <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZFRINTZ,
+ fixedBits: 0x6418e000,
+ args: Zn_T__PgZ__Zd_T__1,
+ },
+ },
+ // ZFRSQRTE
+ {
+ // ZFRSQRTE <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZFRSQRTE,
+ fixedBits: 0x650f3000,
+ args: Zn_T__Zd_T__1,
+ },
+ },
+ // ZFRSQRTS
+ {
+ // ZFRSQRTS <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZFRSQRTS,
+ fixedBits: 0x65001c00,
+ args: Zm_T__Zn_T__Zd_T__3,
+ },
+ },
+ // ZFSCALE
+ {
+ // ZFSCALE <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZFSCALE,
+ fixedBits: 0x65098000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__3,
+ },
+ },
+ // ZFSQRT
+ {
+ // ZFSQRT <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZFSQRT,
+ fixedBits: 0x641ba000,
+ args: Zn_T__PgZ__Zd_T__1,
+ },
+ // ZFSQRT <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZFSQRT,
+ fixedBits: 0x650da000,
+ args: Zn_T__PgM__Zd_T__1,
+ },
+ },
+ // ZFSUB
+ {
+ // ZFSUB <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZFSUB,
+ fixedBits: 0x65000400,
+ args: Zm_T__Zn_T__Zd_T__2,
+ },
+ // ZFSUB <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZFSUB,
+ fixedBits: 0x65018000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__3,
+ },
+ },
+ // ZFSUBR
+ {
+ // ZFSUBR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZFSUBR,
+ fixedBits: 0x65038000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__2,
+ },
+ },
+ // ZFTSMUL
+ {
+ // ZFTSMUL <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZFTSMUL,
+ fixedBits: 0x65000c00,
+ args: Zm_T__Zn_T__Zd_T__3,
+ },
+ },
+ // ZFTSSEL
+ {
+ // ZFTSSEL <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZFTSSEL,
+ fixedBits: 0x420b000,
+ args: Zm_T__Zn_T__Zd_T__3,
+ },
+ },
+ // ZHISTCNT
+ {
+ // ZHISTCNT <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZHISTCNT,
+ fixedBits: 0x45a0c000,
+ args: Zm_T__Zn_T__PgZ__Zd_T,
+ },
+ },
+ // ZHISTSEG
+ {
+ // ZHISTSEG <Zm>.B, <Zn>.B, <Zd>.B
+ {
+ goOp: AZHISTSEG,
+ fixedBits: 0x4520a000,
+ args: Zm_B__Zn_B__Zd_B,
+ },
+ },
+ // ZINCP
+ {
+ // ZINCP <Pm>.<T>, <Zdn>.<T>
+ {
+ goOp: AZINCP,
+ fixedBits: 0x252c8000,
+ args: Pm_T__Zdn_T,
+ },
+ },
+ // ZLSL
+ {
+ // ZLSL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZLSL,
+ fixedBits: 0x4138000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ // ZLSL <Zm>.D, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZLSL,
+ fixedBits: 0x41b8000,
+ args: Zm_D__Zdn_T__PgM__Zdn_T,
+ },
+ // ZLSL <Zm>.D, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZLSL,
+ fixedBits: 0x4208c00,
+ args: Zm_D__Zn_T__Zd_T,
+ },
+ },
+ // ZLSLR
+ {
+ // ZLSLR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZLSLR,
+ fixedBits: 0x4178000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZLSR
+ {
+ // ZLSR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZLSR,
+ fixedBits: 0x4118000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ // ZLSR <Zm>.D, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZLSR,
+ fixedBits: 0x4208400,
+ args: Zm_D__Zn_T__Zd_T,
+ },
+ // ZLSR <Zm>.D, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZLSR,
+ fixedBits: 0x4198000,
+ args: Zm_D__Zdn_T__PgM__Zdn_T,
+ },
+ },
+ // ZLSRR
+ {
+ // ZLSRR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZLSRR,
+ fixedBits: 0x4158000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZMAD
+ {
+ // ZMAD <Za>.<T>, <Zm>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZMAD,
+ fixedBits: 0x400c000,
+ args: Za_T__Zm_T__PgM__Zdn_T__2,
+ },
+ },
+ // ZMADPT
+ {
+ // ZMADPT <Za>.D, <Zm>.D, <Zdn>.D
+ {
+ goOp: AZMADPT,
+ fixedBits: 0x44c0d800,
+ args: Za_D__Zm_D__Zdn_D,
+ },
+ },
+ // ZMATCH
+ {
+ // ZMATCH <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZMATCH,
+ fixedBits: 0x45208000,
+ args: Zm_T__Zn_T__PgZ__Pd_T__3,
+ },
+ },
+ // ZMLA
+ {
+ // ZMLA <Zm>.<T>, <Zn>.<T>, <Pg>/M, <Zda>.<T>
+ {
+ goOp: AZMLA,
+ fixedBits: 0x4004000,
+ args: Zm_T__Zn_T__PgM__Zda_T__2,
+ },
+ },
+ // ZMLAPT
+ {
+ // ZMLAPT <Zm>.D, <Zn>.D, <Zda>.D
+ {
+ goOp: AZMLAPT,
+ fixedBits: 0x44c0d000,
+ args: Zm_D__Zn_D__Zda_D,
+ },
+ },
+ // ZMLS
+ {
+ // ZMLS <Zm>.<T>, <Zn>.<T>, <Pg>/M, <Zda>.<T>
+ {
+ goOp: AZMLS,
+ fixedBits: 0x4006000,
+ args: Zm_T__Zn_T__PgM__Zda_T__2,
+ },
+ },
+ // ZMOVPRFX
+ {
+ // ZMOVPRFX <Zn>.<T>, <Pg>/<ZM>, <Zd>.<T>
+ {
+ goOp: AZMOVPRFX,
+ fixedBits: 0x4102000,
+ args: Zn_T__PgZM__Zd_T,
+ },
+ // ZMOVPRFX <Zn>, <Zd>
+ {
+ goOp: AZMOVPRFX,
+ fixedBits: 0x420bc00,
+ args: Zn__Zd,
+ },
+ },
+ // ZMSB
+ {
+ // ZMSB <Za>.<T>, <Zm>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZMSB,
+ fixedBits: 0x400e000,
+ args: Za_T__Zm_T__PgM__Zdn_T__2,
+ },
+ },
+ // ZMUL
+ {
+ // ZMUL <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZMUL,
+ fixedBits: 0x4206000,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ // ZMUL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZMUL,
+ fixedBits: 0x4100000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZNBSL
+ {
+ // ZNBSL <Zk>.D, <Zm>.D, <Zdn>.D, <Zdn>.D
+ {
+ goOp: AZNBSL,
+ fixedBits: 0x4e03c00,
+ args: Zk_D__Zm_D__Zdn_D__Zdn_D,
+ },
+ },
+ // ZNEG
+ {
+ // ZNEG <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZNEG,
+ fixedBits: 0x417a000,
+ args: Zn_T__PgM__Zd_T__2,
+ },
+ // ZNEG <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZNEG,
+ fixedBits: 0x407a000,
+ args: Zn_T__PgZ__Zd_T__2,
+ },
+ },
+ // ZNMATCH
+ {
+ // ZNMATCH <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
+ {
+ goOp: AZNMATCH,
+ fixedBits: 0x45208010,
+ args: Zm_T__Zn_T__PgZ__Pd_T__3,
+ },
+ },
+ // ZNOT
+ {
+ // ZNOT <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZNOT,
+ fixedBits: 0x41ea000,
+ args: Zn_T__PgM__Zd_T__2,
+ },
+ // ZNOT <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZNOT,
+ fixedBits: 0x40ea000,
+ args: Zn_T__PgZ__Zd_T__2,
+ },
+ },
+ // ZORQV
+ {
+ // ZORQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
+ {
+ goOp: AZORQV,
+ fixedBits: 0x41c2000,
+ args: Zn_Tb__Pg__Vd_T__1,
+ },
+ },
+ // ZORR
+ {
+ // ZORR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZORR,
+ fixedBits: 0x4180000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ // ZORR <Zm>.D, <Zn>.D, <Zd>.D
+ {
+ goOp: AZORR,
+ fixedBits: 0x4603000,
+ args: Zm_D__Zn_D__Zd_D,
+ },
+ },
+ // ZPMOV
+ {
+ // ZPMOV <Pn>.B, <Zd>
+ {
+ goOp: AZPMOV,
+ fixedBits: 0x52b3800,
+ args: Pn_B__Zd,
+ },
+ // ZPMOV <Zn>, <Pd>.B
+ {
+ goOp: AZPMOV,
+ fixedBits: 0x52a3800,
+ args: Zn__Pd_B,
+ },
+ },
+ // ZPMUL
+ {
+ // ZPMUL <Zm>.B, <Zn>.B, <Zd>.B
+ {
+ goOp: AZPMUL,
+ fixedBits: 0x4206400,
+ args: Zm_B__Zn_B__Zd_B,
+ },
+ },
+ // ZPMULLB
+ {
+ // ZPMULLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZPMULLB,
+ fixedBits: 0x45006800,
+ args: Zm_Tb__Zn_Tb__Zd_T__3,
+ },
+ // ZPMULLB <Zm>.D, <Zn>.D, <Zd>.Q
+ {
+ goOp: AZPMULLB,
+ fixedBits: 0x45006800,
+ args: Zm_D__Zn_D__Zd_Q,
+ },
+ },
+ // ZPMULLT
+ {
+ // ZPMULLT <Zm>.D, <Zn>.D, <Zd>.Q
+ {
+ goOp: AZPMULLT,
+ fixedBits: 0x45006c00,
+ args: Zm_D__Zn_D__Zd_Q,
+ },
+ // ZPMULLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZPMULLT,
+ fixedBits: 0x45006c00,
+ args: Zm_Tb__Zn_Tb__Zd_T__3,
+ },
+ },
+ // ZRADDHNB
+ {
+ // ZRADDHNB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZRADDHNB,
+ fixedBits: 0x45206800,
+ args: Zm_Tb__Zn_Tb__Zd_T__2,
+ },
+ },
+ // ZRADDHNT
+ {
+ // ZRADDHNT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZRADDHNT,
+ fixedBits: 0x45206c00,
+ args: Zm_Tb__Zn_Tb__Zd_T__2,
+ },
+ },
+ // ZRAX1
+ {
+ // ZRAX1 <Zm>.D, <Zn>.D, <Zd>.D
+ {
+ goOp: AZRAX1,
+ fixedBits: 0x4520f400,
+ args: Zm_D__Zn_D__Zd_D,
+ },
+ },
+ // ZRBIT
+ {
+ // ZRBIT <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZRBIT,
+ fixedBits: 0x527a000,
+ args: Zn_T__PgZ__Zd_T__2,
+ },
+ // ZRBIT <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZRBIT,
+ fixedBits: 0x5278000,
+ args: Zn_T__PgM__Zd_T__2,
+ },
+ },
+ // ZREV
+ {
+ // ZREV <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZREV,
+ fixedBits: 0x5383800,
+ args: Zn_T__Zd_T__2,
+ },
+ },
+ // ZREVB
+ {
+ // ZREVB <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZREVB,
+ fixedBits: 0x524a000,
+ args: Zn_T__PgZ__Zd_T__4,
+ },
+ // ZREVB <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZREVB,
+ fixedBits: 0x5248000,
+ args: Zn_T__PgM__Zd_T__4,
+ },
+ },
+ // ZREVD
+ {
+ // ZREVD <Zn>.Q, <Pg>/M, <Zd>.Q
+ {
+ goOp: AZREVD,
+ fixedBits: 0x52e8000,
+ args: Zn_Q__PgM__Zd_Q,
+ },
+ // ZREVD <Zn>.Q, <Pg>/Z, <Zd>.Q
+ {
+ goOp: AZREVD,
+ fixedBits: 0x52ea000,
+ args: Zn_Q__PgZ__Zd_Q,
+ },
+ },
+ // ZREVH
+ {
+ // ZREVH <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZREVH,
+ fixedBits: 0x5a5a000,
+ args: Zn_T__PgZ__Zd_T__5,
+ },
+ // ZREVH <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZREVH,
+ fixedBits: 0x5a58000,
+ args: Zn_T__PgM__Zd_T__5,
+ },
+ },
+ // ZREVW
+ {
+ // ZREVW <Zn>.D, <Pg>/Z, <Zd>.D
+ {
+ goOp: AZREVW,
+ fixedBits: 0x5e6a000,
+ args: Zn_D__PgZ__Zd_D,
+ },
+ // ZREVW <Zn>.D, <Pg>/M, <Zd>.D
+ {
+ goOp: AZREVW,
+ fixedBits: 0x5e68000,
+ args: Zn_D__PgM__Zd_D,
+ },
+ },
+ // ZRSUBHNB
+ {
+ // ZRSUBHNB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZRSUBHNB,
+ fixedBits: 0x45207800,
+ args: Zm_Tb__Zn_Tb__Zd_T__2,
+ },
+ },
+ // ZRSUBHNT
+ {
+ // ZRSUBHNT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZRSUBHNT,
+ fixedBits: 0x45207c00,
+ args: Zm_Tb__Zn_Tb__Zd_T__2,
+ },
+ },
+ // ZSABA
+ {
+ // ZSABA <Zm>.<T>, <Zn>.<T>, <Zda>.<T>
+ {
+ goOp: AZSABA,
+ fixedBits: 0x4500f800,
+ args: Zm_T__Zn_T__Zda_T__2,
+ },
+ },
+ // ZSABAL
+ {
+ // ZSABAL <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
+ {
+ goOp: AZSABAL,
+ fixedBits: 0x4400d400,
+ args: Zm_Tb__Zn_Tb__Zda_T__1,
+ },
+ },
+ // ZSABALB
+ {
+ // ZSABALB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
+ {
+ goOp: AZSABALB,
+ fixedBits: 0x4500c000,
+ args: Zm_Tb__Zn_Tb__Zda_T__1,
+ },
+ },
+ // ZSABALT
+ {
+ // ZSABALT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
+ {
+ goOp: AZSABALT,
+ fixedBits: 0x4500c400,
+ args: Zm_Tb__Zn_Tb__Zda_T__1,
+ },
+ },
+ // ZSABD
+ {
+ // ZSABD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSABD,
+ fixedBits: 0x40c0000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZSABDLB
+ {
+ // ZSABDLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZSABDLB,
+ fixedBits: 0x45003000,
+ args: Zm_Tb__Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZSABDLT
+ {
+ // ZSABDLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZSABDLT,
+ fixedBits: 0x45003400,
+ args: Zm_Tb__Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZSADALP
+ {
+ // ZSADALP <Zn>.<Tb>, <Pg>/M, <Zda>.<T>
+ {
+ goOp: AZSADALP,
+ fixedBits: 0x4404a000,
+ args: Zn_Tb__PgM__Zda_T,
+ },
+ },
+ // ZSADDLB
+ {
+ // ZSADDLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZSADDLB,
+ fixedBits: 0x45000000,
+ args: Zm_Tb__Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZSADDLBT
+ {
+ // ZSADDLBT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZSADDLBT,
+ fixedBits: 0x45008000,
+ args: Zm_Tb__Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZSADDLT
+ {
+ // ZSADDLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZSADDLT,
+ fixedBits: 0x45000400,
+ args: Zm_Tb__Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZSADDWB
+ {
+ // ZSADDWB <Zm>.<Tb>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZSADDWB,
+ fixedBits: 0x45004000,
+ args: Zm_Tb__Zn_T__Zd_T,
+ },
+ },
+ // ZSADDWT
+ {
+ // ZSADDWT <Zm>.<Tb>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZSADDWT,
+ fixedBits: 0x45004400,
+ args: Zm_Tb__Zn_T__Zd_T,
+ },
+ },
+ // ZSBCLB
+ {
+ // ZSBCLB <Zm>.<T>, <Zn>.<T>, <Zda>.<T>
+ {
+ goOp: AZSBCLB,
+ fixedBits: 0x4580d000,
+ args: Zm_T__Zn_T__Zda_T__1,
+ },
+ },
+ // ZSBCLT
+ {
+ // ZSBCLT <Zm>.<T>, <Zn>.<T>, <Zda>.<T>
+ {
+ goOp: AZSBCLT,
+ fixedBits: 0x4580d400,
+ args: Zm_T__Zn_T__Zda_T__1,
+ },
+ },
+ // ZSCLAMP
+ {
+ // ZSCLAMP <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZSCLAMP,
+ fixedBits: 0x4400c000,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ },
+ // ZSCVTF
+ {
+ // ZSCVTF <Zn>.S, <Pg>/M, <Zd>.D
+ {
+ goOp: AZSCVTF,
+ fixedBits: 0x65d0a000,
+ args: Zn_S__PgM__Zd_D,
+ },
+ // ZSCVTF <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZSCVTF,
+ fixedBits: 0x650c3000,
+ args: Zn_Tb__Zd_T__1,
+ },
+ // ZSCVTF <Zn>.D, <Pg>/M, <Zd>.S
+ {
+ goOp: AZSCVTF,
+ fixedBits: 0x65d4a000,
+ args: Zn_D__PgM__Zd_S,
+ },
+ // ZSCVTF <Zn>.D, <Pg>/Z, <Zd>.S
+ {
+ goOp: AZSCVTF,
+ fixedBits: 0x64dd8000,
+ args: Zn_D__PgZ__Zd_S,
+ },
+ // ZSCVTF <Zn>.D, <Pg>/M, <Zd>.D
+ {
+ goOp: AZSCVTF,
+ fixedBits: 0x65d6a000,
+ args: Zn_D__PgM__Zd_D,
+ },
+ // ZSCVTF <Zn>.D, <Pg>/Z, <Zd>.D
+ {
+ goOp: AZSCVTF,
+ fixedBits: 0x64ddc000,
+ args: Zn_D__PgZ__Zd_D,
+ },
+ // ZSCVTF <Zn>.H, <Pg>/Z, <Zd>.H
+ {
+ goOp: AZSCVTF,
+ fixedBits: 0x645cc000,
+ args: Zn_H__PgZ__Zd_H,
+ },
+ // ZSCVTF <Zn>.S, <Pg>/M, <Zd>.H
+ {
+ goOp: AZSCVTF,
+ fixedBits: 0x6554a000,
+ args: Zn_S__PgM__Zd_H,
+ },
+ // ZSCVTF <Zn>.S, <Pg>/Z, <Zd>.H
+ {
+ goOp: AZSCVTF,
+ fixedBits: 0x645d8000,
+ args: Zn_S__PgZ__Zd_H,
+ },
+ // ZSCVTF <Zn>.D, <Pg>/Z, <Zd>.H
+ {
+ goOp: AZSCVTF,
+ fixedBits: 0x645dc000,
+ args: Zn_D__PgZ__Zd_H,
+ },
+ // ZSCVTF <Zn>.D, <Pg>/M, <Zd>.H
+ {
+ goOp: AZSCVTF,
+ fixedBits: 0x6556a000,
+ args: Zn_D__PgM__Zd_H,
+ },
+ // ZSCVTF <Zn>.S, <Pg>/Z, <Zd>.D
+ {
+ goOp: AZSCVTF,
+ fixedBits: 0x64dc8000,
+ args: Zn_S__PgZ__Zd_D,
+ },
+ // ZSCVTF <Zn>.H, <Pg>/M, <Zd>.H
+ {
+ goOp: AZSCVTF,
+ fixedBits: 0x6552a000,
+ args: Zn_H__PgM__Zd_H,
+ },
+ // ZSCVTF <Zn>.S, <Pg>/Z, <Zd>.S
+ {
+ goOp: AZSCVTF,
+ fixedBits: 0x649d8000,
+ args: Zn_S__PgZ__Zd_S,
+ },
+ // ZSCVTF <Zn>.S, <Pg>/M, <Zd>.S
+ {
+ goOp: AZSCVTF,
+ fixedBits: 0x6594a000,
+ args: Zn_S__PgM__Zd_S,
+ },
+ },
+ // ZSCVTFLT
+ {
+ // ZSCVTFLT <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZSCVTFLT,
+ fixedBits: 0x650c3800,
+ args: Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZSDIV
+ {
+ // ZSDIV <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSDIV,
+ fixedBits: 0x4940000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__4,
+ },
+ },
+ // ZSDIVR
+ {
+ // ZSDIVR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSDIVR,
+ fixedBits: 0x4960000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__4,
+ },
+ },
+ // ZSDOT
+ {
+ // ZSDOT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
+ {
+ goOp: AZSDOT,
+ fixedBits: 0x44800000,
+ args: Zm_Tb__Zn_Tb__Zda_T__2,
+ },
+ // ZSDOT <Zm>.H, <Zn>.H, <Zda>.S
+ {
+ goOp: AZSDOT,
+ fixedBits: 0x4400c800,
+ args: Zm_H__Zn_H__Zda_S,
+ },
+ // ZSDOT <Zm>.B, <Zn>.B, <Zda>.H
+ {
+ goOp: AZSDOT,
+ fixedBits: 0x44400000,
+ args: Zm_B__Zn_B__Zda_H,
+ },
+ },
+ // ZSEL
+ {
+ // ZSEL <Zm>.<T>, <Zn>.<T>, <Pv>, <Zd>.<T>
+ {
+ goOp: AZSEL,
+ fixedBits: 0x520c000,
+ args: Zm_T__Zn_T__Pv__Zd_T,
+ },
+ },
+ // ZSHADD
+ {
+ // ZSHADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSHADD,
+ fixedBits: 0x44108000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZSHSUB
+ {
+ // ZSHSUB <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSHSUB,
+ fixedBits: 0x44128000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZSHSUBR
+ {
+ // ZSHSUBR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSHSUBR,
+ fixedBits: 0x44168000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZSM4E
+ {
+ // ZSM4E <Zm>.S, <Zdn>.S, <Zdn>.S
+ {
+ goOp: AZSM4E,
+ fixedBits: 0x4523e000,
+ args: Zm_S__Zdn_S__Zdn_S,
+ },
+ },
+ // ZSM4EKEY
+ {
+ // ZSM4EKEY <Zm>.S, <Zn>.S, <Zd>.S
+ {
+ goOp: AZSM4EKEY,
+ fixedBits: 0x4520f000,
+ args: Zm_S__Zn_S__Zd_S,
+ },
+ },
+ // ZSMAX
+ {
+ // ZSMAX <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSMAX,
+ fixedBits: 0x4080000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZSMAXP
+ {
+ // ZSMAXP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSMAXP,
+ fixedBits: 0x4414a000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZSMAXQV
+ {
+ // ZSMAXQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
+ {
+ goOp: AZSMAXQV,
+ fixedBits: 0x40c2000,
+ args: Zn_Tb__Pg__Vd_T__1,
+ },
+ },
+ // ZSMIN
+ {
+ // ZSMIN <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSMIN,
+ fixedBits: 0x40a0000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZSMINP
+ {
+ // ZSMINP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSMINP,
+ fixedBits: 0x4416a000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZSMINQV
+ {
+ // ZSMINQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
+ {
+ goOp: AZSMINQV,
+ fixedBits: 0x40e2000,
+ args: Zn_Tb__Pg__Vd_T__1,
+ },
+ },
+ // ZSMLALB
+ {
+ // ZSMLALB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
+ {
+ goOp: AZSMLALB,
+ fixedBits: 0x44004000,
+ args: Zm_Tb__Zn_Tb__Zda_T__1,
+ },
+ },
+ // ZSMLALT
+ {
+ // ZSMLALT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
+ {
+ goOp: AZSMLALT,
+ fixedBits: 0x44004400,
+ args: Zm_Tb__Zn_Tb__Zda_T__1,
+ },
+ },
+ // ZSMLSLB
+ {
+ // ZSMLSLB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
+ {
+ goOp: AZSMLSLB,
+ fixedBits: 0x44005000,
+ args: Zm_Tb__Zn_Tb__Zda_T__1,
+ },
+ },
+ // ZSMLSLT
+ {
+ // ZSMLSLT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
+ {
+ goOp: AZSMLSLT,
+ fixedBits: 0x44005400,
+ args: Zm_Tb__Zn_Tb__Zda_T__1,
+ },
+ },
+ // ZSMMLA
+ {
+ // ZSMMLA <Zm>.B, <Zn>.B, <Zda>.S
+ {
+ goOp: AZSMMLA,
+ fixedBits: 0x45009800,
+ args: Zm_B__Zn_B__Zda_S,
+ },
+ },
+ // ZSMULH
+ {
+ // ZSMULH <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZSMULH,
+ fixedBits: 0x4206800,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ // ZSMULH <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSMULH,
+ fixedBits: 0x4120000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZSMULLB
+ {
+ // ZSMULLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZSMULLB,
+ fixedBits: 0x45007000,
+ args: Zm_Tb__Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZSMULLT
+ {
+ // ZSMULLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZSMULLT,
+ fixedBits: 0x45007400,
+ args: Zm_Tb__Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZSPLICE
+ {
+ // ZSPLICE <Zm>.<T>, <Zdn>.<T>, <Pv>, <Zdn>.<T>
+ {
+ goOp: AZSPLICE,
+ fixedBits: 0x52c8000,
+ args: Zm_T__Zdn_T__Pv__Zdn_T,
+ },
+ },
+ // ZSQABS
+ {
+ // ZSQABS <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZSQABS,
+ fixedBits: 0x4408a000,
+ args: Zn_T__PgM__Zd_T__2,
+ },
+ // ZSQABS <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZSQABS,
+ fixedBits: 0x440aa000,
+ args: Zn_T__PgZ__Zd_T__2,
+ },
+ },
+ // ZSQADD
+ {
+ // ZSQADD <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZSQADD,
+ fixedBits: 0x4201000,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ // ZSQADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSQADD,
+ fixedBits: 0x44188000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZSQDECP
+ {
+ // ZSQDECP <Pm>.<T>, <Zdn>.<T>
+ {
+ goOp: AZSQDECP,
+ fixedBits: 0x252a8000,
+ args: Pm_T__Zdn_T,
+ },
+ },
+ // ZSQDMLALB
+ {
+ // ZSQDMLALB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
+ {
+ goOp: AZSQDMLALB,
+ fixedBits: 0x44006000,
+ args: Zm_Tb__Zn_Tb__Zda_T__1,
+ },
+ },
+ // ZSQDMLALBT
+ {
+ // ZSQDMLALBT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
+ {
+ goOp: AZSQDMLALBT,
+ fixedBits: 0x44000800,
+ args: Zm_Tb__Zn_Tb__Zda_T__1,
+ },
+ },
+ // ZSQDMLALT
+ {
+ // ZSQDMLALT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
+ {
+ goOp: AZSQDMLALT,
+ fixedBits: 0x44006400,
+ args: Zm_Tb__Zn_Tb__Zda_T__1,
+ },
+ },
+ // ZSQDMLSLB
+ {
+ // ZSQDMLSLB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
+ {
+ goOp: AZSQDMLSLB,
+ fixedBits: 0x44006800,
+ args: Zm_Tb__Zn_Tb__Zda_T__1,
+ },
+ },
+ // ZSQDMLSLBT
+ {
+ // ZSQDMLSLBT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
+ {
+ goOp: AZSQDMLSLBT,
+ fixedBits: 0x44000c00,
+ args: Zm_Tb__Zn_Tb__Zda_T__1,
+ },
+ },
+ // ZSQDMLSLT
+ {
+ // ZSQDMLSLT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
+ {
+ goOp: AZSQDMLSLT,
+ fixedBits: 0x44006c00,
+ args: Zm_Tb__Zn_Tb__Zda_T__1,
+ },
+ },
+ // ZSQDMULH
+ {
+ // ZSQDMULH <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZSQDMULH,
+ fixedBits: 0x4207000,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ },
+ // ZSQDMULLB
+ {
+ // ZSQDMULLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZSQDMULLB,
+ fixedBits: 0x45006000,
+ args: Zm_Tb__Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZSQDMULLT
+ {
+ // ZSQDMULLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZSQDMULLT,
+ fixedBits: 0x45006400,
+ args: Zm_Tb__Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZSQINCP
+ {
+ // ZSQINCP <Pm>.<T>, <Zdn>.<T>
+ {
+ goOp: AZSQINCP,
+ fixedBits: 0x25288000,
+ args: Pm_T__Zdn_T,
+ },
+ },
+ // ZSQNEG
+ {
+ // ZSQNEG <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZSQNEG,
+ fixedBits: 0x4409a000,
+ args: Zn_T__PgM__Zd_T__2,
+ },
+ // ZSQNEG <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZSQNEG,
+ fixedBits: 0x440ba000,
+ args: Zn_T__PgZ__Zd_T__2,
+ },
+ },
+ // ZSQRDMLAH
+ {
+ // ZSQRDMLAH <Zm>.<T>, <Zn>.<T>, <Zda>.<T>
+ {
+ goOp: AZSQRDMLAH,
+ fixedBits: 0x44007000,
+ args: Zm_T__Zn_T__Zda_T__2,
+ },
+ },
+ // ZSQRDMLSH
+ {
+ // ZSQRDMLSH <Zm>.<T>, <Zn>.<T>, <Zda>.<T>
+ {
+ goOp: AZSQRDMLSH,
+ fixedBits: 0x44007400,
+ args: Zm_T__Zn_T__Zda_T__2,
+ },
+ },
+ // ZSQRDMULH
+ {
+ // ZSQRDMULH <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZSQRDMULH,
+ fixedBits: 0x4207400,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ },
+ // ZSQRSHL
+ {
+ // ZSQRSHL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSQRSHL,
+ fixedBits: 0x440a8000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZSQRSHLR
+ {
+ // ZSQRSHLR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSQRSHLR,
+ fixedBits: 0x440e8000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZSQSHL
+ {
+ // ZSQSHL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSQSHL,
+ fixedBits: 0x44088000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZSQSHLR
+ {
+ // ZSQSHLR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSQSHLR,
+ fixedBits: 0x440c8000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZSQSUB
+ {
+ // ZSQSUB <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZSQSUB,
+ fixedBits: 0x4201800,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ // ZSQSUB <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSQSUB,
+ fixedBits: 0x441a8000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZSQSUBR
+ {
+ // ZSQSUBR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSQSUBR,
+ fixedBits: 0x441e8000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZSQXTNB
+ {
+ // ZSQXTNB <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZSQXTNB,
+ fixedBits: 0x45204000,
+ args: Zn_Tb__Zd_T__2,
+ },
+ },
+ // ZSQXTNT
+ {
+ // ZSQXTNT <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZSQXTNT,
+ fixedBits: 0x45204400,
+ args: Zn_Tb__Zd_T__2,
+ },
+ },
+ // ZSQXTUNB
+ {
+ // ZSQXTUNB <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZSQXTUNB,
+ fixedBits: 0x45205000,
+ args: Zn_Tb__Zd_T__2,
+ },
+ },
+ // ZSQXTUNT
+ {
+ // ZSQXTUNT <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZSQXTUNT,
+ fixedBits: 0x45205400,
+ args: Zn_Tb__Zd_T__2,
+ },
+ },
+ // ZSRHADD
+ {
+ // ZSRHADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSRHADD,
+ fixedBits: 0x44148000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZSRSHL
+ {
+ // ZSRSHL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSRSHL,
+ fixedBits: 0x44028000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZSRSHLR
+ {
+ // ZSRSHLR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSRSHLR,
+ fixedBits: 0x44068000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZSSUBLB
+ {
+ // ZSSUBLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZSSUBLB,
+ fixedBits: 0x45001000,
+ args: Zm_Tb__Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZSSUBLBT
+ {
+ // ZSSUBLBT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZSSUBLBT,
+ fixedBits: 0x45008800,
+ args: Zm_Tb__Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZSSUBLT
+ {
+ // ZSSUBLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZSSUBLT,
+ fixedBits: 0x45001400,
+ args: Zm_Tb__Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZSSUBLTB
+ {
+ // ZSSUBLTB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZSSUBLTB,
+ fixedBits: 0x45008c00,
+ args: Zm_Tb__Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZSSUBWB
+ {
+ // ZSSUBWB <Zm>.<Tb>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZSSUBWB,
+ fixedBits: 0x45005000,
+ args: Zm_Tb__Zn_T__Zd_T,
+ },
+ },
+ // ZSSUBWT
+ {
+ // ZSSUBWT <Zm>.<Tb>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZSSUBWT,
+ fixedBits: 0x45005400,
+ args: Zm_Tb__Zn_T__Zd_T,
+ },
+ },
+ // ZSUB
+ {
+ // ZSUB <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZSUB,
+ fixedBits: 0x4200400,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ // ZSUB <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSUB,
+ fixedBits: 0x4010000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZSUBHNB
+ {
+ // ZSUBHNB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZSUBHNB,
+ fixedBits: 0x45207000,
+ args: Zm_Tb__Zn_Tb__Zd_T__2,
+ },
+ },
+ // ZSUBHNT
+ {
+ // ZSUBHNT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZSUBHNT,
+ fixedBits: 0x45207400,
+ args: Zm_Tb__Zn_Tb__Zd_T__2,
+ },
+ },
+ // ZSUBP
+ {
+ // ZSUBP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSUBP,
+ fixedBits: 0x4410a000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZSUBPT
+ {
+ // ZSUBPT <Zm>.D, <Zn>.D, <Zd>.D
+ {
+ goOp: AZSUBPT,
+ fixedBits: 0x4e00c00,
+ args: Zm_D__Zn_D__Zd_D,
+ },
+ // ZSUBPT <Zm>.D, <Zdn>.D, <Pg>/M, <Zdn>.D
+ {
+ goOp: AZSUBPT,
+ fixedBits: 0x4c50000,
+ args: Zm_D__Zdn_D__PgM__Zdn_D,
+ },
+ },
+ // ZSUBR
+ {
+ // ZSUBR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSUBR,
+ fixedBits: 0x4030000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZSUNPKHI
+ {
+ // ZSUNPKHI <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZSUNPKHI,
+ fixedBits: 0x5313800,
+ args: Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZSUNPKLO
+ {
+ // ZSUNPKLO <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZSUNPKLO,
+ fixedBits: 0x5303800,
+ args: Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZSUQADD
+ {
+ // ZSUQADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZSUQADD,
+ fixedBits: 0x441c8000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZSXTB
+ {
+ // ZSXTB <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZSXTB,
+ fixedBits: 0x400a000,
+ args: Zn_T__PgZ__Zd_T__4,
+ },
+ // ZSXTB <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZSXTB,
+ fixedBits: 0x410a000,
+ args: Zn_T__PgM__Zd_T__4,
+ },
+ },
+ // ZSXTH
+ {
+ // ZSXTH <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZSXTH,
+ fixedBits: 0x492a000,
+ args: Zn_T__PgM__Zd_T__5,
+ },
+ // ZSXTH <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZSXTH,
+ fixedBits: 0x482a000,
+ args: Zn_T__PgZ__Zd_T__5,
+ },
+ },
+ // ZSXTW
+ {
+ // ZSXTW <Zn>.D, <Pg>/M, <Zd>.D
+ {
+ goOp: AZSXTW,
+ fixedBits: 0x4d4a000,
+ args: Zn_D__PgM__Zd_D,
+ },
+ // ZSXTW <Zn>.D, <Pg>/Z, <Zd>.D
+ {
+ goOp: AZSXTW,
+ fixedBits: 0x4c4a000,
+ args: Zn_D__PgZ__Zd_D,
+ },
+ },
+ // ZTBX
+ {
+ // ZTBX <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZTBX,
+ fixedBits: 0x5202c00,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ },
+ // ZTBXQ
+ {
+ // ZTBXQ <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZTBXQ,
+ fixedBits: 0x5203400,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ },
+ // ZTRN1
+ {
+ // ZTRN1 <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZTRN1,
+ fixedBits: 0x5207000,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ // ZTRN1 <Zm>.Q, <Zn>.Q, <Zd>.Q
+ {
+ goOp: AZTRN1,
+ fixedBits: 0x5a01800,
+ args: Zm_Q__Zn_Q__Zd_Q,
+ },
+ },
+ // ZTRN2
+ {
+ // ZTRN2 <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZTRN2,
+ fixedBits: 0x5207400,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ // ZTRN2 <Zm>.Q, <Zn>.Q, <Zd>.Q
+ {
+ goOp: AZTRN2,
+ fixedBits: 0x5a01c00,
+ args: Zm_Q__Zn_Q__Zd_Q,
+ },
+ },
+ // ZUABA
+ {
+ // ZUABA <Zm>.<T>, <Zn>.<T>, <Zda>.<T>
+ {
+ goOp: AZUABA,
+ fixedBits: 0x4500fc00,
+ args: Zm_T__Zn_T__Zda_T__2,
+ },
+ },
+ // ZUABAL
+ {
+ // ZUABAL <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
+ {
+ goOp: AZUABAL,
+ fixedBits: 0x4400dc00,
+ args: Zm_Tb__Zn_Tb__Zda_T__1,
+ },
+ },
+ // ZUABALB
+ {
+ // ZUABALB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
+ {
+ goOp: AZUABALB,
+ fixedBits: 0x4500c800,
+ args: Zm_Tb__Zn_Tb__Zda_T__1,
+ },
+ },
+ // ZUABALT
+ {
+ // ZUABALT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
+ {
+ goOp: AZUABALT,
+ fixedBits: 0x4500cc00,
+ args: Zm_Tb__Zn_Tb__Zda_T__1,
+ },
+ },
+ // ZUABD
+ {
+ // ZUABD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZUABD,
+ fixedBits: 0x40d0000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZUABDLB
+ {
+ // ZUABDLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZUABDLB,
+ fixedBits: 0x45003800,
+ args: Zm_Tb__Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZUABDLT
+ {
+ // ZUABDLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZUABDLT,
+ fixedBits: 0x45003c00,
+ args: Zm_Tb__Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZUADALP
+ {
+ // ZUADALP <Zn>.<Tb>, <Pg>/M, <Zda>.<T>
+ {
+ goOp: AZUADALP,
+ fixedBits: 0x4405a000,
+ args: Zn_Tb__PgM__Zda_T,
+ },
+ },
+ // ZUADDLB
+ {
+ // ZUADDLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZUADDLB,
+ fixedBits: 0x45000800,
+ args: Zm_Tb__Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZUADDLT
+ {
+ // ZUADDLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZUADDLT,
+ fixedBits: 0x45000c00,
+ args: Zm_Tb__Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZUADDWB
+ {
+ // ZUADDWB <Zm>.<Tb>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZUADDWB,
+ fixedBits: 0x45004800,
+ args: Zm_Tb__Zn_T__Zd_T,
+ },
+ },
+ // ZUADDWT
+ {
+ // ZUADDWT <Zm>.<Tb>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZUADDWT,
+ fixedBits: 0x45004c00,
+ args: Zm_Tb__Zn_T__Zd_T,
+ },
+ },
+ // ZUCLAMP
+ {
+ // ZUCLAMP <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZUCLAMP,
+ fixedBits: 0x4400c400,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ },
+ // ZUCVTF
+ {
+ // ZUCVTF <Zn>.D, <Pg>/Z, <Zd>.S
+ {
+ goOp: AZUCVTF,
+ fixedBits: 0x64dda000,
+ args: Zn_D__PgZ__Zd_S,
+ },
+ // ZUCVTF <Zn>.D, <Pg>/M, <Zd>.H
+ {
+ goOp: AZUCVTF,
+ fixedBits: 0x6557a000,
+ args: Zn_D__PgM__Zd_H,
+ },
+ // ZUCVTF <Zn>.S, <Pg>/Z, <Zd>.H
+ {
+ goOp: AZUCVTF,
+ fixedBits: 0x645da000,
+ args: Zn_S__PgZ__Zd_H,
+ },
+ // ZUCVTF <Zn>.S, <Pg>/M, <Zd>.S
+ {
+ goOp: AZUCVTF,
+ fixedBits: 0x6595a000,
+ args: Zn_S__PgM__Zd_S,
+ },
+ // ZUCVTF <Zn>.S, <Pg>/Z, <Zd>.S
+ {
+ goOp: AZUCVTF,
+ fixedBits: 0x649da000,
+ args: Zn_S__PgZ__Zd_S,
+ },
+ // ZUCVTF <Zn>.S, <Pg>/M, <Zd>.D
+ {
+ goOp: AZUCVTF,
+ fixedBits: 0x65d1a000,
+ args: Zn_S__PgM__Zd_D,
+ },
+ // ZUCVTF <Zn>.S, <Pg>/Z, <Zd>.D
+ {
+ goOp: AZUCVTF,
+ fixedBits: 0x64dca000,
+ args: Zn_S__PgZ__Zd_D,
+ },
+ // ZUCVTF <Zn>.H, <Pg>/M, <Zd>.H
+ {
+ goOp: AZUCVTF,
+ fixedBits: 0x6553a000,
+ args: Zn_H__PgM__Zd_H,
+ },
+ // ZUCVTF <Zn>.D, <Pg>/Z, <Zd>.H
+ {
+ goOp: AZUCVTF,
+ fixedBits: 0x645de000,
+ args: Zn_D__PgZ__Zd_H,
+ },
+ // ZUCVTF <Zn>.D, <Pg>/M, <Zd>.S
+ {
+ goOp: AZUCVTF,
+ fixedBits: 0x65d5a000,
+ args: Zn_D__PgM__Zd_S,
+ },
+ // ZUCVTF <Zn>.H, <Pg>/Z, <Zd>.H
+ {
+ goOp: AZUCVTF,
+ fixedBits: 0x645ce000,
+ args: Zn_H__PgZ__Zd_H,
+ },
+ // ZUCVTF <Zn>.D, <Pg>/M, <Zd>.D
+ {
+ goOp: AZUCVTF,
+ fixedBits: 0x65d7a000,
+ args: Zn_D__PgM__Zd_D,
+ },
+ // ZUCVTF <Zn>.D, <Pg>/Z, <Zd>.D
+ {
+ goOp: AZUCVTF,
+ fixedBits: 0x64dde000,
+ args: Zn_D__PgZ__Zd_D,
+ },
+ // ZUCVTF <Zn>.S, <Pg>/M, <Zd>.H
+ {
+ goOp: AZUCVTF,
+ fixedBits: 0x6555a000,
+ args: Zn_S__PgM__Zd_H,
+ },
+ // ZUCVTF <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZUCVTF,
+ fixedBits: 0x650c3400,
+ args: Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZUCVTFLT
+ {
+ // ZUCVTFLT <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZUCVTFLT,
+ fixedBits: 0x650c3c00,
+ args: Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZUDIV
+ {
+ // ZUDIV <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZUDIV,
+ fixedBits: 0x4950000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__4,
+ },
+ },
+ // ZUDIVR
+ {
+ // ZUDIVR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZUDIVR,
+ fixedBits: 0x4970000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__4,
+ },
+ },
+ // ZUDOT
+ {
+ // ZUDOT <Zm>.B, <Zn>.B, <Zda>.H
+ {
+ goOp: AZUDOT,
+ fixedBits: 0x44400400,
+ args: Zm_B__Zn_B__Zda_H,
+ },
+ // ZUDOT <Zm>.H, <Zn>.H, <Zda>.S
+ {
+ goOp: AZUDOT,
+ fixedBits: 0x4400cc00,
+ args: Zm_H__Zn_H__Zda_S,
+ },
+ // ZUDOT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
+ {
+ goOp: AZUDOT,
+ fixedBits: 0x44800400,
+ args: Zm_Tb__Zn_Tb__Zda_T__2,
+ },
+ },
+ // ZUHADD
+ {
+ // ZUHADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZUHADD,
+ fixedBits: 0x44118000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZUHSUB
+ {
+ // ZUHSUB <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZUHSUB,
+ fixedBits: 0x44138000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZUHSUBR
+ {
+ // ZUHSUBR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZUHSUBR,
+ fixedBits: 0x44178000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZUMAX
+ {
+ // ZUMAX <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZUMAX,
+ fixedBits: 0x4090000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZUMAXP
+ {
+ // ZUMAXP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZUMAXP,
+ fixedBits: 0x4415a000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZUMAXQV
+ {
+ // ZUMAXQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
+ {
+ goOp: AZUMAXQV,
+ fixedBits: 0x40d2000,
+ args: Zn_Tb__Pg__Vd_T__1,
+ },
+ },
+ // ZUMIN
+ {
+ // ZUMIN <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZUMIN,
+ fixedBits: 0x40b0000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZUMINP
+ {
+ // ZUMINP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZUMINP,
+ fixedBits: 0x4417a000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZUMINQV
+ {
+ // ZUMINQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
+ {
+ goOp: AZUMINQV,
+ fixedBits: 0x40f2000,
+ args: Zn_Tb__Pg__Vd_T__1,
+ },
+ },
+ // ZUMLALB
+ {
+ // ZUMLALB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
+ {
+ goOp: AZUMLALB,
+ fixedBits: 0x44004800,
+ args: Zm_Tb__Zn_Tb__Zda_T__1,
+ },
+ },
+ // ZUMLALT
+ {
+ // ZUMLALT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
+ {
+ goOp: AZUMLALT,
+ fixedBits: 0x44004c00,
+ args: Zm_Tb__Zn_Tb__Zda_T__1,
+ },
+ },
+ // ZUMLSLB
+ {
+ // ZUMLSLB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
+ {
+ goOp: AZUMLSLB,
+ fixedBits: 0x44005800,
+ args: Zm_Tb__Zn_Tb__Zda_T__1,
+ },
+ },
+ // ZUMLSLT
+ {
+ // ZUMLSLT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
+ {
+ goOp: AZUMLSLT,
+ fixedBits: 0x44005c00,
+ args: Zm_Tb__Zn_Tb__Zda_T__1,
+ },
+ },
+ // ZUMMLA
+ {
+ // ZUMMLA <Zm>.B, <Zn>.B, <Zda>.S
+ {
+ goOp: AZUMMLA,
+ fixedBits: 0x45c09800,
+ args: Zm_B__Zn_B__Zda_S,
+ },
+ },
+ // ZUMULH
+ {
+ // ZUMULH <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZUMULH,
+ fixedBits: 0x4130000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ // ZUMULH <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZUMULH,
+ fixedBits: 0x4206c00,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ },
+ // ZUMULLB
+ {
+ // ZUMULLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZUMULLB,
+ fixedBits: 0x45007800,
+ args: Zm_Tb__Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZUMULLT
+ {
+ // ZUMULLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZUMULLT,
+ fixedBits: 0x45007c00,
+ args: Zm_Tb__Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZUQADD
+ {
+ // ZUQADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZUQADD,
+ fixedBits: 0x44198000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ // ZUQADD <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZUQADD,
+ fixedBits: 0x4201400,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ },
+ // ZUQDECP
+ {
+ // ZUQDECP <Pm>.<T>, <Zdn>.<T>
+ {
+ goOp: AZUQDECP,
+ fixedBits: 0x252b8000,
+ args: Pm_T__Zdn_T,
+ },
+ },
+ // ZUQINCP
+ {
+ // ZUQINCP <Pm>.<T>, <Zdn>.<T>
+ {
+ goOp: AZUQINCP,
+ fixedBits: 0x25298000,
+ args: Pm_T__Zdn_T,
+ },
+ },
+ // ZUQRSHL
+ {
+ // ZUQRSHL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZUQRSHL,
+ fixedBits: 0x440b8000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZUQRSHLR
+ {
+ // ZUQRSHLR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZUQRSHLR,
+ fixedBits: 0x440f8000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZUQSHL
+ {
+ // ZUQSHL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZUQSHL,
+ fixedBits: 0x44098000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZUQSHLR
+ {
+ // ZUQSHLR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZUQSHLR,
+ fixedBits: 0x440d8000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZUQSUB
+ {
+ // ZUQSUB <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZUQSUB,
+ fixedBits: 0x441b8000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ // ZUQSUB <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZUQSUB,
+ fixedBits: 0x4201c00,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ },
+ // ZUQSUBR
+ {
+ // ZUQSUBR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZUQSUBR,
+ fixedBits: 0x441f8000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZUQXTNB
+ {
+ // ZUQXTNB <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZUQXTNB,
+ fixedBits: 0x45204800,
+ args: Zn_Tb__Zd_T__2,
+ },
+ },
+ // ZUQXTNT
+ {
+ // ZUQXTNT <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZUQXTNT,
+ fixedBits: 0x45204c00,
+ args: Zn_Tb__Zd_T__2,
+ },
+ },
+ // ZURECPE
+ {
+ // ZURECPE <Zn>.S, <Pg>/M, <Zd>.S
+ {
+ goOp: AZURECPE,
+ fixedBits: 0x4480a000,
+ args: Zn_S__PgM__Zd_S,
+ },
+ // ZURECPE <Zn>.S, <Pg>/Z, <Zd>.S
+ {
+ goOp: AZURECPE,
+ fixedBits: 0x4482a000,
+ args: Zn_S__PgZ__Zd_S,
+ },
+ },
+ // ZURHADD
+ {
+ // ZURHADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZURHADD,
+ fixedBits: 0x44158000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZURSHL
+ {
+ // ZURSHL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZURSHL,
+ fixedBits: 0x44038000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZURSHLR
+ {
+ // ZURSHLR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZURSHLR,
+ fixedBits: 0x44078000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZURSQRTE
+ {
+ // ZURSQRTE <Zn>.S, <Pg>/M, <Zd>.S
+ {
+ goOp: AZURSQRTE,
+ fixedBits: 0x4481a000,
+ args: Zn_S__PgM__Zd_S,
+ },
+ // ZURSQRTE <Zn>.S, <Pg>/Z, <Zd>.S
+ {
+ goOp: AZURSQRTE,
+ fixedBits: 0x4483a000,
+ args: Zn_S__PgZ__Zd_S,
+ },
+ },
+ // ZUSDOT
+ {
+ // ZUSDOT <Zm>.B, <Zn>.B, <Zda>.S
+ {
+ goOp: AZUSDOT,
+ fixedBits: 0x44807800,
+ args: Zm_B__Zn_B__Zda_S,
+ },
+ },
+ // ZUSMMLA
+ {
+ // ZUSMMLA <Zm>.B, <Zn>.B, <Zda>.S
+ {
+ goOp: AZUSMMLA,
+ fixedBits: 0x45809800,
+ args: Zm_B__Zn_B__Zda_S,
+ },
+ },
+ // ZUSQADD
+ {
+ // ZUSQADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
+ {
+ goOp: AZUSQADD,
+ fixedBits: 0x441d8000,
+ args: Zm_T__Zdn_T__PgM__Zdn_T__1,
+ },
+ },
+ // ZUSUBLB
+ {
+ // ZUSUBLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZUSUBLB,
+ fixedBits: 0x45001800,
+ args: Zm_Tb__Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZUSUBLT
+ {
+ // ZUSUBLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZUSUBLT,
+ fixedBits: 0x45001c00,
+ args: Zm_Tb__Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZUSUBWB
+ {
+ // ZUSUBWB <Zm>.<Tb>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZUSUBWB,
+ fixedBits: 0x45005800,
+ args: Zm_Tb__Zn_T__Zd_T,
+ },
+ },
+ // ZUSUBWT
+ {
+ // ZUSUBWT <Zm>.<Tb>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZUSUBWT,
+ fixedBits: 0x45005c00,
+ args: Zm_Tb__Zn_T__Zd_T,
+ },
+ },
+ // ZUUNPKHI
+ {
+ // ZUUNPKHI <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZUUNPKHI,
+ fixedBits: 0x5333800,
+ args: Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZUUNPKLO
+ {
+ // ZUUNPKLO <Zn>.<Tb>, <Zd>.<T>
+ {
+ goOp: AZUUNPKLO,
+ fixedBits: 0x5323800,
+ args: Zn_Tb__Zd_T__1,
+ },
+ },
+ // ZUXTB
+ {
+ // ZUXTB <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZUXTB,
+ fixedBits: 0x411a000,
+ args: Zn_T__PgM__Zd_T__4,
+ },
+ // ZUXTB <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZUXTB,
+ fixedBits: 0x401a000,
+ args: Zn_T__PgZ__Zd_T__4,
+ },
+ },
+ // ZUXTH
+ {
+ // ZUXTH <Zn>.<T>, <Pg>/M, <Zd>.<T>
+ {
+ goOp: AZUXTH,
+ fixedBits: 0x493a000,
+ args: Zn_T__PgM__Zd_T__5,
+ },
+ // ZUXTH <Zn>.<T>, <Pg>/Z, <Zd>.<T>
+ {
+ goOp: AZUXTH,
+ fixedBits: 0x483a000,
+ args: Zn_T__PgZ__Zd_T__5,
+ },
+ },
+ // ZUXTW
+ {
+ // ZUXTW <Zn>.D, <Pg>/M, <Zd>.D
+ {
+ goOp: AZUXTW,
+ fixedBits: 0x4d5a000,
+ args: Zn_D__PgM__Zd_D,
+ },
+ // ZUXTW <Zn>.D, <Pg>/Z, <Zd>.D
+ {
+ goOp: AZUXTW,
+ fixedBits: 0x4c5a000,
+ args: Zn_D__PgZ__Zd_D,
+ },
+ },
+ // ZUZP1
+ {
+ // ZUZP1 <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZUZP1,
+ fixedBits: 0x5206800,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ // ZUZP1 <Zm>.Q, <Zn>.Q, <Zd>.Q
+ {
+ goOp: AZUZP1,
+ fixedBits: 0x5a00800,
+ args: Zm_Q__Zn_Q__Zd_Q,
+ },
+ },
+ // ZUZP2
+ {
+ // ZUZP2 <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZUZP2,
+ fixedBits: 0x5206c00,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ // ZUZP2 <Zm>.Q, <Zn>.Q, <Zd>.Q
+ {
+ goOp: AZUZP2,
+ fixedBits: 0x5a00c00,
+ args: Zm_Q__Zn_Q__Zd_Q,
+ },
+ },
+ // ZUZPQ1
+ {
+ // ZUZPQ1 <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZUZPQ1,
+ fixedBits: 0x4400e800,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ },
+ // ZUZPQ2
+ {
+ // ZUZPQ2 <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZUZPQ2,
+ fixedBits: 0x4400ec00,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ },
+ // ZZIP1
+ {
+ // ZZIP1 <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZZIP1,
+ fixedBits: 0x5206000,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ // ZZIP1 <Zm>.Q, <Zn>.Q, <Zd>.Q
+ {
+ goOp: AZZIP1,
+ fixedBits: 0x5a00000,
+ args: Zm_Q__Zn_Q__Zd_Q,
+ },
+ },
+ // ZZIP2
+ {
+ // ZZIP2 <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZZIP2,
+ fixedBits: 0x5206400,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ // ZZIP2 <Zm>.Q, <Zn>.Q, <Zd>.Q
+ {
+ goOp: AZZIP2,
+ fixedBits: 0x5a00400,
+ args: Zm_Q__Zn_Q__Zd_Q,
+ },
+ },
+ // ZZIPQ1
+ {
+ // ZZIPQ1 <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZZIPQ1,
+ fixedBits: 0x4400e000,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ },
+ // ZZIPQ2
+ {
+ // ZZIPQ2 <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
+ {
+ goOp: AZZIPQ2,
+ fixedBits: 0x4400e400,
+ args: Zm_T__Zn_T__Zd_T__1,
+ },
+ },
+}
+
+var a_ARNG_PNd_SizeBHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodePNd, enc_PNd},
+ {encodeSizeBHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_Pd_ArngBCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodePd, enc_Pd},
+ {encodeArngBCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Pd_ArngHCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodePd, enc_Pd},
+ {encodeArngHCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Pd_Size0BH2223 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodePd, enc_Pd},
+ {encodeSize0BH2223, enc_size0},
+ },
+}
+
+var a_ARNG_Pd_SizeBHS2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodePd, enc_Pd},
+ {encodeSizeBHS2224, enc_size},
+ },
+}
+
+var a_ARNG_Pd_SizeBHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodePd, enc_Pd},
+ {encodeSizeBHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_Pd_SizeHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodePd, enc_Pd},
+ {encodeSizeHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_PdmDest_ArngBCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodePdmDest, enc_Pdm},
+ {encodeArngBCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_PdnDest_SizeBHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodePdnDest, enc_Pdn},
+ {encodeSizeBHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_PdnSrcDst_ArngBCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodePdnSrcDst, enc_Pdn},
+ {encodeArngBCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Pm1620_ArngBCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodePm1620, enc_Pm},
+ {encodeArngBCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Pm1620_SizeBHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodePm1620, enc_Pm},
+ {encodeSizeBHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_Pm59v1_SizeHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodePm59v1, enc_Pm},
+ {encodeSizeHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_Pn59_ArngBCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodePn59, enc_Pn},
+ {encodeArngBCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Pn59_SizeBHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodePn59, enc_Pn},
+ {encodeSizeBHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_Pn59v2_ArngBCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodePn59v2, enc_Pn},
+ {encodeArngBCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Pn59v2_SizeBHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodePn59v2, enc_Pn},
+ {encodeSizeBHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_Vd_Size16B8H4S2D = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeVd, enc_Vd},
+ {encodeSize16B8H4S2D, enc_size},
+ },
+}
+
+var a_ARNG_Vd_Size8H4S2D = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeVd, enc_Vd},
+ {encodeSize8H4S2D, enc_size},
+ },
+}
+
+var a_ARNG_Za16213Rd_SizeHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZa16213Rd, enc_Za},
+ {encodeSizeHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_Za5103Rd_ArngDCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZa5103Rd, enc_Za},
+ {encodeArngDCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Za5103Rd_SizeBHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZa5103Rd, enc_Za},
+ {encodeSizeBHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_Zd_ArngBCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZd, enc_Zd},
+ {encodeArngBCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zd_ArngDCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZd, enc_Zd},
+ {encodeArngDCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zd_ArngHCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZd, enc_Zd},
+ {encodeArngHCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zd_ArngQCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZd, enc_Zd},
+ {encodeArngQCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zd_ArngSCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZd, enc_Zd},
+ {encodeArngSCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zd_Size0HalfwordMergeZero = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZd, enc_Zd},
+ {encodeSize0HalfwordMergeZero, enc_size0},
+ },
+}
+
+var a_ARNG_Zd_Size0SD2223 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZd, enc_Zd},
+ {encodeSize0SD2223, enc_size0},
+ },
+}
+
+var a_ARNG_Zd_SizeBHS2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZd, enc_Zd},
+ {encodeSizeBHS2224, enc_size},
+ },
+}
+
+var a_ARNG_Zd_SizeBHS2224Offset1 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZd, enc_Zd},
+ {encodeSizeBHS2224Offset1, enc_size},
+ },
+}
+
+var a_ARNG_Zd_SizeBHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZd, enc_Zd},
+ {encodeSizeBHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_Zd_SizeByteMergeZero = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZd, enc_Zd},
+ {encodeSizeByteMergeZero, enc_size},
+ },
+}
+
+var a_ARNG_Zd_SizeHD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZd, enc_Zd},
+ {encodeSizeHD2224, enc_size},
+ },
+}
+
+var a_ARNG_Zd_SizeHSD1315 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZd, enc_Zd},
+ {encodeSizeHSD1315, enc_size},
+ },
+}
+
+var a_ARNG_Zd_SizeHSD1719 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZd, enc_Zd},
+ {encodeSizeHSD1719, enc_size},
+ },
+}
+
+var a_ARNG_Zd_SizeHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZd, enc_Zd},
+ {encodeSizeHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_Zd_SizeHSD2224No00 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZd, enc_Zd},
+ {encodeSizeHSD2224No00, enc_size},
+ },
+}
+
+var a_ARNG_Zd_SzByteHalfword = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZd, enc_Zd},
+ {encodeSzByteHalfword, enc_sz},
+ },
+}
+
+var a_ARNG_Zd_SzSD1415 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZd, enc_Zd},
+ {encodeSzSD1415, enc_sz},
+ },
+}
+
+var a_ARNG_Zd_SzSD1718 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZd, enc_Zd},
+ {encodeSzSD1718, enc_sz},
+ },
+}
+
+var a_ARNG_Zd_SzWordDoubleword = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZd, enc_Zd},
+ {encodeSzWordDoubleword, enc_sz},
+ },
+}
+
+var a_ARNG_Zd_TszhTszlBHS = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZd, enc_Zd},
+ {encodeTszhTszlBHS, enc_tszh_tszl},
+ },
+}
+
+var a_ARNG_Zda3RdSrcDst_ArngDCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZda3RdSrcDst, enc_Zda},
+ {encodeArngDCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zda3RdSrcDst_ArngHCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZda3RdSrcDst, enc_Zda},
+ {encodeArngHCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zda3RdSrcDst_ArngSCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZda3RdSrcDst, enc_Zda},
+ {encodeArngSCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zda3RdSrcDst_Size0SD2223 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZda3RdSrcDst, enc_Zda},
+ {encodeSize0SD2223, enc_size0},
+ },
+}
+
+var a_ARNG_Zda3RdSrcDst_SizeBHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZda3RdSrcDst, enc_Zda},
+ {encodeSizeBHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_Zda3RdSrcDst_SizeHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZda3RdSrcDst, enc_Zda},
+ {encodeSizeHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_Zda3RdSrcDst_SizeHSD2224No00 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZda3RdSrcDst, enc_Zda},
+ {encodeSizeHSD2224No00, enc_size},
+ },
+}
+
+var a_ARNG_Zda3RdSrcDst_SzSD2223 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZda3RdSrcDst, enc_Zda},
+ {encodeSzSD2223, enc_sz},
+ },
+}
+
+var a_ARNG_ZdaDest_SizeHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZdaDest, enc_Zda},
+ {encodeSizeHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_ZdnDest_ArngBCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZdnDest, enc_Zdn},
+ {encodeArngBCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_ZdnDest_ArngDCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZdnDest, enc_Zdn},
+ {encodeArngDCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_ZdnDest_ArngHCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZdnDest, enc_Zdn},
+ {encodeArngHCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_ZdnDest_ArngSCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZdnDest, enc_Zdn},
+ {encodeArngSCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_ZdnDest_Size0SD2223 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZdnDest, enc_Zdn},
+ {encodeSize0SD2223, enc_size0},
+ },
+}
+
+var a_ARNG_ZdnDest_SizeBHS2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZdnDest, enc_Zdn},
+ {encodeSizeBHS2224, enc_size},
+ },
+}
+
+var a_ARNG_ZdnDest_SizeBHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZdnDest, enc_Zdn},
+ {encodeSizeBHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_ZdnDest_SizeHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZdnDest, enc_Zdn},
+ {encodeSizeHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_ZdnDest_SizeHSD2224No00 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZdnDest, enc_Zdn},
+ {encodeSizeHSD2224No00, enc_size},
+ },
+}
+
+var a_ARNG_ZdnSrcDst_ArngBCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZdnSrcDst, enc_Zdn},
+ {encodeArngBCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_ZdnSrcDst_SizeHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZdnSrcDst, enc_Zdn},
+ {encodeSizeHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_Zk5103Rd_ArngDCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZk5103Rd, enc_Zk},
+ {encodeArngDCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zm1621_ArngBCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm1621, enc_Zm},
+ {encodeArngBCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zm1621_ArngDCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm1621, enc_Zm},
+ {encodeArngDCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zm1621_ArngHCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm1621, enc_Zm},
+ {encodeArngHCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zm1621_ArngQCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm1621, enc_Zm},
+ {encodeArngQCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zm1621_ArngSCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm1621, enc_Zm},
+ {encodeArngSCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zm1621_Size0BH2223 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm1621, enc_Zm},
+ {encodeSize0BH2223, enc_size0},
+ },
+}
+
+var a_ARNG_Zm1621_Size0SD2223 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm1621, enc_Zm},
+ {encodeSize0SD2223, enc_size0},
+ },
+}
+
+var a_ARNG_Zm1621_Size0TbBH2223 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm1621, enc_Zm},
+ {encodeSize0TbBH2223, enc_size0},
+ },
+}
+
+var a_ARNG_Zm1621_SizeBHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm1621, enc_Zm},
+ {encodeSizeBHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_Zm1621_SizeHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm1621, enc_Zm},
+ {encodeSizeHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_Zm1621_SizeHSD2224No00 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm1621, enc_Zm},
+ {encodeSizeHSD2224No00, enc_size},
+ },
+}
+
+var a_ARNG_Zm1621_SizeTbBHS2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm1621, enc_Zm},
+ {encodeSizeTbBHS2224, enc_size},
+ },
+}
+
+var a_ARNG_Zm1621_SizeTbBS2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm1621, enc_Zm},
+ {encodeSizeTbBS2224, enc_size},
+ },
+}
+
+var a_ARNG_Zm1621_SizeTbHSD2224Offset1 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm1621, enc_Zm},
+ {encodeSizeTbHSD2224Offset1, enc_size},
+ },
+}
+
+var a_ARNG_Zm1621_SzSD2223 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm1621, enc_Zm},
+ {encodeSzSD2223, enc_sz},
+ },
+}
+
+var a_ARNG_Zm510_ArngBCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm510, enc_Zm},
+ {encodeArngBCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zm510_ArngDCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm510, enc_Zm},
+ {encodeArngDCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zm510_ArngHCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm510, enc_Zm},
+ {encodeArngHCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zm510_ArngSCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm510, enc_Zm},
+ {encodeArngSCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zm510_Size0SD2223 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm510, enc_Zm},
+ {encodeSize0SD2223, enc_size0},
+ },
+}
+
+var a_ARNG_Zm510_SizeBHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm510, enc_Zm},
+ {encodeSizeBHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_Zm510_SizeHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm510, enc_Zm},
+ {encodeSizeHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_Zm510_SizeHSD2224No00 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZm510, enc_Zm},
+ {encodeSizeHSD2224No00, enc_size},
+ },
+}
+
+var a_ARNG_Zn510Src_ArngBCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510Src, enc_Zn},
+ {encodeArngBCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zn510Src_ArngDCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510Src, enc_Zn},
+ {encodeArngDCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zn510Src_ArngHCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510Src, enc_Zn},
+ {encodeArngHCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zn510Src_ArngQCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510Src, enc_Zn},
+ {encodeArngQCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zn510Src_ArngSCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510Src, enc_Zn},
+ {encodeArngSCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zn510Src_Size0HalfwordMergeZero = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510Src, enc_Zn},
+ {encodeSize0HalfwordMergeZero, enc_size0},
+ },
+}
+
+var a_ARNG_Zn510Src_SizeBHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510Src, enc_Zn},
+ {encodeSizeBHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_Zn510Src_SizeByteMergeZero = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510Src, enc_Zn},
+ {encodeSizeByteMergeZero, enc_size},
+ },
+}
+
+var a_ARNG_Zn510Src_SizeHSD1315 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510Src, enc_Zn},
+ {encodeSizeHSD1315, enc_size},
+ },
+}
+
+var a_ARNG_Zn510Src_SizeHSD1719 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510Src, enc_Zn},
+ {encodeSizeHSD1719, enc_size},
+ },
+}
+
+var a_ARNG_Zn510Src_SizeHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510Src, enc_Zn},
+ {encodeSizeHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_Zn510Src_SizeTbBHS2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510Src, enc_Zn},
+ {encodeSizeTbBHS2224, enc_size},
+ },
+}
+
+var a_ARNG_Zn510Src_SizeTbBHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510Src, enc_Zn},
+ {encodeSizeTbBHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_Zn510Src_SizeTbHSD2224Offset1 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510Src, enc_Zn},
+ {encodeSizeTbHSD2224Offset1, enc_size},
+ },
+}
+
+var a_ARNG_Zn510Src_SzByteHalfword = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510Src, enc_Zn},
+ {encodeSzByteHalfword, enc_sz},
+ },
+}
+
+var a_ARNG_Zn510Src_SzSD1415 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510Src, enc_Zn},
+ {encodeSzSD1415, enc_sz},
+ },
+}
+
+var a_ARNG_Zn510Src_SzSD1718 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510Src, enc_Zn},
+ {encodeSzSD1718, enc_sz},
+ },
+}
+
+var a_ARNG_Zn510Src_SzWordDoubleword = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510Src, enc_Zn},
+ {encodeSzWordDoubleword, enc_sz},
+ },
+}
+
+var a_ARNG_Zn510Src_TszhTszlTbHSD = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510Src, enc_Zn},
+ {encodeTszhTszlTbHSD, enc_tszh_tszl},
+ },
+}
+
+var a_ARNG_Zn510_ArngBCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510, enc_Zn},
+ {encodeArngBCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zn510_ArngDCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510, enc_Zn},
+ {encodeArngDCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zn510_ArngHCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510, enc_Zn},
+ {encodeArngHCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zn510_ArngQCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510, enc_Zn},
+ {encodeArngQCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zn510_ArngSCheck = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510, enc_Zn},
+ {encodeArngSCheck, enc_NIL},
+ },
+}
+
+var a_ARNG_Zn510_Size0BH2223 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510, enc_Zn},
+ {encodeSize0BH2223, enc_size0},
+ },
+}
+
+var a_ARNG_Zn510_Size0SD2223 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510, enc_Zn},
+ {encodeSize0SD2223, enc_size0},
+ },
+}
+
+var a_ARNG_Zn510_Size0TbBH2223 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510, enc_Zn},
+ {encodeSize0TbBH2223, enc_size0},
+ },
+}
+
+var a_ARNG_Zn510_SizeBHS2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510, enc_Zn},
+ {encodeSizeBHS2224, enc_size},
+ },
+}
+
+var a_ARNG_Zn510_SizeBHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510, enc_Zn},
+ {encodeSizeBHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_Zn510_SizeHSD2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510, enc_Zn},
+ {encodeSizeHSD2224, enc_size},
+ },
+}
+
+var a_ARNG_Zn510_SizeHSD2224No00 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510, enc_Zn},
+ {encodeSizeHSD2224No00, enc_size},
+ },
+}
+
+var a_ARNG_Zn510_SizeTbBHS2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510, enc_Zn},
+ {encodeSizeTbBHS2224, enc_size},
+ },
+}
+
+var a_ARNG_Zn510_SizeTbBS2224 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510, enc_Zn},
+ {encodeSizeTbBS2224, enc_size},
+ },
+}
+
+var a_ARNG_Zn510_SizeTbHSD2224Offset1 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510, enc_Zn},
+ {encodeSizeTbHSD2224Offset1, enc_size},
+ },
+}
+
+var a_ARNG_Zn510_SzSD2223 = operand{
+ class: AC_ARNG, elemEncoders: []elemEncoder{
+ {encodeZn510, enc_Zn},
+ {encodeSzSD2223, enc_sz},
+ },
+}
+
+var a_PREGZM_Pg1013_MergePredCheck = operand{
+ class: AC_PREGZM, elemEncoders: []elemEncoder{
+ {encodePg1013, enc_Pg},
+ {encodeMergePredCheck, enc_NIL},
+ },
+}
+
+var a_PREGZM_Pg1013_PredQualM1617 = operand{
+ class: AC_PREGZM, elemEncoders: []elemEncoder{
+ {encodePg1013, enc_Pg},
+ {encodePredQualM1617, enc_M},
+ },
+}
+
+var a_PREGZM_Pg1013_ZeroPredCheck = operand{
+ class: AC_PREGZM, elemEncoders: []elemEncoder{
+ {encodePg1013, enc_Pg},
+ {encodeZeroPredCheck, enc_NIL},
+ },
+}
+
+var a_PREGZM_Pg1014_PredQualM45 = operand{
+ class: AC_PREGZM, elemEncoders: []elemEncoder{
+ {encodePg1014, enc_Pg},
+ {encodePredQualM45, enc_M},
+ },
+}
+
+var a_PREGZM_Pg1014_ZeroPredCheck = operand{
+ class: AC_PREGZM, elemEncoders: []elemEncoder{
+ {encodePg1014, enc_Pg},
+ {encodeZeroPredCheck, enc_NIL},
+ },
+}
+
+var a_PREGZM_Pg59_ZeroPredCheck = operand{
+ class: AC_PREGZM, elemEncoders: []elemEncoder{
+ {encodePg59, enc_Pg},
+ {encodeZeroPredCheck, enc_NIL},
+ },
+}
+
+var a_PREG_Pg1013_Noop = operand{
+ class: AC_PREG, elemEncoders: []elemEncoder{
+ {encodePg1013, enc_Pg},
+ {encodeNoop, enc_NIL},
+ },
+}
+
+var a_PREG_Pg1014_Noop = operand{
+ class: AC_PREG, elemEncoders: []elemEncoder{
+ {encodePg1014, enc_Pg},
+ {encodeNoop, enc_NIL},
+ },
+}
+
+var a_PREG_Pg59_Noop = operand{
+ class: AC_PREG, elemEncoders: []elemEncoder{
+ {encodePg59, enc_Pg},
+ {encodeNoop, enc_NIL},
+ },
+}
+
+var a_PREG_Pv1013_Noop = operand{
+ class: AC_PREG, elemEncoders: []elemEncoder{
+ {encodePv1013, enc_Pv},
+ {encodeNoop, enc_NIL},
+ },
+}
+
+var a_PREG_Pv1014_Noop = operand{
+ class: AC_PREG, elemEncoders: []elemEncoder{
+ {encodePv1014, enc_Pv},
+ {encodeNoop, enc_NIL},
+ },
+}
+
+var a_PREG_Pv59_Noop = operand{
+ class: AC_PREG, elemEncoders: []elemEncoder{
+ {encodePv59, enc_Pv},
+ {encodeNoop, enc_NIL},
+ },
+}
+
+var a_ZREG_Zd_Noop = operand{
+ class: AC_ZREG, elemEncoders: []elemEncoder{
+ {encodeZd, enc_Zd},
+ {encodeNoop, enc_NIL},
+ },
+}
+
+var a_ZREG_Zn510Src_Noop = operand{
+ class: AC_ZREG, elemEncoders: []elemEncoder{
+ {encodeZn510Src, enc_Zn},
+ {encodeNoop, enc_NIL},
+ },
+}
+
+var PNd_T = []operand{
+ a_ARNG_PNd_SizeBHSD2224,
+}
+
+var Pd_B = []operand{
+ a_ARNG_Pd_ArngBCheck,
+}
+
+var Pdm_B__Pn_B__PgZ__Pdm_B = []operand{
+ a_ARNG_PdmDest_ArngBCheck,
+ a_ARNG_Pn59_ArngBCheck,
+ a_PREGZM_Pg1014_ZeroPredCheck,
+ a_ARNG_PdmDest_ArngBCheck,
+}
+
+var Pdn_B__Pg__Pdn_B = []operand{
+ a_ARNG_PdnSrcDst_ArngBCheck,
+ a_PREG_Pg59_Noop,
+ a_ARNG_PdnSrcDst_ArngBCheck,
+}
+
+var Pdn_T__Pv__Pdn_T = []operand{
+ a_ARNG_PdnDest_SizeBHSD2224,
+ a_PREG_Pv59_Noop,
+ a_ARNG_PdnDest_SizeBHSD2224,
+}
+
+var PgZ__Pd_B = []operand{
+ a_PREGZM_Pg59_ZeroPredCheck,
+ a_ARNG_Pd_ArngBCheck,
+}
+
+var Pm_B__Pn_B__PgZ__Pd_B = []operand{
+ a_ARNG_Pm1620_ArngBCheck,
+ a_ARNG_Pn59_ArngBCheck,
+ a_PREGZM_Pg1014_ZeroPredCheck,
+ a_ARNG_Pd_ArngBCheck,
+}
+
+var Pm_B__Pn_B__Pg__Pd_B = []operand{
+ a_ARNG_Pm1620_ArngBCheck,
+ a_ARNG_Pn59_ArngBCheck,
+ a_PREG_Pg1014_Noop,
+ a_ARNG_Pd_ArngBCheck,
+}
+
+var Pm_T__Pn_T__Pd_T = []operand{
+ a_ARNG_Pm1620_SizeBHSD2224,
+ a_ARNG_Pn59_SizeBHSD2224,
+ a_ARNG_Pd_SizeBHSD2224,
+}
+
+var Pm_T__Zdn_T = []operand{
+ a_ARNG_Pm59v1_SizeHSD2224,
+ a_ARNG_ZdnSrcDst_SizeHSD2224,
+}
+
+var Pn_B = []operand{
+ a_ARNG_Pn59v2_ArngBCheck,
+}
+
+var Pn_B__Pd_H = []operand{
+ a_ARNG_Pn59v2_ArngBCheck,
+ a_ARNG_Pd_ArngHCheck,
+}
+
+var Pn_B__Pg = []operand{
+ a_ARNG_Pn59v2_ArngBCheck,
+ a_PREG_Pg1014_Noop,
+}
+
+var Pn_B__PgZM__Pd_B = []operand{
+ a_ARNG_Pn59v2_ArngBCheck,
+ a_PREGZM_Pg1014_PredQualM45,
+ a_ARNG_Pd_ArngBCheck,
+}
+
+var Pn_B__PgZ__Pd_B = []operand{
+ a_ARNG_Pn59v2_ArngBCheck,
+ a_PREGZM_Pg1014_ZeroPredCheck,
+ a_ARNG_Pd_ArngBCheck,
+}
+
+var Pn_B__Zd = []operand{
+ a_ARNG_Pn59v2_ArngBCheck,
+ a_ZREG_Zd_Noop,
+}
+
+var Pn_T__Pd_T = []operand{
+ a_ARNG_Pn59v2_SizeBHSD2224,
+ a_ARNG_Pd_SizeBHSD2224,
+}
+
+var Za_D__Zm_D__Zdn_D = []operand{
+ a_ARNG_Za5103Rd_ArngDCheck,
+ a_ARNG_Zm1621_ArngDCheck,
+ a_ARNG_ZdnDest_ArngDCheck,
+}
+
+var Za_T__Zm_T__PgM__Zdn_T__1 = []operand{
+ a_ARNG_Za16213Rd_SizeHSD2224,
+ a_ARNG_Zm510_SizeHSD2224,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_ZdnDest_SizeHSD2224,
+}
+
+var Za_T__Zm_T__PgM__Zdn_T__2 = []operand{
+ a_ARNG_Za5103Rd_SizeBHSD2224,
+ a_ARNG_Zm1621_SizeBHSD2224,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_ZdnDest_SizeBHSD2224,
+}
+
+var Zdn_B__Zdn_B = []operand{
+ a_ARNG_ZdnSrcDst_ArngBCheck,
+ a_ARNG_ZdnSrcDst_ArngBCheck,
+}
+
+var Zk_D__Zm_D__Zdn_D__Zdn_D = []operand{
+ a_ARNG_Zk5103Rd_ArngDCheck,
+ a_ARNG_Zm1621_ArngDCheck,
+ a_ARNG_ZdnDest_ArngDCheck,
+ a_ARNG_ZdnDest_ArngDCheck,
+}
+
+var Zm_B__Zdn_B__Zdn_B = []operand{
+ a_ARNG_Zm510_ArngBCheck,
+ a_ARNG_ZdnDest_ArngBCheck,
+ a_ARNG_ZdnDest_ArngBCheck,
+}
+
+var Zm_B__Zn_B__Zd_B = []operand{
+ a_ARNG_Zm1621_ArngBCheck,
+ a_ARNG_Zn510_ArngBCheck,
+ a_ARNG_Zd_ArngBCheck,
+}
+
+var Zm_B__Zn_B__Zda_H = []operand{
+ a_ARNG_Zm1621_ArngBCheck,
+ a_ARNG_Zn510_ArngBCheck,
+ a_ARNG_Zda3RdSrcDst_ArngHCheck,
+}
+
+var Zm_B__Zn_B__Zda_S = []operand{
+ a_ARNG_Zm1621_ArngBCheck,
+ a_ARNG_Zn510_ArngBCheck,
+ a_ARNG_Zda3RdSrcDst_ArngSCheck,
+}
+
+var Zm_D__Zdn_D__PgM__Zdn_D = []operand{
+ a_ARNG_Zm510_ArngDCheck,
+ a_ARNG_ZdnDest_ArngDCheck,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_ZdnDest_ArngDCheck,
+}
+
+var Zm_D__Zdn_T__PgM__Zdn_T = []operand{
+ a_ARNG_Zm510_ArngDCheck,
+ a_ARNG_ZdnDest_SizeBHS2224,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_ZdnDest_SizeBHS2224,
+}
+
+var Zm_D__Zn_D__Zd_D = []operand{
+ a_ARNG_Zm1621_ArngDCheck,
+ a_ARNG_Zn510_ArngDCheck,
+ a_ARNG_Zd_ArngDCheck,
+}
+
+var Zm_D__Zn_D__Zd_Q = []operand{
+ a_ARNG_Zm1621_ArngDCheck,
+ a_ARNG_Zn510_ArngDCheck,
+ a_ARNG_Zd_ArngQCheck,
+}
+
+var Zm_D__Zn_D__Zda_D = []operand{
+ a_ARNG_Zm1621_ArngDCheck,
+ a_ARNG_Zn510_ArngDCheck,
+ a_ARNG_Zda3RdSrcDst_ArngDCheck,
+}
+
+var Zm_D__Zn_T__PgZ__Pd_T = []operand{
+ a_ARNG_Zm1621_ArngDCheck,
+ a_ARNG_Zn510_SizeBHS2224,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_ARNG_Pd_SizeBHS2224,
+}
+
+var Zm_D__Zn_T__Zd_T = []operand{
+ a_ARNG_Zm1621_ArngDCheck,
+ a_ARNG_Zn510_SizeBHS2224,
+ a_ARNG_Zd_SizeBHS2224,
+}
+
+var Zm_H__Zdn_H__PgM__Zdn_H = []operand{
+ a_ARNG_Zm510_ArngHCheck,
+ a_ARNG_ZdnDest_ArngHCheck,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_ZdnDest_ArngHCheck,
+}
+
+var Zm_H__Zn_H__PgM__Zda_H = []operand{
+ a_ARNG_Zm1621_ArngHCheck,
+ a_ARNG_Zn510_ArngHCheck,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_Zda3RdSrcDst_ArngHCheck,
+}
+
+var Zm_H__Zn_H__Zd_H = []operand{
+ a_ARNG_Zm1621_ArngHCheck,
+ a_ARNG_Zn510_ArngHCheck,
+ a_ARNG_Zd_ArngHCheck,
+}
+
+var Zm_H__Zn_H__Zda_H = []operand{
+ a_ARNG_Zm1621_ArngHCheck,
+ a_ARNG_Zn510_ArngHCheck,
+ a_ARNG_Zda3RdSrcDst_ArngHCheck,
+}
+
+var Zm_H__Zn_H__Zda_S = []operand{
+ a_ARNG_Zm1621_ArngHCheck,
+ a_ARNG_Zn510_ArngHCheck,
+ a_ARNG_Zda3RdSrcDst_ArngSCheck,
+}
+
+var Zm_Q__Zn_Q__Zd_Q = []operand{
+ a_ARNG_Zm1621_ArngQCheck,
+ a_ARNG_Zn510_ArngQCheck,
+ a_ARNG_Zd_ArngQCheck,
+}
+
+var Zm_S__Zdn_S__Zdn_S = []operand{
+ a_ARNG_Zm510_ArngSCheck,
+ a_ARNG_ZdnDest_ArngSCheck,
+ a_ARNG_ZdnDest_ArngSCheck,
+}
+
+var Zm_S__Zn_S__Zd_S = []operand{
+ a_ARNG_Zm1621_ArngSCheck,
+ a_ARNG_Zn510_ArngSCheck,
+ a_ARNG_Zd_ArngSCheck,
+}
+
+var Zm_S__Zn_S__Zda_S = []operand{
+ a_ARNG_Zm1621_ArngSCheck,
+ a_ARNG_Zn510_ArngSCheck,
+ a_ARNG_Zda3RdSrcDst_ArngSCheck,
+}
+
+var Zm_T__Zdn_T__PgM__Zdn_T__1 = []operand{
+ a_ARNG_Zm510_SizeBHSD2224,
+ a_ARNG_ZdnDest_SizeBHSD2224,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_ZdnDest_SizeBHSD2224,
+}
+
+var Zm_T__Zdn_T__PgM__Zdn_T__2 = []operand{
+ a_ARNG_Zm510_SizeHSD2224,
+ a_ARNG_ZdnDest_SizeHSD2224,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_ZdnDest_SizeHSD2224,
+}
+
+var Zm_T__Zdn_T__PgM__Zdn_T__3 = []operand{
+ a_ARNG_Zm510_SizeHSD2224No00,
+ a_ARNG_ZdnDest_SizeHSD2224No00,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_ZdnDest_SizeHSD2224No00,
+}
+
+var Zm_T__Zdn_T__PgM__Zdn_T__4 = []operand{
+ a_ARNG_Zm510_Size0SD2223,
+ a_ARNG_ZdnDest_Size0SD2223,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_ZdnDest_Size0SD2223,
+}
+
+var Zm_T__Zdn_T__Pg__Zdn_T = []operand{
+ a_ARNG_Zm510_SizeBHSD2224,
+ a_ARNG_ZdnDest_SizeBHSD2224,
+ a_PREG_Pg1013_Noop,
+ a_ARNG_ZdnDest_SizeBHSD2224,
+}
+
+var Zm_T__Zdn_T__Pv__Zdn_T = []operand{
+ a_ARNG_Zm510_SizeBHSD2224,
+ a_ARNG_ZdnDest_SizeBHSD2224,
+ a_PREG_Pv1013_Noop,
+ a_ARNG_ZdnDest_SizeBHSD2224,
+}
+
+var Zm_T__Zn_T__PgM__Zda_T__1 = []operand{
+ a_ARNG_Zm1621_SizeHSD2224No00,
+ a_ARNG_Zn510_SizeHSD2224No00,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_Zda3RdSrcDst_SizeHSD2224No00,
+}
+
+var Zm_T__Zn_T__PgM__Zda_T__2 = []operand{
+ a_ARNG_Zm1621_SizeBHSD2224,
+ a_ARNG_Zn510_SizeBHSD2224,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_Zda3RdSrcDst_SizeBHSD2224,
+}
+
+var Zm_T__Zn_T__PgZ__Pd_T__1 = []operand{
+ a_ARNG_Zm1621_SizeHSD2224,
+ a_ARNG_Zn510_SizeHSD2224,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_ARNG_Pd_SizeHSD2224,
+}
+
+var Zm_T__Zn_T__PgZ__Pd_T__2 = []operand{
+ a_ARNG_Zm1621_SizeBHSD2224,
+ a_ARNG_Zn510_SizeBHSD2224,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_ARNG_Pd_SizeBHSD2224,
+}
+
+var Zm_T__Zn_T__PgZ__Pd_T__3 = []operand{
+ a_ARNG_Zm1621_Size0BH2223,
+ a_ARNG_Zn510_Size0BH2223,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_ARNG_Pd_Size0BH2223,
+}
+
+var Zm_T__Zn_T__PgZ__Zd_T = []operand{
+ a_ARNG_Zm1621_Size0SD2223,
+ a_ARNG_Zn510_Size0SD2223,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_ARNG_Zd_Size0SD2223,
+}
+
+var Zm_T__Zn_T__Pv__Zd_T = []operand{
+ a_ARNG_Zm1621_SizeBHSD2224,
+ a_ARNG_Zn510_SizeBHSD2224,
+ a_PREG_Pv1014_Noop,
+ a_ARNG_Zd_SizeBHSD2224,
+}
+
+var Zm_T__Zn_T__Zd_T__1 = []operand{
+ a_ARNG_Zm1621_SizeBHSD2224,
+ a_ARNG_Zn510_SizeBHSD2224,
+ a_ARNG_Zd_SizeBHSD2224,
+}
+
+var Zm_T__Zn_T__Zd_T__2 = []operand{
+ a_ARNG_Zm1621_SizeHSD2224No00,
+ a_ARNG_Zn510_SizeHSD2224No00,
+ a_ARNG_Zd_SizeHSD2224No00,
+}
+
+var Zm_T__Zn_T__Zd_T__3 = []operand{
+ a_ARNG_Zm1621_SizeHSD2224,
+ a_ARNG_Zn510_SizeHSD2224,
+ a_ARNG_Zd_SizeHSD2224,
+}
+
+var Zm_T__Zn_T__Zda_T__1 = []operand{
+ a_ARNG_Zm1621_SzSD2223,
+ a_ARNG_Zn510_SzSD2223,
+ a_ARNG_Zda3RdSrcDst_SzSD2223,
+}
+
+var Zm_T__Zn_T__Zda_T__2 = []operand{
+ a_ARNG_Zm1621_SizeBHSD2224,
+ a_ARNG_Zn510_SizeBHSD2224,
+ a_ARNG_Zda3RdSrcDst_SizeBHSD2224,
+}
+
+var Zm_Tb__Zn_T__Zd_T = []operand{
+ a_ARNG_Zm1621_SizeTbBHS2224,
+ a_ARNG_Zn510_SizeHSD2224,
+ a_ARNG_Zd_SizeHSD2224,
+}
+
+var Zm_Tb__Zn_Tb__Zd_T__1 = []operand{
+ a_ARNG_Zm1621_SizeTbBHS2224,
+ a_ARNG_Zn510_SizeTbBHS2224,
+ a_ARNG_Zd_SizeHSD2224,
+}
+
+var Zm_Tb__Zn_Tb__Zd_T__2 = []operand{
+ a_ARNG_Zm1621_SizeTbHSD2224Offset1,
+ a_ARNG_Zn510_SizeTbHSD2224Offset1,
+ a_ARNG_Zd_SizeBHS2224Offset1,
+}
+
+var Zm_Tb__Zn_Tb__Zd_T__3 = []operand{
+ a_ARNG_Zm1621_SizeTbBS2224,
+ a_ARNG_Zn510_SizeTbBS2224,
+ a_ARNG_Zd_SizeHD2224,
+}
+
+var Zm_Tb__Zn_Tb__Zda_T__1 = []operand{
+ a_ARNG_Zm1621_SizeTbBHS2224,
+ a_ARNG_Zn510_SizeTbBHS2224,
+ a_ARNG_Zda3RdSrcDst_SizeHSD2224,
+}
+
+var Zm_Tb__Zn_Tb__Zda_T__2 = []operand{
+ a_ARNG_Zm1621_Size0TbBH2223,
+ a_ARNG_Zn510_Size0TbBH2223,
+ a_ARNG_Zda3RdSrcDst_Size0SD2223,
+}
+
+var Zn_B__Zd_H = []operand{
+ a_ARNG_Zn510Src_ArngBCheck,
+ a_ARNG_Zd_ArngHCheck,
+}
+
+var Zn_D__PgM__Zd_D = []operand{
+ a_ARNG_Zn510Src_ArngDCheck,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_Zd_ArngDCheck,
+}
+
+var Zn_D__PgM__Zd_H = []operand{
+ a_ARNG_Zn510Src_ArngDCheck,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_Zd_ArngHCheck,
+}
+
+var Zn_D__PgM__Zd_S = []operand{
+ a_ARNG_Zn510Src_ArngDCheck,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_Zd_ArngSCheck,
+}
+
+var Zn_D__PgZ__Zd_D = []operand{
+ a_ARNG_Zn510Src_ArngDCheck,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_ARNG_Zd_ArngDCheck,
+}
+
+var Zn_D__PgZ__Zd_H = []operand{
+ a_ARNG_Zn510Src_ArngDCheck,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_ARNG_Zd_ArngHCheck,
+}
+
+var Zn_D__PgZ__Zd_S = []operand{
+ a_ARNG_Zn510Src_ArngDCheck,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_ARNG_Zd_ArngSCheck,
+}
+
+var Zn_H__PgM__Zd_D = []operand{
+ a_ARNG_Zn510Src_ArngHCheck,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_Zd_ArngDCheck,
+}
+
+var Zn_H__PgM__Zd_H = []operand{
+ a_ARNG_Zn510Src_ArngHCheck,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_Zd_ArngHCheck,
+}
+
+var Zn_H__PgM__Zd_S = []operand{
+ a_ARNG_Zn510Src_ArngHCheck,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_Zd_ArngSCheck,
+}
+
+var Zn_H__PgZ__Zd_D = []operand{
+ a_ARNG_Zn510Src_ArngHCheck,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_ARNG_Zd_ArngDCheck,
+}
+
+var Zn_H__PgZ__Zd_H = []operand{
+ a_ARNG_Zn510Src_ArngHCheck,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_ARNG_Zd_ArngHCheck,
+}
+
+var Zn_H__PgZ__Zd_S = []operand{
+ a_ARNG_Zn510Src_ArngHCheck,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_ARNG_Zd_ArngSCheck,
+}
+
+var Zn_Q__PgM__Zd_Q = []operand{
+ a_ARNG_Zn510Src_ArngQCheck,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_Zd_ArngQCheck,
+}
+
+var Zn_Q__PgZ__Zd_Q = []operand{
+ a_ARNG_Zn510Src_ArngQCheck,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_ARNG_Zd_ArngQCheck,
+}
+
+var Zn_S__PgM__Zd_D = []operand{
+ a_ARNG_Zn510Src_ArngSCheck,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_Zd_ArngDCheck,
+}
+
+var Zn_S__PgM__Zd_H = []operand{
+ a_ARNG_Zn510Src_ArngSCheck,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_Zd_ArngHCheck,
+}
+
+var Zn_S__PgM__Zd_S = []operand{
+ a_ARNG_Zn510Src_ArngSCheck,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_Zd_ArngSCheck,
+}
+
+var Zn_S__PgZ__Zd_D = []operand{
+ a_ARNG_Zn510Src_ArngSCheck,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_ARNG_Zd_ArngDCheck,
+}
+
+var Zn_S__PgZ__Zd_H = []operand{
+ a_ARNG_Zn510Src_ArngSCheck,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_ARNG_Zd_ArngHCheck,
+}
+
+var Zn_S__PgZ__Zd_S = []operand{
+ a_ARNG_Zn510Src_ArngSCheck,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_ARNG_Zd_ArngSCheck,
+}
+
+var Zn_T__PgM__Zd_T__1 = []operand{
+ a_ARNG_Zn510Src_SizeHSD2224,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_Zd_SizeHSD2224,
+}
+
+var Zn_T__PgM__Zd_T__2 = []operand{
+ a_ARNG_Zn510Src_SizeBHSD2224,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_Zd_SizeBHSD2224,
+}
+
+var Zn_T__PgM__Zd_T__3 = []operand{
+ a_ARNG_Zn510Src_SzSD1718,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_Zd_SzSD1718,
+}
+
+var Zn_T__PgM__Zd_T__4 = []operand{
+ a_ARNG_Zn510Src_SizeByteMergeZero,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_Zd_SizeByteMergeZero,
+}
+
+var Zn_T__PgM__Zd_T__5 = []operand{
+ a_ARNG_Zn510Src_Size0HalfwordMergeZero,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_Zd_Size0HalfwordMergeZero,
+}
+
+var Zn_T__PgM__Zd_T__6 = []operand{
+ a_ARNG_Zn510Src_SizeHSD1719,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_Zd_SizeHSD1719,
+}
+
+var Zn_T__PgZM__Zd_T = []operand{
+ a_ARNG_Zn510Src_SizeBHSD2224,
+ a_PREGZM_Pg1013_PredQualM1617,
+ a_ARNG_Zd_SizeBHSD2224,
+}
+
+var Zn_T__PgZ__Zd_T__1 = []operand{
+ a_ARNG_Zn510Src_SizeHSD2224,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_ARNG_Zd_SizeHSD2224,
+}
+
+var Zn_T__PgZ__Zd_T__2 = []operand{
+ a_ARNG_Zn510Src_SizeBHSD2224,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_ARNG_Zd_SizeBHSD2224,
+}
+
+var Zn_T__PgZ__Zd_T__3 = []operand{
+ a_ARNG_Zn510Src_SzSD1415,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_ARNG_Zd_SzSD1415,
+}
+
+var Zn_T__PgZ__Zd_T__4 = []operand{
+ a_ARNG_Zn510Src_SizeByteMergeZero,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_ARNG_Zd_SizeByteMergeZero,
+}
+
+var Zn_T__PgZ__Zd_T__5 = []operand{
+ a_ARNG_Zn510Src_Size0HalfwordMergeZero,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_ARNG_Zd_Size0HalfwordMergeZero,
+}
+
+var Zn_T__PgZ__Zd_T__6 = []operand{
+ a_ARNG_Zn510Src_SizeHSD1315,
+ a_PREGZM_Pg1013_ZeroPredCheck,
+ a_ARNG_Zd_SizeHSD1315,
+}
+
+var Zn_T__Pg__Zd_T__1 = []operand{
+ a_ARNG_Zn510Src_SzByteHalfword,
+ a_PREG_Pg1013_Noop,
+ a_ARNG_Zd_SzByteHalfword,
+}
+
+var Zn_T__Pg__Zd_T__2 = []operand{
+ a_ARNG_Zn510Src_SzWordDoubleword,
+ a_PREG_Pg1013_Noop,
+ a_ARNG_Zd_SzWordDoubleword,
+}
+
+var Zn_T__Pg__Zd_T__3 = []operand{
+ a_ARNG_Zn510Src_SizeBHSD2224,
+ a_PREG_Pg1013_Noop,
+ a_ARNG_Zd_SizeBHSD2224,
+}
+
+var Zn_T__Zd_T__1 = []operand{
+ a_ARNG_Zn510Src_SizeHSD2224,
+ a_ARNG_Zd_SizeHSD2224,
+}
+
+var Zn_T__Zd_T__2 = []operand{
+ a_ARNG_Zn510Src_SizeBHSD2224,
+ a_ARNG_Zd_SizeBHSD2224,
+}
+
+var Zn_Tb__PgM__Zda_T = []operand{
+ a_ARNG_Zn510_SizeTbBHS2224,
+ a_PREGZM_Pg1013_MergePredCheck,
+ a_ARNG_ZdaDest_SizeHSD2224,
+}
+
+var Zn_Tb__Pg__Vd_T__1 = []operand{
+ a_ARNG_Zn510Src_SizeTbBHSD2224,
+ a_PREG_Pg1013_Noop,
+ a_ARNG_Vd_Size16B8H4S2D,
+}
+
+var Zn_Tb__Pg__Vd_T__2 = []operand{
+ a_ARNG_Zn510Src_SizeTbHSD2224Offset1,
+ a_PREG_Pg1013_Noop,
+ a_ARNG_Vd_Size8H4S2D,
+}
+
+var Zn_Tb__Zd_T__1 = []operand{
+ a_ARNG_Zn510Src_SizeTbBHS2224,
+ a_ARNG_Zd_SizeHSD2224,
+}
+
+var Zn_Tb__Zd_T__2 = []operand{
+ a_ARNG_Zn510Src_TszhTszlTbHSD,
+ a_ARNG_Zd_TszhTszlBHS,
+}
+
+var Zn__Pd_B = []operand{
+ a_ZREG_Zn510Src_Noop,
+ a_ARNG_Pd_ArngBCheck,
+}
+
+var Zn__Zd = []operand{
+ a_ZREG_Zn510Src_Noop,
+ a_ZREG_Zd_Noop,
+}
+
+var oc = []operand{}
diff --git a/src/cmd/internal/obj/arm64/list7.go b/src/cmd/internal/obj/arm64/list7.go
index 0654139642..424da1c22d 100644
--- a/src/cmd/internal/obj/arm64/list7.go
+++ b/src/cmd/internal/obj/arm64/list7.go
@@ -90,6 +90,12 @@ func arrange(a int) string {
return "D"
case ARNG_1Q:
return "Q1"
+ case ARNG_Q:
+ return "Q"
+ case PRED_M:
+ return "M"
+ case PRED_Z:
+ return "Z"
default:
return ""
}
@@ -109,6 +115,12 @@ func rconv(r int) string {
return fmt.Sprintf("F%d", r-REG_F0)
case REG_V0 <= r && r <= REG_V31:
return fmt.Sprintf("V%d", r-REG_V0)
+ case REG_Z0 <= r && r <= REG_Z31:
+ return fmt.Sprintf("Z%d", r-REG_Z0)
+ case REG_P0 <= r && r <= REG_P15:
+ return fmt.Sprintf("P%d", r-REG_P0)
+ case REG_PN0 <= r && r <= REG_PN15:
+ return fmt.Sprintf("PN%d", r-REG_PN0)
case r == REGSP:
return "RSP"
case REG_UXTB <= r && r < REG_UXTH:
@@ -166,6 +178,19 @@ func rconv(r int) string {
return fmt.Sprintf("V%d.%s", r&31, arrange((r>>5)&15))
case REG_ELEM <= r && r < REG_ELEM_END:
return fmt.Sprintf("V%d.%s", r&31, arrange((r>>5)&15))
+ case REG_ZARNG <= r && r < REG_PARNGZM:
+ return fmt.Sprintf("Z%d.%s", r&31, arrange((r>>5)&15))
+ case REG_PARNGZM <= r && r < REG_PARNGZM_END:
+ // SVE predicate register with arrangement.
+ // Pn.<T> or Pn/M, Pn/Z.
+ arng := (r >> 5) & 31
+ suffix := arrange(arng)
+ reg := r & 31
+ if reg >= 16 {
+ // PN registers
+ return fmt.Sprintf("PN%d.%s", reg-16, suffix)
+ }
+ return fmt.Sprintf("P%d.%s", reg, suffix)
}
// Return system register name.
name, _, _ := SysRegEnc(int16(r))
diff --git a/src/cmd/internal/obj/util.go b/src/cmd/internal/obj/util.go
index 86ba4deb73..8d53a7b412 100644
--- a/src/cmd/internal/obj/util.go
+++ b/src/cmd/internal/obj/util.go
@@ -514,12 +514,12 @@ const (
RBaseAMD64 = 2 * 1024
RBaseARM = 3 * 1024
RBasePPC64 = 4 * 1024 // range [4k, 8k)
- RBaseARM64 = 8 * 1024 // range [8k, 13k)
- RBaseMIPS = 13 * 1024 // range [13k, 14k)
- RBaseS390X = 14 * 1024 // range [14k, 15k)
- RBaseRISCV = 15 * 1024 // range [15k, 16k)
- RBaseWasm = 16 * 1024
- RBaseLOONG64 = 19 * 1024 // range [19K, 22k)
+ RBaseARM64 = 8 * 1024 // range [8k, 18k)
+ RBaseMIPS = 18 * 1024 // range [18k, 19k)
+ RBaseS390X = 19 * 1024 // range [19k, 20k)
+ RBaseRISCV = 20 * 1024 // range [20k, 21k)
+ RBaseWasm = 21 * 1024
+ RBaseLOONG64 = 22 * 1024 // range [22K, 25k)
)
// RegisterRegister binds a pretty-printer (Rconv) for register
generated by cgit v1.3-5-g9baa (git 2.53.0) at 2026-04-17 14:12:54 +0000