diff options
| author | Jayanth Krishnamurthy jayanth.krishnamurthy@ibm.com <jayanth.krishnamurthy@ibm.com> | 2024-10-29 16:11:37 -0500 |
|---|---|---|
| committer | Gopher Robot <gobot@golang.org> | 2024-11-21 18:27:17 +0000 |
| commit | 7403a6a122a28f715448d4a9b360efe2df15423d (patch) | |
| tree | 176a00440dc874e51ae7e73c331ab5c5ae29e272 /src/cmd/internal/obj | |
| parent | c37d9a0f9313ff2936b1b0b82476416e6cb03c62 (diff) | |
| download | go-7403a6a122a28f715448d4a9b360efe2df15423d.tar.xz | |
cmd/internal/obj/ppc64: support for decimal floating point instructions
1. Support for decimal arithmetic quad instructions of powerpc: DADDQ, DSUBQ, DMULQ
and DDIVQ.
2. Support for decimal compare ordered, unordered, quad instructions of powerpc:
DCMPU, DCMPO, DCMPUQ, and DCMPOQ.
Change-Id: I32a15a7f0a127b022b1f43d376e0ab0f7e9dd108
Cq-Include-Trybots: luci.golang.try:gotip-linux-ppc64_power10,gotip-linux-ppc64_power8,gotip-linux-ppc64le_power8,gotip-linux-ppc64le_power9,gotip-linux-ppc64le_power10
Reviewed-on: https://go-review.googlesource.com/c/go/+/623036
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Auto-Submit: Paul Murphy <murp@ibm.com>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
Reviewed-by: Paul Murphy <murp@ibm.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Diffstat (limited to 'src/cmd/internal/obj')
| -rw-r--r-- | src/cmd/internal/obj/ppc64/a.out.go | 8 | ||||
| -rw-r--r-- | src/cmd/internal/obj/ppc64/anames.go | 8 | ||||
| -rw-r--r-- | src/cmd/internal/obj/ppc64/asm9.go | 34 |
3 files changed, 50 insertions, 0 deletions
diff --git a/src/cmd/internal/obj/ppc64/a.out.go b/src/cmd/internal/obj/ppc64/a.out.go index 0c980ef476..aa7bcd3068 100644 --- a/src/cmd/internal/obj/ppc64/a.out.go +++ b/src/cmd/internal/obj/ppc64/a.out.go @@ -506,7 +506,13 @@ const ( ACRORN ACRXOR ADADD + ADADDQ + ADCMPO + ADCMPOQ + ADCMPU + ADCMPUQ ADDIV + ADDIVQ ADIVW ADIVWCC ADIVWVCC @@ -516,7 +522,9 @@ const ( ADIVWUVCC ADIVWUV ADMUL + ADMULQ ADSUB + ADSUBQ AMODUD AMODUW AMODSD diff --git a/src/cmd/internal/obj/ppc64/anames.go b/src/cmd/internal/obj/ppc64/anames.go index f9ec191551..ebcdc95cb5 100644 --- a/src/cmd/internal/obj/ppc64/anames.go +++ b/src/cmd/internal/obj/ppc64/anames.go @@ -58,7 +58,13 @@ var Anames = []string{ "CRORN", "CRXOR", "DADD", + "DADDQ", + "DCMPO", + "DCMPOQ", + "DCMPU", + "DCMPUQ", "DDIV", + "DDIVQ", "DIVW", "DIVWCC", "DIVWVCC", @@ -68,7 +74,9 @@ var Anames = []string{ "DIVWUVCC", "DIVWUV", "DMUL", + "DMULQ", "DSUB", + "DSUBQ", "MODUD", "MODUW", "MODSD", diff --git a/src/cmd/internal/obj/ppc64/asm9.go b/src/cmd/internal/obj/ppc64/asm9.go index a9ef420e3d..b30976c85d 100644 --- a/src/cmd/internal/obj/ppc64/asm9.go +++ b/src/cmd/internal/obj/ppc64/asm9.go @@ -199,11 +199,15 @@ var optabBase = []Optab{ {as: ARLDCL, a1: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4}, {as: AFADD, a1: C_FREG, a6: C_FREG, type_: 2, size: 4}, {as: AFADD, a1: C_FREG, a2: C_FREG, a6: C_FREG, type_: 2, size: 4}, + {as: ADADDQ, a1: C_FREGP, a6: C_FREGP, type_: 2, size: 4}, + {as: ADADDQ, a1: C_FREGP, a2: C_FREGP, a6: C_FREGP, type_: 2, size: 4}, {as: AFABS, a1: C_FREG, a6: C_FREG, type_: 33, size: 4}, {as: AFABS, a6: C_FREG, type_: 33, size: 4}, {as: AFMADD, a1: C_FREG, a2: C_FREG, a3: C_FREG, a6: C_FREG, type_: 34, size: 4}, {as: AFMUL, a1: C_FREG, a6: C_FREG, type_: 32, size: 4}, {as: AFMUL, a1: C_FREG, a2: C_FREG, a6: C_FREG, type_: 32, size: 4}, + {as: ADMULQ, a1: C_FREGP, a6: C_FREGP, type_: 32, size: 4}, + {as: ADMULQ, a1: C_FREGP, a2: C_FREGP, a6: C_FREGP, type_: 32, size: 4}, {as: AMOVBU, a1: C_REG, a6: C_SOREG, type_: 7, size: 4}, {as: AMOVBU, a1: C_REG, a6: C_XOREG, type_: 108, size: 4}, @@ -481,6 +485,8 @@ var optabBase = []Optab{ {as: ACMPU, a1: C_REG, a2: C_CREG, a6: C_U16CON, type_: 70, size: 4}, {as: AFCMPO, a1: C_FREG, a6: C_FREG, type_: 70, size: 4}, {as: AFCMPO, a1: C_FREG, a2: C_CREG, a6: C_FREG, type_: 70, size: 4}, + {as: ADCMPOQ, a1: C_FREGP, a6: C_FREGP, type_: 70, size: 4}, + {as: ADCMPOQ, a1: C_FREGP, a2: C_CREG, a6: C_FREGP, type_: 70, size: 4}, {as: ATW, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 60, size: 4}, {as: ATW, a1: C_32CON, a2: C_REG, a6: C_S16CON, type_: 61, size: 4}, {as: ADCBF, a1: C_SOREG, type_: 43, size: 4}, @@ -1876,6 +1882,10 @@ func buildop(ctxt *obj.Link) { opset(ADDIV, r0) opset(ADSUB, r0) + case ADADDQ: + opset(ADDIVQ, r0) + opset(ADSUBQ, r0) + case AFMADD: opset(AFMADDCC, r0) opset(AFMADDS, r0) @@ -1901,8 +1911,16 @@ func buildop(ctxt *obj.Link) { opset(AFMULSCC, r0) opset(ADMUL, r0) + case ADMULQ: + opset(ADMULQ, r0) + case AFCMPO: opset(AFCMPU, r0) + opset(ADCMPU, r0) + opset(ADCMPO, r0) + + case ADCMPOQ: + opset(ADCMPUQ, r0) case AMTFSB0: opset(AMTFSB0CC, r0) @@ -4008,6 +4026,22 @@ func (c *ctxt9) oprrr(a obj.As) uint32 { return OPVCC(59, 34, 0, 0) case ADSUB: return OPVCC(59, 514, 0, 0) + case ADADDQ: + return OPVCC(63, 2, 0, 0) + case ADDIVQ: + return OPVCC(63, 546, 0, 0) + case ADMULQ: + return OPVCC(63, 34, 0, 0) + case ADSUBQ: + return OPVCC(63, 514, 0, 0) + case ADCMPU: + return OPVCC(59, 642, 0, 0) + case ADCMPUQ: + return OPVCC(63, 642, 0, 0) + case ADCMPO: + return OPVCC(59, 130, 0, 0) + case ADCMPOQ: + return OPVCC(63, 130, 0, 0) case ADCBF: return OPVCC(31, 86, 0, 0) |
