diff options
| author | Ben Shi <powerman1st@163.com> | 2017-04-28 10:55:41 +0000 |
|---|---|---|
| committer | Cherry Zhang <cherryyz@google.com> | 2017-05-06 01:28:38 +0000 |
| commit | 4b2f7b4b51180424c4e84b50d99e1fba5b6f3e89 (patch) | |
| tree | 2367280ea958e75ecca88e55d1373b01975b16f6 /src/cmd/internal/obj | |
| parent | 6d9b900a6f25274ca28a33c2cb5550dbb5f01be1 (diff) | |
| download | go-4b2f7b4b51180424c4e84b50d99e1fba5b6f3e89.tar.xz | |
cmd/asm: fix operand order of ARM's MULA instruction
As discussion in issue #19141, the addend should be the third
argument of MULA. This patch fixes it in both the front end
and the back end of the assembler. And also tests are added to
the encoding test.
Fixes #19141
Change-Id: Idbc6f338b8fdfcad97a135f27a98c5b375b27d43
Reviewed-on: https://go-review.googlesource.com/42028
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Diffstat (limited to 'src/cmd/internal/obj')
| -rw-r--r-- | src/cmd/internal/obj/arm/asm5.go | 10 | ||||
| -rw-r--r-- | src/cmd/internal/obj/util.go | 2 |
2 files changed, 5 insertions, 7 deletions
diff --git a/src/cmd/internal/obj/arm/asm5.go b/src/cmd/internal/obj/arm/asm5.go index 1770ab6129..28bd7f8020 100644 --- a/src/cmd/internal/obj/arm/asm5.go +++ b/src/cmd/internal/obj/arm/asm5.go @@ -165,7 +165,6 @@ var optab = []Optab{ {ADIVHW, C_REG, C_REG, C_REG, 105, 4, 0, 0, 0}, {ADIVHW, C_REG, C_NONE, C_REG, 105, 4, 0, 0, 0}, {AMULL, C_REG, C_REG, C_REGREG, 17, 4, 0, 0, 0}, - {AMULA, C_REG, C_REG, C_REGREG2, 17, 4, 0, 0, 0}, {AMOVW, C_REG, C_NONE, C_SAUTO, 20, 4, REGSP, 0, 0}, {AMOVW, C_REG, C_NONE, C_SOREG, 20, 4, 0, 0, 0}, {AMOVB, C_REG, C_NONE, C_SAUTO, 20, 4, REGSP, 0, 0}, @@ -1526,6 +1525,7 @@ func buildop(ctxt *obj.Link) { case AMULAWT: opset(AMULAWB, r0) opset(AMULABB, r0) + opset(AMULA, r0) opset(AMULS, r0) opset(AMMULA, r0) opset(AMMULS, r0) @@ -1536,12 +1536,10 @@ func buildop(ctxt *obj.Link) { opset(AREVSH, r0) opset(ARBIT, r0) - case AMULA, - ALDREX, + case ALDREX, ASTREX, ALDREXD, ASTREXD, - ATST, APLD, obj.AUNDEF, obj.AFUNCDATA, @@ -2489,10 +2487,10 @@ func (c *ctxt5) asmout(p *obj.Prog, o *Optab, out []uint32) { case 99: /* MULAW{T,B} Rs, Rm, Rn, Rd */ o1 = c.oprrr(p, p.As, int(p.Scond)) - o1 |= (uint32(p.To.Reg) & 15) << 12 + o1 |= (uint32(p.To.Reg) & 15) << 16 o1 |= (uint32(p.From.Reg) & 15) << 8 o1 |= (uint32(p.Reg) & 15) << 0 - o1 |= uint32((p.To.Offset & 15) << 16) + o1 |= uint32((p.To.Offset & 15) << 12) // DATABUNDLE: BKPT $0x5be0, signify the start of NaCl data bundle; // DATABUNDLEEND: zero width alignment marker diff --git a/src/cmd/internal/obj/util.go b/src/cmd/internal/obj/util.go index 2e3ba15542..9bcdbbd127 100644 --- a/src/cmd/internal/obj/util.go +++ b/src/cmd/internal/obj/util.go @@ -240,7 +240,7 @@ func Dconv(p *Prog, a *Addr) string { str = fmt.Sprintf("(%v, %v)", Rconv(int(a.Reg)), Rconv(int(a.Offset))) case TYPE_REGREG2: - str = fmt.Sprintf("%v, %v", Rconv(int(a.Reg)), Rconv(int(a.Offset))) + str = fmt.Sprintf("%v, %v", Rconv(int(a.Offset)), Rconv(int(a.Reg))) case TYPE_REGLIST: str = regListConv(int(a.Offset)) |