diff options
| author | wangboyao <wangboyao@bytedance.com> | 2025-07-24 14:49:44 +0800 |
|---|---|---|
| committer | Joel Sing <joel@sing.id.au> | 2025-09-24 06:21:53 -0700 |
| commit | 371c1d2fcb48fa79ac30812231ecef0e26f539dc (patch) | |
| tree | 03e8539410a951a09c8ff335d53ef17690f46be2 /src/cmd/internal/obj | |
| parent | 411c250d64304033181c46413a6e9381e8fe9b82 (diff) | |
| download | go-371c1d2fcb48fa79ac30812231ecef0e26f539dc.tar.xz | |
cmd/internal/obj/riscv: add support for vector unit-stride fault-only-first load instructions
Add support for vector unit-stride fault-only-first load instructions to the RISC-V
assembler. This includes vle8ff, vle16ff, vle32ff and vle64ff.
Change-Id: I5575a1ea155663852f92194fb79f08b5d52203de
Reviewed-on: https://go-review.googlesource.com/c/go/+/690115
Reviewed-by: Junyang Shao <shaojunyang@google.com>
Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Reviewed-by: Joel Sing <joel@sing.id.au>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Diffstat (limited to 'src/cmd/internal/obj')
| -rw-r--r-- | src/cmd/internal/obj/riscv/obj.go | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/cmd/internal/obj/riscv/obj.go b/src/cmd/internal/obj/riscv/obj.go index 9d595f301c..91642ffbcb 100644 --- a/src/cmd/internal/obj/riscv/obj.go +++ b/src/cmd/internal/obj/riscv/obj.go @@ -2176,6 +2176,12 @@ var instructions = [ALAST & obj.AMask]instructionData{ AVSOXEI32V & obj.AMask: {enc: sVIVEncoding}, AVSOXEI64V & obj.AMask: {enc: sVIVEncoding}, + // 31.7.7: Unit-stride Fault-Only-First Loads + AVLE8FFV & obj.AMask: {enc: iVEncoding}, + AVLE16FFV & obj.AMask: {enc: iVEncoding}, + AVLE32FFV & obj.AMask: {enc: iVEncoding}, + AVLE64FFV & obj.AMask: {enc: iVEncoding}, + // 31.7.8: Vector Load/Store Segment Instructions AVLSEG2E8V & obj.AMask: {enc: iVEncoding}, AVLSEG3E8V & obj.AMask: {enc: iVEncoding}, @@ -3839,7 +3845,7 @@ func instructionsForProg(p *obj.Prog) []*instruction { ins.rs1 = uint32(p.From.Offset) } - case AVLE8V, AVLE16V, AVLE32V, AVLE64V, AVSE8V, AVSE16V, AVSE32V, AVSE64V, AVLMV, AVSMV, + case AVLE8V, AVLE16V, AVLE32V, AVLE64V, AVSE8V, AVSE16V, AVSE32V, AVSE64V, AVLE8FFV, AVLE16FFV, AVLE32FFV, AVLE64FFV, AVLMV, AVSMV, AVLSEG2E8V, AVLSEG3E8V, AVLSEG4E8V, AVLSEG5E8V, AVLSEG6E8V, AVLSEG7E8V, AVLSEG8E8V, AVLSEG2E16V, AVLSEG3E16V, AVLSEG4E16V, AVLSEG5E16V, AVLSEG6E16V, AVLSEG7E16V, AVLSEG8E16V, AVLSEG2E32V, AVLSEG3E32V, AVLSEG4E32V, AVLSEG5E32V, AVLSEG6E32V, AVLSEG7E32V, AVLSEG8E32V, |