diff options
| author | Qiu Weihong <953950914@qq.com> | 2025-09-24 17:03:40 +0800 |
|---|---|---|
| committer | Joel Sing <joel@sing.id.au> | 2026-04-03 22:25:40 -0700 |
| commit | 081aa64e610b175e295159c2117f25ecf49953ed (patch) | |
| tree | 60abf845aa8b61e6a0f4aef58d7bfa56d753ff3c /src/cmd/internal/obj | |
| parent | 2a902c8a8a37935abc4adc93605276c9d2103e45 (diff) | |
| download | go-081aa64e610b175e295159c2117f25ecf49953ed.tar.xz | |
cmd/internal/obj/riscv: add assembly support for Zihintpause extensions
Add support for the PAUSE instruction provided by the Zihintpause
extension.
Change-Id: If06cce4ca57137275f567b5fe29ef85517f381ef
Reviewed-on: https://go-review.googlesource.com/c/go/+/710495
Reviewed-by: Joel Sing <joel@sing.id.au>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
Reviewed-by: Junyang Shao <shaojunyang@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Diffstat (limited to 'src/cmd/internal/obj')
| -rw-r--r-- | src/cmd/internal/obj/riscv/anames.go | 1 | ||||
| -rw-r--r-- | src/cmd/internal/obj/riscv/cpu.go | 1 | ||||
| -rw-r--r-- | src/cmd/internal/obj/riscv/obj.go | 4 |
3 files changed, 6 insertions, 0 deletions
diff --git a/src/cmd/internal/obj/riscv/anames.go b/src/cmd/internal/obj/riscv/anames.go index 1f777dd195..9bc4ac4725 100644 --- a/src/cmd/internal/obj/riscv/anames.go +++ b/src/cmd/internal/obj/riscv/anames.go @@ -939,6 +939,7 @@ var Anames = []string{ "NEG", "NEGW", "NOT", + "PAUSE", "RDCYCLE", "RDINSTRET", "RDTIME", diff --git a/src/cmd/internal/obj/riscv/cpu.go b/src/cmd/internal/obj/riscv/cpu.go index 433c8e1e89..8112c56ee0 100644 --- a/src/cmd/internal/obj/riscv/cpu.go +++ b/src/cmd/internal/obj/riscv/cpu.go @@ -1508,6 +1508,7 @@ const ( ANEG ANEGW ANOT + APAUSE ARDCYCLE ARDINSTRET ARDTIME diff --git a/src/cmd/internal/obj/riscv/obj.go b/src/cmd/internal/obj/riscv/obj.go index 50c687f722..332df52f87 100644 --- a/src/cmd/internal/obj/riscv/obj.go +++ b/src/cmd/internal/obj/riscv/obj.go @@ -4421,6 +4421,10 @@ func instructionsForProg(p *obj.Prog, compress bool) []*instruction { ins.imm = int64((pred << 4) | succ) } + case APAUSE: + ins.as, ins.rd, ins.rs1, ins.rs2 = AFENCE, REG_ZERO, REG_ZERO, obj.REG_NONE + ins.imm = 0x010 + case AFCVTWS, AFCVTLS, AFCVTWUS, AFCVTLUS, AFCVTWD, AFCVTLD, AFCVTWUD, AFCVTLUD: // Set the default rounding mode in funct3 to round to zero. if p.Scond&rmSuffixBit == 0 { |