diff options
| author | fanzha02 <fannie.zhang@arm.com> | 2018-03-08 10:33:14 +0000 |
|---|---|---|
| committer | Cherry Zhang <cherryyz@google.com> | 2018-03-19 23:45:50 +0000 |
| commit | 910c3a9dfc4ff8ea4c25d725783bce4887d790f2 (patch) | |
| tree | 19d0954999c23541b920cd0055575475051f3d46 /src/cmd/internal/obj/util.go | |
| parent | 7974f0815e071448cd429d7c30c1d6c24b04a589 (diff) | |
| download | go-910c3a9dfc4ff8ea4c25d725783bce4887d790f2.tar.xz | |
cmd/asm: add ARM64 assembler check for incorrect input
Current ARM64 assembler has no check for the invalid value of both
shift amount and post-index immediate offset of LD1/ST1. This patch
adds the check.
This patch also fixes the printing error of register number equals
to 31, which should be printed as ZR instead of R31. Test cases
are also added.
Change-Id: I476235f3ab3a3fc91fe89c5a3149a4d4529c05c7
Reviewed-on: https://go-review.googlesource.com/100255
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
Diffstat (limited to 'src/cmd/internal/obj/util.go')
| -rw-r--r-- | src/cmd/internal/obj/util.go | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cmd/internal/obj/util.go b/src/cmd/internal/obj/util.go index 245e9e9e9b..9b25231bb4 100644 --- a/src/cmd/internal/obj/util.go +++ b/src/cmd/internal/obj/util.go @@ -263,7 +263,8 @@ func Dconv(p *Prog, a *Addr) string { } case "arm64": op := ops[((v>>22)&3)<<1:] - str = fmt.Sprintf("R%d%c%c%d", (v>>16)&31, op[0], op[1], (v>>10)&63) + r := (v >> 16) & 31 + str = fmt.Sprintf("%s%c%c%d", Rconv(r+RBaseARM64), op[0], op[1], (v>>10)&63) default: panic("TYPE_SHIFT is not supported on " + objabi.GOARCH) } |